US20160111293A1 - Manufacturing method of wafer level chip scale package structure - Google Patents
Manufacturing method of wafer level chip scale package structure Download PDFInfo
- Publication number
- US20160111293A1 US20160111293A1 US14/694,256 US201514694256A US2016111293A1 US 20160111293 A1 US20160111293 A1 US 20160111293A1 US 201514694256 A US201514694256 A US 201514694256A US 2016111293 A1 US2016111293 A1 US 2016111293A1
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- electrode
- manufacturing
- layer
- package structure
- wafer level
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Definitions
- the instant disclosure relates to a semiconductor package process, in particular, to a manufacturing method of a wafer level chip scale package structure.
- the wafer level chip scale packaging (WLCSP) process is an advanced packaging technology, which allows a large quantity of wafers to be encapsulated in the same process. Additionally, after the wafer level chip scale packaging process, the size of the product is equal to or slightly larger than that of the power semiconductor chip. Accordingly, the technology of encapsulating the power devices by using the WLCSP process has been developed in today's industry.
- the object of the instant disclosure is to provide a manufacturing method of a wafer level chip scale package structure, in which a conductive structure is arranged in the channel portion to connect the back electrode layer of the semiconductor device.
- the conductive structure does not extend to a cutting portion, and a cutting process is performed to form a plurality of separated package structures along the cutting portion without the conductive structure.
- a manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer having a plurality of semiconductor devices is provided. One of the semiconductor devices, a first semiconductor device, has an active surface and a back surface. The active surface includes an active region and an outer region. A first electrode and a second electrode are arranged in the active region, and the outer region is divided into a cutting portion and a channel portion. Subsequently, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first electrode, the second electrode, and the channel portion.
- a thinning process is performed upon the first semiconductor device from the back surface, and then a back electrode layer is formed on the back surface of the first semiconductor device. Subsequently, an etching process is performed to form a trench exposing the back electrode layer at the channel portion. Thereafter, a conductive structure is formed through the trench to connect the back electrode layer. Subsequently, a cutting process is performed on the cutting portion.
- the trench formed in the channel portion of the outer region extends from the active surface to the back surface so that the conductive structure formed through the trench can be in contact with the back electrode layer. Accordingly, the back electrode layer can be electrically connected to the other components through the conductive structure exposed on the active surface.
- the wafer is cut along the cutting portion. That is, during the cutting process, the cutting tool of the cutting machine is used to cut the semiconductor material and a thinner back electrode layer instead of a thicker metal material layer. Accordingly, the attrition rate of the cutting tool can be reduced.
- FIG. 1 shows a flow chart of the manufacturing method of wafer level chip scale package structure in accordance with an embodiment of the instant disclosure
- FIG. 2A shows a top view of a wafer
- FIG. 2B shows an enlarged view of a first and second semiconductor devices shown in FIG. 2A ;
- FIG. 2C shows a sectional view taken along a line I-I in FIG. 2B ;
- FIG. 3 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure
- FIG. 4 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure
- FIG. 5 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure
- FIG. 6 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure
- FIG. 7A shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure
- FIG. 7B shows a top view of the localized wafer level chip scale package structure in a step of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure
- FIG. 8A shows a sectional view of the package structure after the cutting process of the manufacturing method in accordance with another embodiment of the instant disclosure
- FIG. 8B shows a top view of the localized wafer level chip scale package structure in a step of the manufacturing method in accordance with another embodiment of the instant disclosure
- FIG. 9 shows a flow chart of the manufacturing method of wafer level chip scale package structure in accordance with another embodiment of the instant disclosure.
- FIG. 10A shows a top view of a first semiconductor device
- FIG. 10B shows a sectional view taken along a line H-H in FIG. 10A ;
- FIG. 10C to FIG. 10J respectively show sectional views of the localized wafer level chip scale package structure in different steps of the manufacturing method in FIG. 9 in accordance with another embodiment of the instant disclosure;
- FIG. 10K shows a sectional view of the wafer level chip scale package structure after a cutting process
- FIG. 10L shows a top view of the wafer level chip scale package structure after a cutting process
- FIG. 11 shows a top view of the package structure placed on a lead frame.
- FIG. 1 shows a flow chart of the manufacturing method of wafer level chip scale package structure in accordance with an embodiment of the instant disclosure.
- a wafer 100 is provided.
- the wafer is usually made of Si or other semiconductor materials, such as GaAs.
- the wafer 100 has a thickness of 350 to 680 ⁇ m.
- FIG. 2A shows a top view of the wafer 100 .
- the processes of fabricating the devices on the wafer 100 have been completed, and the wafer 100 includes a plurality of semiconductor devices.
- the first semiconductor device 1 and the second semiconductor device 2 of the semiconductor devices are taken as an example to clarify the manufacturing method of a wafer level chip scale package structure.
- the first semiconductor device 1 and the second semiconductor device 2 are vertical metal-oxide-semiconductor field effect transistors (MOSFET) or other power devices.
- MOSFET vertical metal-oxide-semiconductor field effect transistors
- the first and second semiconductor devices 1 and 2 are vertical MOSFETs.
- the first and second semiconductor devices 1 and 2 are packaged in a common package structure.
- each of the package structures can have at least two semiconductor devices.
- only one semiconductor device, such as only the first semiconductor device is packaged in one package structure after the manufacturing method of the wafer level chip scale package structure.
- FIG. 2B shows an enlarged view of the first and second semiconductor devices shown in FIG. 2A
- FIG. 2C shows a sectional view taken along a line I-I in FIG. 2B
- the first semiconductor device 1 has an active surface 10 and a back surface 11 opposite thereto, in which the back surface 11 is a portion of the back of the wafer 100 .
- the active surface 10 of the first semiconductor device 1 has an outer region 101 and an active region 102 defined thereon, in which the outer region 101 surrounds the active region 102 , i.e., the outer region 101 is formed on a peripheral region of the first semiconductor device 1 .
- the active region 102 is defined in a central region of the first semiconductor device 1 .
- a first electrode 103 and a second electrode 104 are arranged in the active region 102 .
- the second semiconductor device 2 is immediately adjacent to the first semiconductor device 1 and has a structure similar to that of the first semiconductor device 1 .
- the active surface 10 of second semiconductor device 2 also has an active region 202 and an outer region 201 , and a first electrode 203 and a second electrode 204 are arranged in the active region 202 .
- the first electrodes 103 , 203 can serve as gate electrodes
- the second electrodes 104 , 204 can serve as source electrodes.
- one of the source electrodes has a stacked structure, such as a Cu/Si/Al stacked structure.
- outer region 201 of the second semiconductor device 2 and the outer region 101 of the first semiconductor device 1 mate to form a continuous surface which surrounds the active region 102 of the first semiconductor device 1 and the active region 202 of the second semiconductor device 2 .
- the outer region 101 of the first semiconductor device 1 can be divided into a cutting portion 101 a and a channel portion 101 b , in which the channel portion 101 b is located between the active region 102 of the first semiconductor device 1 and the active region 202 of the second semiconductor device 2 .
- each of semiconductor devices can correspond to one channel portion, or a plurality of the semiconductor device corresponds to one channel portion.
- the configuration and the correspondence between the semiconductor device and the channel portion are not intended to limit the instant disclosure.
- a patterned protecting layer 12 is formed on the active surface 10 .
- the patterned protecting layer 12 can be a dielectric layer for protecting the active region 102 of the first semiconductor device 1 and the active region 202 of the second semiconductor device 2 from being contaminated, which may impact on the device characteristics.
- the patterned protecting layer 12 can serve as a mask during the subsequent process steps.
- the patterned protecting layer 12 can be made of phosphosilicate glass, polyimide or nitride. In the instant embodiment, the patterned protecting layer 12 has a thickness ranging from 1 ⁇ m to 10 ⁇ m.
- FIG. 3 illustrates a sectional view of the localized wafer level chip scale package structure in a step S 101 of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure.
- the patterned protecting layer 12 has a plurality of openings 12 a - 12 e .
- the openings 12 a - 12 c respectively expose the first electrode 103 , the second electrode 104 and the channel portion 101 b of the first semiconductor device 1
- the openings 12 d - 12 e respectively expose the first electrode 203 and the second electrode 204 of the second semiconductor device 2 .
- a margin area of the first electrodes 103 and a margin area of the second electrode 104 of the first semiconductor device 1 are covered by the patterned protecting layer 12 , but a central area of the first electrode 103 and a central area of the second electrode 104 are exposed respectively through the openings 12 a and 12 b .
- the patterned protecting layer 12 covers the margin areas of the first and second electrodes 203 and 204 of the second semiconductor device 2 but exposes the central areas of the first and second electrodes 203 and 204 .
- the opening 12 c of the patterned protecting layer 12 exposes the channel portion 101 b .
- the patterned protecting layer 12 completely covers the cutting portion 101 a of the first semiconductor device 1 and the outer region 201 of the second semiconductor device 2 .
- FIG. 4 shows a sectional view of the localized wafer level chip scale package structure in the step S 102 of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure. In the embodiment shown in FIG. 4 , taking the first and second semiconductor devices 1 and 2 as examples for description.
- the thinning process can be a back-grinding process, i.e., the thinning process is performed upon the first semiconductor device 1 and the second semiconductor device 2 from the back surface 11 by using a grinding machine. That is, the thinning process is performed upon the back of the wafer 100 to reduce the thickness of the wafer 100 .
- the active surface 10 having the active regions 102 and 202 of the first and second semiconductor devices 1 and 2 can be protected by attaching an adhesive tape.
- the thickness of the wafer 100 is reduced to a range between 125 ⁇ m to 180 ⁇ m.
- FIG. 5 shows a sectional view of the localized wafer level chip scale package structure in the step S 103 of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure.
- the back electrode layer 13 extends from the back surface 11 ′ of the first semiconductor device 1 to the back surface 11 ′ of the second semiconductor device 2 so that the first semiconductor device 1 and the second semiconductor device 1 share the same back electrode layer 13 .
- FIG. 5 shows the back electrode layer 13 is formed on the back surfaces 11 ′ of the first and second semiconductor devices 1 and 2 , one of ordinary skill in the art knows, in reality, the back electrode layer 13 is formed on the entire wafer back.
- the back electrode layer 13 can be a conductive layer to serve as a drain electrode of the first semiconductor device 1 .
- the back electrode layer 13 is a metal-stacked layer, such as a Ti/Ni/Ag stacked layer, in which the titanium layer has a thickness of 200 nm, the nickel layer has a thickness of 300 nm, and the silver layer has a thickness of 2000 nm.
- the back electrode layer 13 can be a Ti/Cu stacked layer.
- the other material also can be made of the back electrode layer 13 , and thus the aforementioned materials and the structure of the back electrode layer 13 are not intended to limit the instant disclosure.
- the back electrode layer 13 can be formed by, but not limit to, chemical vapor deposition (CVD) or physical vapor deposition (PVD), such as evaporation or sputtering deposition.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- step S 104 an etching process is performed to form a trench 101 h exposing the back electrode layer 13 at the channel portion 101 b .
- FIG. 6 shows a sectional view of the localized wafer level chip scale package structure in the step S 104 of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure.
- a selective etching process such as a silicon etching process, is performed.
- the region of the channel portion 101 b exposed by the opening 12 c is not covered by any electrode layer. Accordingly, the portion of wafer 100 located in the exposed region of the channel portion is removed during the silicon etching process to form the trench 101 h.
- the back electrode layer 13 can serve as an etch stop layer.
- the channel portion 101 b is etched until the top surface of the back electrode layer 13 is exposed.
- the trench 101 h extends from the active surface 10 to the top surface of the back electrode layer 13 to expose a portion of the back electrode layer 13 after the selective etching process is performed.
- the trench 101 h has a width (W) ranging from 3 to 30 ⁇ m.
- the wafer may be cut by a knife through the opening 12 c , and then be etched by a wet etching to form the trench 101 h.
- FIG. 7A shows a sectional view of the localized wafer level chip scale package structure in the step S 105 of the manufacturing method in FIG. 1
- FIG. 7B shows a top view of the localized wafer level chip scale package structure in the step S 105 of the manufacturing method in FIG. 1 in accordance with another embodiment of the instant disclosure.
- a conductive structure 20 is formed through the trench to connect the back electrode layer 13 .
- the conductive structure has a wall body, and the top of the wall body is disposed at a higher level than the top surface of the patterned protecting layer 12 .
- a first pad 21 in contact with the first electrode 103 of the first semiconductor device 1 and a second pad 22 in contact with the second electrode 104 can be formed respectively through the openings 12 a and 12 b at the same step of forming the conductive structure 20 .
- a first pad 21 ′ in contact with the first electrode 203 of the second semiconductor device 2 and a second pad 22 ′ of the second electrode 204 can be formed respectively through the openings 12 d and 12 e at the same step of forming the conductive structure 20 .
- the conductive structure 20 is located between the first pad 21 of the first semiconductor device 1 and the second pad 22 ′ of the second semiconductor device 2 .
- first pad 21 and the second pad 22 of the first semiconductor device 1 and the first pad 21 ′ and the second pad 22 ′ of the second semiconductor device 2 are formed on the active surface 10 .
- the first electrode 103 , the second electrode 104 , and the back electrode layer 13 of the first semiconductor device 1 are, respectively by the first pad 21 , the second pad 22 , and the conductive structure 20 , electrically connected to the components (not shown) mounted on the printed circuit board (not shown).
- the first and second electrodes 203 and 204 of the second semiconductor device 1 can be, respectively by the first and second pad 21 ′ and 22 ′, electrically connected to the other components mounted on the printed circuit board.
- the conductive structure 20 is formed between the active region 102 of the first semiconductor device 1 and the active region 202 of the second semiconductor device 2 .
- the conductive structure 20 to function as a drain pad, is electrically connected to the back electrode layer 13 shared by the first and second semiconductor devices 1 and 2 .
- the first and second semiconductor devices 1 and 2 can share the same drain pad. That is, the drain regions of the first and second semiconductor devices 1 and 2 are electrically connected to each other through the back electrode layer 13 , and the drain pad, i.e., the conductive structure 20 , of the first and second semiconductor devices 1 and 2 can be exposed on the active surface 10 .
- the conductive structure 20 also can serve as the electrode pad for testing purposes.
- the printed circuit board can provide a heat dissipation effect for the first and second semiconductor devices 1 and 2 by connecting to the conductive structure 20 .
- the conductive structure 20 of the instant embodiment is formed in a localized region of the channel portion 101 b .
- the conductive structure 20 may formed transversely through the length of the channel portion 101 b between the first and second semiconductor devices 1 and 2 .
- step S 106 a cutting process is performed to form a plurality of separated package structures M 1 .
- the cutting process is performed on the cutting portion 101 a of the outer region 101 and the outer region 201 .
- the cutting process is performed by a cutting machine.
- FIGS. 7A, 7B, 8A and 8B in which FIG. 8A shows a sectional view of the package structure after the cutting process in accordance with another embodiment of the instant disclosure, and FIG. 8B shows a top view of the package structure after the cutting process in accordance with another embodiment of the instant disclosure. As shown in FIGS.
- the cutting process includes the step of cutting the wafer 100 along a plurality of cutting lines 4 (only two are shown in FIGS. 7A and 7B ) defined on the outer region 201 and the cutting portion 101 a of the outer region 101 . Because the conductive structure 20 is not formed on the cutting portion 101 a of the outer region 101 , the cutting tool of the cutting machine is used to cut the semiconductor material and a thinner back electrode layer instead of a thicker metal material layer. Accordingly, the attrition rate of the cutting tool can be reduced.
- FIG. 9 shows a flow chat of the manufacturing method of wafer level chip scale package structure in accordance with another embodiment of the instant disclosure.
- a difference between this embodiment and the previous embodiment is that only one semiconductor device, instead of two semiconductor devices, is packaged to form the package structure.
- each of the packaged semiconductor device corresponds to one channel portion.
- the first semiconductor device 1 is taken as an example in the following description to explain the manufacturing method of wafer level chip scale package structure in detail. The same components as those described in aforementioned embodiments are denoted by the same reference numerals.
- FIG. 10A shows a top view of a first semiconductor device
- FIG. 10B shows a sectional view taken along a line H-H in FIG. 10A .
- the active surface 10 of the first semiconductor device 1 has the outer region 101 and the active region 102 defined thereon, in which the outer region 101 of the first semiconductor device 1 is also divided into a cutting portion 101 a and a channel portion 101 b .
- the cutting portion 101 a and the channel portion 101 b located at the same side of the active region 102 of the first semiconductor device 1 , and the cutting portion 101 a is farther from the active region 102 than the channel portion 101 b . That is, the channel portion 101 b is located between the active region 102 and the cutting portion 101 a.
- FIGS. 10B to 10D are respectively corresponding to the steps S 200 to S 204 shown in FIG. 9 . Because the steps S 200 to S 204 are respectively the same as the steps S 100 to S 104 , the descriptions of the common portion are omitted. That is, as shown in FIG. 10D , after the step S 204 , the patterned protecting layer 12 and the back electrode layer 13 are respectively formed on the active surface and the back surface of the first semiconductor device 1 , and the channel portion 101 b has the trench 101 h formed therein.
- a difference between this embodiment and the previous embodiment is the step of forming the conductive structure through the trench 101 h to connect the back electrode layer 13 , and the step of forming the first pad 21 and the second pad 22 . Specifically, after the step S 204 is performed, proceed to the step S 205 .
- FIG. 10E shows a sectional view of the localized wafer level chip scale package structure in step S 205 of the manufacturing method in FIG. 9 in accordance with another embodiment of the instant disclosure.
- step S 205 at least one metal barrier layer 14 is formed.
- the metal barrier layer 14 conformingly covers the inner walls of the trench 101 h , the patterned protecting layer 12 , the first electrode 103 , and the second electrode 104 .
- the metal barrier layer 14 can be formed by evaporation or sputtering deposition and the metal barrier layer 14 can be made of the material selected from the group consisting of titanium, copper, tungsten and the combination thereof.
- the metal barrier layer 14 has a thickness ranging from 50 nm to 300 nm.
- a photoresist layer 15 which has a first opening pattern 15 a , a second opening pattern 15 b , and a third opening pattern 15 c , is formed on the metal barrier layer 14 .
- FIG. 10F shows a sectional view of the localized wafer level chip scale package structure in step S 206 .
- the first opening pattern 15 a , the second opening pattern 15 b and the third opening pattern 15 c of the photoresist layer 15 respectively correspond to the positions of the first electrode 103 , the second electrode 104 and the channel portion 101 b to respectively define the locations and the shapes of the pads which will be formed in the following steps.
- the pads are such as the first pad 21 and the second pad 22 described in the previous embodiment.
- the thickness of the photoresist layer 15 is equal to the height of the pads which will be formed in the following step.
- the cutting portion 101 a of the outer region 101 is completely covered by the photoresist layer 15 .
- the size of the third opening pattern 15 c is greater than the width of the trench 101 h to expose the trench 101 h , and portions of the metal barrier layer 14 formed on the channel portion 101 b of the outer region 101 and formed on the active region 102 .
- the shape and the position of a contact pad for electrically connecting to the back electrode layer 13 can be defined by the third opening pattern 15 c .
- the contact pad may be used to electrically connect the back electrode layer 13 to the component mounted on the printed circuit board in the following processes.
- a metal conductive layer is formed in the first opening pattern 15 a , the second opening pattern 15 b , and the third opening pattern 15 c .
- the metal conductive layer has a laminated structure.
- FIGS. 10G and 10H show sectional views of the localized wafer level chip scale package structure in step S 207 .
- the first opening pattern 15 a , the second opening pattern 15 b , the third opening pattern 15 c , and the trench 101 h are respectively filled with a plurality of first metal structures 16 a - 16 d during the same step S 207 .
- the trench 101 h is filled with the first metal structure 16 d
- the first opening pattern 15 a , the second opening pattern 15 b , and the third opening pattern 15 c are respectively filled with other first metal structures 16 a - 16 c.
- the first metal structure 16 a is in contact with the first electrode 103
- another first metal structure 16 b is in contact with the second electrode 104
- the first metal structure 16 d is formed inside the trench 101 h to be in contact with the back electrode layer 13
- the first metal structure 16 c formed on the region of the active surface 10 which is immediately adjacent to the trench 101 h and extends from the position of the trench 101 h to the active region 102 .
- the first metal structures 16 a - 16 d can be made of copper, nickel or the combination thereof. In another embodiment, the first metal structures 16 a - 16 d may be made of other conductive materials. In the instant embodiment, each of the top portions of the first metal structures 16 a - 16 d is lower than the top of the photoresist layer 15 .
- the first opening pattern 15 a , the second opening pattern 15 b , and the third opening pattern 15 c are respectively filled with a plurality of second metal structures 17 a - 17 c .
- each of the top portions of the second metal structures 17 a - 17 c is disposed at the same level as the top of the photoresist layer 15 .
- the second metal structures 17 a - 17 c can be made of, for example, tin so that the first semiconductor device 1 can be assembled on the printed circuit board.
- the step S 208 is performed, in which the photoresist layer 15 and a portion of the metal barrier layer 14 covered by the photoresist layer 15 are removed.
- FIG. 10I shows a sectional view of the localized wafer level chip scale package structure in step S 208 . After the photoresist layer 15 and the portion of the metal barrier layer 14 are removed, the metal conductive layers respectively formed in the first opening pattern 15 a , the second opening pattern 15 b , and the third opening pattern 15 c are insulated from each other.
- the combination of the first and second metal structures 16 a and 17 a has a function similar to that of the first pad 21 shown in FIG. 7A .
- the combination of the first and second metal structures 16 b and 17 b has a function similar to that of the second pad 22 shown in FIG. 7A .
- the first metal structure 16 d formed inside the trench 101 h is used to connect the back electrode layer 13
- the combination of the first and second metal structures 16 c and 17 c has a function similar to that of the contact pad for electrically connecting to the printed circuit board.
- the conductive structure which is used to contact the back electrode layer 13 through the trench 101 h , has a connecting portion (the first metal structure 16 d ) formed inside the trench 101 h and a contact pad (the combination of the first and second metal structures 16 c and 17 c ) formed on the active surface 10 .
- the connecting portion has a wall body connected between the back electrode layer 13 and the contact pad.
- the ball drop process is taken as an example to describe the instant disclosure.
- the solder bumping process or the Cu pillar bump process can be performed instead of the ball drop process.
- FIG. 10J shows a sectional view of the localized wafer level chip scale package structure in step S 209 .
- a cutting process is performed on the cutting portion 101 a of the outer region 101 to form a plurality of separated package structures M 2 .
- the cutting process includes the step of separating the two immediately adjacent package structures M 2 from each other along a plurality of cutting lines 4 ′ (only two are shown in FIG. 10J ) at the cutting portion 101 a.
- FIG. 10K shows a sectional view of the wafer level chip scale package structure after the cutting process in accordance with another embodiment of the instant disclosure.
- FIG. 10L shows a top view of the wafer level chip scale package structure after the cutting process of the manufacturing method in accordance with another embodiment of the instant disclosure.
- the package structure M 2 has a patterned protecting layer 12 formed on the active surface 10 .
- at least one electrical connection between the package structure M 2 and the component mounted on the printed circuit board can be established through the second metal structures 17 a - 17 c.
- FIG. 11 shows a top view of package structure placed on a lead frame.
- the package structure can be the package structure M 1 shown in FIGS. 8A and 8B or the package structure M 2 shown in FIGS. 10K and 10L .
- the manufacturing method of the wafer level chip scale package structure in accordance with the embodiment of the instant disclosure can further include the following steps:
- the lead frame 3 includes a plurality of die pads 30 , each of which has a surface to be in contact with the package structure M 1 (or M 2 ), as shown in FIG. 11 .
- the individual package structures M 1 (or M 2 ) after the cutting process are fixed on the die pads 30 by a thermal-conductive adhesive, and each of the package structures M 1 (or M 2 ) and each of the die pads 30 are assigned in a one-to-one manner with respect to each other.
- the thermal-conductive adhesive is, for example, an electrical-conductive adhesive, an insulation thermal conductive adhesive or a tin paste.
- each of the package structures M 1 (or M 2 ) can be picked up and respectively placed on the corresponding die pads 30 by a pick and place apparatus.
- a thermal process is performed to cure the thermal conductive adhesive so that each of the package structures M 1 (or M 2 ) is fixed on the corresponding die pad 30 .
- the thermal process can be performed by transferring the lead frame 3 into an oven and raising the temperature of the lead frame 3 . Subsequently, the lead frame 3 is cut so that the plurality of die pads 30 is separated from the lead frame 3 .
- the lead frame 3 has a frame (not labeled) and a plurality of strips (not labeled) for holding each of the die pads 30 .
- the cutting tool can be used to cut the strips along the cutting lines 5 shown in FIG. 11 so that the die pads 30 are separated from the lead frame 3 and the final products (the wafer level scale package structures) are completed.
- the manufacturing methods of a wafer level chip scale package structure are provided in the abovementioned embodiments.
- the channel portion has a trench which is filled with a conductive structure so that the back electrode layer can be electrically connected to other components through the conductive structure.
- the cutting process is performed on the cutting portion subsequent to forming the conductive structure.
- a metal plate having thicker thickness is attached to the back of the wafer to serve as the back electrode.
- the scribing line has a groove formed therein and filled with the metal material so that the back electrode can extend to the active surface to serve as the pad for electrically connecting to the printed circuit board. Therefore, during the following cutting step, it is unavoidable for the cutting tool to cut the metal material and the metal plate.
- the cutting tool of the cutting machine usually has a thinner blade, and the metal plate and the metal material formed in the groove of the scribing line may result in higher attrition rate of the cutting tool.
- the back electrode layer is thinner. Accordingly, only the semiconductor material and a thinner back electrode layer need to be cut by the cutting tool, which can reduce the attrition rate of the cutting tool.
- the package structures are fixed on the die pads by the thermal-conductive adhesive after the cutting process.
- the heat generated due to the operation of the semiconductor device packaged in the package structure can be dissipated through the thermal conductive adhesive and the die pad, which can avoid the performance of the semiconductor device from being impacted due to high temperature.
Abstract
Description
- 1. Field of the Invention
- The instant disclosure relates to a semiconductor package process, in particular, to a manufacturing method of a wafer level chip scale package structure.
- 2. Description of Related Art
- The wafer level chip scale packaging (WLCSP) process is an advanced packaging technology, which allows a large quantity of wafers to be encapsulated in the same process. Additionally, after the wafer level chip scale packaging process, the size of the product is equal to or slightly larger than that of the power semiconductor chip. Accordingly, the technology of encapsulating the power devices by using the WLCSP process has been developed in today's industry.
- The object of the instant disclosure is to provide a manufacturing method of a wafer level chip scale package structure, in which a conductive structure is arranged in the channel portion to connect the back electrode layer of the semiconductor device. In addition, the conductive structure does not extend to a cutting portion, and a cutting process is performed to form a plurality of separated package structures along the cutting portion without the conductive structure.
- In order to achieve the aforementioned objects, according to an embodiment of the instant disclosure, a manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer having a plurality of semiconductor devices is provided. One of the semiconductor devices, a first semiconductor device, has an active surface and a back surface. The active surface includes an active region and an outer region. A first electrode and a second electrode are arranged in the active region, and the outer region is divided into a cutting portion and a channel portion. Subsequently, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first electrode, the second electrode, and the channel portion. Next, a thinning process is performed upon the first semiconductor device from the back surface, and then a back electrode layer is formed on the back surface of the first semiconductor device. Subsequently, an etching process is performed to form a trench exposing the back electrode layer at the channel portion. Thereafter, a conductive structure is formed through the trench to connect the back electrode layer. Subsequently, a cutting process is performed on the cutting portion.
- In the manufacturing method of a wafer level chip scale package structure according to an embodiment of the instant disclosure, the trench formed in the channel portion of the outer region extends from the active surface to the back surface so that the conductive structure formed through the trench can be in contact with the back electrode layer. Accordingly, the back electrode layer can be electrically connected to the other components through the conductive structure exposed on the active surface.
- Additionally, when the cutting process is performed, the wafer is cut along the cutting portion. That is, during the cutting process, the cutting tool of the cutting machine is used to cut the semiconductor material and a thinner back electrode layer instead of a thicker metal material layer. Accordingly, the attrition rate of the cutting tool can be reduced.
- In order to further the understanding regarding the instant disclosure, the following embodiments are provided along with illustrations to facilitate the disclosure of the instant disclosure.
-
FIG. 1 shows a flow chart of the manufacturing method of wafer level chip scale package structure in accordance with an embodiment of the instant disclosure; -
FIG. 2A shows a top view of a wafer; -
FIG. 2B shows an enlarged view of a first and second semiconductor devices shown inFIG. 2A ; -
FIG. 2C shows a sectional view taken along a line I-I inFIG. 2B ; -
FIG. 3 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure; -
FIG. 4 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure; -
FIG. 5 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure; -
FIG. 6 shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure; -
FIG. 7A shows a sectional view of the localized wafer level chip scale package structure in a step of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure; -
FIG. 7B shows a top view of the localized wafer level chip scale package structure in a step of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure; -
FIG. 8A shows a sectional view of the package structure after the cutting process of the manufacturing method in accordance with another embodiment of the instant disclosure; -
FIG. 8B shows a top view of the localized wafer level chip scale package structure in a step of the manufacturing method in accordance with another embodiment of the instant disclosure; -
FIG. 9 shows a flow chart of the manufacturing method of wafer level chip scale package structure in accordance with another embodiment of the instant disclosure; -
FIG. 10A shows a top view of a first semiconductor device; -
FIG. 10B shows a sectional view taken along a line H-H inFIG. 10A ; -
FIG. 10C toFIG. 10J respectively show sectional views of the localized wafer level chip scale package structure in different steps of the manufacturing method inFIG. 9 in accordance with another embodiment of the instant disclosure; -
FIG. 10K shows a sectional view of the wafer level chip scale package structure after a cutting process; -
FIG. 10L shows a top view of the wafer level chip scale package structure after a cutting process; and -
FIG. 11 shows a top view of the package structure placed on a lead frame. - In the following description, numerous specific details of the manufacturing method of wafer level chip scale package structure according to the embodiments of the instant disclosure are set forth in order to provide a thorough understanding of one or more aspects and/or features described herein. It will be apparent, to one skilled in the art, to readily understand the advantages and the effectiveness of the instant disclosure. Furthermore, the instant disclosure can also be implemented or applied by various other specific examples. The details in the following descriptions can also be modified or changed based on different perspectives and applications without departing from the spirit of the instant disclosure. In addition, the drawings as referred to throughout the description of the instant disclosure are for illustrative purpose only, but not drawn according to actual scale, i.e., the actual scale of the related structure is not illustrated. The relative techniques of the instant disclosure will be set forth through the following embodiments, but are not intended to limit the scope of the instant disclosure.
- Please refer to
FIG. 1 .FIG. 1 shows a flow chart of the manufacturing method of wafer level chip scale package structure in accordance with an embodiment of the instant disclosure. - In step S100, a
wafer 100 is provided. The wafer is usually made of Si or other semiconductor materials, such as GaAs. In the embodiment of the instant disclosure, thewafer 100 has a thickness of 350 to 680 μm. Please refer toFIG. 2A , which shows a top view of thewafer 100. In the embodiment of the instant disclosure, the processes of fabricating the devices on thewafer 100 have been completed, and thewafer 100 includes a plurality of semiconductor devices. - In an embodiment of the instant disclosure, the
first semiconductor device 1 and thesecond semiconductor device 2 of the semiconductor devices are taken as an example to clarify the manufacturing method of a wafer level chip scale package structure. Thefirst semiconductor device 1 and thesecond semiconductor device 2, for example, are vertical metal-oxide-semiconductor field effect transistors (MOSFET) or other power devices. In the instant embodiment, the first andsecond semiconductor devices - In the manufacturing method of the wafer level chip scale package structure, the first and
second semiconductor devices - Please refer to
FIG. 2B andFIG. 2C .FIG. 2B shows an enlarged view of the first and second semiconductor devices shown inFIG. 2A , andFIG. 2C shows a sectional view taken along a line I-I inFIG. 2B . Thefirst semiconductor device 1 has anactive surface 10 and aback surface 11 opposite thereto, in which theback surface 11 is a portion of the back of thewafer 100. - The
active surface 10 of thefirst semiconductor device 1 has anouter region 101 and anactive region 102 defined thereon, in which theouter region 101 surrounds theactive region 102, i.e., theouter region 101 is formed on a peripheral region of thefirst semiconductor device 1. Theactive region 102 is defined in a central region of thefirst semiconductor device 1. Afirst electrode 103 and asecond electrode 104 are arranged in theactive region 102. - The
second semiconductor device 2 is immediately adjacent to thefirst semiconductor device 1 and has a structure similar to that of thefirst semiconductor device 1. Specifically, theactive surface 10 ofsecond semiconductor device 2 also has anactive region 202 and anouter region 201, and afirst electrode 203 and asecond electrode 204 are arranged in theactive region 202. In an embodiment of the instant disclosure, thefirst electrodes second electrodes - Additionally, the
outer region 201 of thesecond semiconductor device 2 and theouter region 101 of thefirst semiconductor device 1 mate to form a continuous surface which surrounds theactive region 102 of thefirst semiconductor device 1 and theactive region 202 of thesecond semiconductor device 2. - It is worth nothing that the
outer region 101 of thefirst semiconductor device 1 can be divided into a cuttingportion 101 a and achannel portion 101 b, in which thechannel portion 101 b is located between theactive region 102 of thefirst semiconductor device 1 and theactive region 202 of thesecond semiconductor device 2. - In the instant embodiment, notably, two semiconductor devices sharing the same channel portion are taken as an example. In another embodiment of the instant disclosure, each of semiconductor devices can correspond to one channel portion, or a plurality of the semiconductor device corresponds to one channel portion. Thus, the configuration and the correspondence between the semiconductor device and the channel portion are not intended to limit the instant disclosure.
- Please refer to
FIG. 1 andFIG. 3 . Subsequently, in the step S101, apatterned protecting layer 12 is formed on theactive surface 10. The patternedprotecting layer 12 can be a dielectric layer for protecting theactive region 102 of thefirst semiconductor device 1 and theactive region 202 of thesecond semiconductor device 2 from being contaminated, which may impact on the device characteristics. In addition, the patterned protectinglayer 12 can serve as a mask during the subsequent process steps. - The patterned
protecting layer 12 can be made of phosphosilicate glass, polyimide or nitride. In the instant embodiment, the patterned protectinglayer 12 has a thickness ranging from 1 μm to 10 μm. - Please refer to
FIG. 3 .FIG. 3 illustrates a sectional view of the localized wafer level chip scale package structure in a step S101 of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure. As shown inFIG. 3 , the patterned protectinglayer 12 has a plurality ofopenings 12 a-12 e. In the instant embodiment, theopenings 12 a-12 c respectively expose thefirst electrode 103, thesecond electrode 104 and thechannel portion 101 b of thefirst semiconductor device 1, and theopenings 12 d-12 e respectively expose thefirst electrode 203 and thesecond electrode 204 of thesecond semiconductor device 2. - Specifically, in an embodiment of the instant disclosure, a margin area of the
first electrodes 103 and a margin area of thesecond electrode 104 of thefirst semiconductor device 1 are covered by the patterned protectinglayer 12, but a central area of thefirst electrode 103 and a central area of thesecond electrode 104 are exposed respectively through theopenings layer 12 covers the margin areas of the first andsecond electrodes second semiconductor device 2 but exposes the central areas of the first andsecond electrodes - In addition, in the instant embodiment, the
opening 12 c of the patterned protectinglayer 12 exposes thechannel portion 101 b. Specifically, the patterned protectinglayer 12 completely covers the cuttingportion 101 a of thefirst semiconductor device 1 and theouter region 201 of thesecond semiconductor device 2. - Please refer to
FIG. 1 again. In the step S102, a thinning process is performed upon thefirst semiconductor device 1 and thesecond semiconductor device 2 from theback surface 11. In the instant embodiment, the back surfaces 11 of the first andsecond semiconductor devices second semiconductor devices wafer 100. Accordingly, the same reference numerals are given to the back surfaces of the first andsecond semiconductor devices FIG. 4 .FIG. 4 shows a sectional view of the localized wafer level chip scale package structure in the step S102 of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure. In the embodiment shown inFIG. 4 , taking the first andsecond semiconductor devices - In one embodiment, the thinning process can be a back-grinding process, i.e., the thinning process is performed upon the
first semiconductor device 1 and thesecond semiconductor device 2 from theback surface 11 by using a grinding machine. That is, the thinning process is performed upon the back of thewafer 100 to reduce the thickness of thewafer 100. In addition, before the thinning process is performed, theactive surface 10 having theactive regions second semiconductor devices wafer 100 is reduced to a range between 125 μm to 180 μm. - Please refer to
FIG. 1 , after the thinning process, proceed to step S103, in which aback electrode layer 13 is formed on the back surfaces 11′ of the grinded first andsecond semiconductor devices FIG. 5 .FIG. 5 shows a sectional view of the localized wafer level chip scale package structure in the step S103 of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure. Notably, in the embodiment shown inFIG. 5 , theback electrode layer 13 extends from theback surface 11′ of thefirst semiconductor device 1 to theback surface 11′ of thesecond semiconductor device 2 so that thefirst semiconductor device 1 and thesecond semiconductor device 1 share the sameback electrode layer 13. AlthoughFIG. 5 shows theback electrode layer 13 is formed on the back surfaces 11′ of the first andsecond semiconductor devices back electrode layer 13 is formed on the entire wafer back. - Furthermore, the
back electrode layer 13 can be a conductive layer to serve as a drain electrode of thefirst semiconductor device 1. In one embodiment, theback electrode layer 13 is a metal-stacked layer, such as a Ti/Ni/Ag stacked layer, in which the titanium layer has a thickness of 200 nm, the nickel layer has a thickness of 300 nm, and the silver layer has a thickness of 2000 nm. In another embodiment, theback electrode layer 13 can be a Ti/Cu stacked layer. However, the other material also can be made of theback electrode layer 13, and thus the aforementioned materials and the structure of theback electrode layer 13 are not intended to limit the instant disclosure. - In addition, in step S103, the
back electrode layer 13 can be formed by, but not limit to, chemical vapor deposition (CVD) or physical vapor deposition (PVD), such as evaporation or sputtering deposition. - Please refer to
FIG. 1 . In step S104, an etching process is performed to form atrench 101 h exposing theback electrode layer 13 at thechannel portion 101 b. Please refer toFIG. 6 .FIG. 6 shows a sectional view of the localized wafer level chip scale package structure in the step S104 of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure. In one embodiment, a selective etching process, such as a silicon etching process, is performed. - Notably, unlike the
first electrodes second electrode channel portion 101 b exposed by theopening 12 c is not covered by any electrode layer. Accordingly, the portion ofwafer 100 located in the exposed region of the channel portion is removed during the silicon etching process to form thetrench 101 h. - In addition, in the selective etching process, the
back electrode layer 13 can serve as an etch stop layer. For example, during the silicon etching process, thechannel portion 101 b is etched until the top surface of theback electrode layer 13 is exposed. Thus, thetrench 101 h extends from theactive surface 10 to the top surface of theback electrode layer 13 to expose a portion of theback electrode layer 13 after the selective etching process is performed. In the embodiment of the instant disclosure, thetrench 101 h has a width (W) ranging from 3 to 30 μm. - However, the abovementioned embodiment does not intend to limit the instant disclosure. In another embodiment, the wafer may be cut by a knife through the
opening 12 c, and then be etched by a wet etching to form thetrench 101 h. - Please refer to
FIG. 1 and together withFIGS. 7A and 7B .FIG. 7A shows a sectional view of the localized wafer level chip scale package structure in the step S105 of the manufacturing method inFIG. 1 , andFIG. 7B shows a top view of the localized wafer level chip scale package structure in the step S105 of the manufacturing method inFIG. 1 in accordance with another embodiment of the instant disclosure. - Subsequently, in step S105 illustrated in
FIG. 1 , aconductive structure 20 is formed through the trench to connect theback electrode layer 13. As shown inFIGS. 7A and 7B , the conductive structure has a wall body, and the top of the wall body is disposed at a higher level than the top surface of the patterned protectinglayer 12. - In addition, a
first pad 21 in contact with thefirst electrode 103 of thefirst semiconductor device 1 and asecond pad 22 in contact with thesecond electrode 104 can be formed respectively through theopenings conductive structure 20. Similarly, afirst pad 21′ in contact with thefirst electrode 203 of thesecond semiconductor device 2 and asecond pad 22′ of thesecond electrode 204 can be formed respectively through theopenings conductive structure 20. In the instant embodiment of the instant disclosure, theconductive structure 20 is located between thefirst pad 21 of thefirst semiconductor device 1 and thesecond pad 22′ of thesecond semiconductor device 2. - It is worth nothing that the
first pad 21 and thesecond pad 22 of thefirst semiconductor device 1 and thefirst pad 21′ and thesecond pad 22′ of thesecond semiconductor device 2 are formed on theactive surface 10. When the first andsecond semiconductor devices first electrode 103, thesecond electrode 104, and theback electrode layer 13 of thefirst semiconductor device 1 are, respectively by thefirst pad 21, thesecond pad 22, and theconductive structure 20, electrically connected to the components (not shown) mounted on the printed circuit board (not shown). Similarly, the first andsecond electrodes second semiconductor device 1 can be, respectively by the first andsecond pad 21′ and 22′, electrically connected to the other components mounted on the printed circuit board. - Notably, in the instant embodiment, the
conductive structure 20 is formed between theactive region 102 of thefirst semiconductor device 1 and theactive region 202 of thesecond semiconductor device 2. In addition, theconductive structure 20, to function as a drain pad, is electrically connected to theback electrode layer 13 shared by the first andsecond semiconductor devices second semiconductor devices second semiconductor devices back electrode layer 13, and the drain pad, i.e., theconductive structure 20, of the first andsecond semiconductor devices active surface 10. In addition, theconductive structure 20 also can serve as the electrode pad for testing purposes. Furthermore, after the first andsecond semiconductor devices conductive structure 20, the printed circuit board can provide a heat dissipation effect for the first andsecond semiconductor devices conductive structure 20. - In addition, as illustrated in
FIG. 7B , theconductive structure 20 of the instant embodiment is formed in a localized region of thechannel portion 101 b. In another embodiment, theconductive structure 20 may formed transversely through the length of thechannel portion 101 b between the first andsecond semiconductor devices - Please refer to
FIG. 1 . Subsequently, in step S106, a cutting process is performed to form a plurality of separated package structures M1. In the instant embodiment, the cutting process is performed on the cuttingportion 101 a of theouter region 101 and theouter region 201. In one embodiment, the cutting process is performed by a cutting machine. Please refer toFIGS. 7A, 7B, 8A and 8B , in whichFIG. 8A shows a sectional view of the package structure after the cutting process in accordance with another embodiment of the instant disclosure, andFIG. 8B shows a top view of the package structure after the cutting process in accordance with another embodiment of the instant disclosure. As shown inFIGS. 7A and 7B , the cutting process includes the step of cutting thewafer 100 along a plurality of cutting lines 4 (only two are shown inFIGS. 7A and 7B ) defined on theouter region 201 and the cuttingportion 101 a of theouter region 101. Because theconductive structure 20 is not formed on the cuttingportion 101 a of theouter region 101, the cutting tool of the cutting machine is used to cut the semiconductor material and a thinner back electrode layer instead of a thicker metal material layer. Accordingly, the attrition rate of the cutting tool can be reduced. - Please refer to
FIG. 9 .FIG. 9 shows a flow chat of the manufacturing method of wafer level chip scale package structure in accordance with another embodiment of the instant disclosure. - A difference between this embodiment and the previous embodiment is that only one semiconductor device, instead of two semiconductor devices, is packaged to form the package structure. In addition, in the instant embodiment, each of the packaged semiconductor device corresponds to one channel portion. The
first semiconductor device 1 is taken as an example in the following description to explain the manufacturing method of wafer level chip scale package structure in detail. The same components as those described in aforementioned embodiments are denoted by the same reference numerals. - Please refer to
FIGS. 9, 10A and 10B .FIG. 10A shows a top view of a first semiconductor device,FIG. 10B shows a sectional view taken along a line H-H inFIG. 10A . - In the instant embodiment, the
active surface 10 of thefirst semiconductor device 1 has theouter region 101 and theactive region 102 defined thereon, in which theouter region 101 of thefirst semiconductor device 1 is also divided into a cuttingportion 101 a and achannel portion 101 b. Notably, in the instant embodiment, the cuttingportion 101 a and thechannel portion 101 b located at the same side of theactive region 102 of thefirst semiconductor device 1, and the cuttingportion 101 a is farther from theactive region 102 than thechannel portion 101 b. That is, thechannel portion 101 b is located between theactive region 102 and the cuttingportion 101 a. - Additionally,
FIGS. 10B to 10D are respectively corresponding to the steps S200 to S204 shown inFIG. 9 . Because the steps S200 to S204 are respectively the same as the steps S100 to S104, the descriptions of the common portion are omitted. That is, as shown inFIG. 10D , after the step S204, the patterned protectinglayer 12 and theback electrode layer 13 are respectively formed on the active surface and the back surface of thefirst semiconductor device 1, and thechannel portion 101 b has thetrench 101 h formed therein. - A difference between this embodiment and the previous embodiment is the step of forming the conductive structure through the
trench 101 h to connect theback electrode layer 13, and the step of forming thefirst pad 21 and thesecond pad 22. Specifically, after the step S204 is performed, proceed to the step S205. - Please refer to
FIG. 10E .FIG. 10E shows a sectional view of the localized wafer level chip scale package structure in step S205 of the manufacturing method inFIG. 9 in accordance with another embodiment of the instant disclosure. In step S205, at least onemetal barrier layer 14 is formed. - As shown in
FIG. 10E , themetal barrier layer 14 conformingly covers the inner walls of thetrench 101 h, the patterned protectinglayer 12, thefirst electrode 103, and thesecond electrode 104. In the instant embodiment, themetal barrier layer 14 can be formed by evaporation or sputtering deposition and themetal barrier layer 14 can be made of the material selected from the group consisting of titanium, copper, tungsten and the combination thereof. In addition, themetal barrier layer 14 has a thickness ranging from 50 nm to 300 nm. - Please refer to
FIGS. 9 and 10F . In step S206, aphotoresist layer 15, which has afirst opening pattern 15 a, asecond opening pattern 15 b, and athird opening pattern 15 c, is formed on themetal barrier layer 14. - Please refer to
FIG. 10F .FIG. 10F shows a sectional view of the localized wafer level chip scale package structure in step S206. As illustrated inFIG. 10F , thefirst opening pattern 15 a, thesecond opening pattern 15 b and thethird opening pattern 15 c of thephotoresist layer 15 respectively correspond to the positions of thefirst electrode 103, thesecond electrode 104 and thechannel portion 101 b to respectively define the locations and the shapes of the pads which will be formed in the following steps. In the instant embodiment, the pads are such as thefirst pad 21 and thesecond pad 22 described in the previous embodiment. In addition, in the instant embodiment, the thickness of thephotoresist layer 15 is equal to the height of the pads which will be formed in the following step. - In one embodiment, the cutting
portion 101 a of theouter region 101 is completely covered by thephotoresist layer 15. In addition, the size of thethird opening pattern 15 c is greater than the width of thetrench 101 h to expose thetrench 101 h, and portions of themetal barrier layer 14 formed on thechannel portion 101 b of theouter region 101 and formed on theactive region 102. Notably, the shape and the position of a contact pad for electrically connecting to theback electrode layer 13 can be defined by thethird opening pattern 15 c. The contact pad may be used to electrically connect theback electrode layer 13 to the component mounted on the printed circuit board in the following processes. - Please refer to
FIG. 9 . In step S207, a metal conductive layer is formed in thefirst opening pattern 15 a, thesecond opening pattern 15 b, and thethird opening pattern 15 c. In the instant embodiment, the metal conductive layer has a laminated structure. - Please refer to
FIGS. 10G and 10H .FIGS. 10G and 10H show sectional views of the localized wafer level chip scale package structure in step S207. As shown inFIG. 10G , thefirst opening pattern 15 a, thesecond opening pattern 15 b, thethird opening pattern 15 c, and thetrench 101 h are respectively filled with a plurality of first metal structures 16 a-16 d during the same step S207. Specifically, thetrench 101 h is filled with thefirst metal structure 16 d, thereafter, thefirst opening pattern 15 a, thesecond opening pattern 15 b, and thethird opening pattern 15 c are respectively filled with other first metal structures 16 a-16 c. - That is, the
first metal structure 16 a is in contact with thefirst electrode 103, while anotherfirst metal structure 16 b is in contact with thesecond electrode 104. In addition, thefirst metal structure 16 d is formed inside thetrench 101 h to be in contact with theback electrode layer 13, and thefirst metal structure 16 c formed on the region of theactive surface 10 which is immediately adjacent to thetrench 101 h and extends from the position of thetrench 101 h to theactive region 102. - The first metal structures 16 a-16 d can be made of copper, nickel or the combination thereof. In another embodiment, the first metal structures 16 a-16 d may be made of other conductive materials. In the instant embodiment, each of the top portions of the first metal structures 16 a-16 d is lower than the top of the
photoresist layer 15. - Subsequently, as shown in
FIG. 10H , thefirst opening pattern 15 a, thesecond opening pattern 15 b, and thethird opening pattern 15 c are respectively filled with a plurality of second metal structures 17 a-17 c. In the instant embodiment, each of the top portions of the second metal structures 17 a-17 c is disposed at the same level as the top of thephotoresist layer 15. In addition, the second metal structures 17 a-17 c can be made of, for example, tin so that thefirst semiconductor device 1 can be assembled on the printed circuit board. - Please refer to
FIG. 9 . Subsequently, the step S208 is performed, in which thephotoresist layer 15 and a portion of themetal barrier layer 14 covered by thephotoresist layer 15 are removed. Please refer toFIG. 10I .FIG. 10I shows a sectional view of the localized wafer level chip scale package structure in step S208. After thephotoresist layer 15 and the portion of themetal barrier layer 14 are removed, the metal conductive layers respectively formed in thefirst opening pattern 15 a, thesecond opening pattern 15 b, and thethird opening pattern 15 c are insulated from each other. - Please refer to
FIG. 10I . The combination of the first andsecond metal structures first pad 21 shown inFIG. 7A . The combination of the first andsecond metal structures second pad 22 shown inFIG. 7A . Additionally, thefirst metal structure 16 d formed inside thetrench 101 h is used to connect theback electrode layer 13, and the combination of the first andsecond metal structures back electrode layer 13 through thetrench 101 h, has a connecting portion (thefirst metal structure 16 d) formed inside thetrench 101 h and a contact pad (the combination of the first andsecond metal structures active surface 10. The connecting portion has a wall body connected between theback electrode layer 13 and the contact pad. - In the instant embodiment, the ball drop process is taken as an example to describe the instant disclosure. However, in another embodiment, after the step S104 (or S204), the solder bumping process or the Cu pillar bump process can be performed instead of the ball drop process.
- Subsequently, please refer to
FIGS. 9 and 10J .FIG. 10J shows a sectional view of the localized wafer level chip scale package structure in step S209. Similar to the step S106 described in the previous embodiment, in step S209, a cutting process is performed on the cuttingportion 101 a of theouter region 101 to form a plurality of separated package structures M2. As shown inFIG. 10J , in the instant embodiment, the cutting process includes the step of separating the two immediately adjacent package structures M2 from each other along a plurality of cuttinglines 4′ (only two are shown inFIG. 10J ) at the cuttingportion 101 a. - Please refer to
FIGS. 10K and 10L .FIG. 10K shows a sectional view of the wafer level chip scale package structure after the cutting process in accordance with another embodiment of the instant disclosure.FIG. 10L shows a top view of the wafer level chip scale package structure after the cutting process of the manufacturing method in accordance with another embodiment of the instant disclosure. After the manufacturing method shown inFIG. 9 is completed, the package structure M2 has a patternedprotecting layer 12 formed on theactive surface 10. In addition, at least one electrical connection between the package structure M2 and the component mounted on the printed circuit board can be established through the second metal structures 17 a-17 c. - Please refer to
FIG. 11 .FIG. 11 shows a top view of package structure placed on a lead frame. The package structure can be the package structure M1 shown inFIGS. 8A and 8B or the package structure M2 shown inFIGS. 10K and 10L . In addition, the manufacturing method of the wafer level chip scale package structure in accordance with the embodiment of the instant disclosure can further include the following steps: - First, a lead frame 3 is provided. Specifically, the lead frame includes a plurality of
die pads 30, each of which has a surface to be in contact with the package structure M1 (or M2), as shown inFIG. 11 . - Subsequently, the individual package structures M1 (or M2) after the cutting process are fixed on the
die pads 30 by a thermal-conductive adhesive, and each of the package structures M1 (or M2) and each of thedie pads 30 are assigned in a one-to-one manner with respect to each other. Specifically, before the package structures M1 (or M2) are placed on thedie pads 30, the surface of each of diepads 30 is printed with the thermal-conductive adhesive (not shown). The thermal-conductive adhesive is, for example, an electrical-conductive adhesive, an insulation thermal conductive adhesive or a tin paste. Subsequently, each of the package structures M1 (or M2) can be picked up and respectively placed on thecorresponding die pads 30 by a pick and place apparatus. - Thereafter, a thermal process is performed to cure the thermal conductive adhesive so that each of the package structures M1 (or M2) is fixed on the
corresponding die pad 30. The thermal process can be performed by transferring the lead frame 3 into an oven and raising the temperature of the lead frame 3. Subsequently, the lead frame 3 is cut so that the plurality ofdie pads 30 is separated from the lead frame 3. - In the instant embodiment shown in
FIG. 11 , the lead frame 3 has a frame (not labeled) and a plurality of strips (not labeled) for holding each of thedie pads 30. When the lead frame 3 is cut, the cutting tool can be used to cut the strips along thecutting lines 5 shown inFIG. 11 so that thedie pads 30 are separated from the lead frame 3 and the final products (the wafer level scale package structures) are completed. - In summary, the manufacturing methods of a wafer level chip scale package structure are provided in the abovementioned embodiments. In the manufacturing method, the channel portion has a trench which is filled with a conductive structure so that the back electrode layer can be electrically connected to other components through the conductive structure. Furthermore, the cutting process is performed on the cutting portion subsequent to forming the conductive structure.
- Notably, during some of the wafer level chip scale package processes, a metal plate having thicker thickness is attached to the back of the wafer to serve as the back electrode. In addition, the scribing line has a groove formed therein and filled with the metal material so that the back electrode can extend to the active surface to serve as the pad for electrically connecting to the printed circuit board. Therefore, during the following cutting step, it is unavoidable for the cutting tool to cut the metal material and the metal plate. However, the cutting tool of the cutting machine usually has a thinner blade, and the metal plate and the metal material formed in the groove of the scribing line may result in higher attrition rate of the cutting tool.
- In contrast, in the embodiments of the instant disclosure, no metal material is formed in the cutting portion, and the back electrode layer is thinner. Accordingly, only the semiconductor material and a thinner back electrode layer need to be cut by the cutting tool, which can reduce the attrition rate of the cutting tool.
- Furthermore, the package structures are fixed on the die pads by the thermal-conductive adhesive after the cutting process. As such, the heat generated due to the operation of the semiconductor device packaged in the package structure can be dissipated through the thermal conductive adhesive and the die pad, which can avoid the performance of the semiconductor device from being impacted due to high temperature.
- The descriptions illustrated supra set forth simply the preferred embodiments of the instant disclosure; however, the characteristics of the instant disclosure are by no means restricted thereto. All changes, alterations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the instant disclosure delineated by the following claims.
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CN109155281A (en) * | 2018-08-03 | 2019-01-04 | 深圳市为通博科技有限责任公司 | The method of chip package |
US10446510B2 (en) * | 2017-02-22 | 2019-10-15 | Sumitomo Electric Device Innovations, Inc. | Process of forming semiconductor apparatus mounting on substrate |
US20220223548A1 (en) * | 2021-01-14 | 2022-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Device and Method |
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CN110660765B (en) * | 2019-09-23 | 2021-06-25 | 上海朕芯微电子科技有限公司 | CSP (chip scale package) packaging structure and CSP packaging method for triode separator |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US8263492B2 (en) * | 2009-04-29 | 2012-09-11 | International Business Machines Corporation | Through substrate vias |
US8951839B2 (en) * | 2010-03-15 | 2015-02-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP |
TW201222759A (en) * | 2010-11-25 | 2012-06-01 | Ind Tech Res Inst | Semiconductor structure and process thereof |
US8642385B2 (en) * | 2011-08-09 | 2014-02-04 | Alpha & Omega Semiconductor, Inc. | Wafer level package structure and the fabrication method thereof |
US9620430B2 (en) * | 2012-01-23 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sawing underfill in packaging processes |
US8963336B2 (en) * | 2012-08-03 | 2015-02-24 | Samsung Electronics Co., Ltd. | Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same |
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US9685354B2 (en) * | 2014-04-03 | 2017-06-20 | Xintec Inc. | Separation apparatus and a method for separating a cap layer from a chip package by means of the separation apparatus |
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US10446510B2 (en) * | 2017-02-22 | 2019-10-15 | Sumitomo Electric Device Innovations, Inc. | Process of forming semiconductor apparatus mounting on substrate |
CN109155281A (en) * | 2018-08-03 | 2019-01-04 | 深圳市为通博科技有限责任公司 | The method of chip package |
US20220223548A1 (en) * | 2021-01-14 | 2022-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Device and Method |
US11855017B2 (en) * | 2021-01-14 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
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