US20160104639A1 - Surface treatment to improve cctba based cvd co nucleation on dielectric substrate - Google Patents

Surface treatment to improve cctba based cvd co nucleation on dielectric substrate Download PDF

Info

Publication number
US20160104639A1
US20160104639A1 US14/975,945 US201514975945A US2016104639A1 US 20160104639 A1 US20160104639 A1 US 20160104639A1 US 201514975945 A US201514975945 A US 201514975945A US 2016104639 A1 US2016104639 A1 US 2016104639A1
Authority
US
United States
Prior art keywords
substrate
cobalt
cvd
layer
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/975,945
Inventor
Bhushan N. ZOPE
Avgerinos V. Gelatos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to US14/975,945 priority Critical patent/US20160104639A1/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GELATOS, AVGERINOS V., ZOPE, Bhushan N.
Publication of US20160104639A1 publication Critical patent/US20160104639A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0245Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0272Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/0281Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the invention generally relate to the field of semiconductor manufacturing processes, more particularly, to methods for forming a contact metal layer on dielectric substrate.
  • Semiconductor processing involves a number of different chemical and physical processes whereby minute integrated circuits are created on a substrate.
  • Layers of materials which make up the integrated circuit are created by chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxial growth, and the like. Some of the layers of material are patterned using photoresist masks and wet or dry etching techniques.
  • the substrate utilized to form integrated circuits may be silicon, gallium arsenide, indium phosphide, glass, or other appropriate material.
  • CVD cobalt may be used as metal deposition technique for application as metal interconnects.
  • a cobalt thin film is grown on dielectric material such as silicon dioxide or low-k dielectric.
  • dielectric material such as silicon dioxide or low-k dielectric.
  • organometallic precursors negates the need of a barrier layer, which is used in alternate metal CVD processes utilizing halide based chemistry.
  • incubation (growth) of the cobalt layer on the dielectric material is poor and results in non-continuous growth.
  • a titanium nitride (TiN) nucleation layer may be formed on the dielectric material prior to CVD deposition of cobalt layer.
  • titanium nitride will not deposit on the dielectric material at less than 300° C.
  • the cobalt layer is deposited at a temperature between 100° C. and 250° C.
  • two processing chambers may be utilized for the depositions of the nucleation layer and the cobalt layer.
  • Embodiments of the present invention generally relate to a method of forming a cobalt layer on a dielectric material without incubation delay.
  • the surface of the dielectric material Prior to depositing the cobalt layer using CVD, the surface of the dielectric material is pretreated at a temperature between 100° C. and 250° C. Since the subsequent CVD cobalt process is also performed at between 100° C. and 250° C., only one processing chamber is used for the forming of the cobalt layer.
  • a method for forming a metal interconnect includes placing a substrate into a processing chamber, pretreating a surface of the substrate at a temperature between 100° C. and 250° C., wherein a monolayer of molecules is formed on the surface of the substrate, and depositing a metal layer on the pretreated surface.
  • a transfer chamber connecting a plurality of processing chambers has a transfer chamber, at least two cobalt chemical vapor deposition chambers, at least one physical vapor deposition chamber, and at least one plasma enhanced chemical vapor deposition chamber.
  • FIG. 1 illustrates a cross sectional view of a substrate having a metal interconnect formed thereon according to one embodiment of the invention.
  • FIG. 2 illustrates a method for depositing a cobalt layer according to one embodiment of the invention.
  • FIG. 3 is a chart showing a relationship between CVD cobalt thickness and deposition time.
  • FIG. 4 is a schematic cross sectional view of a processing chamber which may be adapted to perform the processes disclosed herein.
  • FIG. 5 is a schematic top view of a multi-chamber processing system which may be adapted to perform the processes disclosed herein.
  • Embodiments of the present invention generally relate to a method of forming a cobalt layer on a dielectric material without incubation delay.
  • the surface of the dielectric material Prior to depositing the cobalt layer using CVD, the surface of the dielectric material is pretreated at a temperature between 100° C. and 250° C. Since the subsequent CVD cobalt process is also performed at between 100° C. and 250° C., only one processing chamber is used for the forming of the cobalt layer.
  • a device 100 may include a metal interconnect structure 101 , which may generally comprise a substrate 102 , a dielectric layer 104 and a metal layer 106 .
  • the metal interconnect structure 101 may be disposed within or atop the substrate 102 .
  • the metal interconnect structure 101 may be formed within a feature 108 formed, for example, in the dielectric layer 104 disposed over the substrate 102 .
  • the substrate 102 may be any substrate capable of having material deposited thereon, such as a silicon substrate, for example crystalline silicon (e.g., Si ⁇ 100>or Si ⁇ 111>), silicon oxide, strained silicon, doped or undoped polysilicon, or the like, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, a solar array, solar panel, a light emitting diode (LED) substrate, a semiconductor wafer, or the like.
  • a silicon substrate for example crystalline silicon (e.g., Si ⁇ 100>or Si ⁇ 111>), silicon oxide, strained silicon, doped or undoped polysilicon, or the like, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi-substrate, a silicon-on-
  • the substrate 102 may include a p-type or n-type region defined therein (not shown).
  • the substrate 102 may include other structures or features 108 at least partially formed therein.
  • the feature 108 e.g., a via, a trench, a dual damascene feature, high aspect ratio feature, or the like
  • the dielectric layer 104 may be formed within any suitable process or processes, such as an etch process.
  • the dielectric layer 104 may contain silicon dioxide or a low-k dielectric material, such as a silicon carbide oxide material, or a carbon doped silicon oxide material.
  • the dielectric layer 104 may be formed via any process suitable to provide the dielectric layer 104 having a desired thickness. Suitable processes may include CVD, PVD, atomic layer deposition (ALD), and plasma enhanced CVD (PECVD).
  • the metal layer 106 is a cobalt layer and is deposited using CVD.
  • Organometallic precursors may be used for the CVD process, and one example of the organometallic precursors is dicobalt hexacarbonyl tertbutyl acetylene (CCTBA).
  • CCTBA based CVD cobalt is deposited at a temperature from about 100° C. to about 250° C.
  • the processing temperature may be in the range of 125° C.-175° C.
  • a nucleation layer such as a TiN layer may be first deposited on the dielectric layer 104 and the cobalt layer 106 is deposited on the TiN layer.
  • TiN does not deposit on the dielectric layer 104 at a temperature that is less than 300° C.
  • the processing temperature of TiN deposition is much higher than the processing temperature of cobalt deposition, thus two processing chambers are used for any process using cobalt as a metal interconnect material, causing loss of productivity by decreasing system throughput.
  • Depositing the cobalt layer 106 without the TiN nucleation layer may cause incubation delay. Incubation delay, or growth delay, means the growth rate of the cobalt layer 106 is very slow at the beginning of the deposition process. To eliminate any incubation delay, the surface of the dielectric layer 104 is pre-treated before the cobalt layer 106 is deposited on the dielectric layer 104 .
  • FIG. 2 illustrates a method 200 for depositing a cobalt layer without any incubation delay according to one embodiment of the invention.
  • the surface of the dielectric layer 104 is pretreated prior to the deposition of the cobalt layer 106 into the feature 108 .
  • the pretreatment includes exposing the dielectric layer 104 to a precursor gas containing titanium at process temperature used during CVD cobalt deposition.
  • the precursor gas may be tetrakis(dimethylamino)titanium (TDMAT), titanium tetrachloride (TiCl 4 ) or the like.
  • TDMAT tetrakis(dimethylamino)titanium
  • TiCl 4 titanium tetrachloride
  • the surface of the dielectric layer 104 is exposed to the precursor gas at the same temperature as the CVD cobalt deposition temperature, such as from about 100° C.
  • the pretreatment and the CVD cobalt deposition have the same process temperature, ranging from about 125° C. to about 175° C. At these temperature ranges, no TiN layer is deposited; instead a monolayer of the precursor molecules is deposited on the surface of the dielectric layer 104 , including the surface of dielectric layer 104 inside the feature 108 .
  • the surface of the dielectric layer 104 is pretreated with an ammonia or nitrogen based plasma.
  • the plasma pretreatment is also performed at process temperature used during CVD cobalt deposition.
  • a monolayer of nitrogen molecules is formed on the dielectric layer 104 .
  • both TDMAT exposure and ammonia or nitrogen plasma treatment are utilized. The TDMAT exposure may be performed before the ammonia or nitrogen plasma treatment, or performed after the ammonia or nitrogen plasma treatment.
  • the cobalt layer 106 is deposited on the dielectric layer 104 , including on the dielectric layer 104 inside the feature 108 .
  • the cobalt layer 106 is deposited using a CVD process and the CVD process is performed in the chamber in which the pretreatment process is performed.
  • the precursor used in the CVD process may be CCTBA and the cobalt layer 106 may have a thickness of less than 10 nanometers.
  • Pretreating the dielectric surface 104 eliminated any incubation delay during CVD cobalt deposition.
  • the cobalt layer 106 deposited on the pretreated dielectric surface has lower resistivity compared to cobalt layers formed on untreated dielectric surface.
  • FIG. 3 is a chart 300 showing a relationship between CVD cobalt layer thickness and deposition time for no pretreatment, ammonia plasma treatment and TDMAT exposure treatment. As shown in chart 300 , both ammonia plasma and TDMAT exposure treatments result in a thicker cobalt layer at early stage of the deposition process.
  • FIG. 4 is a schematic cross sectional view of a processing chamber 400 which may be adapted to perform the processes disclosed herein.
  • the processing chamber 400 may be a CVD chamber that is adapted to perform the pretreatment step 202 and the CVD cobalt deposition step 204 , as described in FIG. 2 .
  • the chamber 400 comprises a chamber body 402 having sidewalls 404 and a bottom 406 .
  • a liner such as a quartz liner, may line the sidewalls 404 and the bottom 406 of the chamber body 402 to provide thermal and/or electrical insulation.
  • An opening 408 in the chamber 400 provides access for a robot (not shown) to deliver and retrieve substrates 410 to the chamber 100 .
  • a substrate support 412 supports the substrate 410 in the chamber 400 on a substrate receiving surface 411 .
  • the substrate support 412 is mounted to a lift motor 414 to raise and lower the substrate support 412 and a substrate 410 disposed thereon.
  • a lift plate 416 connected to a lift motor 418 is mounted in the chamber and raises and lowers pins 420 movably disposed through the substrate support 412 .
  • the pins 420 raise and lower the substrate 410 over the surface of the substrate support 412 .
  • the substrate support 412 may be heated to heat the substrate 410 disposed thereon.
  • the substrate support 412 may have an embedded heating element 422 to resistively heat the substrate support 412 by applying an electric current from a power supply (not shown).
  • a temperature sensor 426 such as a thermocouple, may be embedded in the substrate support 412 to monitor the temperature of the substrate support 412 .
  • a measured temperature may be used in a feedback loop to control electric current applied to the heating element 422 from a power supply (not shown), such that the substrate temperature can be maintained or controlled at a desired temperature or within a desired temperature range.
  • the substrate 410 may be heated using radiant heat, such as by lamps.
  • a gas distribution system 430 is disposed at an upper portion of the chamber body 402 to provide two gas flows distributed in a substantially uniform manner over a substrate 410 disposed on the substrate receiving surface 411 in which the two gas flows are delivered in separate discrete paths through the gas distribution system 430 .
  • One gas flow path may be used for the pretreatment step 202 while the other may be used for the CVD cobalt deposition step 204 .
  • the gas distribution system 430 comprises a gas box 432 , a blocker plate 460 positioned below the gas box 432 , and a showerhead 470 positioned below the blocker plate 460 .
  • the gas distribution system 430 provides two gas flows through two discrete paths to a processing region 428 defined between the showerhead 470 and the substrate support 412 .
  • the gas box 432 as used herein is defined as a gas manifold coupling gas sources to the chamber.
  • the gas box 432 comprises a first gas channel 437 and a second gas channel 443 providing two separate paths for the flow of gases through the gas box 432 .
  • the first gas channel 437 comprises a first gas input 434 and a first gas outlet 438 .
  • the first gas input is adapted to receive a first gas from a first gas source 435 through valve 436 .
  • the first gas outlet 438 is adapted to deliver the first gas to the top of the blocker plate 460 .
  • the second gas channel 443 of the gas box 432 comprises a second gas input 440 and a second gas outlet 444 .
  • the second gas input 440 is adapted to receive a second gas from a second gas source 441 through valve 442 .
  • the second gas outlet 444 is adapted to deliver the second gas to top of the showerhead 470 .
  • the term “gas” as used herein is intended to mean a single gas or a gas mixture.
  • the valves 436 , 442 control delivery of the first gas and the second gas into the first gas input 434 and the second gas input 440 respectively.
  • Gas sources 435 , 441 may be adapted to store a gas or liquid precursor in a cooled, heated, or maintained at ambient environment.
  • the gas lines fluidly coupling the gas sources 435 , 441 to the gas inputs 434 , 440 may also be heated, cooled, or at ambient temperature.
  • FIG. 5 is a schematic top view of a multi-chamber processing system 500 which may be adapted to perform the processes disclosed herein.
  • suitable multi-chamber processing systems include the ENDURA® and PRODUCER® processing systems, commercially available from Applied Materials, Inc. of Santa Clara, Calif.
  • the system 500 generally includes load lock chambers 502 , 504 , for the transfer of substrates (such as substrates 102 described above) into and out from the system 500 . Since the system 500 is operated under vacuum, the load lock chambers 502 , 504 may be “pumped down” to maintain to facilitate entry and egress of substrates to the system.
  • a first robot 510 disposed in a first transfer chamber 520 may transfer the substrate between the load lock chambers 502 , 504 , processing chambers 512 , 514 , passthrough chambers 522 , 524 , and other processing chambers 516 , 518 .
  • Each processing chamber 512 , 514 , 516 , 518 may be outfitted to perform a number of substrate processing operations such as ALD, CVD, PVD, etch, preclean, degas, orientation and other substrate processes.
  • the passthrough chambers 522 , 524 typically are used for cool down of the substrates.
  • the passthrough chambers 522 , 524 are connected to a second transfer chamber 540 .
  • the second transfer chamber 540 is connected to a plurality of processing chambers.
  • processing chambers 532 , 534 , 536 and 538 are connected to the second transfer chamber 540 .
  • An optional anneal chamber (not shown) may be connected to the second transfer chamber 540 .
  • a second robot 530 disposed in the second transfer chamber 540 may transfer the substrate between processing chambers 532 , 534 , 536 , 538 and the passthrough chambers 522 , 524 .
  • the processing chambers 532 , 534 , 536 , 538 include essentially at least two CVD cobalt deposition chambers, at least one PVD chamber, and at least one plasma enhanced CVD chamber.
  • the at least two CVD cobalt deposition chambers may be the processing chamber 400 described above.
  • processing chambers 534 , 536 are the processing chambers that are adapted to perform both the pretreatment process and the CVD cobalt deposition, such as the processing chamber 400 .
  • the processing chamber 532 is a PVD chamber used for PVD cobalt deposition.
  • the processing chamber 538 is a plasma processing chamber such as a plasma enhanced CVD chamber used for contact applications.
  • a single processing chamber is utilized to perform both pretreatment of the dielectric layer and CVD cobalt deposition.
  • the pretreatment of the dielectric layer includes exposing the dielectric layer to a TDMAT precursor gas or to an ammonia plasma or a nitrogen plasma.
  • the processing temperature for the pretreatment and the CVD cobalt deposition may be the same.
  • Pretreating the dielectric layer prior to CVD cobalt deposition eliminates incubation delay.
  • throughput is increased since two CVD cobalt deposition chambers may be included in a processing system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Embodiments of the present invention generally relate to a method of forming a cobalt layer on a dielectric material without incubation delay. Prior to depositing the cobalt layer using CVD, the surface of the dielectric material is pretreated at a temperature between 100° C. and 250° C. Since the subsequent CVD cobalt process is also performed at between 100° C. and 250° C., one processing chamber is used for pretreating the dielectric material and forming of the cobalt layer. The combination of processing steps enables use of two processing chambers to deposit cobalt.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of co-pending U.S. patent application Ser. No. 14/026,147, filed on Sep. 13, 2013, which herein is incorporated by reference.
  • BACKGROUND
  • 1. Field
  • Embodiments of the invention generally relate to the field of semiconductor manufacturing processes, more particularly, to methods for forming a contact metal layer on dielectric substrate.
  • 2. Description of the Related Art
  • Semiconductor processing involves a number of different chemical and physical processes whereby minute integrated circuits are created on a substrate. Layers of materials which make up the integrated circuit are created by chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxial growth, and the like. Some of the layers of material are patterned using photoresist masks and wet or dry etching techniques. The substrate utilized to form integrated circuits may be silicon, gallium arsenide, indium phosphide, glass, or other appropriate material.
  • As feature sizes have become smaller, the cross section dimensions of logic metal contacts and subsequent metal interconnect layers are decreasing rapidly. CVD cobalt may be used as metal deposition technique for application as metal interconnects. Conventionally, a cobalt thin film is grown on dielectric material such as silicon dioxide or low-k dielectric. Use of organometallic precursors negates the need of a barrier layer, which is used in alternate metal CVD processes utilizing halide based chemistry. However, incubation (growth) of the cobalt layer on the dielectric material is poor and results in non-continuous growth. A titanium nitride (TiN) nucleation layer may be formed on the dielectric material prior to CVD deposition of cobalt layer. However, titanium nitride will not deposit on the dielectric material at less than 300° C. The cobalt layer is deposited at a temperature between 100° C. and 250° C. Thus, two processing chambers may be utilized for the depositions of the nucleation layer and the cobalt layer.
  • Therefore, an improved method of forming a cobalt layer is needed.
  • SUMMARY
  • Embodiments of the present invention generally relate to a method of forming a cobalt layer on a dielectric material without incubation delay. Prior to depositing the cobalt layer using CVD, the surface of the dielectric material is pretreated at a temperature between 100° C. and 250° C. Since the subsequent CVD cobalt process is also performed at between 100° C. and 250° C., only one processing chamber is used for the forming of the cobalt layer.
  • In one embodiment, a method for forming a metal interconnect is disclosed. The method includes placing a substrate into a processing chamber, pretreating a surface of the substrate at a temperature between 100° C. and 250° C., wherein a monolayer of molecules is formed on the surface of the substrate, and depositing a metal layer on the pretreated surface.
  • In another embodiment, a transfer chamber connecting a plurality of processing chambers is disclosed. The transfer chamber connecting a plurality of processing chambers has a transfer chamber, at least two cobalt chemical vapor deposition chambers, at least one physical vapor deposition chamber, and at least one plasma enhanced chemical vapor deposition chamber.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIG. 1 illustrates a cross sectional view of a substrate having a metal interconnect formed thereon according to one embodiment of the invention.
  • FIG. 2 illustrates a method for depositing a cobalt layer according to one embodiment of the invention.
  • FIG. 3 is a chart showing a relationship between CVD cobalt thickness and deposition time.
  • FIG. 4 is a schematic cross sectional view of a processing chamber which may be adapted to perform the processes disclosed herein.
  • FIG. 5 is a schematic top view of a multi-chamber processing system which may be adapted to perform the processes disclosed herein.
  • To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
  • DETAILED DESCRIPTION
  • Embodiments of the present invention generally relate to a method of forming a cobalt layer on a dielectric material without incubation delay. Prior to depositing the cobalt layer using CVD, the surface of the dielectric material is pretreated at a temperature between 100° C. and 250° C. Since the subsequent CVD cobalt process is also performed at between 100° C. and 250° C., only one processing chamber is used for the forming of the cobalt layer.
  • Referring to FIG. 1, in some embodiments, a device 100 may include a metal interconnect structure 101, which may generally comprise a substrate 102, a dielectric layer 104 and a metal layer 106. In some embodiments, the metal interconnect structure 101 may be disposed within or atop the substrate 102. In such embodiments, the metal interconnect structure 101 may be formed within a feature 108 formed, for example, in the dielectric layer 104 disposed over the substrate 102.
  • The substrate 102 may be any substrate capable of having material deposited thereon, such as a silicon substrate, for example crystalline silicon (e.g., Si<100>or Si<111>), silicon oxide, strained silicon, doped or undoped polysilicon, or the like, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, a solar array, solar panel, a light emitting diode (LED) substrate, a semiconductor wafer, or the like.
  • In some embodiments, the substrate 102 may include a p-type or n-type region defined therein (not shown). The substrate 102 may include other structures or features 108 at least partially formed therein. For example, in some embodiments, the feature 108 (e.g., a via, a trench, a dual damascene feature, high aspect ratio feature, or the like) may be formed within the dielectric layer 104 through any suitable process or processes, such as an etch process.
  • The dielectric layer 104 may contain silicon dioxide or a low-k dielectric material, such as a silicon carbide oxide material, or a carbon doped silicon oxide material. The dielectric layer 104 may be formed via any process suitable to provide the dielectric layer 104 having a desired thickness. Suitable processes may include CVD, PVD, atomic layer deposition (ALD), and plasma enhanced CVD (PECVD).
  • The metal layer 106 is a cobalt layer and is deposited using CVD. Organometallic precursors may be used for the CVD process, and one example of the organometallic precursors is dicobalt hexacarbonyl tertbutyl acetylene (CCTBA). The CCTBA based CVD cobalt is deposited at a temperature from about 100° C. to about 250° C. To minimize impurities in the cobalt layer 106, the processing temperature may be in the range of 125° C.-175° C. Conventionally, a nucleation layer such as a TiN layer may be first deposited on the dielectric layer 104 and the cobalt layer 106 is deposited on the TiN layer. TiN does not deposit on the dielectric layer 104 at a temperature that is less than 300° C. The processing temperature of TiN deposition is much higher than the processing temperature of cobalt deposition, thus two processing chambers are used for any process using cobalt as a metal interconnect material, causing loss of productivity by decreasing system throughput. Depositing the cobalt layer 106 without the TiN nucleation layer may cause incubation delay. Incubation delay, or growth delay, means the growth rate of the cobalt layer 106 is very slow at the beginning of the deposition process. To eliminate any incubation delay, the surface of the dielectric layer 104 is pre-treated before the cobalt layer 106 is deposited on the dielectric layer 104.
  • FIG. 2 illustrates a method 200 for depositing a cobalt layer without any incubation delay according to one embodiment of the invention. At step 202, the surface of the dielectric layer 104 is pretreated prior to the deposition of the cobalt layer 106 into the feature 108. In one embodiment, the pretreatment includes exposing the dielectric layer 104 to a precursor gas containing titanium at process temperature used during CVD cobalt deposition. The precursor gas may be tetrakis(dimethylamino)titanium (TDMAT), titanium tetrachloride (TiCl4) or the like. The surface of the dielectric layer 104 is exposed to the precursor gas at the same temperature as the CVD cobalt deposition temperature, such as from about 100° C. to about 250° C. In one embodiment, the pretreatment and the CVD cobalt deposition have the same process temperature, ranging from about 125° C. to about 175° C. At these temperature ranges, no TiN layer is deposited; instead a monolayer of the precursor molecules is deposited on the surface of the dielectric layer 104, including the surface of dielectric layer 104 inside the feature 108.
  • In another embodiment, the surface of the dielectric layer 104 is pretreated with an ammonia or nitrogen based plasma. The plasma pretreatment is also performed at process temperature used during CVD cobalt deposition. A monolayer of nitrogen molecules is formed on the dielectric layer 104. In another embodiment, both TDMAT exposure and ammonia or nitrogen plasma treatment are utilized. The TDMAT exposure may be performed before the ammonia or nitrogen plasma treatment, or performed after the ammonia or nitrogen plasma treatment.
  • Next, at step 204, the cobalt layer 106 is deposited on the dielectric layer 104, including on the dielectric layer 104 inside the feature 108. The cobalt layer 106 is deposited using a CVD process and the CVD process is performed in the chamber in which the pretreatment process is performed. The precursor used in the CVD process may be CCTBA and the cobalt layer 106 may have a thickness of less than 10 nanometers. Pretreating the dielectric surface 104 eliminated any incubation delay during CVD cobalt deposition. In addition, the cobalt layer 106 deposited on the pretreated dielectric surface has lower resistivity compared to cobalt layers formed on untreated dielectric surface.
  • FIG. 3 is a chart 300 showing a relationship between CVD cobalt layer thickness and deposition time for no pretreatment, ammonia plasma treatment and TDMAT exposure treatment. As shown in chart 300, both ammonia plasma and TDMAT exposure treatments result in a thicker cobalt layer at early stage of the deposition process.
  • FIG. 4 is a schematic cross sectional view of a processing chamber 400 which may be adapted to perform the processes disclosed herein. The processing chamber 400 may be a CVD chamber that is adapted to perform the pretreatment step 202 and the CVD cobalt deposition step 204, as described in FIG. 2. The chamber 400 comprises a chamber body 402 having sidewalls 404 and a bottom 406. A liner, such as a quartz liner, may line the sidewalls 404 and the bottom 406 of the chamber body 402 to provide thermal and/or electrical insulation. An opening 408 in the chamber 400 provides access for a robot (not shown) to deliver and retrieve substrates 410 to the chamber 100.
  • A substrate support 412 supports the substrate 410 in the chamber 400 on a substrate receiving surface 411. The substrate support 412 is mounted to a lift motor 414 to raise and lower the substrate support 412 and a substrate 410 disposed thereon. A lift plate 416 connected to a lift motor 418 is mounted in the chamber and raises and lowers pins 420 movably disposed through the substrate support 412. The pins 420 raise and lower the substrate 410 over the surface of the substrate support 412.
  • The substrate support 412 may be heated to heat the substrate 410 disposed thereon. For example, the substrate support 412 may have an embedded heating element 422 to resistively heat the substrate support 412 by applying an electric current from a power supply (not shown). A temperature sensor 426, such as a thermocouple, may be embedded in the substrate support 412 to monitor the temperature of the substrate support 412. For example, a measured temperature may be used in a feedback loop to control electric current applied to the heating element 422 from a power supply (not shown), such that the substrate temperature can be maintained or controlled at a desired temperature or within a desired temperature range. Alternatively, the substrate 410 may be heated using radiant heat, such as by lamps.
  • A gas distribution system 430 is disposed at an upper portion of the chamber body 402 to provide two gas flows distributed in a substantially uniform manner over a substrate 410 disposed on the substrate receiving surface 411 in which the two gas flows are delivered in separate discrete paths through the gas distribution system 430. One gas flow path may be used for the pretreatment step 202 while the other may be used for the CVD cobalt deposition step 204. In the embodiment shown, the gas distribution system 430 comprises a gas box 432, a blocker plate 460 positioned below the gas box 432, and a showerhead 470 positioned below the blocker plate 460. The gas distribution system 430 provides two gas flows through two discrete paths to a processing region 428 defined between the showerhead 470 and the substrate support 412.
  • The gas box 432 as used herein is defined as a gas manifold coupling gas sources to the chamber. The gas box 432 comprises a first gas channel 437 and a second gas channel 443 providing two separate paths for the flow of gases through the gas box 432. The first gas channel 437 comprises a first gas input 434 and a first gas outlet 438. The first gas input is adapted to receive a first gas from a first gas source 435 through valve 436. The first gas outlet 438 is adapted to deliver the first gas to the top of the blocker plate 460. The second gas channel 443 of the gas box 432 comprises a second gas input 440 and a second gas outlet 444. The second gas input 440 is adapted to receive a second gas from a second gas source 441 through valve 442. The second gas outlet 444 is adapted to deliver the second gas to top of the showerhead 470. The term “gas” as used herein is intended to mean a single gas or a gas mixture. The valves 436, 442 control delivery of the first gas and the second gas into the first gas input 434 and the second gas input 440 respectively. Gas sources 435, 441 may be adapted to store a gas or liquid precursor in a cooled, heated, or maintained at ambient environment. The gas lines fluidly coupling the gas sources 435, 441 to the gas inputs 434, 440 may also be heated, cooled, or at ambient temperature.
  • FIG. 5 is a schematic top view of a multi-chamber processing system 500 which may be adapted to perform the processes disclosed herein. Examples of suitable multi-chamber processing systems include the ENDURA® and PRODUCER® processing systems, commercially available from Applied Materials, Inc. of Santa Clara, Calif. The system 500 generally includes load lock chambers 502, 504, for the transfer of substrates (such as substrates 102 described above) into and out from the system 500. Since the system 500 is operated under vacuum, the load lock chambers 502, 504 may be “pumped down” to maintain to facilitate entry and egress of substrates to the system. A first robot 510 disposed in a first transfer chamber 520 may transfer the substrate between the load lock chambers 502, 504, processing chambers 512, 514, passthrough chambers 522, 524, and other processing chambers 516, 518. Each processing chamber 512, 514, 516, 518 may be outfitted to perform a number of substrate processing operations such as ALD, CVD, PVD, etch, preclean, degas, orientation and other substrate processes. The passthrough chambers 522, 524 typically are used for cool down of the substrates.
  • The passthrough chambers 522, 524 are connected to a second transfer chamber 540. The second transfer chamber 540 is connected to a plurality of processing chambers. In one embodiment, processing chambers 532, 534, 536 and 538 are connected to the second transfer chamber 540. An optional anneal chamber (not shown) may be connected to the second transfer chamber 540. A second robot 530 disposed in the second transfer chamber 540 may transfer the substrate between processing chambers 532, 534, 536, 538 and the passthrough chambers 522, 524.
  • In one embodiment, the processing chambers 532, 534, 536, 538 include essentially at least two CVD cobalt deposition chambers, at least one PVD chamber, and at least one plasma enhanced CVD chamber. The at least two CVD cobalt deposition chambers may be the processing chamber 400 described above. In one embodiment, processing chambers 534, 536 are the processing chambers that are adapted to perform both the pretreatment process and the CVD cobalt deposition, such as the processing chamber 400. The processing chamber 532 is a PVD chamber used for PVD cobalt deposition. The processing chamber 538 is a plasma processing chamber such as a plasma enhanced CVD chamber used for contact applications. Conventional method of forming a TiN nucleation layer prior to CVD cobalt deposition would utilize an additional processing chamber, leaving only one CVD cobalt deposition chamber connected to the transfer chamber 530. Since CVD cobalt deposition is relatively slow, having two pretreatment/CVD cobalt deposition processing chambers helps increasing throughput.
  • In summary, a single processing chamber is utilized to perform both pretreatment of the dielectric layer and CVD cobalt deposition. The pretreatment of the dielectric layer includes exposing the dielectric layer to a TDMAT precursor gas or to an ammonia plasma or a nitrogen plasma. The processing temperature for the pretreatment and the CVD cobalt deposition may be the same. Pretreating the dielectric layer prior to CVD cobalt deposition eliminates incubation delay. In addition, throughput is increased since two CVD cobalt deposition chambers may be included in a processing system.
  • While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (11)

1. A method for forming a metal interconnect, comprising:
placing a substrate into a processing chamber;
pretreating a surface of the substrate at a temperature between 100° C. and 250° C., wherein the pretreating the surface of the substrate comprises exposing the surface to an ammonia or nitrogen plasma; and
depositing a cobalt layer on the pretreated surface.
2. The method of claim 1, wherein the monolayer of molecules further comprises nitrogen.
3. The method of claim 1, wherein the pretreating the surface of the substrate further comprises exposing the surface to a titanium containing precursor gas prior to exposing the surface to the ammonia or nitrogen plasma.
4. The method of claim 3, wherein the titanium containing precursor gas comprises tetrakis(dimethylamino)titanium or titanium tetrachloride.
5. The method of claim 1, wherein the pretreating the surface of the substrate further comprises exposing the surface to a titanium containing precursor gas after exposing the surface to the ammonia or nitrogen plasma.
6. The method of claim 5, wherein the titanium containing precursor gas comprises tetrakis(dimethylamino)titanium or titanium tetrachloride.
7. The method of claim 1, wherein the cobalt layer is deposited by a chemical vapor deposition process.
8. The method of claim 7, wherein an organometallic precursor gas is used in the chemical vapor deposition process.
9. The method of claim 8, wherein the organometallic precursor gas comprises dicobalt hexacarbonyl tertbutyl acetylene.
10. The method of claim 9, wherein the chemical vapor deposition is performed at a temperature between 100° C. and 250° C.
11. The method of claim 10, wherein the surface of the substrate comprises silicon dioxide or a low-k dielectric.
US14/975,945 2013-09-13 2015-12-21 Surface treatment to improve cctba based cvd co nucleation on dielectric substrate Abandoned US20160104639A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/975,945 US20160104639A1 (en) 2013-09-13 2015-12-21 Surface treatment to improve cctba based cvd co nucleation on dielectric substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/026,147 US9218980B2 (en) 2013-09-13 2013-09-13 Surface treatment to improve CCTBA based CVD co nucleation on dielectric substrate
US14/975,945 US20160104639A1 (en) 2013-09-13 2015-12-21 Surface treatment to improve cctba based cvd co nucleation on dielectric substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/026,147 Division US9218980B2 (en) 2013-09-13 2013-09-13 Surface treatment to improve CCTBA based CVD co nucleation on dielectric substrate

Publications (1)

Publication Number Publication Date
US20160104639A1 true US20160104639A1 (en) 2016-04-14

Family

ID=52666142

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/026,147 Active 2033-10-26 US9218980B2 (en) 2013-09-13 2013-09-13 Surface treatment to improve CCTBA based CVD co nucleation on dielectric substrate
US14/975,945 Abandoned US20160104639A1 (en) 2013-09-13 2015-12-21 Surface treatment to improve cctba based cvd co nucleation on dielectric substrate

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/026,147 Active 2033-10-26 US9218980B2 (en) 2013-09-13 2013-09-13 Surface treatment to improve CCTBA based CVD co nucleation on dielectric substrate

Country Status (5)

Country Link
US (2) US9218980B2 (en)
KR (1) KR20160055215A (en)
CN (1) CN105518826A (en)
TW (1) TWI570261B (en)
WO (1) WO2015038270A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150140233A1 (en) * 2013-11-18 2015-05-21 Applied Materials, Inc. Methods for preferential growth of cobalt within substrate features

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018052479A1 (en) * 2016-09-15 2018-03-22 Applied Materials, Inc. Integrated system for semiconductor process
US10304732B2 (en) * 2017-09-21 2019-05-28 Applied Materials, Inc. Methods and apparatus for filling substrate features with cobalt
US10867905B2 (en) 2017-11-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming the same
US11011413B2 (en) 2017-11-30 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming the same
US11424132B2 (en) * 2018-11-03 2022-08-23 Applied Materials, Inc. Methods and apparatus for controlling contact resistance in cobalt-titanium structures
TWI801631B (en) * 2018-11-09 2023-05-11 台灣積體電路製造股份有限公司 Semiconductor device manufacturing method and semiconductor device
WO2021080726A1 (en) 2019-10-21 2021-04-29 Applied Materials, Inc. Method of depositing layers

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
US9051641B2 (en) * 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US7235482B2 (en) * 2003-09-08 2007-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology
US20060141780A1 (en) * 2004-12-23 2006-06-29 Cadien Kenneth C Methods for the plasma formation of a microelectronic barrier layer
US7078326B1 (en) 2005-01-19 2006-07-18 Marsh Eugene P Nucleation method for atomic layer deposition of cobalt on bare silicon during the formation of a semiconductor device
US7473637B2 (en) 2005-07-20 2009-01-06 Micron Technology, Inc. ALD formed titanium nitride films
KR101576033B1 (en) 2008-08-19 2015-12-11 삼성전자주식회사 A precursor composition method of forming a layer method of manufacturing a gate structure and method of manufacturing a capacitor
US8637390B2 (en) * 2010-06-04 2014-01-28 Applied Materials, Inc. Metal gate structures and methods for forming thereof
US8524600B2 (en) 2011-03-31 2013-09-03 Applied Materials, Inc. Post deposition treatments for CVD cobalt films
US8586479B2 (en) * 2012-01-23 2013-11-19 Applied Materials, Inc. Methods for forming a contact metal layer in semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150140233A1 (en) * 2013-11-18 2015-05-21 Applied Materials, Inc. Methods for preferential growth of cobalt within substrate features
US9637819B2 (en) * 2013-11-18 2017-05-02 Applied Materials, Inc. Methods for preferential growth of cobalt within substrate features

Also Published As

Publication number Publication date
WO2015038270A1 (en) 2015-03-19
US9218980B2 (en) 2015-12-22
TWI570261B (en) 2017-02-11
CN105518826A (en) 2016-04-20
KR20160055215A (en) 2016-05-17
TW201514330A (en) 2015-04-16
US20150079784A1 (en) 2015-03-19

Similar Documents

Publication Publication Date Title
US9218980B2 (en) Surface treatment to improve CCTBA based CVD co nucleation on dielectric substrate
US9673146B2 (en) Low temperature tungsten film deposition for small critical dimension contacts and interconnects
JP6339066B2 (en) PVD buffer layer for LED manufacturing
TWI394858B (en) Method of depositing tungsten film with reduced resistivity and improved surface morphology
CN101715602B (en) Film forming method and film forming apparatus
CN107964647B (en) Fabrication of gallium nitride-based light emitting diodes with physical vapor deposition to form aluminum nitride buffer layers
US20150311061A1 (en) Methods and apparatus for cleaning substrate surfaces with atomic hydrogen
US20120199887A1 (en) Methods of controlling tungsten film properties
US20090065816A1 (en) Modulating the stress of poly-crystaline silicon films and surrounding layers through the use of dopants and multi-layer silicon films with controlled crystal structure
US10879081B2 (en) Methods of reducing or eliminating defects in tungsten film
US20130189840A1 (en) Methods for forming a contact metal layer in semiconductor devices
US9879341B2 (en) Method and apparatus for microwave assisted chalcogen radicals generation for 2-D materials
US20140179110A1 (en) Methods and apparatus for processing germanium containing material, a iii-v compound containing material, or a ii-vi compound containing material disposed on a substrate using a hot wire source
KR102336537B1 (en) Methods for forming germanium and silicon germanium nanowire devices
KR102357328B1 (en) Method of Growing Doped Group IV Materials
US20100203243A1 (en) Method for forming a polysilicon film
Chow Equipment and manufacturability issues in CVD processes
KR20210118236A (en) polysilicon liners
Chow Intel Corporation, 2200 Mission College Boulevard, Santa Clara, CA, USA

Legal Events

Date Code Title Description
AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZOPE, BHUSHAN N.;GELATOS, AVGERINOS V.;REEL/FRAME:037337/0338

Effective date: 20130910

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION