US20160103158A1 - Peak voltage detector and related method of generating an envelope voltage - Google Patents
Peak voltage detector and related method of generating an envelope voltage Download PDFInfo
- Publication number
- US20160103158A1 US20160103158A1 US14/510,925 US201414510925A US2016103158A1 US 20160103158 A1 US20160103158 A1 US 20160103158A1 US 201414510925 A US201414510925 A US 201414510925A US 2016103158 A1 US2016103158 A1 US 2016103158A1
- Authority
- US
- United States
- Prior art keywords
- voltage
- switch
- auxiliary
- command signal
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
Definitions
- This disclosure relates to detectors of voltage peaks of oscillating signals and more particularly to a novel architecture, realizable in a completely integrated form, adapted to generate an envelope voltage corresponding to the instantaneous peak value of an input oscillating voltage and to a related method.
- PFC active power factor correction
- PFC pre-regulators are switching converters controlled such to obtain a regulated DC output voltage from an input AC voltage.
- PFC regulators are capable of absorbing a sinusoidal current in phase with the voltage of the mains, thus obtaining in this way a power factor close to 1 and a reduced total harmonic distortion of the current absorbed from the mains.
- FIG. 1 is an example of a known PFC pre-regulator with a “Transition Mode” control.
- the amplifier VA compares a fraction of the output voltage with an internal reference voltage VREF for generating an error signal that is sent to the multiplier.
- the multiplier MULTIPLIER carries out the product between a fraction of the mains voltage and the output signal of the amplifier VA, thus outputting a sinusoidal signal in phase with the mains voltage and having an amplitude proportional to the error signal itself.
- the PWM comparator compares the signal generated by the multiplier with a value proportional to the current flowing through the inductor L and turns off the power MOSFET M as soon as the two values match each other, thus determining the envelope of the current through the inductor itself.
- the inductor L discharges through the load the energy stored during the previous phase. At this point, the MOSFET M is turned on again by the switching of the zero-cross comparator ZCD and the loop restarts.
- the current absorbed from the mains, because of the input filter, will be the low-pass component of the current flowing throughout the inductor L, thus its mean value at each switching cycle, equal to one half of the envelope of the peaks and with a sinusoidal waveform in phase with the mains voltage itself, as shown in FIG. 2 .
- a compensation factor can be introduced, in the loop gain, which is inversely proportional to the square of the input voltage.
- This compensation technique called “voltage feedforward”, consists in deriving a voltage proportional to the RMS value of the input voltage, providing this value to a squaring/dividing circuit (corrector 1/V FF 2 ) and providing the resulting signal to the multiplier that generates the reference for the peak current of the system.
- a variation of the supply voltage causes a variation inversely proportional to the amplitude of the sinusoid generated by the multiplier; if the supply voltage doubles, the amplitude of the signal generated by the multiplier halves and vice versa.
- the reference for the peak current is, in this way, immediately adapted to the new working conditions without need of intervention of the error amplifier.
- the loop gain will remain constant for any value of the input voltage, thus sensibly improving the dynamical behavior of the pre-regulator.
- the design of the external network for ensuring the stability of the system is simplified.
- the circuit for sensing the RMS value is fully effective if it is capable of following fluctuations of the input voltage in both directions.
- a fast detection of peaks may be insufficient when they increase but also when their value decreases. Indeed, if the detection of the peak reduction of the mains voltage is very slow, the setting of the correct feedforward action will be delayed, with a consequent excessive overshoot of the output voltage of the pre-regulator because of great variations of the supply voltage.
- a so-called integrated “ideal diode” comprising an operational amplifier configured as voltage follower in the feedback path, with an external capacitor C FF for storing information and an external resistance R FF as shown in FIG. 3 .
- the resistance R FF properly determined, provides the discharge path of the capacitor and makes the system capable of adapting itself, with a time constant R FF C FF , to reductions of the root mean square value of the input voltage.
- the time constant R FF C FF is determined such to make the discharge phenomenon not detectable inside each half period of the mains voltage; the RMS value of the mains voltage is thus close to a continuous value.
- a drawback of this type of circuit besides using two discrete external components, consists in that the system responds according to an exponential law with a time constant R FF C FF that, for the reasons stated above, will be relatively great (typically in the order of several hundreds of ms). This implies a loss of effectiveness of the feedforward technique for a longer time the greater the variation of the input voltage and thus the greater the time constant R FF C FF .
- a mains drop detector shown in FIG. 4 , used in the integrated control L6564 of STMicroelectronics, stores on an inner capacitance C 1 the peak of a scaled replica of the mains voltage (excluding any voltage offset).
- V FFi The voltage on this capacitance, called V FFi , is used as threshold of a comparator that compares it with a peak voltage V FF (minus a voltage drop across a resistor R 1 .
- the threshold and the external RC filter R FF C FF are dimensioned such that, in a mains voltage period, the voltage V FF does not decrease sufficiently to switch the comparator. Should an abrupt decrease of the mains voltage occur, the voltage on the external capacitor C FF , after a certain number of periods, drops below the threshold thus switching the comparator that, on its turn, turns on transistor M 6 that acts as a fast discharge circuit of the capacitance C FF , which will be charged with a new peak value.
- a detector of voltage peak values adapted to generate an envelope voltage of an oscillating voltage is provided.
- the detector has an architecture realizable in a completely integrated form capable of keeping the information on the value of the last detected peak in an accurate fashion also in case of long periods of time between two consecutive peak events.
- the detector has an integrated tank capacitor referred to a reference potential, on which a voltage representing the last detected peak value is made available.
- the capacitor is charged with the value of the oscillating voltage shortly before a peak event, and is disconnected from the remaining part of the circuit at the end of the event, in order to limit as much as possible leakage currents.
- a controlled switch is configured to connect the tank capacitor to a rectified replica of the oscillating voltage when the switch is closed and to isolate the capacitor from the oscillating voltage when the switch is open.
- a rectifying circuit is input with the oscillating voltage and generates the rectified replica voltage on an output coupled to the tank capacitor, through the controlled switch. The rectifying circuit is adapted to replicate the oscillating voltage on the output when the controlled switch is closed.
- a comparator is configured to compare an offset value corresponding to the envelope voltage stored on the capacitor, and the oscillating voltage, and to generate a command signal adapted to close the controlled switch when the difference voltage is smaller than the offset voltage.
- the time elapsed from the last detected active switching edge of the command signal is measured and the controlled switch is closed when the command signal is active or when a pre-established time interval has elapsed from the last active switching edge of the command signal, and the control switch is opened otherwise.
- FIG. 1 shows a typical power factor correction system PFC with “transition mode” control.
- FIG. 2 is a time graph of the current flowing through components of the system of FIG. 1 .
- FIG. 3 shows elements of a PFC system that includes the detection structure of the peak voltage used in the known PFC L6563 of STMicroelectronics, disclosed also in U.S. Pat. No. 7,239,120.
- FIG. 4 shows elements of a PFC system that includes a mains drop detector used in the known PFC L6564 of STMicroelectronics.
- FIG. 5 shows a basic fully integrated architecture adapted to store the peak value of an oscillating voltage, according to an embodiment.
- FIGS. 6 and 7 show exemplary time graphs of the envelope voltage of an oscillating voltage.
- FIG. 8 shows a fully integrated peak detector of an oscillating voltage according to a further embodiment.
- FIG. 9 shows time graphs obtained through simulation of the functioning of the peak detector of FIG. 8 .
- FIG. 10 shows a peak detector according to an alternative embodiment.
- FIG. 11 shows a time graph obtained in a particular case through simulation of the functioning of the peak detector of FIG. 8 .
- FIG. 12 shows a peak detector with an auxiliary capacitor according to yet another alternative embodiment.
- FIG. 13 shows a time graph obtained through the functioning of the peak detector of FIG. 12 .
- FIG. 14 compares time graphs obtained in a particular case through the functioning of the peak detector of FIG. 8 and of FIG. 12 .
- the circuit of FIG. 4 is burdened by the drawback of using two external discrete components R FF and C FF .
- the activation time of the tracking mechanism (fast feedforward), tied to the constant R FF C FF and to a fixed threshold, will further depend from the value of the peak voltage itself. Therefore, the higher the input voltage, the longer the time that will elapse before the threshold is surpassed, and thus the slower the system when following eventual abrupt variations of the oscillating voltage V MULT .
- One embodiment of the present disclosure provides an architecture realizable in a completely integrated form that implements a related method for detecting the peak voltage of low frequency oscillating signals, without requiring external discrete components and capable of following abrupt variations of the oscillating input voltage and of keeping constant with a good approximation the envelope voltage between two consecutive peaks, if they have substantially the same amplitude.
- a peak detector 100 shown in FIG. 5 is based on the principle of isolating completely, through properly biased junctions, an integrated storage capacitance 102 between one peak value and the next. In this way, the drift of the stored datum between two consecutive peaks is reduced and the problem of controlling the discharge current of the capacitance is solved.
- the integrated storage capacitance 102 is completely isolated by the switch 104 of FIG. 5 , except for a connection to the comparator 106 , which effectively has an infinite input (DC) impedance; in this way the previously detected voltage peak V C remains stored on the capacitor 102 .
- DC infinite input
- the switch 104 used for the isolation, can be optionally equipped with a circuit for reducing as much as possible leakage currents of the junction and thus the drift of the stored datum ( FIG. 10 ).
- An offset voltage source 108 is coupled between the storage capacitance 102 and a first input of the comparator 106 .
- the offset voltage source 108 provides a selected offset voltage V OS , which is subtracted from the voltage V C stored by the capacitor 102 , and the resulting value (V C ⁇ V OS ) is supplied at the first input of the comparator 106 .
- An oscillating voltage signal V MULT that is proportional to a rectified power supply input is supplied at the second input of the comparator 106 .
- a rectifying circuit 109 is coupled between an input terminal 110 , which receives the oscillating voltage (V MULT ), and a first conduction terminal of the switch 104 which has a second conduction terminal coupled to the capacitor 102 .
- the rectifying circuit 109 is configured to generate a rectified replica voltage that is used to charge the capacitor 102 when the controlled switch 104 is closed and when the rectified replica voltage is greater than the voltage V C stored on the tank capacitor.
- the switch 104 remains open as long as the input voltage V MULT does not reach a threshold value V C ⁇ V OS . As soon as the input voltage V MULT surpasses this value, the switch 104 is closed by a signal ov_th output by the comparator 106 and the capacitance 102 is connected to the remaining portion of the circuit and starts functioning as a classic detector, tracking the new peak value. The circuit remains in this configuration, with the switch closed, as long as the input voltage V MULT remains above the threshold voltage V C ⁇ V OS (instant t 2 in FIG. 7 ).
- the peak detector 100 is capable of detecting that a new peak value has been attained when it is greater than or equal to the previously stored value. Also, this technique does not require connecting the capacitor 102 longer than a time to store such a value. For the remaining part of the cycle, the capacitor 102 is practically isolated from the circuit and thus a minimum drift of the stored datum will occur, due only to leakage phenomena of the junction of the switch 104 .
- the described architecture works optimally in particular when the new peak value is close to or greater than the stored value and when it is possible to ensure that the leakage of the switch 104 tends only to discharge the capacitance 102 .
- the system can be equipped with a further circuit for refreshing, at each cycle, the value stored on the capacitance 102 itself.
- the peak detection circuit of FIG. 8 includes a clamping circuit 111 configured to clamp the envelope voltage V C to an instantaneous value of the oscillating voltage V MULT .
- the clamping circuit 111 includes the rectifying circuit 109 implemented using an op-amp 112 , a diode 114 , and a switch 116 .
- the op-amp 112 has a non-inverting input coupled to the input terminal that receives the oscillating signal V MULT , an inverting input coupled to the second conduction terminal of the switch 104 , and an output coupled to a cathode of the diode 114 , which has an anode coupled to the first conduction terminal of the switch 104 .
- the switch 116 is coupled in parallel to the diode 114 in order to bypass the diode when a control terminal of the switch 116 is activated.
- the clamping circuit 111 also includes first and second OR gates 118 , 120 , a timer 122 , and a monostable multivibrator (one-shot) 124 .
- the first OR gate 118 has a first input coupled to the output of the comparator 106 , a second input coupled to the output of the timer 122 , and an output coupled to a control terminal of the switch 104 .
- the timer 122 and one-shot 124 have respective inputs coupled to the output of the comparator 106 and respective outputs coupled respectively to first and second inputs of the second OR gate 120 .
- the second OR gate has an output coupled to the control terminal of the switch 116 .
- V P in FIG. 8 a pulse control signal
- the charge stored in the previous period can discharge through the switches 104 , 116 and the op-amp 112 , and is thus nullified and in proximity of each peak value the stored value is refreshed.
- Pk ERROR Pk DECAY +V OS ⁇ V OS .
- the error value Pk DECAY represents the drift of the voltage due to the leakage current of the switch that charges/discharges the storage capacitance and may be expressed as follows:
- FIG. 8 also depicts a circuit that allows the system to track the mains voltage when abrupt reductions of the peak value occur.
- the timer 122 If the oscillating input voltage V MULT of the peak detector does not attain the threshold value V C ⁇ V OS within a pre-established period of time T PK (this happens, for example, when the new peak value is smaller than the previously stored value), the timer 122 generates a signal V TRK that closes the switch 116 via the second OR gate 116 and forces the system to work as an operational amplifier closed in a buffer configuration, for a short time (for example 40 ⁇ s) sufficient for the operational amplifier op-amp 114 to attain a steady state condition.
- a short time for example 40 ⁇ s
- the capacitance 102 is instantaneously brought to the present value of the input voltage and V C and V MULT thus are equal to each other.
- V MULT >V C ⁇ V OS is still verified and the capacitance 102 is still connected to the rest of the circuit that may continue working as voltage follower until the detection of the next peak.
- time Tpk should be designed such to be slightly longer than the maximum period of the involved signals.
- FIG. 9 shows simulation graphs of transient functioning of the circuit of FIG. 8 .
- the peak value is tracked fast when it is greater than the previously stored value.
- the peak detector is capable of tracking the new value practically instantaneously.
- the circuit has a response time Tpk to make the circuit capable of tracking the input voltage and detecting a new peak value.
- the circuit waits until the input voltage reaches a minimum enabling value before being configured as a voltage buffer.
- the switch 104 is implemented using a MOSFET transistor 126 , an offset voltage source 128 , and an op-amp 130 coupled to the body of the transistor 120 in a voltage follower configuration.
- the offset voltage source 128 supplies an input voltage to the op-amp 130 that is offset so as to be slightly below the value V C stored on the capacitor 102 , which value is provided at the body terminal of the transistor 126 by the op-amp 130 . Accordingly, any leakage current of the transistor 126 will tend to discharge the capacitor 102 .
- THD Total harmonic distortion
- the circuit of FIG. 12 comprises an auxiliary capacitor 102 B, substantially identical to the tank capacitor 102 on which the voltage Vc is made available, that may be charged with the current delivered by the op-amp 112 when the auxiliary switch 104 B is closed.
- the auxiliary capacitor 102 B is coupled at comparator 106 and op-amp 112 inputs.
- the OR gate 118 receives the signal ov_th output of comparator 106 and a command 136 for closing the switch 104 B when the charge voltage of the auxiliary capacitor 102 B has to track the input voltage V MULT .
- Command 136 generated by the logic circuit 134 , is a pulse signal triggered when a time interval from a last active edge of ov_th signal has elapsed, in order to close the auxiliary switch 104 B when the charge voltage V AUX of the auxiliary capacitor 102 B remains greater than the input voltage V MULT , as in the circuit of FIG. 8 .
- the auxiliary command STORE generated by the logic circuit 134 is high, it enables ov_th signal to close both switches 104 and 104 B thus refreshing the voltage value of both Vc tank capacitor 102 and auxiliary capacitor 102 B.
- the logic circuit 134 waits for a time T o and, if the charge voltage V AUX is greater than the input voltage V MULT , for all this time interval, it asserts the signal 136 for closing the auxiliary switch 104 B.
- the signal ov_th switches logically high but it is masked since auxiliary command STORE is forced low, thus the switch 104 controlled by the logic AND gate 132 remains open and only the charge voltage V AUX of the auxiliary capacitor is refreshed. Therefore, the charge voltages Vc and V AUX become different.
- the auxiliary command STORE is released high.
- the signal ov_th switches again logically high and allows the refreshing of tank capacitor Vc exactly in correspondence of a peak of the input voltage V MULT .
- the logic circuit 134 comprises a timer for generating the signal 136 , a logic block that forces low the command STORE before assertion of the signal 136 and an extra timer to ensure that the masking signal STORE is released high after a fixed time allowing both switches to close and both capacitors to track next input peak value as soon as ov_th goes again high.
- the exemplary time graphs of FIG. 14 compare the output voltage Vc of the circuit of FIG. 8 (up) and of the circuit of FIG. 12 (down) in case of an input voltage V MULT corrupted by a noise peak, indicated with an arrow.
- the charge voltage Vc of the tank capacitor is refreshed in correspondence of the noise peak.
- the voltage Vc is refreshed as soon as the time interval T o expires
- the voltage Vc is refreshed only in correspondence of first input voltage peak following the refresh of the charge voltage V AUX of the auxiliary capacitor 102 B after the end of the time interval To.
- the voltage Vc output by the circuit of FIG. 12 is less distorted than the voltage Vc of the circuit of FIG. 8 , thus leading to enhancement of THD figures.
Abstract
Description
- 1. Technical Field
- This disclosure relates to detectors of voltage peaks of oscillating signals and more particularly to a novel architecture, realizable in a completely integrated form, adapted to generate an envelope voltage corresponding to the instantaneous peak value of an input oscillating voltage and to a related method.
- 2. Description of the Related Art
- Forced switching power supplies and, more particularly, systems for active power factor correction (PFC), store information about peak values of an input voltage, that typically is the voltage of the mains, thus at a low frequency.
- In general, PFC pre-regulators are switching converters controlled such to obtain a regulated DC output voltage from an input AC voltage. Using particular switching techniques, PFC regulators are capable of absorbing a sinusoidal current in phase with the voltage of the mains, thus obtaining in this way a power factor close to 1 and a reduced total harmonic distortion of the current absorbed from the mains.
-
FIG. 1 is an example of a known PFC pre-regulator with a “Transition Mode” control. - The amplifier VA compares a fraction of the output voltage with an internal reference voltage VREF for generating an error signal that is sent to the multiplier.
- The multiplier MULTIPLIER carries out the product between a fraction of the mains voltage and the output signal of the amplifier VA, thus outputting a sinusoidal signal in phase with the mains voltage and having an amplitude proportional to the error signal itself.
- The PWM comparator compares the signal generated by the multiplier with a value proportional to the current flowing through the inductor L and turns off the power MOSFET M as soon as the two values match each other, thus determining the envelope of the current through the inductor itself.
- Once the MOSFET M is off, the inductor L discharges through the load the energy stored during the previous phase. At this point, the MOSFET M is turned on again by the switching of the zero-cross comparator ZCD and the loop restarts.
- The current absorbed from the mains, because of the input filter, will be the low-pass component of the current flowing throughout the inductor L, thus its mean value at each switching cycle, equal to one half of the envelope of the peaks and with a sinusoidal waveform in phase with the mains voltage itself, as shown in
FIG. 2 . - From an analysis of the functioning, it is evident that the gain of the power stage of a PFC pre-regulator depends with a quadratic law from the RMS value of the mains voltage. In case of fluctuations of the mains voltage, the error amplifier intervenes in an appropriate manner for bringing the sinusoidal reference (input to the PWM comparator) to the value that obtains a correct regulation of the output.
- This quadratic function that ties the gain to the value of the input voltage causes the followings drawbacks:
-
- the error amplifier has linear dynamics in a very extended range. In systems with a so-called universal supply the input voltage may vary by a
factor 3 or more, thus the gain may vary by a factor 9. Therefore the error amplifier, for a same load, should be capable of reducing its output at least by nine times; - the quadratic variation of the gain implies a similar variation of the cut-off frequency of the open loop transfer function, with consequent difficulty of compensating the system and a relatively slow dynamical response when functioning at the maximum voltage. Indeed, the frequency response of the system has a single pole. This pole is independent from the input voltage and is tied to the resistance and to the capacitance on the output of the pre-regulator. Therefore, if the error amplifier is compensated for having a band of 20 Hz for the open loop transfer function at the maximum voltage, the band will be of about 2 Hz at the minimum mains voltage, thus causing an even slower dynamical response;
- undershoots/overshoots of the output voltage of the pre-regulator, in response to great fluctuations of the mains voltage. With the same load, at each variation of the input voltage, in order to make the system remain regulated, there should be a corresponding opposite variation of the output of the error amplifier. The amplifier is relatively slow thus, before being capable of following and compensating the variation, output undershoots/overshoots may occur.
- the error amplifier has linear dynamics in a very extended range. In systems with a so-called universal supply the input voltage may vary by a
- In order to compensate these phenomena, a compensation factor can be introduced, in the loop gain, which is inversely proportional to the square of the input voltage. This compensation technique, called “voltage feedforward”, consists in deriving a voltage proportional to the RMS value of the input voltage, providing this value to a squaring/dividing circuit (
corrector 1/VFF 2) and providing the resulting signal to the multiplier that generates the reference for the peak current of the system. - With this technique, a variation of the supply voltage causes a variation inversely proportional to the amplitude of the sinusoid generated by the multiplier; if the supply voltage doubles, the amplitude of the signal generated by the multiplier halves and vice versa. The reference for the peak current is, in this way, immediately adapted to the new working conditions without need of intervention of the error amplifier. The loop gain will remain constant for any value of the input voltage, thus sensibly improving the dynamical behavior of the pre-regulator. Moreover, the design of the external network for ensuring the stability of the system is simplified.
- From the above considerations, the circuit for sensing the RMS value (peak detector) is fully effective if it is capable of following fluctuations of the input voltage in both directions. A fast detection of peaks may be insufficient when they increase but also when their value decreases. Indeed, if the detection of the peak reduction of the mains voltage is very slow, the setting of the correct feedforward action will be delayed, with a consequent excessive overshoot of the output voltage of the pre-regulator because of great variations of the supply voltage.
- Commonly, as disclosed in U.S. Pat. No. 7,239,120, and employed in controller L6563 of STMicroelectronics, in order to obtain this function, a so-called integrated “ideal diode” is used, comprising an operational amplifier configured as voltage follower in the feedback path, with an external capacitor CFF for storing information and an external resistance RFF as shown in
FIG. 3 . - The resistance RFF, properly determined, provides the discharge path of the capacitor and makes the system capable of adapting itself, with a time constant RFFCFF, to reductions of the root mean square value of the input voltage. The time constant RFFCFF is determined such to make the discharge phenomenon not detectable inside each half period of the mains voltage; the RMS value of the mains voltage is thus close to a continuous value.
- A drawback of this type of circuit, besides using two discrete external components, consists in that the system responds according to an exponential law with a time constant RFFCFF that, for the reasons stated above, will be relatively great (typically in the order of several hundreds of ms). This implies a loss of effectiveness of the feedforward technique for a longer time the greater the variation of the input voltage and thus the greater the time constant RFFCFF.
- A mains drop detector, shown in
FIG. 4 , used in the integrated control L6564 of STMicroelectronics, stores on an inner capacitance C1 the peak of a scaled replica of the mains voltage (excluding any voltage offset). - The voltage on this capacitance, called VFFi, is used as threshold of a comparator that compares it with a peak voltage VFF (minus a voltage drop across a resistor R1. The threshold and the external RC filter RFFCFF are dimensioned such that, in a mains voltage period, the voltage VFF does not decrease sufficiently to switch the comparator. Should an abrupt decrease of the mains voltage occur, the voltage on the external capacitor CFF, after a certain number of periods, drops below the threshold thus switching the comparator that, on its turn, turns on transistor M6 that acts as a fast discharge circuit of the capacitance CFF, which will be charged with a new peak value.
- According to one embodiment, a detector of voltage peak values adapted to generate an envelope voltage of an oscillating voltage is provided. The detector has an architecture realizable in a completely integrated form capable of keeping the information on the value of the last detected peak in an accurate fashion also in case of long periods of time between two consecutive peak events.
- The detector has an integrated tank capacitor referred to a reference potential, on which a voltage representing the last detected peak value is made available. The capacitor is charged with the value of the oscillating voltage shortly before a peak event, and is disconnected from the remaining part of the circuit at the end of the event, in order to limit as much as possible leakage currents. A controlled switch is configured to connect the tank capacitor to a rectified replica of the oscillating voltage when the switch is closed and to isolate the capacitor from the oscillating voltage when the switch is open. A rectifying circuit is input with the oscillating voltage and generates the rectified replica voltage on an output coupled to the tank capacitor, through the controlled switch. The rectifying circuit is adapted to replicate the oscillating voltage on the output when the controlled switch is closed. A comparator is configured to compare an offset value corresponding to the envelope voltage stored on the capacitor, and the oscillating voltage, and to generate a command signal adapted to close the controlled switch when the difference voltage is smaller than the offset voltage.
- According to a preferred embodiment, the time elapsed from the last detected active switching edge of the command signal is measured and the controlled switch is closed when the command signal is active or when a pre-established time interval has elapsed from the last active switching edge of the command signal, and the control switch is opened otherwise.
-
FIG. 1 shows a typical power factor correction system PFC with “transition mode” control. -
FIG. 2 is a time graph of the current flowing through components of the system ofFIG. 1 . -
FIG. 3 shows elements of a PFC system that includes the detection structure of the peak voltage used in the known PFC L6563 of STMicroelectronics, disclosed also in U.S. Pat. No. 7,239,120. -
FIG. 4 shows elements of a PFC system that includes a mains drop detector used in the known PFC L6564 of STMicroelectronics. -
FIG. 5 shows a basic fully integrated architecture adapted to store the peak value of an oscillating voltage, according to an embodiment. -
FIGS. 6 and 7 show exemplary time graphs of the envelope voltage of an oscillating voltage. -
FIG. 8 shows a fully integrated peak detector of an oscillating voltage according to a further embodiment. -
FIG. 9 shows time graphs obtained through simulation of the functioning of the peak detector ofFIG. 8 . -
FIG. 10 shows a peak detector according to an alternative embodiment. -
FIG. 11 shows a time graph obtained in a particular case through simulation of the functioning of the peak detector ofFIG. 8 . -
FIG. 12 shows a peak detector with an auxiliary capacitor according to yet another alternative embodiment. -
FIG. 13 shows a time graph obtained through the functioning of the peak detector ofFIG. 12 . -
FIG. 14 compares time graphs obtained in a particular case through the functioning of the peak detector ofFIG. 8 and ofFIG. 12 . - The circuit of
FIG. 4 is burdened by the drawback of using two external discrete components RFF and CFF. Also, the activation time of the tracking mechanism (fast feedforward), tied to the constant RFFCFF and to a fixed threshold, will further depend from the value of the peak voltage itself. Therefore, the higher the input voltage, the longer the time that will elapse before the threshold is surpassed, and thus the slower the system when following eventual abrupt variations of the oscillating voltage VMULT. - One embodiment of the present disclosure provides an architecture realizable in a completely integrated form that implements a related method for detecting the peak voltage of low frequency oscillating signals, without requiring external discrete components and capable of following abrupt variations of the oscillating input voltage and of keeping constant with a good approximation the envelope voltage between two consecutive peaks, if they have substantially the same amplitude.
- A peak detector 100 shown in
FIG. 5 is based on the principle of isolating completely, through properly biased junctions, anintegrated storage capacitance 102 between one peak value and the next. In this way, the drift of the stored datum between two consecutive peaks is reduced and the problem of controlling the discharge current of the capacitance is solved. - In prior art circuits, it is not possible to use an integrated capacitor with a controlled discharge. The integrated capacitors, because of limited silicon area occupation, are small and, if the storage times are in the order of milliseconds, the discharge current should be about one pA, thus hardly controllable with sufficient precision. The poor control of the value and even of the polarity of these currents (if the leakage phenomenon was exploited for discharging the capacitor CFF) could cause a relevant variation of the stored information.
- However, according to the embodiment of
FIG. 5 , between one voltage peak and the next, theintegrated storage capacitance 102 is completely isolated by theswitch 104 ofFIG. 5 , except for a connection to thecomparator 106, which effectively has an infinite input (DC) impedance; in this way the previously detected voltage peak VC remains stored on thecapacitor 102. - The
switch 104, used for the isolation, can be optionally equipped with a circuit for reducing as much as possible leakage currents of the junction and thus the drift of the stored datum (FIG. 10 ). - An offset
voltage source 108 is coupled between thestorage capacitance 102 and a first input of thecomparator 106. The offsetvoltage source 108 provides a selected offset voltage VOS, which is subtracted from the voltage VC stored by thecapacitor 102, and the resulting value (VC−VOS) is supplied at the first input of thecomparator 106. An oscillating voltage signal VMULT that is proportional to a rectified power supply input is supplied at the second input of thecomparator 106. - In addition, a
rectifying circuit 109 is coupled between aninput terminal 110, which receives the oscillating voltage (VMULT), and a first conduction terminal of theswitch 104 which has a second conduction terminal coupled to thecapacitor 102. The rectifyingcircuit 109 is configured to generate a rectified replica voltage that is used to charge thecapacitor 102 when the controlledswitch 104 is closed and when the rectified replica voltage is greater than the voltage VC stored on the tank capacitor. - The
switch 104 remains open as long as the input voltage VMULT does not reach a threshold value VC−VOS. As soon as the input voltage VMULT surpasses this value, theswitch 104 is closed by a signal ov_th output by thecomparator 106 and thecapacitance 102 is connected to the remaining portion of the circuit and starts functioning as a classic detector, tracking the new peak value. The circuit remains in this configuration, with the switch closed, as long as the input voltage VMULT remains above the threshold voltage VC−VOS (instant t2 inFIG. 7 ). - With this technique the peak detector 100 is capable of detecting that a new peak value has been attained when it is greater than or equal to the previously stored value. Also, this technique does not require connecting the
capacitor 102 longer than a time to store such a value. For the remaining part of the cycle, thecapacitor 102 is practically isolated from the circuit and thus a minimum drift of the stored datum will occur, due only to leakage phenomena of the junction of theswitch 104. - The described architecture works optimally in particular when the new peak value is close to or greater than the stored value and when it is possible to ensure that the leakage of the
switch 104 tends only to discharge thecapacitance 102. - If the leakage tends to store charges on the
capacitance 102, bringing the stored voltage to drift towards greater values, the system can be equipped with a further circuit for refreshing, at each cycle, the value stored on thecapacitance 102 itself. - An increasing drift of the stored voltage VC could indeed make the stored value (thus the threshold VC−VOS), if the peak does not change, after a certain number of cycles, to be too different from the next peak value without permitting the detection and the connection of the capacitance.
- It is possible to obviate this limitation by using a further embodiment, as shown in
FIG. 8 . The peak detection circuit ofFIG. 8 includes aclamping circuit 111 configured to clamp the envelope voltage VC to an instantaneous value of the oscillating voltage VMULT. Theclamping circuit 111 includes the rectifyingcircuit 109 implemented using an op-amp 112, adiode 114, and aswitch 116. The op-amp 112 has a non-inverting input coupled to the input terminal that receives the oscillating signal VMULT, an inverting input coupled to the second conduction terminal of theswitch 104, and an output coupled to a cathode of thediode 114, which has an anode coupled to the first conduction terminal of theswitch 104. Theswitch 116 is coupled in parallel to thediode 114 in order to bypass the diode when a control terminal of theswitch 116 is activated. - The
clamping circuit 111 also includes first and second ORgates timer 122, and a monostable multivibrator (one-shot) 124. The first ORgate 118 has a first input coupled to the output of thecomparator 106, a second input coupled to the output of thetimer 122, and an output coupled to a control terminal of theswitch 104. Thetimer 122 and one-shot 124 have respective inputs coupled to the output of thecomparator 106 and respective outputs coupled respectively to first and second inputs of the second ORgate 120. The second OR gate has an output coupled to the control terminal of theswitch 116. - According to this further embodiment, each time the
comparator 106 detects the input voltage VMULT overcoming the threshold VC−VOS, besides closing theisolation switch 104 via the first ORgate 118, it causes the one-shot 124 to generate a pulse control signal (signal VP inFIG. 8 ) that closes theswitch 116, bypassing thediode 114, which brings the peak detector to work as an operational amplifier closed in a buffer configuration (typically for about 40 μs). In this configuration, the charge stored in the previous period can discharge through theswitches amp 112, and is thus nullified and in proximity of each peak value the stored value is refreshed. - A drawback of this solution is the presence of a small ripple of the voltage VC at t3 immediately before attaining the successive voltage peak, as shown in
FIG. 7 . Nevertheless, this ripple (equal to the offset voltage employed in detecting the peak itself) is controllable and may be made smaller than the ripple that is commonly present in detectors with external capacitance and controlled discharge: -
Pk ERROR =Pk DECAY +V OS ≈V OS. - The error value PkDECAY represents the drift of the voltage due to the leakage current of the switch that charges/discharges the storage capacitance and may be expressed as follows:
-
- In the case in which it is possible to fix the polarity of the leakage current, and in particular to make it discharge the
capacitance 102, it is possible to remove the refreshing circuit and to use the simplified structure depicted inFIG. 10 . -
FIG. 8 also depicts a circuit that allows the system to track the mains voltage when abrupt reductions of the peak value occur. - If the oscillating input voltage VMULT of the peak detector does not attain the threshold value VC−VOS within a pre-established period of time TPK (this happens, for example, when the new peak value is smaller than the previously stored value), the
timer 122 generates a signal VTRK that closes theswitch 116 via the second ORgate 116 and forces the system to work as an operational amplifier closed in a buffer configuration, for a short time (for example 40 μs) sufficient for the operational amplifier op-amp 114 to attain a steady state condition. - With this technique, the
capacitance 102 is instantaneously brought to the present value of the input voltage and VC and VMULT thus are equal to each other. - At the end of this short time, the condition VMULT>VC−VOS is still verified and the
capacitance 102 is still connected to the rest of the circuit that may continue working as voltage follower until the detection of the next peak. - Obviously, the time Tpk should be designed such to be slightly longer than the maximum period of the involved signals.
-
FIG. 9 shows simulation graphs of transient functioning of the circuit ofFIG. 8 . In particular, it is possible to notice that the peak value is tracked fast when it is greater than the previously stored value. The peak detector is capable of tracking the new value practically instantaneously. - In the case in which the peak voltage is smaller than the stored voltage, the circuit has a response time Tpk to make the circuit capable of tracking the input voltage and detecting a new peak value.
- Besides the above considerations, if voltage peaks are to be detected when they are greater than a certain minimum threshold, according to an embodiment, at the end of the period Tpk, the circuit waits until the input voltage reaches a minimum enabling value before being configured as a voltage buffer.
- By controlling the polarity of the leakage current, for example as shown in
FIG. 10 , it is possible to use the buffer configuration when tracking peak values smaller than the stored value. InFIG. 10 , theswitch 104 is implemented using aMOSFET transistor 126, an offsetvoltage source 128, and an op-amp 130 coupled to the body of thetransistor 120 in a voltage follower configuration. The offsetvoltage source 128 supplies an input voltage to the op-amp 130 that is offset so as to be slightly below the value VC stored on thecapacitor 102, which value is provided at the body terminal of thetransistor 126 by the op-amp 130. Accordingly, any leakage current of thetransistor 126 will tend to discharge thecapacitor 102. Additionally, because the voltage difference between the body of thetransistor 126 and thecapacitor 102 is small, leakage current is likewise very small. In this way, the ripple on the output voltage, generated when the peak detector circuit is switched in a buffer configuration before each peak event, is avoided, and the overall ripple produced by the peak detector circuit is minimal. - Further studies carried out by the inventors have shown an increase of input current distortion, when the Peak detector embodiment of
FIG. 8 is used in a PFC application. Total harmonic distortion (THD) increases if the peak detector output does not lock to the peak value of input voltage VMULT but to a random value. This happens in correspondence of the temporized mechanism activation. The worst case for THD is a possible tracking in correspondence of a valley as schematically shown in the time graph ofFIG. 11 . In order to obviate to this limitation, the circuit shown inFIG. 12 is proposed. The components having the same reference numerals as inFIG. 8 perform the same functions. - Differently from what is shown in
FIG. 8 , the circuit ofFIG. 12 comprises anauxiliary capacitor 102B, substantially identical to thetank capacitor 102 on which the voltage Vc is made available, that may be charged with the current delivered by the op-amp 112 when theauxiliary switch 104B is closed. Theauxiliary capacitor 102B, differently from thetank capacitor 102, is coupled atcomparator 106 and op-amp 112 inputs. The ORgate 118 receives the signal ov_th output ofcomparator 106 and acommand 136 for closing theswitch 104B when the charge voltage of theauxiliary capacitor 102B has to track the input voltage VMULT. Command 136, generated by thelogic circuit 134, is a pulse signal triggered when a time interval from a last active edge of ov_th signal has elapsed, in order to close theauxiliary switch 104B when the charge voltage VAUX of theauxiliary capacitor 102B remains greater than the input voltage VMULT, as in the circuit ofFIG. 8 . When the auxiliary command STORE generated by thelogic circuit 134 is high, it enables ov_th signal to close bothswitches Vc tank capacitor 102 andauxiliary capacitor 102B. When low, it prevents closure ofswitch 104 avoidingtank capacitor 102 refresh. It is forced low by thelogic circuit 134, for a fixed timing window, as a consequence of an internal temporization To elapsing; said temporization starts after last ov_th detection. In order to better understand how the circuit ofFIG. 12 operates, reference is made to the time graph ofFIG. 13 . As long as the input voltage VMULT has a peak value that exceeds the difference between the voltage VAUX (equal to the voltage Vc) and the offset VOS, theswitches tank capacitor 102 and theauxiliary capacitor 102B are charged at a same voltage. Thelogic circuit 134 waits for a time To and, if the charge voltage VAUX is greater than the input voltage VMULT, for all this time interval, it asserts thesignal 136 for closing theauxiliary switch 104B. The signal ov_th switches logically high but it is masked since auxiliary command STORE is forced low, thus theswitch 104 controlled by the logic ANDgate 132 remains open and only the charge voltage VAUX of the auxiliary capacitor is refreshed. Therefore, the charge voltages Vc and VAUX become different. After an internal temporization the auxiliary command STORE is released high. At the peak of the next half-wave of the input voltage VMULT, the signal ov_th switches again logically high and allows the refreshing of tank capacitor Vc exactly in correspondence of a peak of the input voltage VMULT. - The
logic circuit 134 comprises a timer for generating thesignal 136, a logic block that forces low the command STORE before assertion of thesignal 136 and an extra timer to ensure that the masking signal STORE is released high after a fixed time allowing both switches to close and both capacitors to track next input peak value as soon as ov_th goes again high. - The exemplary time graphs of
FIG. 14 compare the output voltage Vc of the circuit ofFIG. 8 (up) and of the circuit ofFIG. 12 (down) in case of an input voltage VMULT corrupted by a noise peak, indicated with an arrow. In both circuits the charge voltage Vc of the tank capacitor is refreshed in correspondence of the noise peak. While in the circuit ofFIG. 8 , the voltage Vc is refreshed as soon as the time interval To expires, in the circuit ofFIG. 12 the voltage Vc is refreshed only in correspondence of first input voltage peak following the refresh of the charge voltage VAUX of theauxiliary capacitor 102B after the end of the time interval To. The voltage Vc output by the circuit ofFIG. 12 is less distorted than the voltage Vc of the circuit ofFIG. 8 , thus leading to enhancement of THD figures. - The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/510,925 US9329209B1 (en) | 2014-10-09 | 2014-10-09 | Peak voltage detector and related method of generating an envelope voltage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/510,925 US9329209B1 (en) | 2014-10-09 | 2014-10-09 | Peak voltage detector and related method of generating an envelope voltage |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160103158A1 true US20160103158A1 (en) | 2016-04-14 |
US9329209B1 US9329209B1 (en) | 2016-05-03 |
Family
ID=55655281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/510,925 Active 2034-11-13 US9329209B1 (en) | 2014-10-09 | 2014-10-09 | Peak voltage detector and related method of generating an envelope voltage |
Country Status (1)
Country | Link |
---|---|
US (1) | US9329209B1 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105929720A (en) * | 2016-06-17 | 2016-09-07 | 山东理工大学 | Current tracking control method and device |
US20170117814A1 (en) * | 2015-03-06 | 2017-04-27 | Stmicroelectronics S.R.L. | Control method and device for quasi-rosonant high-power-factor flyback converter |
US9913329B2 (en) | 2016-06-30 | 2018-03-06 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter without analog divider and line-sensing |
US20180095493A1 (en) * | 2016-10-04 | 2018-04-05 | Rohm Co., Ltd. | Enable signal generation circuit |
CN107966604A (en) * | 2017-11-21 | 2018-04-27 | 广电计量检测(西安)有限公司 | Peak voltage triggering catches circuit and system |
US10128761B2 (en) | 2014-12-16 | 2018-11-13 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter |
US20190138758A1 (en) * | 2017-11-09 | 2019-05-09 | Texas Instruments Incorporated | Peak detector circuit |
CN111934654A (en) * | 2020-08-20 | 2020-11-13 | 桂林电子科技大学 | Ultra-high speed maximum detector based on FPGA |
CN113419102A (en) * | 2021-06-26 | 2021-09-21 | 广州金升阳科技有限公司 | Wave crest detection circuit and application thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10345348B2 (en) | 2014-11-04 | 2019-07-09 | Stmicroelectronics S.R.L. | Detection circuit for an active discharge circuit of an X-capacitor, related active discharge circuit, integrated circuit and method |
JP7059647B2 (en) * | 2018-01-24 | 2022-04-26 | 株式会社ソシオネクスト | Peak / bottom detection circuit, A / D converter and integrated circuit |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4086651A (en) | 1976-06-29 | 1978-04-25 | The Perkin-Elmer Corporation | Electrical output peak detecting apparatus |
US4445093A (en) | 1979-09-26 | 1984-04-24 | Toledo Transducers, Inc. | Press cycle monitor |
JPS62123365A (en) | 1985-11-22 | 1987-06-04 | Nec Corp | Peak hold circuit |
JP2503598B2 (en) | 1988-08-08 | 1996-06-05 | 日本電気株式会社 | Peak voltage holding circuit |
US5302863A (en) | 1993-01-29 | 1994-04-12 | Hewlett-Packard Company | CMOS peak amplitude detector |
US5757210A (en) | 1995-08-30 | 1998-05-26 | Cherry Semiconductor Corporation | Comparator with latch |
US6215334B1 (en) | 1997-10-24 | 2001-04-10 | General Electronics Applications, Inc. | Analog signal processing circuit with noise immunity and reduced delay |
US6512399B1 (en) | 2001-12-03 | 2003-01-28 | Brookhaven Science Associates Llc | Offset-free rail-to-rail derandomizing peak detect-and-hold circuit |
ITMI20042004A1 (en) * | 2004-10-21 | 2005-01-21 | St Microelectronics Srl | "DEVICE FOR CORRECTION OF THE POWER FACTOR IN FORCED SWITCHED FEEDERS." |
GB0501593D0 (en) | 2005-01-25 | 2005-03-02 | Innovision Res & Tech Plc | Demodulation apparatus and method |
WO2008018094A1 (en) | 2006-08-07 | 2008-02-14 | Stmicroelectronics S.R.L. | Control device for power factor correction device in forced switching power supplies |
US8743577B2 (en) | 2009-11-19 | 2014-06-03 | University Of Florida Research Foundation, Inc. | Method and apparatus for high efficiency AC/DC conversion of low voltage input |
-
2014
- 2014-10-09 US US14/510,925 patent/US9329209B1/en active Active
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10468991B2 (en) | 2014-12-16 | 2019-11-05 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter |
US10128761B2 (en) | 2014-12-16 | 2018-11-13 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter |
US20170117814A1 (en) * | 2015-03-06 | 2017-04-27 | Stmicroelectronics S.R.L. | Control method and device for quasi-rosonant high-power-factor flyback converter |
US10181796B2 (en) | 2015-03-06 | 2019-01-15 | Stmicroelectronics S.R.L. | Control method and device for quasi-resonant high-power-factor flyback converter |
US9973095B2 (en) * | 2015-03-06 | 2018-05-15 | Stmicroelectronics S.R.L. | Control method and device for quasi-resonant high-power-factor flyback converter |
CN105929720A (en) * | 2016-06-17 | 2016-09-07 | 山东理工大学 | Current tracking control method and device |
US10051698B2 (en) | 2016-06-30 | 2018-08-14 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter without analog divider and line-sensing |
US9913329B2 (en) | 2016-06-30 | 2018-03-06 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter without analog divider and line-sensing |
US10175714B2 (en) * | 2016-10-04 | 2019-01-08 | Rohm Co., Ltd. | Enable signal generation circuit |
US20180095493A1 (en) * | 2016-10-04 | 2018-04-05 | Rohm Co., Ltd. | Enable signal generation circuit |
US20190138758A1 (en) * | 2017-11-09 | 2019-05-09 | Texas Instruments Incorporated | Peak detector circuit |
US10395070B2 (en) * | 2017-11-09 | 2019-08-27 | Texas Instruments Incorporated | Peak detector circuit |
CN107966604A (en) * | 2017-11-21 | 2018-04-27 | 广电计量检测(西安)有限公司 | Peak voltage triggering catches circuit and system |
CN111934654A (en) * | 2020-08-20 | 2020-11-13 | 桂林电子科技大学 | Ultra-high speed maximum detector based on FPGA |
CN113419102A (en) * | 2021-06-26 | 2021-09-21 | 广州金升阳科技有限公司 | Wave crest detection circuit and application thereof |
Also Published As
Publication number | Publication date |
---|---|
US9329209B1 (en) | 2016-05-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9329209B1 (en) | Peak voltage detector and related method of generating an envelope voltage | |
US8884654B2 (en) | Peak voltage detector and related method of generating an envelope voltage | |
US10879791B2 (en) | DC/DC resonant converters and power factor correction using resonant converters, and corresponding control methods | |
US9065347B2 (en) | Controller for a switched mode power supply | |
CN109983686B (en) | Power converter controller with stability compensation | |
US9461558B2 (en) | Control device of a switching power supply | |
US10263510B2 (en) | DC/DC resonant converters and power factor correction using resonant converters, and corresponding control methods | |
EP3414823B1 (en) | Dc/dc resonant converters and power factor correction using resonant converters, and corresponding control methods | |
US9941792B2 (en) | DC offset correction for inductor current ripple based, constant-on-time DC-DC converters | |
US20160172979A1 (en) | Zero-crossing detection circuit and switching power supply thereof | |
US10734889B2 (en) | DC/DC resonant converters and power factor correction using resonant converters, and corresponding control methods | |
TWI700882B (en) | Circuit for use with a switching converter and method performed by a switching converter | |
EP3414822B1 (en) | Dc/dc resonant converters and power factor correction using resonant converters, and corresponding control methods | |
WO2017137342A1 (en) | Dc/dc resonant converters and power factor correction using resonant converters, and corresponding control methods | |
US11336201B2 (en) | Integrated circuit and power supply circuit | |
US20210175791A1 (en) | Integrated circuit and power supply circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: STMICROELECTRONICS S.R.L., ITALY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GRAVATI, MIRKO;TRIPODI, DOMENICO;SIGNING DATES FROM 20140919 TO 20140922;REEL/FRAME:034006/0157 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |