US20160099051A1 - Resistance change memory and forming method of the resistance change device - Google Patents
Resistance change memory and forming method of the resistance change device Download PDFInfo
- Publication number
- US20160099051A1 US20160099051A1 US14/967,457 US201514967457A US2016099051A1 US 20160099051 A1 US20160099051 A1 US 20160099051A1 US 201514967457 A US201514967457 A US 201514967457A US 2016099051 A1 US2016099051 A1 US 2016099051A1
- Authority
- US
- United States
- Prior art keywords
- electrode
- resistance change
- voltage
- forming treatment
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000015654 memory Effects 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title description 12
- 239000000463 material Substances 0.000 abstract description 22
- 150000004767 nitrides Chemical class 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000006185 dispersion Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 3
- 229910005855 NiOx Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/32—Material having simple binary metal oxide structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Definitions
- the present invention relates to a resistance change memory and a forming method of a resistance change device.
- Resistance change memories have been known as a kind of volatile memories (for example, refer to: W. W. Zhuang, et al., “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM, 7.5, pp. 193-196, 2002 (Non-Patent Document 1),
- Non-Patent Document 2 “Observation of electric-field induced Ni filament channels in polycrystalline NiO x film”, APL, Vol. 91, pp. 222103, 2007 (Non-Patent Document 2),
- Non-Patent Document 4 “High Thermal Robust ReRAM with a New Method for Suppressing Read Disturb”, 2011 Symposium on VLSI Technology, Digest of Technical Papers, pp. 50-51, 2011 (Non-Patent Document 4)).
- the resistance change memory uses a resistance change device as a memory cell and stores data based on the change of the resistance in a non-volatile manner.
- a typical resistance change device has a first electrode 110 , a second electrode 120 , and a resistance change layer 130 interposed between the first electrode 110 and the second electrode 120 .
- the resistance value of the resistance change layer 130 can be changed thereby capable of rewriting data.
- Non-Patent Document 1 a PCMO (Pr 0.7 Ca 0.3 MnO 3 ) film and a YBCO (YBa 2 Cu 3 O y ) film are used as the resistance change layer 130 .
- Non-Patent Document 3 a crystallite TiO 2 film of 80 nm thickness is used as the resistance change layer 130 .
- the material for the first electrode 110 is Ru and the material for the second electrode 120 is W.
- a treatment referred to as “forming” is necessary for initial setting. Forming is to form a conduction path referred to as “filament” in the resistance change layer 130 by application of a high voltage between the first electrode 110 and the second electrode 120 . It is considered that the filament is formed by collection of defects in the resistance change layer 130 .
- a filament 140 (conduction path) is formed in the resistance change layer 130 so as to connect the first electrode 110 and the second electrode 120 .
- the state corresponds to “an ON state” in which the resistance of the resistance change device is low. After the forming, ON/OFF switching is possible.
- a resistance change memory has a resistance change device and a control circuit for controlling voltage application to the resistance change memory.
- the resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode.
- the material for the second electrode includes one member selected from the group consisting of W, Ti, Ta and nitrides thereof.
- the control circuit performs a first forming treatment and a second forming treatment succeeding to the first forming method.
- the first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode.
- the second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
- a forming method of a resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode.
- the material for the second electrode includes one member selected from the group consisting of W, Ti, Ta, and nitrides thereof.
- the forming method includes a first forming treatment and a second forming treatment that is performed succeeding to the first forming treatment.
- the first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode.
- the second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
- a satisfactory filament is formed to suppress occurrence of a high ON resistance cell.
- dispersion of the resistance values is decreased to improve the characteristics of the resistance change memory.
- FIG. 1 is a conceptional view illustrating a forming method of a typical resistance change device
- FIG. 2 illustrates a configuration of a resistance change device according to a first embodiment
- FIG. 3 is a flow chart showing a forming method according to the first embodiment
- FIG. 4 is a schematic view illustrating a forming treatment according to the first embodiment
- FIG. 5 is a conceptional view showing an ON/OFF switching method of the resistance change device according to the first embodiment
- FIG. 6 is a graph for explaining the effect according to the first embodiment
- FIG. 7 is a graph for explaining the effect according to the first embodiment
- FIG. 8 is a flow chart illustrating a forming method according to a second embodiment
- FIG. 9 is a conceptional view showing a forming treatment according to the second embodiment.
- FIG. 10 is a graph for explaining the effect according to the second embodiment.
- FIG. 11 schematically illustrates a configuration of resistance change memory according to the embodiment
- FIG. 12 illustrates an example of voltage application to a memory cell array in the embodiment
- FIG. 13 illustrates another example of voltage application to the memory cell array in the embodiment
- FIG. 14 illustrates a further example of voltage application to the memory cell array in the embodiment.
- FIG. 15 illustrates a still further example of voltage application to the memory cell array in the embodiment:
- FIG. 2 illustrates a configuration of a resistance change device 1 according to a first embodiment.
- the resistance change device 1 has a first electrode 10 , a second electrode 20 , and a resistance change layer 30 interposed between the first electrode 10 and the second electrode 20 .
- the resistance value of the resistance change layer 30 can be switched by applying a voltage between the first electrode 10 and the second electrode 20 thereby capable of rewriting data.
- the material for the resistance change layer 30 includes insulators comprising, for example, Ta 2 O 5 , HfO 2 , ZrO 2 , TiO 2 , and Al 2 O 3 .
- the material for the first electrode 10 and the material for the second electrode 20 are different (asymmetric electrode).
- the material for the first electrode 10 comprises Ru or Pt and the material for the second electrode 20 comprises W, Ti, Ta, or nitrides thereof. The reason that the asymmetric electrode is preferred is to be described later.
- Various controls are performed by application of voltage on the first electrode 10 and the second electrode 20 .
- application of voltage such that the potential of the first electrode 10 is higher than the potential of the second electrode 20 is simply referred to as “positive voltage is applied on the first electrode 10 ”.
- application of voltage such that the potential of the second electrode 20 is higher than the potential of the first electrode 10 is simply referred to as “positive voltage is applied on the second electrode 20 ”.
- FIG. 3 is a flow chart illustrating a forming method according to the first embodiment.
- FIG. 4 is a conceptional view illustrating a forming treatment according to the first embodiment. The forming treatment according to the first embodiment is to be described specifically with reference to FIG. 3 and FIG. 4 .
- Step S 1 First Forming Treatment
- a first forming treatment is carried out.
- a first positive voltage VF 1 is applied on the first electrode 10 .
- electrons are injected from the second electrode 20 to the resistance change layer 30 .
- a filament 40 is formed so as to extend from the second electrode 20 to the inside of the resistance change layer 30 .
- the filament 40 when the filament 40 is not formed completely, electric connection between the first electrode 10 and the second electrode 20 is not complete. This means occurrence of a high ON resistance cell, which is not preferred with a view point of dispersion of the resistance values. Then, according to this embodiment, the following second forming treatment is carried out succeeding to the first forming treatment.
- Step S 2 Second Forming Treatment
- a voltage is applied in a direction opposite to that in the first forming treatment. That is, a second positive voltage VF 2 is applied on the second electrode 20 .
- electrons are injected from the first electrode 10 to the resistance change layer 30 .
- a filament 40 is formed also from the first electrode 10 , and connected with the filament 40 formed in the step 51 .
- the high resistance portion is eliminated to provide good electric connection between the first electrode 10 and the second electrode 20 . That is, occurrence of the high ON resistance cell is suppressed.
- the voltage is applied at least twice during forming. It can be said that the first forming treatment is preliminary forming and the second forming treatment is finish forming. Typically, the second positive voltage VF 2 applied in the finishing second forming treatment is equal to or is lower than the first positive voltage VF 1 applied in the first forming treatment (VF 2 ⁇ VF 1 ).
- the first forming treatment and the second forming treatment are carried out as a set. It is not judged after the first forming treatment whether the second forming treatment is carried or not in accordance with the state of electric conduction. This is for avoiding complexity of the treatment and the circuit configuration.
- FIG. 5 illustrates usual operation of the resistance change device 1 (ON/OFF switching) after the forming. Just after the forming, the first electrode 10 and the second electrode 20 are electrically conducted by way of a filament 40 and the resistance change device 1 is in “the ON state (low resistance state)”.
- Free energy for oxide formation in each of the electrodes is to be considered.
- the free energy for oxide formation is a value obtained by dividing the heat of reaction upon forming an oxide by the number of oxygen atoms of the oxide.
- the free energy for oxide formation of main electrode materials is as follows: Ti (472.5 kJ/mol)>Ta (409.2 kJ/mol)>TiN (303.5 kJ/mol)>W (280.1 kJ/mol)>Ru (152.5 kJ/mol).
- a positive voltage VF 2 is applied on the second electrode 20 in the second forming treatment succeeding to the first forming treatment.
- the filament 40 which has been preliminarily formed in the first forming treatment is disconnected, it should be meaningless.
- the material for the second electrode 20 those materials having high oxide forming energy and less generating off switching are used preferably.
- W, Ti, Ta and nitrides thereof are used preferably.
- materials such as W and Ti are suitable.
- the second electrode 20 is formed of a material that less generates OFF switching, a positive voltage Voff is applied on the first electrode 10 upon OFF switching (refer to FIG. 5 ) in usual operation.
- the first electrode 10 is preferably formed of a material that relatively tends to generate OFF switching, that is, a material having low free energy for oxide formation. Such material includes Ru and Pt.
- asymmetric electrode structure in which materials are different between the first electrode 10 and the second electrode 20 is preferred.
- the free energy for oxide formation is preferably lower in the first electrode 10 and higher in the second electrode 20 .
- the second forming treatment is carried out succeeding to the first forming treatment.
- a satisfactory filament 40 is formed to prevent occurrence of the high ON resistance cell.
- dispersion of the resistance values is decreased and read characteristics, etc. of the resistance change memory are improved.
- step S 2 OFF switching in the second forming treatment
- FIG. 6 and FIG. 7 illustrate Weibull distributions with respect to the resistance value of a number of cells (resistance change device) obtained as a result of the forming treatment.
- FIG. 6 illustrates a case where only the first forming treatment is carried out which corresponds to the case of the conventional technique.
- FIG. 7 illustrates a case where the second forming treatment is carried out succeeding to the first forming treatment.
- FIG. 8 is a flow chart showing a forming method according to a second embodiment.
- FIG. 9 is a conceptional view illustrating the forming treatment according to the second embodiment. The forming treatment according to the second embodiment is to be described with reference to FIG. 8 and FIG. 9 . Descriptions overlapping with those of the first embodiment are to be omitted optionally.
- the first forming treatment is performed in a multistage for lowering voltage and current.
- the first forming treatment includes a step S 1 a and a step S 1 b.
- Step S 1 a
- a positive voltage VF 1 a is applied on a second electrode 20 .
- electrons are injected from the first electrode 10 to the resistance change layer 30 .
- a filament 40 is formed so as to extend from the first electrode 10 to the resistance change layer 30 .
- the positive voltage VF 1 a may be lower than the first positive voltage VF 1 in the first embodiment.
- Step S 1 b
- a positive voltage VF 1 b is applied on the first electrode 10 .
- electrons are injected from the second electrode 20 to the resistance change layer 30 .
- a filament 40 is formed so as to extend from the second electrode 20 to the inside of the resistance change layer 30 .
- the positive voltage VF 1 b may be lower than the first positive voltage VF 1 in the first embodiment.
- step S 1 a and step S 1 b may be reversed.
- a second forming treatment (step S 2 ) and a usual operation (ON/OFF switching) are identical with those in the first embodiment.
- the following effect is also obtained in addition to the effect according to the first embodiment. That is, by increasing the number of steps of voltage application, the applied voltage and the applied current can be decreased in each of the cycles.
- FIG. 10 shows the change of the resistance value by application of voltage during forming.
- the abscissa denotes the number of steps of application of voltage and the ordinate denotes the resistance value.
- the filament 40 is formed and the ON state is achieved by the application of voltage during forming.
- the applied voltage and the applied current on each step cam be lowered when the forming is performed by application of voltage for three steps than that in the application of voltage for one step. That is, according to the second embodiment, the voltage and the current can be decreased.
- applied voltage during forming is higher than the applied voltage during usual operation. Accordingly, while a transistor size that can withstand forming is necessary, this is not always necessary in usual operation. When the voltage and current required for the forming treatment are decreased, the transistor size can also be reduced by so much. This is preferred with a view point of the circuit area and the manufacturing cost.
- FIG. 11 schematically illustrates a configuration of a resistance change memory according to the embodiment.
- the resistance change memory has a memory cell MC.
- the memory cell MC has a resistance change device 1 and a transistor 50 (1T-1R cell configuration).
- a first electrode 10 of the resistance change device 1 is connected to a common line PL.
- a drain electrode 51 of the transistor 50 is connected to a second electrode 20 of the resistance change device 1 .
- a source electrode 52 of the transistor 50 is connected to a bit line BL.
- a gate electrode 53 of the transistor 50 is connected to a word line WL.
- a control circuit 60 controls application of voltage to the resistance change device 1 .
- the control circuit 60 is connected to the bit line BL, the word line WL, and the common line PL.
- the control circuit 60 applies appropriate voltages to the bit line BL, the word line WL, and the common line PL to perform a first forming treatment, a second forming treatment, an ON switching, and an OFF switching respectively.
- the positive voltage is applied on the first electrode 10 as described below.
- the control circuit 60 applies a voltage at a high level to the word line WL.
- the transistor 50 turns ON to electrically connect the bit line BL and the second electrode 20 of the resistance change device 1 .
- the control circuit 60 applies a voltage at a high level to the common line PL and applies a voltage at a low level to the bit line BL.
- a positive voltage is applied on the first electrode 10 .
- the positive voltage is applied on the second electrode 20 as described below.
- the control circuit 60 applies a voltage at a high level to the word line WL.
- the transistor 50 turns ON to electrically connect the bit line BL and the second electrode 20 of the resistance change device 1 .
- the control circuit 60 applies a voltage at a low level to the common line PL and applies a voltage at a high level to the bit line BL.
- a positive voltage is applied on the second electrode 20 .
- the resistance change memory has a plurality of memory cells MC arranged in an array. Voltage is applied, for example, on every memory cell MC.
- the memory cell MC as a target of voltage application is hereinafter referred to as a selected memory cell MCs.
- the word lines WL, the bit line BL, and the common line PL connected to the selected memory cells MCs are referred to as a selected word line WLs, a selected bit line BLs, and a selected common line PLs, respectively,
- FIG. 12 illustrates a state when a positive voltage is applied on the first electrode 10 of the resistance change device 1 of the selected memory cell MCs, the control circuit 60 is not illustrated.
- the control circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a low level to the selected bit line BLs, and applies a voltage at a high level to the selected common line PLs.
- a positive voltage is applied on the first electrode 10 of the resistance change device 1 of the selected memory cell MCs.
- control circuit 60 applies a voltage at a low level to other word lines WL than the selected word line WLs. Further, the control circuit 60 applies a voltage at a low level to other bit lines BL than the selected bit line BLs, and applies a voltage at a low level to other common lines PL than the selected common line PLs. Thus, application of voltage between the first electrode 10 and the second electrode 20 in other memory cells MC than the selected memory cell MCs is inhibited.
- FIG. 13 illustrates a state when a positive voltage is applied on the second electrode 20 of the resistance change device 1 of the selected memory cell MCs.
- the control circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a high level to the selected bit line BLs, and applies a voltage at a low level to the selected common line PLs.
- a positive voltage is applied on the second electrode 20 of the resistance change device 1 of the selected memory cell MCs.
- control circuit 60 applies a voltage at a low level to other word lines WL than the selected word line WLs. Further, the control circuit 60 applies a voltage at a low level to other bit lines BL than the selected bit line BLs, and applies a voltage at a high level to other common lines PL than the selected common line PLs. Thus, application of voltage between the first electrode 10 and the second electrode 20 in other memory cells MC than the selected memory cell MCs is inhibited.
- the voltage may be applied collectively to a plurality of memory cells MC.
- voltage can be applied simultaneously also to all of the memory cells MC in the memory cell array.
- FIG. 14 illustrates a case in which a positive voltage is applied on the first electrode 10 of the resistance change device 1 in all of the memory cells MC.
- all of the memory cells MC are selected memory cells MCs.
- the control circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a low level to the selected bit line BLs, and applies a voltage at a high level to the selected common line PLs.
- a positive voltage is applied on the first electrode 10 of the resistance change device 1 in all of the memory cells MC.
- FIG. 15 illustrates a case in which a positive voltage is applied on the second electrode 20 of the resistance change device 1 in all of the memory cells MC.
- all of the memory cells MC are selected memory cells MCs.
- the control circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a high level to the selected bit line BLs, and applies a voltage at a low level to the selected common line PLs.
- the positive voltage is applied on the second electrode 20 of the resistance change device 1 in all of the memory cells MC.
- control circuit 60 can perform forming collectively to the plurality of memory cells MC (resistance change device 1 ). As a result, the processing time required for the forming to the entire resistance change memory can be shortened and the cost is also saved.
- the first forming treatment and the second forming treatment are performed as a set. Therefore, collective forming for the plurality of memory cells MC is possible.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
Description
- This application is a Continuation Application of U.S. application Ser. No. 13/905,951, filed on May 30, 2013, which claims priority under 35 U.S.C. §119 from Japanese Patent Application No. 2012-137826, filed on Jun. 19, 2012, in the Japanese Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
- The present invention relates to a resistance change memory and a forming method of a resistance change device.
- Resistance change memories (ReRAM: Resistance RAM) have been known as a kind of volatile memories (for example, refer to: W. W. Zhuang, et al., “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM, 7.5, pp. 193-196, 2002 (Non-Patent Document 1),
- G.-S. Park, et al., “Observation of electric-field induced Ni filament channels in polycrystalline NiOx film”, APL, Vol. 91, pp. 222103, 2007 (Non-Patent Document 2),
- C. Yoshida et al., “High speed resistive switching in Pt/TiO2/TiN film for nonvolatile memory application” APL, Vol. 91, pp. 223510, 2007 (Non-Patent Document 3), and
- M. Terai et al., “High Thermal Robust ReRAM with a New Method for Suppressing Read Disturb”, 2011 Symposium on VLSI Technology, Digest of Technical Papers, pp. 50-51, 2011 (Non-Patent Document 4)).
- The resistance change memory uses a resistance change device as a memory cell and stores data based on the change of the resistance in a non-volatile manner.
- As shown in
FIG. 1 , a typical resistance change device has afirst electrode 110, asecond electrode 120, and aresistance change layer 130 interposed between thefirst electrode 110 and thesecond electrode 120. By applying voltage between thefirst electrode 110 and thesecond electrode 120, the resistance value of theresistance change layer 130 can be changed thereby capable of rewriting data. - In the
Non-Patent Document 1, a PCMO (Pr0.7Ca0.3MnO3) film and a YBCO (YBa2Cu3Oy) film are used as theresistance change layer 130. - In the
Non-Patent Document 2, a polycrystal NiOx (x=1 to 1.5) film of about 50 nm thickness is used as theresistance change layer 130. - In the
Non-Patent Document 3, a crystallite TiO2 film of 80 nm thickness is used as theresistance change layer 130. - In the
Non-Patent Document 4, different materials are used for thefirst electrode 110 and the second electrode 120 (asymmetric electrode) with an aim of decreasing read disturb. For example, the material for thefirst electrode 110 is Ru and the material for thesecond electrode 120 is W. - When such a resistance change device is utilized, a treatment referred to as “forming” is necessary for initial setting. Forming is to form a conduction path referred to as “filament” in the
resistance change layer 130 by application of a high voltage between thefirst electrode 110 and thesecond electrode 120. It is considered that the filament is formed by collection of defects in theresistance change layer 130. - As illustrated in
FIG. 1 , a filament 140 (conduction path) is formed in theresistance change layer 130 so as to connect thefirst electrode 110 and thesecond electrode 120. The state corresponds to “an ON state” in which the resistance of the resistance change device is low. After the forming, ON/OFF switching is possible. - When the
filament 140 is not formed completely by the forming, electric connection between thefirst electrode 110 and thesecond electrode 120 is not complete. This means that a resistance change device of high ON resistance (high ON resistance cell) is formed. Increase of the high ON resistance cell varies the resistance value greatly, and imposes a problem of deteriorating read characteristics, etc. of the resistance change memory. - Other subjects and novel features of the invention will be apparent with reference to the description of the present specification and the accompanying drawings.
- According to an aspect of the present invention, there is provided a resistance change memory. The resistance change memory has a resistance change device and a control circuit for controlling voltage application to the resistance change memory. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. The material for the second electrode includes one member selected from the group consisting of W, Ti, Ta and nitrides thereof. In the forming of the resistance change device, the control circuit performs a first forming treatment and a second forming treatment succeeding to the first forming method. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
- According to another aspect of the present invention, there is provided a forming method of a resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. The material for the second electrode includes one member selected from the group consisting of W, Ti, Ta, and nitrides thereof. The forming method includes a first forming treatment and a second forming treatment that is performed succeeding to the first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
- In the forming of the resistance change device, a satisfactory filament is formed to suppress occurrence of a high ON resistance cell. As a result, dispersion of the resistance values is decreased to improve the characteristics of the resistance change memory.
-
FIG. 1 is a conceptional view illustrating a forming method of a typical resistance change device; -
FIG. 2 illustrates a configuration of a resistance change device according to a first embodiment; -
FIG. 3 is a flow chart showing a forming method according to the first embodiment; -
FIG. 4 is a schematic view illustrating a forming treatment according to the first embodiment; -
FIG. 5 is a conceptional view showing an ON/OFF switching method of the resistance change device according to the first embodiment; -
FIG. 6 is a graph for explaining the effect according to the first embodiment; -
FIG. 7 is a graph for explaining the effect according to the first embodiment; -
FIG. 8 is a flow chart illustrating a forming method according to a second embodiment; -
FIG. 9 is a conceptional view showing a forming treatment according to the second embodiment; -
FIG. 10 is a graph for explaining the effect according to the second embodiment; -
FIG. 11 schematically illustrates a configuration of resistance change memory according to the embodiment; -
FIG. 12 illustrates an example of voltage application to a memory cell array in the embodiment; -
FIG. 13 illustrates another example of voltage application to the memory cell array in the embodiment; -
FIG. 14 illustrates a further example of voltage application to the memory cell array in the embodiment; and -
FIG. 15 illustrates a still further example of voltage application to the memory cell array in the embodiment: - 1-1 Configuration of Resistance Change Device
-
FIG. 2 illustrates a configuration of aresistance change device 1 according to a first embodiment. Theresistance change device 1 has afirst electrode 10, asecond electrode 20, and aresistance change layer 30 interposed between thefirst electrode 10 and thesecond electrode 20. The resistance value of theresistance change layer 30 can be switched by applying a voltage between thefirst electrode 10 and thesecond electrode 20 thereby capable of rewriting data. - The material for the
resistance change layer 30 includes insulators comprising, for example, Ta2O5, HfO2, ZrO2, TiO2, and Al2O3. - It is preferred that the material for the
first electrode 10 and the material for thesecond electrode 20 are different (asymmetric electrode). For example, the material for thefirst electrode 10 comprises Ru or Pt and the material for thesecond electrode 20 comprises W, Ti, Ta, or nitrides thereof. The reason that the asymmetric electrode is preferred is to be described later. - Various controls are performed by application of voltage on the
first electrode 10 and thesecond electrode 20. In the following description, application of voltage such that the potential of thefirst electrode 10 is higher than the potential of thesecond electrode 20 is simply referred to as “positive voltage is applied on thefirst electrode 10”. On the contrary, application of voltage such that the potential of thesecond electrode 20 is higher than the potential of thefirst electrode 10 is simply referred to as “positive voltage is applied on thesecond electrode 20”. - 1-2 Forming Method
-
FIG. 3 is a flow chart illustrating a forming method according to the first embodiment.FIG. 4 is a conceptional view illustrating a forming treatment according to the first embodiment. The forming treatment according to the first embodiment is to be described specifically with reference toFIG. 3 andFIG. 4 . - Step S1: First Forming Treatment
- At first, a first forming treatment is carried out. In the first forming treatment, a first positive voltage VF1 is applied on the
first electrode 10. In this step, electrons are injected from thesecond electrode 20 to theresistance change layer 30. As a result, as shown inFIG. 4 , afilament 40 is formed so as to extend from thesecond electrode 20 to the inside of theresistance change layer 30. - However, when the
filament 40 is not formed completely, electric connection between thefirst electrode 10 and thesecond electrode 20 is not complete. This means occurrence of a high ON resistance cell, which is not preferred with a view point of dispersion of the resistance values. Then, according to this embodiment, the following second forming treatment is carried out succeeding to the first forming treatment. - Step S2: Second Forming Treatment
- In the second forming treatment succeeding to the first forming treatment, a voltage is applied in a direction opposite to that in the first forming treatment. That is, a second positive voltage VF2 is applied on the
second electrode 20. In this step, electrons are injected from thefirst electrode 10 to theresistance change layer 30. As a result, as shown inFIG. 4 , afilament 40 is formed also from thefirst electrode 10, and connected with thefilament 40 formed in thestep 51. Thus, the high resistance portion is eliminated to provide good electric connection between thefirst electrode 10 and thesecond electrode 20. That is, occurrence of the high ON resistance cell is suppressed. - As described above according to this embodiment, the voltage is applied at least twice during forming. It can be said that the first forming treatment is preliminary forming and the second forming treatment is finish forming. Typically, the second positive voltage VF2 applied in the finishing second forming treatment is equal to or is lower than the first positive voltage VF1 applied in the first forming treatment (VF2≦VF1). The first forming treatment and the second forming treatment are carried out as a set. It is not judged after the first forming treatment whether the second forming treatment is carried or not in accordance with the state of electric conduction. This is for avoiding complexity of the treatment and the circuit configuration.
-
FIG. 5 illustrates usual operation of the resistance change device 1 (ON/OFF switching) after the forming. Just after the forming, thefirst electrode 10 and thesecond electrode 20 are electrically conducted by way of afilament 40 and theresistance change device 1 is in “the ON state (low resistance state)”. - When a positive voltage Voff is applied on the
first electrode 10 in theresistance change device 1 in the ON state, a portion of thefilament 40 is disconnected near thefirst electrode 10 on the positive side. Thus, the resistance value of theresistance change device 1 increases greatly. This is “an OFF state (high resistance state)” and change of the state of theresistance change device 1 from “the ON state (low resistance state)” to “the OFF state (high resistance state)” is “OFF switching”. - On the contrary, change of the state of the
resistance change device 1 from “the OFF state (high resistance state)” to “the ON state (low resistance state)” is “ON switching”. In the state of ON switching, a positive voltage Von is applied on thesecond electrode 20. It should be noted that the direction of the application of voltage is identical with the case of the second forming treatment described above. As a result of application of the positive voltage Von on thesecond electrode 20, thefilament 40 is formed again at the disconnected position to recover the electric connection between thefirst electrode 10 and thesecond electrode 20. That is, the state of theresistance change device 1 is again turned to “ON state (low resistance state)”. - 1-3 Free Energy for Oxide Formation
- “Free energy for oxide formation” in each of the electrodes is to be considered. The free energy for oxide formation is a value obtained by dividing the heat of reaction upon forming an oxide by the number of oxygen atoms of the oxide. The free energy for oxide formation of main electrode materials is as follows: Ti (472.5 kJ/mol)>Ta (409.2 kJ/mol)>TiN (303.5 kJ/mol)>W (280.1 kJ/mol)>Ru (152.5 kJ/mol).
- It is reported that when the free energy for oxide formation in the electrode is high, even if a positive voltage is applied to the electrode, Off switching (disconnection of filament 40) is less generated (for example, refer to the Non-Patent Document 4). Accordingly, it can be said that materials such as Ti, Ta, TiN, and W are electrode materials that less generates off switching. On the other hand, it can be said that Ru is an electrode material that relatively tends to generate OFF switching.
- As has been described above according to this embodiment, a positive voltage VF2 is applied on the
second electrode 20 in the second forming treatment succeeding to the first forming treatment. In this case, if thefilament 40 which has been preliminarily formed in the first forming treatment is disconnected, it should be meaningless. Then, as the material for thesecond electrode 20, those materials having high oxide forming energy and less generating off switching are used preferably. Specifically, as the material for thesecond electrode 20, W, Ti, Ta and nitrides thereof are used preferably. For example, materials such as W and Ti are suitable. By using such materials for thesecond electrode 20, OFF switching can be prevented in the second forming treatment. - Further, since the
second electrode 20 is formed of a material that less generates OFF switching, a positive voltage Voff is applied on thefirst electrode 10 upon OFF switching (refer toFIG. 5 ) in usual operation. Accordingly, thefirst electrode 10 is preferably formed of a material that relatively tends to generate OFF switching, that is, a material having low free energy for oxide formation. Such material includes Ru and Pt. - As described above, with a view point of OFF switching, “asymmetric electrode structure” in which materials are different between the
first electrode 10 and thesecond electrode 20 is preferred. The free energy for oxide formation is preferably lower in thefirst electrode 10 and higher in thesecond electrode 20. - 1-4 Effect
- As has been described above, according to this embodiment, the second forming treatment is carried out succeeding to the first forming treatment. As a result, a
satisfactory filament 40 is formed to prevent occurrence of the high ON resistance cell. As a result, dispersion of the resistance values is decreased and read characteristics, etc. of the resistance change memory are improved. - Further, due to the asymmetric electrode structure, OFF switching in the second forming treatment (step S2) can be prevented to achieve appropriate forming.
-
FIG. 6 andFIG. 7 illustrate Weibull distributions with respect to the resistance value of a number of cells (resistance change device) obtained as a result of the forming treatment.FIG. 6 illustrates a case where only the first forming treatment is carried out which corresponds to the case of the conventional technique. On the other hand,FIG. 7 illustrates a case where the second forming treatment is carried out succeeding to the first forming treatment. - In
FIG. 6 , considerable number of high ON resistance cells which are caused as a result of incomplete forming are confirmed. Due to the presence of the high ON resistance cells, dispersion of the resistance values increases. However, it can be seen fromFIG. 7 that the high ON resistance cells are decreased greatly by performing the second forming treatment and the dispersion of the resistance values can be suppressed. That is, according to this embodiment, dispersion of the resistance values is decreased and characteristics of the resistance change memory are improved. -
FIG. 8 is a flow chart showing a forming method according to a second embodiment.FIG. 9 is a conceptional view illustrating the forming treatment according to the second embodiment. The forming treatment according to the second embodiment is to be described with reference toFIG. 8 andFIG. 9 . Descriptions overlapping with those of the first embodiment are to be omitted optionally. - In the second embodiment, the first forming treatment is performed in a multistage for lowering voltage and current. Specifically, the first forming treatment (step S1) includes a step S1 a and a step S1 b.
- Step S1 a:
- A positive voltage VF1 a is applied on a
second electrode 20. In this case, electrons are injected from thefirst electrode 10 to theresistance change layer 30. As a result, as shown inFIG. 9 , afilament 40 is formed so as to extend from thefirst electrode 10 to theresistance change layer 30. The positive voltage VF1 a may be lower than the first positive voltage VF1 in the first embodiment. - Step S1 b:
- A positive voltage VF1 b is applied on the
first electrode 10. In this step, electrons are injected from thesecond electrode 20 to theresistance change layer 30. As a result, as shown inFIG. 9 , afilament 40 is formed so as to extend from thesecond electrode 20 to the inside of theresistance change layer 30. The positive voltage VF1 b may be lower than the first positive voltage VF1 in the first embodiment. - The sequence of the step S1 a and step S1 b may be reversed.
- A second forming treatment (step S2) and a usual operation (ON/OFF switching) are identical with those in the first embodiment.
- According to the second embodiment, the following effect is also obtained in addition to the effect according to the first embodiment. That is, by increasing the number of steps of voltage application, the applied voltage and the applied current can be decreased in each of the cycles.
-
FIG. 10 shows the change of the resistance value by application of voltage during forming. The abscissa denotes the number of steps of application of voltage and the ordinate denotes the resistance value. It can be seen that thefilament 40 is formed and the ON state is achieved by the application of voltage during forming. Further, it can be seen that the applied voltage and the applied current on each step cam be lowered when the forming is performed by application of voltage for three steps than that in the application of voltage for one step. That is, according to the second embodiment, the voltage and the current can be decreased. - Generally, applied voltage during forming is higher than the applied voltage during usual operation. Accordingly, while a transistor size that can withstand forming is necessary, this is not always necessary in usual operation. When the voltage and current required for the forming treatment are decreased, the transistor size can also be reduced by so much. This is preferred with a view point of the circuit area and the manufacturing cost.
-
FIG. 11 schematically illustrates a configuration of a resistance change memory according to the embodiment. The resistance change memory has a memory cell MC. The memory cell MC has aresistance change device 1 and a transistor 50 (1T-1R cell configuration). Afirst electrode 10 of theresistance change device 1 is connected to a common line PL. Adrain electrode 51 of thetransistor 50 is connected to asecond electrode 20 of theresistance change device 1. Asource electrode 52 of thetransistor 50 is connected to a bit line BL. Agate electrode 53 of thetransistor 50 is connected to a word line WL. - A
control circuit 60 controls application of voltage to theresistance change device 1. Specifically, thecontrol circuit 60 is connected to the bit line BL, the word line WL, and the common line PL. Thecontrol circuit 60 applies appropriate voltages to the bit line BL, the word line WL, and the common line PL to perform a first forming treatment, a second forming treatment, an ON switching, and an OFF switching respectively. - The positive voltage is applied on the
first electrode 10 as described below. Thecontrol circuit 60 applies a voltage at a high level to the word line WL. As a result, thetransistor 50 turns ON to electrically connect the bit line BL and thesecond electrode 20 of theresistance change device 1. Further, thecontrol circuit 60 applies a voltage at a high level to the common line PL and applies a voltage at a low level to the bit line BL. Thus, a positive voltage is applied on thefirst electrode 10. - The positive voltage is applied on the
second electrode 20 as described below. Thecontrol circuit 60 applies a voltage at a high level to the word line WL. As a result, thetransistor 50 turns ON to electrically connect the bit line BL and thesecond electrode 20 of theresistance change device 1. Further, thecontrol circuit 60 applies a voltage at a low level to the common line PL and applies a voltage at a high level to the bit line BL. Thus, a positive voltage is applied on thesecond electrode 20. - 3-1 Voltage Application on Every Memory Cell
- The resistance change memory has a plurality of memory cells MC arranged in an array. Voltage is applied, for example, on every memory cell MC. The memory cell MC as a target of voltage application is hereinafter referred to as a selected memory cell MCs. Further, the word lines WL, the bit line BL, and the common line PL connected to the selected memory cells MCs are referred to as a selected word line WLs, a selected bit line BLs, and a selected common line PLs, respectively,
-
FIG. 12 illustrates a state when a positive voltage is applied on thefirst electrode 10 of theresistance change device 1 of the selected memory cell MCs, thecontrol circuit 60 is not illustrated. Thecontrol circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a low level to the selected bit line BLs, and applies a voltage at a high level to the selected common line PLs. Thus, a positive voltage is applied on thefirst electrode 10 of theresistance change device 1 of the selected memory cell MCs. - Further, the
control circuit 60 applies a voltage at a low level to other word lines WL than the selected word line WLs. Further, thecontrol circuit 60 applies a voltage at a low level to other bit lines BL than the selected bit line BLs, and applies a voltage at a low level to other common lines PL than the selected common line PLs. Thus, application of voltage between thefirst electrode 10 and thesecond electrode 20 in other memory cells MC than the selected memory cell MCs is inhibited. -
FIG. 13 illustrates a state when a positive voltage is applied on thesecond electrode 20 of theresistance change device 1 of the selected memory cell MCs. Thecontrol circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a high level to the selected bit line BLs, and applies a voltage at a low level to the selected common line PLs. Thus, a positive voltage is applied on thesecond electrode 20 of theresistance change device 1 of the selected memory cell MCs. - Further, the
control circuit 60 applies a voltage at a low level to other word lines WL than the selected word line WLs. Further, thecontrol circuit 60 applies a voltage at a low level to other bit lines BL than the selected bit line BLs, and applies a voltage at a high level to other common lines PL than the selected common line PLs. Thus, application of voltage between thefirst electrode 10 and thesecond electrode 20 in other memory cells MC than the selected memory cell MCs is inhibited. - 3-2 Collective Voltage Application to a Plurality of Memory Cells
- The voltage may be applied collectively to a plurality of memory cells MC. For example, voltage can be applied simultaneously also to all of the memory cells MC in the memory cell array.
-
FIG. 14 illustrates a case in which a positive voltage is applied on thefirst electrode 10 of theresistance change device 1 in all of the memory cells MC. In this case, all of the memory cells MC are selected memory cells MCs. Thecontrol circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a low level to the selected bit line BLs, and applies a voltage at a high level to the selected common line PLs. Thus, a positive voltage is applied on thefirst electrode 10 of theresistance change device 1 in all of the memory cells MC. -
FIG. 15 illustrates a case in which a positive voltage is applied on thesecond electrode 20 of theresistance change device 1 in all of the memory cells MC. In this case, all of the memory cells MC are selected memory cells MCs. Thecontrol circuit 60 applies a voltage at a high level to the selected word line WLs, applies a voltage at a high level to the selected bit line BLs, and applies a voltage at a low level to the selected common line PLs. Thus, the positive voltage is applied on thesecond electrode 20 of theresistance change device 1 in all of the memory cells MC. - By the voltage application as described above, the
control circuit 60 can perform forming collectively to the plurality of memory cells MC (resistance change device 1). As a result, the processing time required for the forming to the entire resistance change memory can be shortened and the cost is also saved. - In this embodiment, it is not judged after the first forming treatment whether the second forming treatment is performed or not in accordance with the state of electric conduction. The first forming treatment and the second forming treatment are performed as a set. Therefore, collective forming for the plurality of memory cells MC is possible.
- While the invention made by the present inventors has been described specifically with reference to the preferred embodiments, it will be apparent that the invention is not restricted to the embodiments but can be modified variously within a range not departing the gist thereof.
Claims (14)
1. A resistance change memory comprising:
a resistance change device including a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode; and
a control circuit configured to perform a first forming treatment to form an initial first portion of a filament between the first electrode and the second electrode and then a second forming treatment to form an initial second portion of the filament.
2. The resistance change memory according to claim 1 , wherein the initial second portion electrically connects the initial first portion to the second electrode.
3. The resistance change memory according to claim 1 , wherein the filament formed by the initial first portion and the initial second portion electrically connects the first electrode to the second electrode.
4. The resistance change memory according to claim 1 , wherein the first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode, and the second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
5. The resistance change memory according to claim 4 , wherein the first forming treatment further includes application of voltage such that the potential on the second electrode is higher than the potential on the first electrode.
6. A resistance change memory comprising:
a resistance change device including a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode; and
a control circuit configured to perform an initial first forming treatment to form a first portion of the resistance change device and then an initial second forming treatment to form a second portion of the resistance change device,
wherein the first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode, and the second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
7. The resistance change memory according to claim 6 , wherein the second portion electrically connects the first portion to the second electrode.
8. The resistance change memory according to claim 6 , wherein the first portion and the second portion of the resistance change device together form a filament that electrically connects the first electrode to the second electrode.
9. The resistance change memory according to claim 6 , wherein the first forming treatment further includes application of voltage such that the potential on the second electrode is higher than the potential on the first electrode.
10. A resistance change memory comprising:
a resistance change device including a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode; and
a control circuit configured to create a two-part filament in the resistance change layer that electrically connects the first electrode and the second electrode by performing a first forming treatment to form a first part of the two-part filament and performing a second forming treatment different from the first forming treatment to form a second part of the two-part filament.
11. The resistance change memory according to claim 10 , wherein the control circuit is configured to form the second part of the two-part filament after the first part of the two-part filament is already formed.
12. The resistance change memory according to claim 10 , wherein, prior to the control circuit forming the two-part filament, there is no filament in the resistance change layer.
13. The resistance change memory according to claim 10 , wherein the second part of the two-part filament electrically connects the first part of the two-part filament to the second electrode.
14. The resistance change memory according to claim 10 , wherein the first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode, and the second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/967,457 US20160099051A1 (en) | 2012-06-19 | 2015-12-14 | Resistance change memory and forming method of the resistance change device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012137826A JP5909155B2 (en) | 2012-06-19 | 2012-06-19 | Resistance change type memory and resistance change element forming method |
JP2012-137826 | 2012-06-19 | ||
US13/905,951 US9305641B2 (en) | 2012-06-19 | 2013-05-30 | Resistance change memory and forming method of the resistance change device |
US14/967,457 US20160099051A1 (en) | 2012-06-19 | 2015-12-14 | Resistance change memory and forming method of the resistance change device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/905,951 Continuation US9305641B2 (en) | 2012-06-19 | 2013-05-30 | Resistance change memory and forming method of the resistance change device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160099051A1 true US20160099051A1 (en) | 2016-04-07 |
Family
ID=49755763
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/905,951 Expired - Fee Related US9305641B2 (en) | 2012-06-19 | 2013-05-30 | Resistance change memory and forming method of the resistance change device |
US14/967,457 Abandoned US20160099051A1 (en) | 2012-06-19 | 2015-12-14 | Resistance change memory and forming method of the resistance change device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/905,951 Expired - Fee Related US9305641B2 (en) | 2012-06-19 | 2013-05-30 | Resistance change memory and forming method of the resistance change device |
Country Status (3)
Country | Link |
---|---|
US (2) | US9305641B2 (en) |
JP (1) | JP5909155B2 (en) |
CN (1) | CN103514950B (en) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7426128B2 (en) * | 2005-07-11 | 2008-09-16 | Sandisk 3D Llc | Switchable resistive memory with opposite polarity write pulses |
JP4967176B2 (en) | 2007-05-10 | 2012-07-04 | シャープ株式会社 | Variable resistance element, method of manufacturing the same, and nonvolatile semiconductor memory device |
JP2010055719A (en) | 2008-08-29 | 2010-03-11 | Toshiba Corp | Resistance change memory device |
JP2011146111A (en) * | 2010-01-18 | 2011-07-28 | Toshiba Corp | Nonvolatile storage device and method for manufacturing the same |
JP5291248B2 (en) * | 2010-03-30 | 2013-09-18 | パナソニック株式会社 | Method of forming variable resistance nonvolatile memory element and variable resistance nonvolatile memory device |
US8395926B2 (en) * | 2010-06-18 | 2013-03-12 | Sandisk 3D Llc | Memory cell with resistance-switching layers and lateral arrangement |
JP5723253B2 (en) * | 2011-01-31 | 2015-05-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2012
- 2012-06-19 JP JP2012137826A patent/JP5909155B2/en not_active Expired - Fee Related
-
2013
- 2013-05-30 US US13/905,951 patent/US9305641B2/en not_active Expired - Fee Related
- 2013-06-18 CN CN201310240843.4A patent/CN103514950B/en not_active Expired - Fee Related
-
2015
- 2015-12-14 US US14/967,457 patent/US20160099051A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CN103514950A (en) | 2014-01-15 |
US9305641B2 (en) | 2016-04-05 |
CN103514950B (en) | 2018-04-24 |
US20130336043A1 (en) | 2013-12-19 |
JP2014002820A (en) | 2014-01-09 |
JP5909155B2 (en) | 2016-04-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9029187B1 (en) | Using multi-layer MIMCAPs with defective barrier layers as selector element for a cross bar memory array | |
US20190019551A1 (en) | Nonvolatile memory device and method of operating nonvolatile memory device | |
KR102118768B1 (en) | Three or more resistive state random access memory cell | |
US9734902B2 (en) | Resistive memory device with ramp-up/ramp-down program/erase pulse | |
US9087582B2 (en) | Driving method of non-volatile memory element and non-volatile memory device | |
TWI433362B (en) | Nonvolatile semiconductor memory device | |
US8279656B2 (en) | Nonvolatile stacked nand memory | |
US20110176351A1 (en) | Nonvolatile memory device and method for manufacturing same | |
US20130223131A1 (en) | Method for driving variable resistance element, and nonvolatile memory device | |
Li et al. | Utilizing sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication | |
US20120243292A1 (en) | Memory device | |
US8331137B2 (en) | Nonvolatile semiconductor memory device | |
US8514607B2 (en) | Semiconductor memory device | |
US20150137062A1 (en) | Mimcaps with quantum wells as selector elements for crossbar memory arrays | |
US20140353566A1 (en) | ReRAM materials stack for low-operating-power and high-density applications | |
US9917250B2 (en) | Switching device, method of fabricating the same, and resistive random access memory including the switching device as a selection device | |
US20130228737A1 (en) | Nonvolatile semiconductor memory device and method of manufacturing same | |
US10783962B2 (en) | Resistive memory storage apparatus and writing method thereof including disturbance voltage | |
US9305641B2 (en) | Resistance change memory and forming method of the resistance change device | |
US20240015989A1 (en) | Semiconductor device | |
US20140185357A1 (en) | Barrier Design for Steering Elements | |
KR101307253B1 (en) | Method for recording resistance switching element, method for manufacturing resistance switching element and resistance switching element having the same | |
JP2014063549A (en) | Semiconductor storage device | |
US9275913B2 (en) | Memory arrays for both good data retention and low power operation | |
US20160189776A1 (en) | Nonvolatile semiconductor memory device and method of controlling the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |