US20160012870A1 - Static memory apparatus and data reading method thereof - Google Patents
Static memory apparatus and data reading method thereof Download PDFInfo
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- US20160012870A1 US20160012870A1 US14/457,125 US201414457125A US2016012870A1 US 20160012870 A1 US20160012870 A1 US 20160012870A1 US 201414457125 A US201414457125 A US 201414457125A US 2016012870 A1 US2016012870 A1 US 2016012870A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
Definitions
- the invention relates to a static memory apparatus and more particularly relates to a data reading method of the static memory apparatus.
- FIG. 1 is a block diagram of a conventional static memory apparatus.
- a static memory apparatus 100 is a static random access memory apparatus, which includes a plurality of memory cells 111 - 11 M, a plurality of dummy memory cells 121 - 122 , and a sense amplifier 130 .
- the memory cells 111 - 11 M form a memory array 110 and are coupled to the sense amplifier 130 via bit lines BL 1 and BL 1 B.
- a dummy bit line DBL coupled to the dummy memory cells 121 - 122 is connected with an input end of an inverter INV 1 , and an output end of the inverter INV 1 is coupled to the sense amplifier 130 and provides an enable signal EN for enabling a sensing and amplifying operation of the sense amplifier 130 .
- a voltage level of a signal transmitted by the dummy bit line DBL is lowered correspondingly, and the sensing and amplifying operation of the sense amplifier 130 is enabled by the enable signal EN that is raised correspondingly. Meanwhile, the sense amplifier 130 senses and amplifies a difference between signals on the bit lines BL 1 and BL 1 B, so as to obtain readout data.
- the invention provides a static memory apparatus and a data reading method thereof for effectively reducing data reading errors.
- the static memory apparatus of the invention includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster.
- the memory cells are arranged in a memory array that is coupled to a plurality of bit lines.
- the dummy memory cells are coupled to a dummy bit line and respectively include a plurality discharge ends for discharging charges on the dummy bit line.
- the sense amplifier is coupled to the bit lines and the dummy bit line and performs a sensing and amplifying operation on signals on the bit lines according to a signal on the dummy bit line, so as to generate readout data.
- the discharge current adjuster is coupled to at least one controlled discharge end of the discharge ends and adjusts a discharge current on the at least one controlled discharge end according to an operating voltage received by the memory cells.
- the invention provides a data reading method of a static memory apparatus, wherein the static memory apparatus includes a plurality of dummy memory cells, and the dummy memory cells respectively include a plurality of discharge ends.
- the data reading method includes: adjusting a discharge current on at least one controlled discharge end of the discharge ends when the static memory apparatus performs a data reading operation, wherein the discharge ends discharge charges on a dummy bit line.
- a signal on the dummy bit line is provided to enable a sense amplifier to perform a sensing and amplifying operation on signals on a plurality of bit lines, so as to generate readout data.
- the invention when performing the data reading operation, the invention adjusts the discharge current which is discharged from the dummy bit line by the discharge ends in one or multiple dummy memory cells according to the operating voltage, and thereby delays the signal on the dummy bit line. Therefore, a time point that the sense amplifier is enabled is adjusted properly in accordance with the operating voltage, so as to effectively prevent data reading errors that occur because the sense amplifier is enabled too early due to overly low operating voltage, thereby maintaining a proper operation of the static memory apparatus.
- FIG. 1 is a block diagram of a conventional static memory apparatus.
- FIG. 2 is a schematic diagram of a static memory apparatus according to an embodiment of the invention.
- FIG. 3A and FIG. 3B are schematic diagrams illustrating different implementations of a discharge current adjuster according to embodiments of the invention.
- FIG. 4 is a schematic diagram of a bias voltage adjuster according to an embodiment of the invention.
- FIG. 5A to FIG. 5D are schematic diagrams illustrating a voltage dividing circuit according to an embodiment of the invention.
- FIG. 6 is a schematic diagram of a static memory apparatus according to another embodiment of the invention.
- FIG. 7A and FIG. 7B are schematic diagrams respectively illustrating a dummy memory cell according to an embodiment of the invention.
- FIG. 8 is a flowchart illustrating a data reading method of the static memory apparatus according to an embodiment of the invention.
- FIG. 2 is a schematic diagram of a static memory apparatus according to an embodiment of the invention.
- a static memory apparatus 200 includes a plurality of memory cells 211 - 21 M, a plurality of dummy memory cells 221 - 22 N, a sense amplifier 230 , and a discharge current adjuster 240 .
- the memory cells 211 - 21 M are arranged in a memory array 210 , and the memory cells 211 - 21 M are memory cells of a static random access memory.
- the memory array 210 is coupled to a plurality of bit lines BL 1 and BL 1 B.
- the dummy memory cells 221 - 22 N are coupled to a dummy bit line DBL and the dummy bit line DBL is coupled to the sense amplifier 230 .
- the sense amplifier 230 is further coupled to the bit lines BL 1 and BL 1 B and enabled to perform a sensing and amplifying operation on signals on the bit lines BL 1 and BL 1 B according to a signal on the dummy bit line DBL, so as to obtain readout data.
- the dummy memory cells 221 - 22 N respectively include discharge ends CDT 1 -CDTN.
- the discharge ends CDT 1 -CDTN cause the signal on the dummy bit line DBL to perform a discharging operation respectively via circuits in the dummy memory cells 221 - 22 N.
- At least one or multiple controlled discharge ends of the discharge ends CDT 1 -CDTN (in this embodiment, the controlled discharge ends are discharge ends CDT 1 and CDT 2 ) are coupled to the discharge current adjuster 240 , and the discharge current adjuster 240 adjusts a discharge current generated between the controlled discharge ends (the discharge ends CDT 1 and CDT 2 ) and a reference ground voltage GND.
- the discharge end not coupled to the discharge current adjuster 240 (e.g. the discharge end CDTN) is directly coupled to the reference ground voltage GND.
- the static memory apparatus 200 executes a data reading operation
- the dummy memory cells 221 - 22 N cause the discharging operation between the dummy bit line DBL and the discharge ends CDT 1 -CDTN to begin respectively according to dummy word line signals DWL 1 -DWLN received.
- the discharge current adjuster 240 turns on a discharge current adjusting mechanism between the discharge ends CDT 1 and CDT 2 and the reference ground voltage GND.
- a current value of the discharge current provided by the discharge current adjuster 240 is smaller than a current value of the discharge current that the discharge end CDTN directly discharges the reference ground voltage GND.
- the static memory apparatus 200 provides the corresponding discharge current of the discharge current adjuster 240 according to the operating voltage VDD received by the dummy memory cells 221 - 22 N and the memory cells 211 - 21 M and a process temperature variation. More specifically, when the voltage value of the operating voltage VDD gets lower, the current value of the discharge current provided by the discharge current adjuster 240 becomes lower, and the current value of the discharge current is determined according to the discharge current of the weakest memory cell of the memory cells 211 - 21 M.
- the sense amplifier 230 can be enabled at a time point when the difference between the voltage levels of the signals on a pair of bit lines coupled to the weakest memory cell can be accurately sensed, so as to obtain the readout data accurately.
- the discharge current adjuster 240 divides the operating voltage VDD and adjusts the current value of the discharge current according to a division result thereof. Accordingly, the time point of enabling the sense amplifier 230 can be adjusted properly according to the operating voltage VDD, so as to effectively prevent data reading errors caused by change of the operating voltage VDD.
- FIG. 3A and FIG. 3B are schematic diagrams illustrating different implementations of the discharge current adjuster according to embodiments of the invention.
- a discharge current adjuster 301 includes a bias voltage adjuster 310 and a variable resistor VR 1 .
- the bias voltage adjuster 310 provides a bias voltage VB and transmits the bias voltage VB to the variable resistor VR 1 .
- the variable resistor VR 1 adjusts a resistance value thereof according to the bias voltage VB.
- the bias voltage VB can be equal to the operating voltage VDD.
- the bias voltage adjuster 310 when the static memory apparatus performs the data reading operation, the bias voltage adjuster 310 enables an adjusting operation of the bias voltage VB according to a bias voltage adjusting signal BEN, and the bias voltage adjuster 310 divides the operating voltage VDD to lower the voltage value of the bias voltage VB.
- the variable resistor VR 1 raises the resistance value thereof according to the lowered bias voltage VB and thereby lowers the discharge current value between the discharge end CDT 1 and the reference ground voltage GND.
- a discharge current adjuster 302 includes a bias voltage adjuster 320 and a variable resistor VR 2 .
- the variable resistor VR 2 is formed by a transistor M 1 , wherein a first end (e.g. a source) and a second end (e.g. a drain) of the transistor M 1 are connected in series between the discharge end CDT 1 and the reference ground voltage GND, and a control end (e.g. a gate) of the transistor M 1 receives the bias voltage VB.
- the transistor M 1 is an N type transistor.
- FIG. 4 is a schematic diagram of a bias voltage adjuster according to an embodiment of the invention.
- a bias voltage adjuster 400 includes a voltage dividing circuit 410 , transistors MA 1 -MA 3 , and an inverter INV 2 .
- the transistors MA 1 and MA 2 respectively serve as switches, wherein the transistor MA 1 is coupled to a path of an end PT of the voltage dividing circuit 410 receiving the operating voltage VDD, and the transistor MA 2 is coupled to a path of an end NT of the voltage dividing circuit 410 receiving the reference ground voltage GND.
- An input end of the inverter INV 2 receives the bias voltage adjusting signal BEN, and an output end of the inverter INV 2 generates an inverted bias voltage adjusting signal to control a turn-on or turn-off operation of the transistor MA 1 . Moreover, a turn-on or turn-off operation of the transistor MA 2 is determined by the bias voltage adjusting signal BEN.
- the transistor MA 3 is a pull-up circuit and receives the bias voltage adjusting signal BEN to determine whether to be turned on, and when the transistor MA 3 is turned on, the bias voltage VB is pulled up to be equal to the operating voltage VDD.
- the transistors MA 1 and MA 2 when no data reading is performed, the transistors MA 1 and MA 2 can be turned off to cause the voltage dividing circuit 410 to perform no operation.
- the transistor MA 3 is turned on to cause the bias voltage VB to be pulled up to be equal to the operating voltage VDD.
- the transistors MA 1 and MA 2 are turned on to cause the voltage dividing circuit 410 to work, and the transistor MA 3 is turned on. At this moment, the voltage value of the bias voltage VB is determined by the voltage dividing circuit 410 and is lowered accordingly.
- FIG. 5A to FIG. 5D are schematic diagrams illustrating the voltage dividing circuit according to an embodiment of the invention.
- the voltage dividing circuit 410 is formed by a plurality of transistors MB 1 -MB 4 , wherein the transistors MB 1 -MB 4 are connected to form a configuration of a diode and are sequentially connected in series between the ends PT and NT in a direction of a forward bias.
- An end connecting the transistors MB 1 and MB 2 generates the bias voltage VB.
- the transistors MB 1 -MB 4 may all be N type transistors, and under the condition that the transistors MB 1 -MB 4 have the same characteristics, the bias voltage VB can be 3 ⁇ 4 times the operating voltage VDD.
- the end that generates the bias voltage VB may be varied according to the design requirement.
- the end may be an end where the transistors MB 2 and MB 3 are connected, or an end where the transistors MB 3 and MB 4 are connected.
- the number of the transistors that form the diode may also be varied and is not limited to 4.
- the voltage dividing circuit 410 is formed by three transistors MD 1 -MD 3 .
- the bias voltage VB generated by the voltage dividing circuit 410 is determined by the characteristics of multiple transistors. When a process voltage temperature (PVT) varies, the bias voltage VB generated by the voltage dividing circuit 410 is compensated and an unexpected change does not occur. In addition, by the method of the embodiment of the invention, the current consumed by the voltage dividing circuit 410 can be reduced effectively for power saving.
- PVT process voltage temperature
- the transistors may have different configurations.
- transistors MC 1 -MC 3 are N type transistors while a transistor MC 4 is a P type transistor.
- transistors ME 1 -ME 2 are N type transistors while a transistor ME 3 is a P type transistor.
- FIG. 6 is a schematic diagram of a static memory apparatus according to another embodiment of the invention.
- a static memory apparatus 600 includes a plurality of memory cells 611 - 61 M, a plurality of dummy memory cells 621 - 62 N, a sense amplifier 630 , a discharge current adjuster 640 , an inverter INV 3 , and a dummy word line signal delay adjusting circuit 670 .
- the memory cells 611 - 61 M form a memory array 610 .
- FIG. 6 is a schematic diagram of a static memory apparatus according to another embodiment of the invention.
- a static memory apparatus 600 includes a plurality of memory cells 611 - 61 M, a plurality of dummy memory cells 621 - 62 N, a sense amplifier 630 , a discharge current adjuster 640 , an inverter INV 3 , and a dummy word line signal delay adjusting circuit 670 .
- the memory cells 611 - 61 M form a memory array
- the static memory apparatus 600 further performs a delay operation on a dummy word line signal DWL according to a setting signal SET through the dummy word line signal delay adjusting circuit 670 , and respectively transmits delayed dummy word line signals DWL 1 -DWLN to the dummy memory cells 621 - 62 N.
- a pull-down operation of the signal on the dummy bit line DBL is further delayed to prevent the sense amplifier 630 from being enabled too early.
- the inverter INV 3 is configured to perform an inverting operation on the signal on the dummy bit line DBL, and when the signal on the dummy bit line DBL is pulled down, an output signal generated by the inverter INV 3 is pulled up correspondingly, so as to enable the sensing and amplifying operation of the sense amplifier 630 .
- FIG. 7A and FIG. 7B are schematic diagrams respectively illustrating the dummy memory cells according to an embodiment of the invention.
- this embodiment of the invention exemplifies a 6T memory cell (formed of six transistors), this embodiment also applies to other structures, such as an 8T memory cell (formed of eight transistors).
- a dummy memory cell 710 includes transistors MN 1 -MN 4 and transistors MP 1 -MP 2 .
- a first end of the transistor MN 1 is coupled to the dummy bit line DBL, and a control end of the transistor MN 1 is coupled to the dummy word line DWLA 1 .
- a first end of the transistor MN 2 receives the reference ground voltage GND, and a control end of the transistor MN 2 is coupled to the dummy word line DWLA 1 .
- a first end of the transistor MP 1 receives the operating voltage VDD, and a second end of the transistor MP 1 is coupled to a second end of the transistor MN 1 .
- a first end and a second end of the transistor MP 2 receive the operating voltage VDD and are coupled to a control end of the transistor MP 1 .
- a control end of the transistor MP 2 is coupled to the second end of the transistor MN 1 .
- a first end of the transistor MN 3 is coupled to a second end of the transistor MP 1 , a second end of the transistor MN 3 is coupled to the discharge end CDT 1 , and a control end of the transistor MN 3 is coupled to the control end of the transistor MP 1 .
- a first end of the transistor MN 4 is coupled to the second end of the transistor MN 2 , a second end of the transistor MN 4 is coupled to the discharge end CDT 1 , and a control end of the transistor MN 4 is coupled to the control end of the transistor MP 2 .
- a dummy memory cell 720 includes transistors MN 5 -MN 6 .
- a first end of the transistor MN 5 is coupled to the dummy bit line DBL
- a control end of the transistor MN 5 is coupled to the dummy word line DWLA 1
- a first end of the transistor MN 6 is coupled to a second end of the transistor MN 5
- a control end of the transistor MN 6 receives the operating voltage VDD
- a second end of the transistor MN 6 is coupled to the discharge end CDT 1 .
- FIG. 8 is a flowchart illustrating a data reading method of the static memory apparatus according to an embodiment of the invention.
- the static memory apparatus includes a plurality of dummy memory cells, which respectively include a plurality of discharge ends.
- Steps of the data reading method include: in Step S 810 , when the static memory apparatus performs a data reading operation, a discharge current on at least one controlled discharge end of the discharge ends is adjusted, wherein the discharge ends are configured to discharge charges on a dummy bit line; and in Step S 820 , a signal on the dummy bit line is provided to enable a sense amplifier and cause the sense amplifier to perform a sensing and amplifying operation on signals on a plurality of bit lines, so as to generate readout data.
- the invention adjusts the discharge current on at least one of the discharge ends in the dummy memory cells to delay the variation of the signal on the dummy bit line, such that the sense amplifier is enabled at a proper time point.
- the static memory apparatus receives an operating voltage that has a higher voltage value, the variation of the signal on the dummy bit line is not delayed, and therefore, the data reading speed of the static memory apparatus is not slowed down.
- the adjustment of the discharge current can be performed according to the variation of the process voltage temperature, so as to effectively prevent data reading errors caused by the variation of the process voltage temperature.
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Abstract
Description
- This application claims the priority benefit of China application serial no. 201410333266.8, filed on Jul. 14, 2014. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The invention relates to a static memory apparatus and more particularly relates to a data reading method of the static memory apparatus.
- 2. Description of Related Art
- Referring to
FIG. 1 ,FIG. 1 is a block diagram of a conventional static memory apparatus. Astatic memory apparatus 100 is a static random access memory apparatus, which includes a plurality of memory cells 111-11M, a plurality of dummy memory cells 121-122, and asense amplifier 130. The memory cells 111-11M form amemory array 110 and are coupled to thesense amplifier 130 via bit lines BL1 and BL1B. A dummy bit line DBL coupled to the dummy memory cells 121-122 is connected with an input end of an inverter INV1, and an output end of the inverter INV1 is coupled to thesense amplifier 130 and provides an enable signal EN for enabling a sensing and amplifying operation of thesense amplifier 130. - When the
static memory apparatus 100 executes a data reading operation, a voltage level of a signal transmitted by the dummy bit line DBL is lowered correspondingly, and the sensing and amplifying operation of thesense amplifier 130 is enabled by the enable signal EN that is raised correspondingly. Meanwhile, the sense amplifier 130 senses and amplifies a difference between signals on the bit lines BL1 and BL1B, so as to obtain readout data. - However, when a process mismatch occurs on the
static memory apparatus 100, a speed of change of the signal transmitted by the dummy bit line DBL may become far faster than a speed of change of the signals on the bit lines BL1 and BL1B. As a result, when thesense amplifier 130 is enabled, correct readout data cannot be obtained because the difference between the signals on the bit lines BL1 and the BL1B is smaller than an offset voltage of the sense amplifier. The above situation becomes worse when thestatic memory apparatus 100 receives an operating voltage of a lower voltage value. - The invention provides a static memory apparatus and a data reading method thereof for effectively reducing data reading errors.
- The static memory apparatus of the invention includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The memory cells are arranged in a memory array that is coupled to a plurality of bit lines. The dummy memory cells are coupled to a dummy bit line and respectively include a plurality discharge ends for discharging charges on the dummy bit line. The sense amplifier is coupled to the bit lines and the dummy bit line and performs a sensing and amplifying operation on signals on the bit lines according to a signal on the dummy bit line, so as to generate readout data. The discharge current adjuster is coupled to at least one controlled discharge end of the discharge ends and adjusts a discharge current on the at least one controlled discharge end according to an operating voltage received by the memory cells.
- The invention provides a data reading method of a static memory apparatus, wherein the static memory apparatus includes a plurality of dummy memory cells, and the dummy memory cells respectively include a plurality of discharge ends. The data reading method includes: adjusting a discharge current on at least one controlled discharge end of the discharge ends when the static memory apparatus performs a data reading operation, wherein the discharge ends discharge charges on a dummy bit line. A signal on the dummy bit line is provided to enable a sense amplifier to perform a sensing and amplifying operation on signals on a plurality of bit lines, so as to generate readout data.
- Based on the above, when performing the data reading operation, the invention adjusts the discharge current which is discharged from the dummy bit line by the discharge ends in one or multiple dummy memory cells according to the operating voltage, and thereby delays the signal on the dummy bit line. Therefore, a time point that the sense amplifier is enabled is adjusted properly in accordance with the operating voltage, so as to effectively prevent data reading errors that occur because the sense amplifier is enabled too early due to overly low operating voltage, thereby maintaining a proper operation of the static memory apparatus.
- To make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a block diagram of a conventional static memory apparatus. -
FIG. 2 is a schematic diagram of a static memory apparatus according to an embodiment of the invention. -
FIG. 3A andFIG. 3B are schematic diagrams illustrating different implementations of a discharge current adjuster according to embodiments of the invention. -
FIG. 4 is a schematic diagram of a bias voltage adjuster according to an embodiment of the invention. -
FIG. 5A toFIG. 5D are schematic diagrams illustrating a voltage dividing circuit according to an embodiment of the invention. -
FIG. 6 is a schematic diagram of a static memory apparatus according to another embodiment of the invention. -
FIG. 7A andFIG. 7B are schematic diagrams respectively illustrating a dummy memory cell according to an embodiment of the invention. -
FIG. 8 is a flowchart illustrating a data reading method of the static memory apparatus according to an embodiment of the invention. - Referring to
FIG. 2 ,FIG. 2 is a schematic diagram of a static memory apparatus according to an embodiment of the invention. Astatic memory apparatus 200 includes a plurality of memory cells 211-21M, a plurality of dummy memory cells 221-22N, asense amplifier 230, and a discharge current adjuster 240. The memory cells 211-21M are arranged in amemory array 210, and the memory cells 211-21M are memory cells of a static random access memory. In addition, thememory array 210 is coupled to a plurality of bit lines BL1 and BL1B. The dummy memory cells 221-22N are coupled to a dummy bit line DBL and the dummy bit line DBL is coupled to thesense amplifier 230. Thesense amplifier 230 is further coupled to the bit lines BL1 and BL1B and enabled to perform a sensing and amplifying operation on signals on the bit lines BL1 and BL1B according to a signal on the dummy bit line DBL, so as to obtain readout data. - Furthermore, the dummy memory cells 221-22N respectively include discharge ends CDT1-CDTN. The discharge ends CDT1-CDTN cause the signal on the dummy bit line DBL to perform a discharging operation respectively via circuits in the dummy memory cells 221-22N. At least one or multiple controlled discharge ends of the discharge ends CDT1-CDTN (in this embodiment, the controlled discharge ends are discharge ends CDT1 and CDT2) are coupled to the
discharge current adjuster 240, and the discharge current adjuster 240 adjusts a discharge current generated between the controlled discharge ends (the discharge ends CDT1 and CDT2) and a reference ground voltage GND. - The discharge end not coupled to the discharge current adjuster 240 (e.g. the discharge end CDTN) is directly coupled to the reference ground voltage GND.
- Regarding details of the operation, when the
static memory apparatus 200 executes a data reading operation, the dummy memory cells 221-22N cause the discharging operation between the dummy bit line DBL and the discharge ends CDT1-CDTN to begin respectively according to dummy word line signals DWL1-DWLN received. Meanwhile, the discharge current adjuster 240 turns on a discharge current adjusting mechanism between the discharge ends CDT1 and CDT2 and the reference ground voltage GND. When thestatic memory apparatus 200 receives an operating voltage having a lower voltage value, a current value of the discharge current provided by thedischarge current adjuster 240 is smaller than a current value of the discharge current that the discharge end CDTN directly discharges the reference ground voltage GND. - What is important is that the
static memory apparatus 200 provides the corresponding discharge current of thedischarge current adjuster 240 according to the operating voltage VDD received by the dummy memory cells 221-22N and the memory cells 211-21M and a process temperature variation. More specifically, when the voltage value of the operating voltage VDD gets lower, the current value of the discharge current provided by thedischarge current adjuster 240 becomes lower, and the current value of the discharge current is determined according to the discharge current of the weakest memory cell of the memory cells 211-21M. - Further to the above, by lowering the current value of the discharge current between the discharge ends CDT1 and CDT2 and the reference ground voltage GND, a speed that a voltage level of the signal on the dummy bit line DBL is pulled down is reduced. As a result, an enabling time point for determining whether to enable the
sense amplifier 230 according to the signal on the dummy bit line DBL is delayed. In other words, thesense amplifier 230 can be enabled at a time point when the difference between the voltage levels of the signals on a pair of bit lines coupled to the weakest memory cell can be accurately sensed, so as to obtain the readout data accurately. - In an embodiment of the invention, the discharge
current adjuster 240 divides the operating voltage VDD and adjusts the current value of the discharge current according to a division result thereof. Accordingly, the time point of enabling thesense amplifier 230 can be adjusted properly according to the operating voltage VDD, so as to effectively prevent data reading errors caused by change of the operating voltage VDD. - Referring to
FIG. 3A andFIG. 3B ,FIG. 3A andFIG. 3B are schematic diagrams illustrating different implementations of the discharge current adjuster according to embodiments of the invention. InFIG. 3A , a dischargecurrent adjuster 301 includes abias voltage adjuster 310 and a variable resistor VR1. Thebias voltage adjuster 310 provides a bias voltage VB and transmits the bias voltage VB to the variable resistor VR1. The variable resistor VR1 adjusts a resistance value thereof according to the bias voltage VB. In terms of operation, when the static memory apparatus does not perform the data reading operation, the bias voltage VB can be equal to the operating voltage VDD. In contrast, when the static memory apparatus performs the data reading operation, thebias voltage adjuster 310 enables an adjusting operation of the bias voltage VB according to a bias voltage adjusting signal BEN, and thebias voltage adjuster 310 divides the operating voltage VDD to lower the voltage value of the bias voltage VB. Correspondingly, the variable resistor VR1 raises the resistance value thereof according to the lowered bias voltage VB and thereby lowers the discharge current value between the discharge end CDT1 and the reference ground voltage GND. - It should also be noted that, when the bias voltage VB is equal to the operating voltage VDD, the resistance value of the variable resistor VR1 is nearly equal to 0.
- In
FIG. 3B , a dischargecurrent adjuster 302 includes abias voltage adjuster 320 and a variable resistor VR2. UnlikeFIG. 3A , the variable resistor VR2 is formed by a transistor M1, wherein a first end (e.g. a source) and a second end (e.g. a drain) of the transistor M1 are connected in series between the discharge end CDT1 and the reference ground voltage GND, and a control end (e.g. a gate) of the transistor M1 receives the bias voltage VB. In addition, in this embodiment, the transistor M1 is an N type transistor. - Referring to
FIG. 4 ,FIG. 4 is a schematic diagram of a bias voltage adjuster according to an embodiment of the invention. Abias voltage adjuster 400 includes avoltage dividing circuit 410, transistors MA1-MA3, and an inverter INV2. The transistors MA1 and MA2 respectively serve as switches, wherein the transistor MA1 is coupled to a path of an end PT of thevoltage dividing circuit 410 receiving the operating voltage VDD, and the transistor MA2 is coupled to a path of an end NT of thevoltage dividing circuit 410 receiving the reference ground voltage GND. An input end of the inverter INV2 receives the bias voltage adjusting signal BEN, and an output end of the inverter INV2 generates an inverted bias voltage adjusting signal to control a turn-on or turn-off operation of the transistor MA1. Moreover, a turn-on or turn-off operation of the transistor MA2 is determined by the bias voltage adjusting signal BEN. - The transistor MA3 is a pull-up circuit and receives the bias voltage adjusting signal BEN to determine whether to be turned on, and when the transistor MA3 is turned on, the bias voltage VB is pulled up to be equal to the operating voltage VDD.
- In terms of the operation of the
bias voltage adjuster 400, when no data reading is performed, the transistors MA1 and MA2 can be turned off to cause thevoltage dividing circuit 410 to perform no operation. The transistor MA3 is turned on to cause the bias voltage VB to be pulled up to be equal to the operating voltage VDD. On the other hand, when data reading is performed, the transistors MA1 and MA2 are turned on to cause thevoltage dividing circuit 410 to work, and the transistor MA3 is turned on. At this moment, the voltage value of the bias voltage VB is determined by thevoltage dividing circuit 410 and is lowered accordingly. - Regarding implementation of the voltage dividing circuit,
FIG. 5A toFIG. 5D are schematic diagrams illustrating the voltage dividing circuit according to an embodiment of the invention. InFIG. 5A , thevoltage dividing circuit 410 is formed by a plurality of transistors MB1-MB4, wherein the transistors MB1-MB4 are connected to form a configuration of a diode and are sequentially connected in series between the ends PT and NT in a direction of a forward bias. An end connecting the transistors MB1 and MB2 generates the bias voltage VB. The transistors MB1-MB4 may all be N type transistors, and under the condition that the transistors MB1-MB4 have the same characteristics, the bias voltage VB can be ¾ times the operating voltage VDD. - Certainly, the end that generates the bias voltage VB may be varied according to the design requirement. For example, the end may be an end where the transistors MB2 and MB3 are connected, or an end where the transistors MB3 and MB4 are connected. The number of the transistors that form the diode may also be varied and is not limited to 4. Take the embodiment of
FIG. 5C for example, thevoltage dividing circuit 410 is formed by three transistors MD1-MD3. - It should be noted that the bias voltage VB generated by the
voltage dividing circuit 410 is determined by the characteristics of multiple transistors. When a process voltage temperature (PVT) varies, the bias voltage VB generated by thevoltage dividing circuit 410 is compensated and an unexpected change does not occur. In addition, by the method of the embodiment of the invention, the current consumed by thevoltage dividing circuit 410 can be reduced effectively for power saving. - Moreover, in the
voltage dividing circuit 410, the transistors may have different configurations. For example, inFIG. 5B , transistors MC1-MC3 are N type transistors while a transistor MC4 is a P type transistor. InFIG. 5D , for example, transistors ME1-ME2 are N type transistors while a transistor ME3 is a P type transistor. - Next, referring to
FIG. 6 ,FIG. 6 is a schematic diagram of a static memory apparatus according to another embodiment of the invention. Astatic memory apparatus 600 includes a plurality of memory cells 611-61M, a plurality of dummy memory cells 621-62N, asense amplifier 630, a dischargecurrent adjuster 640, an inverter INV3, and a dummy word line signaldelay adjusting circuit 670. The memory cells 611-61M form amemory array 610. UnlikeFIG. 2 , thestatic memory apparatus 600 further performs a delay operation on a dummy word line signal DWL according to a setting signal SET through the dummy word line signaldelay adjusting circuit 670, and respectively transmits delayed dummy word line signals DWL1-DWLN to the dummy memory cells 621-62N. - Through the delay operation of the dummy word line signal
delay adjusting circuit 670, a pull-down operation of the signal on the dummy bit line DBL is further delayed to prevent thesense amplifier 630 from being enabled too early. - The inverter INV3 is configured to perform an inverting operation on the signal on the dummy bit line DBL, and when the signal on the dummy bit line DBL is pulled down, an output signal generated by the inverter INV3 is pulled up correspondingly, so as to enable the sensing and amplifying operation of the
sense amplifier 630. - Hereinafter referring to
FIG. 7A andFIG. 7B ,FIG. 7A andFIG. 7B are schematic diagrams respectively illustrating the dummy memory cells according to an embodiment of the invention. It should be noted that, although this embodiment of the invention exemplifies a 6T memory cell (formed of six transistors), this embodiment also applies to other structures, such as an 8T memory cell (formed of eight transistors). InFIG. 7A , adummy memory cell 710 includes transistors MN1-MN4 and transistors MP1-MP2. A first end of the transistor MN1 is coupled to the dummy bit line DBL, and a control end of the transistor MN1 is coupled to the dummy word line DWLA1. A first end of the transistor MN2 receives the reference ground voltage GND, and a control end of the transistor MN2 is coupled to the dummy word line DWLA1. A first end of the transistor MP1 receives the operating voltage VDD, and a second end of the transistor MP1 is coupled to a second end of the transistor MN1. A first end and a second end of the transistor MP2 receive the operating voltage VDD and are coupled to a control end of the transistor MP1. A control end of the transistor MP2 is coupled to the second end of the transistor MN1. A first end of the transistor MN3 is coupled to a second end of the transistor MP1, a second end of the transistor MN3 is coupled to the discharge end CDT1, and a control end of the transistor MN3 is coupled to the control end of the transistor MP1. A first end of the transistor MN4 is coupled to the second end of the transistor MN2, a second end of the transistor MN4 is coupled to the discharge end CDT1, and a control end of the transistor MN4 is coupled to the control end of the transistor MP2. - In
FIG. 7B , adummy memory cell 720 includes transistors MN5-MN6. A first end of the transistor MN5 is coupled to the dummy bit line DBL, a control end of the transistor MN5 is coupled to the dummy word line DWLA1, a first end of the transistor MN6 is coupled to a second end of the transistor MN5, a control end of the transistor MN6 receives the operating voltage VDD, and a second end of the transistor MN6 is coupled to the discharge end CDT1. - Referring to
FIG. 8 hereinafter,FIG. 8 is a flowchart illustrating a data reading method of the static memory apparatus according to an embodiment of the invention. The static memory apparatus includes a plurality of dummy memory cells, which respectively include a plurality of discharge ends. Steps of the data reading method include: in Step S810, when the static memory apparatus performs a data reading operation, a discharge current on at least one controlled discharge end of the discharge ends is adjusted, wherein the discharge ends are configured to discharge charges on a dummy bit line; and in Step S820, a signal on the dummy bit line is provided to enable a sense amplifier and cause the sense amplifier to perform a sensing and amplifying operation on signals on a plurality of bit lines, so as to generate readout data. - Details of the steps of the method in this embodiment have been specified in the foregoing embodiments and thus will not be repeated hereinafter.
- To conclude the above, when the static memory apparatus receives an operating voltage that has a lower voltage value, the invention adjusts the discharge current on at least one of the discharge ends in the dummy memory cells to delay the variation of the signal on the dummy bit line, such that the sense amplifier is enabled at a proper time point. When the static memory apparatus receives an operating voltage that has a higher voltage value, the variation of the signal on the dummy bit line is not delayed, and therefore, the data reading speed of the static memory apparatus is not slowed down. Moreover, the adjustment of the discharge current can be performed according to the variation of the process voltage temperature, so as to effectively prevent data reading errors caused by the variation of the process voltage temperature.
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CN108305661A (en) * | 2017-01-13 | 2018-07-20 | 华邦电子股份有限公司 | Semiconductor storage and its data read method |
US20220319570A1 (en) * | 2021-03-30 | 2022-10-06 | Yangtze Memory Technologies Co., Ltd. | Memory device and operation method thereof |
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US9865316B2 (en) * | 2016-01-21 | 2018-01-09 | Qualcomm Incorporated | Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power |
US9685209B1 (en) * | 2016-04-19 | 2017-06-20 | Stmicroelectronics International N.V. | Circuit for generating a sense amplifier enable signal with variable timing |
KR20180046580A (en) * | 2016-10-28 | 2018-05-09 | 에스케이하이닉스 주식회사 | Electronic device |
US10971213B1 (en) * | 2019-09-24 | 2021-04-06 | Macronix International Co., Ltd. | Data sensing device and data sensing method thereof |
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US7324393B2 (en) * | 2002-09-24 | 2008-01-29 | Sandisk Corporation | Method for compensated sensing in non-volatile memory |
FR2857149B1 (en) * | 2003-07-01 | 2005-12-16 | St Microelectronics Sa | METHOD FOR CONTROLLING MEMORY READING AMPLIFIERS AND CORRESPONDING MEMORY INTEGRATED CIRCUIT |
CN100338346C (en) * | 2003-07-08 | 2007-09-19 | 日产自动车株式会社 | Combustion control apparatus for internal combustion engine |
JP5022681B2 (en) * | 2006-11-30 | 2012-09-12 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor memory device |
KR100908814B1 (en) * | 2007-08-29 | 2009-07-21 | 주식회사 하이닉스반도체 | Core voltage discharge circuit and semiconductor memory device including same |
US8737120B2 (en) * | 2011-07-29 | 2014-05-27 | Micron Technology, Inc. | Reference voltage generators and sensing circuits |
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CN108305661A (en) * | 2017-01-13 | 2018-07-20 | 华邦电子股份有限公司 | Semiconductor storage and its data read method |
US20220319570A1 (en) * | 2021-03-30 | 2022-10-06 | Yangtze Memory Technologies Co., Ltd. | Memory device and operation method thereof |
WO2022204916A1 (en) * | 2021-03-30 | 2022-10-06 | Yangtze Memory Technologies Co., Ltd. | Memory device and operation method thereof |
US11915786B2 (en) * | 2021-03-30 | 2024-02-27 | Yangtze Memory Technologies Co., Ltd. | Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof |
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