US20150364183A1 - Method and apparatus for bit-line sensing gates on an sram cell - Google Patents
Method and apparatus for bit-line sensing gates on an sram cell Download PDFInfo
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- US20150364183A1 US20150364183A1 US14/305,630 US201414305630A US2015364183A1 US 20150364183 A1 US20150364183 A1 US 20150364183A1 US 201414305630 A US201414305630 A US 201414305630A US 2015364183 A1 US2015364183 A1 US 2015364183A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Definitions
- the present disclosure relates to an interface circuitry of a memory cell.
- the present disclosure is particularly applicable to access gates of a static random access memory (SRAM) cell circuit.
- SRAM static random access memory
- an electronic circuit of a memory cell may be associated with various interface elements and signals that provide access to the memory cell.
- a processor in a computer may utilize the interface circuitry to read data that is stored in an SRAM memory cell or to write/store data in the SRAM memory cell.
- FIG. 1 schematically illustrates a traditional SRAM cell circuitry 100 utilized in an integrated circuit (IC) design.
- the SRAM memory cell includes interface circuitry for accessing the memory cell in order to read data stored therein or to write data in the memory cell.
- the memory cell 100 includes a first access gate having a first transistor 101 and a second access gate having a second transistor 103 that provide access to memory cell inverter circuit 105 , which can store data (e.g., zeroes and ones.)
- one or more interface signals on word-line (WL) 107 , a first bit-line (BL) 109 , and a second BL (BLX) 111 may be utilized to access the memory cell inverter circuit 105 , wherein various combinations of the interface signals can provide for various interactions/operations at the memory cell.
- a high voltage state e.g., at logic 1
- an operation of reading the memory cell content can be initiated.
- the access gate transistors in a conventional SRAM design may be unable to function reliably or consistently.
- a known approach to improve write ability is to include a write assist circuit.
- write assist circuits take additional area on the chip.
- An aspect of the present disclosure is a circuit to provide additional current for access gates in a memory cell without a higher supply voltage, assist circuits, or additional time consumption.
- Another aspect of the present disclosure is a method for implementing a circuit to provide additional current for access gates in a memory cell without a higher supply voltage, assist circuits, or additional time consumption.
- a circuit including: a six transistor SRAM cell that includes a first inverter cross-coupled to a second inverter, a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, and a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor.
- Some aspects further include a circuit where the first transistor and the second transistor include passgate n-type metal-oxide-semiconductor (NMOS) field-effect transistors (FETs).
- NMOS metal-oxide-semiconductor
- bit-line sensing transistors having a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate; a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line; a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; and a sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line.
- each of the third transistor and the fifth transistor includes a write p-type metal-oxide-semiconductor (PMOS) transistor.
- Another aspect includes a circuit where each of the fourth transistor and the sixth transistor includes a write NMOS transistor.
- An additional aspect includes a circuit where the third transistor is in an active state when the first drain, the second bit-line, and the word-line are at a high voltage state, and the first bit-line is at a low voltage state.
- first inverter having a seventh transistor having a seventh source, a seventh drain, and a seventh gate, and an eighth transistor having an eighth source, an eighth drain, and an eighth gate
- the second inverter including a ninth transistor having a ninth source, a ninth drain, and a ninth gate, and a tenth transistor having a tenth source, a tenth drain, and a tenth gate, wherein the seventh source and the ninth source are coupled to a power rail, wherein the eighth source and the tenth source are coupled to a ground rail, wherein the seventh drain, the eighth drain, the ninth gate, and the tenth gate are coupled to the first drain, and wherein the ninth drain, the tenth drain, the seventh gate, and the eighth gate are coupled to the second source.
- the third transistor in the active state sources a higher current level during a write operation when compared to one or more other current levels sourced during one or more other operations at the SRAM cell.
- An additional aspect of the present disclosure is a method including: providing a six transistor SRAM cell including providing a first inverter cross-coupled to a second inverter, providing a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, and providing a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and providing a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor.
- the first transistor and the second transistor include passgate NMOS transistors.
- Another aspect of the present disclosure for providing the plurality of bit-line sensing transistors includes providing a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate; providing a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line; providing a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; and providing a sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line.
- each of the third transistor and the fifth transistor includes a write PMOS transistor.
- each of the fourth transistor and the sixth transistor includes a write NMOS transistor.
- the third transistor is in an active state when the first drain, the second bit-line, and the word-line are at a high voltage state, and the first bit-line is at a low voltage state.
- the method includes providing for the first inverter a seventh transistor having a seventh source, a seventh drain, and a seventh gate, and an eighth transistor having an eighth source, an eighth drain, and an eighth gate; providing for the second inverter a ninth transistor having a ninth source, a ninth drain, and a ninth gate, and a tenth transistor having a tenth source, a tenth drain, and a tenth gate; coupling the seventh source and the ninth source to a power rail; coupling the eighth source and the tenth source to a ground rail; coupling the seventh drain, the eighth drain, the ninth gate, and the tenth gate to the first drain; and coupling the ninth drain, the tenth drain, the seventh gate, and the eighth gate to the second source.
- FIG. 1 schematically illustrates a traditional memory cell circuit utilized in an SRAM design
- FIG. 2 schematically illustrates an SRAM cell design including circuitry to provide additional current to one or more access gates, in accordance with an exemplary embodiment
- FIG. 3 illustrates a table of example combinations of access signals and related operations at an SRAM cell, in accordance with an exemplary embodiment.
- the present disclosure addresses and solves the problems of low supply current available to access gates of an SRAM memory cell and/or additional area requirements for a write assist circuit attendant upon reducing bitcell size for an SRAM memory cell.
- the present disclosure addresses and solves such problems, for instance, by, inter alia, providing more current to the access gates by utilizing additional transistors that can provide the additional current once some of the control signals of the memory cell are activated.
- FIG. 2 schematically illustrates an SRAM cell design including circuitry to provide additional current to one or more access gates, in accordance with an exemplary embodiment.
- FIG. 2 schematically illustrates circuit 200 including the first access gate having the first transistor 101 , the second access gate having the second transistor 103 , the memory cell inverter circuit 105 , the WL 107 , the BL 109 , and the BLX 111 , as in a traditional SRAM cell design.
- the first access gate additionally includes two supplemental transistors, a third transistor 201 and a fourth transistor 203
- the second access gate also includes two supplemental transistors, a fifth transistor 205 and a sixth transistor 207 .
- the memory cell inverter circuit 105 includes two inverters, each with two transistors, as in the traditional SRAM cell. Specifically, the first inverter includes a seventh transistor 209 and an eight transistor 211 , and the second inverter includes a ninth transistor 213 and a tenth transistor 215 .
- the first transistor 101 has a source 1 S coupled to the BL 109 , a drain 1 D coupled to the first inverter, and a gate 1 G coupled to the WL 107 .
- the second transistor 103 has a source 2 S coupled to the second inverter, a drain 2 D coupled to the BLX 111 , and a gate 2 G coupled to the WL 107 .
- the third transistor 201 has a source 3 S and a drain 3 D, coupled to the source 1 S and drain 1 D, respectively, of the first transistor, and a gate 3 G.
- the fourth transistor 203 has a drain 4 D coupled to the gate 3 G, a source 4 S coupled to the BL 109 , and a gate 4 G coupled to the WL 107 .
- the fifth transistor 205 has a source 5 S and a drain 5 D, coupled to the source 2 S and drain 2 D, respectively, of the second transistor, and a gate 5 G.
- the sixth transistor 207 has a source 6 S coupled to the BLX 111 , a drain 6 D coupled to the gate 5 G, and a gate 6 G coupled to the WL 107 .
- the source 7 S of transistor 209 and the source 9 S of transistor 213 are coupled to a power rail 217
- the source 8 S of the transistor 211 and the source 10 S of the transistor 215 are coupled to a ground rail 219 .
- the drains 7 D and 8 D of transistors 209 and 211 and gates 9 G and 10 G of transistors 213 and 215 are coupled to the drain 1 D; and the drains 9 D and 10 D of transistors 213 and 215 , gate 7 G of transistor 209 , and the gate 8 G of transistor 211 are coupled to the source 2 S.
- Each of the third transistor 201 and the fifth transistor 205 include a PMOS transistor. Further, each of the fourth transistor 203 and the sixth transistor 207 may include an NMOS transistor. The third transistor may be in an active state when the drain 1 D, the BLX 111 , and the WL 107 are at a high voltage state, and the BL 109 is at a low voltage state.
- Advantages of the design of FIG. 2 include improved write current levels for a more reliable write operation at the SRAM memory cell and without a need for a higher supply voltage (e.g., no change required to previous design), which could provide for a better yield of memory cells when considering a minimum voltage (Vmin) parameter at an IC. Further, no write assist circuit is required.
- Vmin minimum voltage
- FIG. 3 illustrates a table 300 of example combinations of access signals and related operations at an SRAM cell.
- a “read” operation 301 when signals on the WL 107 , BL 109 , and BLX 111 are at a high voltage state, then the first transistor 101 , the second transistor 103 , the fourth transistor 203 , and the sixth transistor 207 are in active states while the third transistor 201 and the fifth transistor 205 are in an inactive state, which would result in no increase in the “read” mode current.
- a “disturb” operation 305 e.g., half selected cell for a read operation after a write operation
- the first transistor 101 , the second transistor 103 , the fourth transistor 203 , and the sixth transistor 207 are in active states while the third transistor 201 and the fifth transistor 205 are in inactive states, which would result in no degradation of the disturb margin.
- the embodiments of the present disclosure can achieve several technical effects, including improved current levels during a write operation at an SRAM memory cell in an IC device without sacrificing space for a write assist circuit. Further, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM memory cells (e.g., liquid crystal display (LCD) drivers, synchronous random access memories (SRAM), digital processors, etc.)
- SRAM memory cells e.g., liquid crystal display (LCD) drivers, synchronous random access memories (SRAM), digital processors, etc.
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Abstract
Description
- The present disclosure relates to an interface circuitry of a memory cell. The present disclosure is particularly applicable to access gates of a static random access memory (SRAM) cell circuit.
- Generally, an electronic circuit of a memory cell may be associated with various interface elements and signals that provide access to the memory cell. For example, a processor in a computer may utilize the interface circuitry to read data that is stored in an SRAM memory cell or to write/store data in the SRAM memory cell.
-
FIG. 1 schematically illustrates a traditionalSRAM cell circuitry 100 utilized in an integrated circuit (IC) design. The SRAM memory cell includes interface circuitry for accessing the memory cell in order to read data stored therein or to write data in the memory cell. For example, thememory cell 100 includes a first access gate having afirst transistor 101 and a second access gate having asecond transistor 103 that provide access to memorycell inverter circuit 105, which can store data (e.g., zeroes and ones.) Additionally, one or more interface signals on word-line (WL) 107, a first bit-line (BL) 109, and a second BL (BLX) 111 may be utilized to access the memorycell inverter circuit 105, wherein various combinations of the interface signals can provide for various interactions/operations at the memory cell. For example, with the WL signal and pre-charged BL and BLX at a high voltage state (e.g., at logic 1), an operation of reading the memory cell content can be initiated. However, with technological advances in reduced IC node designs (e.g., scaling, smaller transistors) and lower supply voltages, the access gate transistors in a conventional SRAM design may be unable to function reliably or consistently. For instance, lower levels of supply voltage and current (i.e., ampere=I) at an SRAM cell can cause a failure of one or more functions/operations (e.g., read, write, retention, etc.) at the cell. A known approach to improve write ability is to include a write assist circuit. However write assist circuits take additional area on the chip. - A need therefore exists for methodology and circuitry enabling additional current for access gates in a memory cell without increasing supply voltage or sacrificing SRAM array area.
- An aspect of the present disclosure is a circuit to provide additional current for access gates in a memory cell without a higher supply voltage, assist circuits, or additional time consumption.
- Another aspect of the present disclosure is a method for implementing a circuit to provide additional current for access gates in a memory cell without a higher supply voltage, assist circuits, or additional time consumption.
- Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
- According to the present disclosure, some technical effects may be achieved in part by a circuit including: a six transistor SRAM cell that includes a first inverter cross-coupled to a second inverter, a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, and a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor. Some aspects further include a circuit where the first transistor and the second transistor include passgate n-type metal-oxide-semiconductor (NMOS) field-effect transistors (FETs).
- Further aspects include the plurality of bit-line sensing transistors having a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate; a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line; a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; and a sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line. Other aspects include a circuit where each of the third transistor and the fifth transistor includes a write p-type metal-oxide-semiconductor (PMOS) transistor. Another aspect includes a circuit where each of the fourth transistor and the sixth transistor includes a write NMOS transistor. An additional aspect includes a circuit where the third transistor is in an active state when the first drain, the second bit-line, and the word-line are at a high voltage state, and the first bit-line is at a low voltage state.
- Other aspects include the first inverter having a seventh transistor having a seventh source, a seventh drain, and a seventh gate, and an eighth transistor having an eighth source, an eighth drain, and an eighth gate; and the second inverter including a ninth transistor having a ninth source, a ninth drain, and a ninth gate, and a tenth transistor having a tenth source, a tenth drain, and a tenth gate, wherein the seventh source and the ninth source are coupled to a power rail, wherein the eighth source and the tenth source are coupled to a ground rail, wherein the seventh drain, the eighth drain, the ninth gate, and the tenth gate are coupled to the first drain, and wherein the ninth drain, the tenth drain, the seventh gate, and the eighth gate are coupled to the second source.
- In another aspect the third transistor in the active state sources a higher current level during a write operation when compared to one or more other current levels sourced during one or more other operations at the SRAM cell.
- An additional aspect of the present disclosure is a method including: providing a six transistor SRAM cell including providing a first inverter cross-coupled to a second inverter, providing a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, and providing a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and providing a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor. In one aspect the first transistor and the second transistor include passgate NMOS transistors.
- Another aspect of the present disclosure for providing the plurality of bit-line sensing transistors includes providing a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate; providing a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line; providing a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; and providing a sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line. In an additional aspect of the present disclosure each of the third transistor and the fifth transistor includes a write PMOS transistor. In one aspect of the present disclosure each of the fourth transistor and the sixth transistor includes a write NMOS transistor. In a further aspect of the present disclosure the third transistor is in an active state when the first drain, the second bit-line, and the word-line are at a high voltage state, and the first bit-line is at a low voltage state.
- In some aspects of the present disclosure the method includes providing for the first inverter a seventh transistor having a seventh source, a seventh drain, and a seventh gate, and an eighth transistor having an eighth source, an eighth drain, and an eighth gate; providing for the second inverter a ninth transistor having a ninth source, a ninth drain, and a ninth gate, and a tenth transistor having a tenth source, a tenth drain, and a tenth gate; coupling the seventh source and the ninth source to a power rail; coupling the eighth source and the tenth source to a ground rail; coupling the seventh drain, the eighth drain, the ninth gate, and the tenth gate to the first drain; and coupling the ninth drain, the tenth drain, the seventh gate, and the eighth gate to the second source.
- Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
- The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
-
FIG. 1 schematically illustrates a traditional memory cell circuit utilized in an SRAM design; -
FIG. 2 schematically illustrates an SRAM cell design including circuitry to provide additional current to one or more access gates, in accordance with an exemplary embodiment; and -
FIG. 3 illustrates a table of example combinations of access signals and related operations at an SRAM cell, in accordance with an exemplary embodiment. - In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
- The present disclosure addresses and solves the problems of low supply current available to access gates of an SRAM memory cell and/or additional area requirements for a write assist circuit attendant upon reducing bitcell size for an SRAM memory cell. The present disclosure addresses and solves such problems, for instance, by, inter alia, providing more current to the access gates by utilizing additional transistors that can provide the additional current once some of the control signals of the memory cell are activated.
-
FIG. 2 schematically illustrates an SRAM cell design including circuitry to provide additional current to one or more access gates, in accordance with an exemplary embodiment.FIG. 2 schematically illustratescircuit 200 including the first access gate having thefirst transistor 101, the second access gate having thesecond transistor 103, the memorycell inverter circuit 105, theWL 107, theBL 109, and theBLX 111, as in a traditional SRAM cell design. However, the first access gate additionally includes two supplemental transistors, athird transistor 201 and afourth transistor 203, and the second access gate also includes two supplemental transistors, afifth transistor 205 and asixth transistor 207. The memorycell inverter circuit 105 includes two inverters, each with two transistors, as in the traditional SRAM cell. Specifically, the first inverter includes aseventh transistor 209 and an eighttransistor 211, and the second inverter includes aninth transistor 213 and atenth transistor 215. - The
first transistor 101 has asource 1S coupled to theBL 109, adrain 1D coupled to the first inverter, and agate 1G coupled to theWL 107. Thesecond transistor 103 has asource 2S coupled to the second inverter, adrain 2D coupled to theBLX 111, and agate 2G coupled to theWL 107. Thethird transistor 201 has asource 3S and adrain 3D, coupled to thesource 1S anddrain 1D, respectively, of the first transistor, and agate 3G. Thefourth transistor 203 has adrain 4D coupled to thegate 3G, asource 4S coupled to theBL 109, and agate 4G coupled to theWL 107. Similar to thethird transistor 201, thefifth transistor 205 has asource 5S and adrain 5D, coupled to thesource 2S anddrain 2D, respectively, of the second transistor, and agate 5G. Thesixth transistor 207 has asource 6S coupled to theBLX 111, adrain 6D coupled to thegate 5G, and agate 6G coupled to theWL 107. - Regarding the
inverter circuit 105, thesource 7S oftransistor 209 and thesource 9S oftransistor 213 are coupled to apower rail 217, whereas thesource 8S of thetransistor 211 and thesource 10S of thetransistor 215 are coupled to aground rail 219. Thedrains 7D and 8D oftransistors gates transistors drain 1D; and thedrains transistors gate 7G oftransistor 209, and thegate 8G oftransistor 211 are coupled to thesource 2S. - Each of the
third transistor 201 and thefifth transistor 205 include a PMOS transistor. Further, each of thefourth transistor 203 and thesixth transistor 207 may include an NMOS transistor. The third transistor may be in an active state when thedrain 1D, theBLX 111, and theWL 107 are at a high voltage state, and theBL 109 is at a low voltage state. - Advantages of the design of
FIG. 2 include improved write current levels for a more reliable write operation at the SRAM memory cell and without a need for a higher supply voltage (e.g., no change required to previous design), which could provide for a better yield of memory cells when considering a minimum voltage (Vmin) parameter at an IC. Further, no write assist circuit is required. -
FIG. 3 illustrates a table 300 of example combinations of access signals and related operations at an SRAM cell. In the table 300, during a “read”operation 301, when signals on theWL 107,BL 109, andBLX 111 are at a high voltage state, then thefirst transistor 101, thesecond transistor 103, thefourth transistor 203, and thesixth transistor 207 are in active states while thethird transistor 201 and thefifth transistor 205 are in an inactive state, which would result in no increase in the “read” mode current. Further, during a “write”operation 303, when signals on theWL 107 and theBLX 111 are at a high voltage state, and theBL 109 is at a low voltage state, then thefirst transistor 101, thesecond transistor 103, thethird transistor 201, thefourth transistor 203, and thesixth transistor 207 are in active states while thefifth transistor 205 is in an inactive state, which would result an increase in the “write” mode current. Furthermore, during a “disturb” operation 305 (e.g., half selected cell for a read operation after a write operation), when signals on theWL 107,BL 109, andBLX 111 are at a high voltage state, then thefirst transistor 101, thesecond transistor 103, thefourth transistor 203, and thesixth transistor 207 are in active states while thethird transistor 201 and thefifth transistor 205 are in inactive states, which would result in no degradation of the disturb margin. - The embodiments of the present disclosure can achieve several technical effects, including improved current levels during a write operation at an SRAM memory cell in an IC device without sacrificing space for a write assist circuit. Further, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM memory cells (e.g., liquid crystal display (LCD) drivers, synchronous random access memories (SRAM), digital processors, etc.)
- In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
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US14/305,630 Active US9224455B1 (en) | 2014-06-16 | 2014-06-16 | Method and apparatus for bit-line sensing gates on an SRAM cell |
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CN107481754A (en) * | 2016-06-07 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of multiplexer circuit, static RAM and electronic installation |
US20230215487A1 (en) * | 2022-01-05 | 2023-07-06 | Micron Technology, Inc. | Configurable input for an amplifier |
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US10403384B2 (en) | 2016-06-22 | 2019-09-03 | Darryl G. Walker | Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor |
US20170372775A1 (en) | 2016-06-22 | 2017-12-28 | Darryl G. Walker | Semiconductor devices, circuits and methods for read and/or write assist of an sram circuit portion based on voltage detection and/or temperature detection circuits |
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US5532958A (en) * | 1990-06-25 | 1996-07-02 | Dallas Semiconductor Corp. | Dual storage cell memory |
US5828597A (en) * | 1997-04-02 | 1998-10-27 | Texas Instruments Incorporated | Low voltage, low power static random access memory cell |
US7898894B2 (en) * | 2006-04-12 | 2011-03-01 | International Business Machines Corporation | Static random access memory (SRAM) cells |
US7505303B2 (en) * | 2006-12-22 | 2009-03-17 | Cypress Semiconductor Corporation | Method and apparatus to create an erase disturb on a non-volatile static random access memory cell |
US7535751B2 (en) * | 2007-02-12 | 2009-05-19 | Taiwan Semioconductor Manufacturing Co., Ltd. | Dual-port SRAM device |
US7782654B2 (en) * | 2007-05-09 | 2010-08-24 | Nec Electronics Corporation | Static random access memory device |
KR20120101911A (en) * | 2011-03-07 | 2012-09-17 | 삼성전자주식회사 | Sram cell |
US8625334B2 (en) * | 2011-12-16 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107481754A (en) * | 2016-06-07 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of multiplexer circuit, static RAM and electronic installation |
US20230215487A1 (en) * | 2022-01-05 | 2023-07-06 | Micron Technology, Inc. | Configurable input for an amplifier |
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