US20150357292A1 - Methods of fabricating defect-free semiconductor structures - Google Patents
Methods of fabricating defect-free semiconductor structures Download PDFInfo
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- US20150357292A1 US20150357292A1 US14/799,624 US201514799624A US2015357292A1 US 20150357292 A1 US20150357292 A1 US 20150357292A1 US 201514799624 A US201514799624 A US 201514799624A US 2015357292 A1 US2015357292 A1 US 2015357292A1
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- dielectric layer
- semiconductor structure
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- depleted region
- consumable material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title abstract description 70
- 239000000463 material Substances 0.000 claims abstract description 68
- 239000010410 layer Substances 0.000 claims description 106
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 28
- 239000002019 doping agent Substances 0.000 claims description 26
- 239000000203 mixture Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 17
- 229910052698 phosphorus Inorganic materials 0.000 claims description 17
- 239000011574 phosphorus Substances 0.000 claims description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 230000008569 process Effects 0.000 abstract description 43
- 238000004519 manufacturing process Methods 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 45
- 239000000377 silicon dioxide Substances 0.000 description 21
- 235000012239 silicon dioxide Nutrition 0.000 description 19
- 238000005530 etching Methods 0.000 description 17
- 238000002955 isolation Methods 0.000 description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- -1 for example Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 7
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 238000005389 semiconductor device fabrication Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000007792 addition Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000155 isotopic effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to structures and methods of facilitating fabricating semiconductor structures, and more particularly, to structures and methods of fabricating defect-free semiconductor structure, for use, in fabrication of integrated circuits.
- a semiconductor device fabrication such as transistor fabrication, typically involves deposition of dielectric layers within high aspect ratio openings, associated with various circuit features, for instance, intermetal dielectric (IMD) features, pre-metal dielectric (PMD) features or isolation features, including shallow trench isolation regions.
- IMD intermetal dielectric
- PMD pre-metal dielectric
- isolation features including shallow trench isolation regions.
- a method which includes, for instance: providing a dielectric layer, the dielectric layer including at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
- a semiconductor structure which includes: an interlayer structure, the interlayer structure including: at least one first dielectric layer disposed above a semiconductor substrate, one first dielectric layer of the at least one first dielectric layer having a first elemental composition, wherein the first elemental composition includes at least one replacement consumable material; and a second dielectric layer disposed above the at least one first dielectric layer, the second dielectric layer having a second elemental composition, wherein the second elemental composition includes at least one consumable material.
- FIG. 1 is a cross-sectional elevational view of one embodiment of an intermediate semiconductor structure, which includes a dielectric layer disposed over semiconductor substrate, and is obtained during semiconductor fabrication process, in accordance with one or more aspects of the present invention
- FIG. 2 depicts the semiconductor structure of FIG. 1 , after selectively removing a portion of the dielectric layer, leaving, in part, a depleted region, in accordance with one or more aspects of the present invention
- FIG. 3 depicts the semiconductor structure of FIG. 2 , after subjecting the depleted region to a treatment process, in accordance with one or more aspects of the present invention
- FIG. 4 depicts the intermediate semiconductor structure of FIG. 3 , after creating a substantially planar, defect-free semiconductor structure, in accordance with one or more aspects of the present invention
- FIG. 5 depicts the intermediate semiconductor structure of FIG.
- FIG. 6 depicts the intermediate semiconductor structure of FIG. 5 after removal of exposed gate structures, in accordance with one or more aspects of the present invention.
- dielectric layer typically involves deposition of dielectric layer within high aspect ratio openings, associated with various circuit features, for instance, intermetal dielectric (IMD) features, pre-metal dielectric (PMD) features or isolation features, including shallow trench isolation regions.
- dielectric layers may include doped or undoped silicon-based high aspect ratio oxides such as, for instance, High-Density-Plasma silicon dioxide (HDP-SiO 2 ), High Aspect Ratio Process (HARP) oxide or ozone-tetraethylorthosilicate (O 3 -TEOS) oxide.
- HDP-SiO 2 High Aspect Ratio Process
- HTP High Aspect Ratio Process
- O 3 -TEOS ozone-tetraethylorthosilicate
- dielectric layer including, for instance, doped High-Density-Plasma (HDP) silicon dioxide
- CVD thermal chemical vapor deposition
- PECVD plasma enhanced chemical vapor depostion
- an oxygen-containing source such as oxygen (O 2 ) or ozone (O 3 )
- O 2 oxygen
- O 3 ozone
- the multi-step processing technique includes, for instance, deposition, etching and deposition technique (also referred to herein as “dep/etch/dep” processing), wherein a portion of dielectric layer is etched using a suitable etching process, for instance, fluorine-based etching process, followed by deposition of a second layer of dielectric layer.
- a suitable etching process for instance, fluorine-based etching process
- this multi-step processing technique will often result in creating defects between the respective dielectric layers, for instance, due to the loss of dopants during the etching processes, thereby resulting in layering (referred to herein as “layering effect”) of the respective dielectric layers, and in turn, propagating defects within the semiconductor structure.
- a method of facilitating fabrication of substantially planar, defect-free semiconductor structure includes: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
- the dielectric layer includes, for example, a silicon-based high aspect ratio oxide having an initial elemental composition.
- the silicon-based high aspect ratio oxide having the initial elemental composition may include the at least one consumable material such as, for instance, a doped material.
- the doped material may include at least one of nitrogen and phosphorus.
- the selectively removing consumes, in part, a remaining portion of the at least one consumable material, for instance, a doped material, from within the initial elemental composition of the remaining portion of the dielectric layer, leaving, the depleted region within the remaining portion of the dielectric layer.
- the subjecting the depleted region further includes restoring the depleted region, for instance, of the remaining portion of the dielectric layer, to the initial elemental composition with the at least one replacement consumable material.
- the remaining portion of the at least one consumable material consumed within the depleted region and the at least one replacement consumable material restored within the depleted region include a same material, for example, nitrogen, phosphorus and undoped silicon.
- the treatment process includes facilitating an interaction between the depleted region and at least one source of the at least one replacement consumable material, the interaction restoring the depleted region with the at least one replacement consumable material.
- the at least one source of the at least one replacement consumable material includes at least one of nitrogen source such as, ammonia gas; phosphorus source such as, phosphine gas; and undoped silicon source such as silane gas.
- the treatment process includes implanting the depleted region with the at least one replacement consumable material to restore the portion of the consumed at least one consumable material, for instance, the at least one replacement consumable material including at least one of doped material and undoped silicon.
- the doped material includes at least one of nitrogen and phosphorus.
- Selectively removing the portion of the dielectric layer includes selectively etching the portion of the dielectric layer using nitrogen trifluoride plasma.
- the method includes repeating sequentially, in at least one or more iterations, the providing a dielectric layer, the selectively removing the portion of the dielectric layer, and the subjecting the depleted region to the treatment process, to achieve the defect-free semiconductor structure.
- Repeating sequentially further includes providing a plurality of dielectric layer, the providing facilitates minimizing the layering effect between the plurality of dielectric layers, and creating substantially planar, defect-free interlayer structure of the plurality of dielectric layers.
- FIGS. 1-6 depict one detailed embodiment of a method of facilitating fabrication of a defect-free semiconductor structure, for instance, by creating substantially planar, defect-free dielectric layer for use, in fabrication of integrated circuits, in accordance with one or more aspects of the present invention.
- FIG. 1 illustrates an intermediate semiconductor structure 100 , attained during fabrication of one or more interlayer structures, in accordance with one or more aspects of the present invention.
- intermediate structure 100 includes a semiconductor substrate 102 , such as a bulk semiconductor material, for example, a bulk silicon wafer.
- semiconductor substrate 102 may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI), or silicon-on-replacement (SRI) substrates and the like.
- Silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI), or silicon-on-replacement (SRI) substrates and the like.
- Semiconductor substrate 102 may in addition or instead include various isolations, dopings, and/or device features.
- the semiconductor substrate may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, or GaInAsP or combinations thereof.
- germanium germanium
- SiC silicon carbide
- GaAs gallium arsenide
- GaP gallium phosphide
- InP indium phosphide
- InAs indium arsenide
- InSb indium antimonide
- intermediate semiconductor structure 100 may include a plurality of gate structures 104 , 106 and 108 , that may be laterally separated by isolation features 110 , for instance, shallow trench isolation features (STI).
- isolation features 110 for instance, shallow trench isolation features (STI).
- STI shallow trench isolation features
- the formation of isolation regions, such as, shallow trench isolation may include, for instance, forming a recess within the semiconductor substrate and filling the recess with a dielectric material, for instance, high-density-plasma (HDP) silicon dioxide or TEOS (tetraethylorthosilicate) based silicon oxide, silicon nitride and the like.
- gate structures 104 , 106 and 108 may include sacrificial gate material, for instance, amorphous-silicon, to hold the gate position for subsequent metal gate structures to be formed.
- intermediate semiconductor structure 100 may further include source and drain regions (also referred to as active region 112 ) is provided over semiconductor substrate 102 .
- Active region 112 may be formed using any suitable techniques, for instance, ion implantation, epitaxial growth of the embedded source/drain materials and activation anneals.
- Intermediate structure 100 may further include a protective hard mask 114 , which disposed along the sidewalls and the upper surfaces of respective gate structures 104 , 106 and 108 .
- Protective hard mask 114 may be deposited using conventional deposition processes, such as, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure CVD, or plasma-enhanced CVD (PE-CVD).
- CVD chemical vapor deposition
- ALD atomic layer deposition
- PE-CVD plasma-enhanced CVD
- protective hard mask 114 may have conventional thickness and may include or be fabricated of a material such as, for example, silicon nitride.
- a dielectric layer 116 is disposed between and over gate structures 104 , 106 and 108 , in accordance with one or more aspects of the present invention.
- Dielectric layer 116 may include or be fabricated of a dielectric material such as, for example, silicon-based high aspect ratio oxide.
- the silicon-based high aspect ratio oxide may include but are not limited to, High-Density-Plasma (HDP) silicon dioxide, high aspect ratio process (HARP) oxide, and may be conformally deposited using conventional deposition processes such as, chemical vapor deposition (CVD), high-density-plasma CVD (HDP-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) processes and the like.
- CVD chemical vapor deposition
- HDP-CVD high-density-plasma CVD
- ALD atomic layer deposition
- PVD physical vapor deposition
- silicon-based high aspect ratio oxide may include undoped silicon dioxide, with a predetermined initial elemental composition of silicon dioxide (SiO 2 ).
- undoped silicon dioxide may be deposited, by employing high-density-plasma CVD (HDP-CVD) process using process gases that include silicon-containing source (e.g., silane (SiH 4 ), disilane (Si 2 H 6 ), etc.,), an oxygen-containing source (e.g., oxygen (O 2 ), ozone (O 3 ), etc.,) and an inert gas (e.g., argon(Ar), helium (He), etc.,).
- silicon-containing source e.g., silane (SiH 4 ), disilane (Si 2 H 6 ), etc.
- an oxygen-containing source e.g., oxygen (O 2 ), ozone (O 3 ), etc.
- an inert gas e.g., argon(Ar), helium (He), etc
- silicon-based high aspect ratio oxide may also include doped silicon dioxide, with a predetermined initial elemental composition of stoichiometric silicon dioxide (SiO 2 ) compositions with dopant concentrations in the range of about 0.01 to 10 atomic percent (at. wt. %), the dopants being consumable materials.
- the dopants employed may include but are not limited to, n-type dopants. Note that as used herein, n-type dopant refers to the addition of impurities to, for instance, an intrinsic dielectric material/layer, which contribute more electrons to an intrinsic material, and may include (for instance) nitrogen, phosphorus and the like.
- nitrogen-doped silicon dioxide or phosphorus-doped silicon dioxide may be deposited, by employing high-density-plasma CVD (HDP-CVD) process using process gases that include silicon-containing source (e.g., silane (SiH 4 ), disilane (Si 2 H 6 ), etc.,), an oxygen-containing source (e.g., oxygen (O 2 ), ozone (O 3 ), etc.,) and an inert gas (e.g., argon(Ar), helium (He), etc.,) along with suitable dopant precursors such as, for example, ammonia (NH 3 ), phosphine (PH 3 ) respectively.
- silicon-containing source e.g., silane (SiH 4 ), disilane (Si 2 H 6 ), etc.
- an oxygen-containing source e.g., oxygen (O 2 ), ozone (O 3 ), etc.
- an inert gas e.g., argon(
- the thickness of dielectric layer 116 may vary according to the processing node in which the semiconductor device is being fabricated. In one example, the thickness of dielectric layer 116 may be in the range of about 0.1 to 50 nanometers.
- deposition processes employed to provide the dielectric layer between gate structures 104 , 106 and 108 disadvantageously often result in a non-uniform deposition of the dielectric layer within the high aspect ratio openings, thereby resulting in voids or defects within the dielectric layer. Consequently, according to the present invention a portion of dielectric layer may be selectively removed, as depicted in FIG. 2 , by employing suitable fluorine-containing etching chemistries.
- fluorine-containing etchants include nitrogen trifluoride (NF 3 ).
- a controlled etching process may be employed using nitrogen trifluoride (NF 3 ) as a process gas, at a flow rate of about 100 sccm to about 1000 sccm and at temperature ranging from about 300° C. to about 500° C.
- NF 3 nitrogen trifluoride
- This controlled etching process results in removing a portion of dielectric layer, leaving a remaining portion of dielectric layer 116 , between respective gate structures 104 , 106 and 108 .
- this controlled etching process disadvantageously results in consuming, at least in part, a remaining portion of consumable material, for example, a portion of the dopant present within the predetermined initial elemental composition (for instance, stoichiometric silicon dioxide (SiO 2 ) compositions having dopant concentrations), of the remaining portion of dielectric layer 116 .
- a portion of the consumable material for example, a portion of the dopant present within the predetermined initial elemental composition (for instance, stoichiometric silicon dioxide (SiO 2 ) compositions having dopant concentrations)
- This consumption of a portion of the consumable material results in depleted region 118 , within the remaining portion of dielectric layer 116 , the depleted region having a loss of, at least a portion of, dopants.
- the portion of dopant, for example, nitrogen or phosphorus, consumed within depleted region 118 of the remaining portion of dielectric layer 116 results in the loss of dopant in the range of about 0.01 to 5 atomic percent % (at. wt. %).
- controlled in this context means that the conventional process conditions, such as, for instance, flow rate, time, for which the etching process is etched, is typically controlled and limited to the desired portion of the consumable dopant consumed within the depleted region.
- FIG. 3 depicts the semiconductor structure of FIG. 2 after subjecting depleted region 118 (see FIG. 2 ) of remaining portion of dielectric layer 116 to a treatment process, in accordance with one or more aspects of the present invention.
- This treatment process advantageously results in restoring depleted region 118 (see FIG. 2 ) of the remaining portion of dielectric layer 116 , to the same initial elemental composition of the original dielectric layer deposited between gate structures 104 , 106 and 108 , as discussed above in connection with FIG. 1 .
- depleted region 118 (see FIG. 2 ) of the remaining portion of dielectric layer 116 may be restored to the same initial elemental composition with a replacement consumable material, for instance, dopants such as, nitrogen or phosphorus.
- the dopant of the replacement consumable material restored within depleted region 118 will be substantially similar to the consumable material, for instance, dopant consumed within the depleted region.
- depleted region 118 of the remaining portion of dielectric layer 116 may be subjected to a treatment process using process gas, such as ammonia (NH 3 ).
- process gas such as ammonia (NH 3 ).
- depleted region 118 of the remaining portion of dielectric layer 116 may be subjected to a treatment process using, for instance, phosphine as a process gas.
- the treatment process may be accomplished by facilitating an interaction between depleted region 118 (see FIG. 2 ) of the remaining portion of dielectric layer 116 and at least one source of the replacement consumable material, for instance, having an n-type dopant such as, nitrogen or phosphorus.
- An interaction between depleted region 118 (see FIG. 2 ) and the source of the replacement consumable material may be facilitated using conventional processing techniques, including but are not limited to, ion implantation, chemical reaction and the like., using a plasma processing chamber.
- dielectric layer 116 for instance, containing nitrogen-doped silicon dioxide or phosphorus-doped silicon dioxide (also referred to herein as phosphorus silica glass (PSG)) with depleted region 118 (see FIG. 2 ) having a loss of dopants such as, for example, nitrogen or phosphorus, in the range of about 0.01 to about 5 atomic percent % (at.wt.
- PSG phosphorus silica glass
- nitrogen-containing source e.g., ammonia (NH 3 )
- phosphorus-containing source e.g., phosphine (PH 3 )
- undoped silicon-containing source e.g., silane (SiH 4 ), disilane (Si 2 H 6 ), etc.
- oxygen-containing source e.g., oxygen (O 2 ), ozone (O 3 ), etc.
- inert gas e.g., argon(Ar), helium (He), etc., using high-density-plasma CVD (HDP-CVD) process.
- HDP-CVD high-density-plasma CVD
- dielectric layer 116 for instance, containing nitrogen-doped silicon dioxide or phosphorus-doped silicon dioxide, having a depleted region 118 may be implanted with at least one replacement consumable material, having a dopant such as, nitrogen or phosphorus, either in presence of or without the presence of undoped silicon, to restore the portion of the consumable material consumed within the depleted region of the remaining portion of the dielectric layer.
- a replacement consumable material having a dopant such as, nitrogen or phosphorus
- FIG. 4 depicts the intermediate semiconductor structure of FIG. 3 , after repeating the process steps depicted in FIGS. 1-3 , sequentially in one or more iterations, as discussed above, in accordance with one or more aspects of the present invention.
- This sequential repetition of process steps, in the order discussed above, advantageously facilitates in providing a plurality of dielectric layers, for instance, second layer 120 of dielectric layer/material with at least one consumable material such as dopant over a first layer 116 of dielectric layer/material having at least one replacement consumable material.
- the multi-step processing technique includes, for instance, deposition (step of FIG. 1 ), etching (step of FIG. 2 ), treating (step of FIG.
- this multi-step processing technique proceeds by providing a dielectric layer, for instance, a silicon-based high aspect ratio oxide having a predetermined initial elemental composition of doped silicon dioxide, with at least one consumable doping material or undoped silicon dioxide over layer of dielectric material/layer 116 , having a replacement consumable doping material or replacement consumable undoped material.
- a dielectric layer for instance, a silicon-based high aspect ratio oxide having a predetermined initial elemental composition of doped silicon dioxide, with at least one consumable doping material or undoped silicon dioxide over layer of dielectric material/layer 116 , having a replacement consumable doping material or replacement consumable undoped material.
- a portion of second layer 120 of dielectric material/layer may be selectively removed using controlled selective etching process in presence of fluorine-containing etching chemistries, leaving a depleted region within the remaining portion of second layer 120 of dielectric material/layer.
- the depleted region of second layer of dielectric material/layer is then subjected to a treatment process, for instance, ion implantation, to restore the depleted region of the remaining portion of second layer 120 of dielectric layer to the same initial elemental composition with a replacement consumable doping material.
- the dielectric layers 116 , 120 advantageously facilitate in minimizing the layering effect, that would otherwise be caused, for instance, by the loss of dopants during the etching process, thereby creating a substantially planar, defect-free interlayer structure, for example, of one or more dielectric layers and, in turn, facilitating fabrication of defect-free semiconductor structure.
- Such structure may be further processed as shown in FIGS. 5 and 6 , as further discussed, for example, herein to achieve intermediate semiconductor structure as shown in FIG. 6 .
- FIG. 5 depicts the structure of FIG. 4 after further processing to recess protective hard masks 114 (see FIG. 4 ) protecting the underlying gate structures 104 , 106 and 108 .
- Any suitable etching process such as, conventional isotopic or anisotropic dry-etching processes such as, reactive ion etching or plasma etching, may be employed resulting in exposing gate structures 104 , 106 and 108 .
- reactive ion etching may be performed using remote plasma involving process gases such as nitrogen trifluoride (NF 3 ) and hydrogen (H 2 ).
- the protective hard mask may be recessed to a height of about 5 nanometers to about 10 nanometers below the upper surfaces of gate structures 104 , 106 and 108 .
- the exposed gate structures may selectively be removed using any suitable conventional etching process(es).
- the exposed gate structures may be removed using a conventional anisotropic dry etching process or an isotropic wet etching process.
- isotropic wet etching may be performed using wet etchants such as, for example, ammonium hydroxide or HF:Nitric acid:Acetic acid solution (also HNA etch).
- reactive ion etching or plasma etching may also be employed to remove the exposed adjacent gate structures.
- the multi-step processing technique for instance “dep/etch/treat/dep” technique, described in the present invention facilitates in restoring the depleted region of the dielectric layer to the initial elemental composition with a replacement consumable material such as, for example, nitrogen or phosphorus, resulting in eliminating or minimizing the layering effect, that would otherwise be caused by the loss of consumable doping materials, during the etching process.
- This elimination or minimization of layering effect of respective dielectric layers advantageously, results in creating a substantially planar, defect-free interlayer structure, for example, of one or more dielectric layers, which in turn, facilitates in fabricating a defect-free semiconductor structure.
- the resultant deposited structure minimizes or eliminates distinguishable layers yielding a uniform defect minimized or free semiconductor structure.
- the fabrication processing described herein may be employed in providing a defect-free interlayer structure of one or more dielectric layers, within other high aspect ratio openings, associated with various circuit features, for instance, intermetal dielectric (IMD) features, pre-metal dielectric (PMD) features or isolation features, including shallow trench isolation regions, across the semiconductor wafer, and thereby facilitating fabricating a defect-free semiconductor structure.
- IMD intermetal dielectric
- PMD pre-metal dielectric
- isolation features including shallow trench isolation regions
- a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements.
- a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features.
- a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
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Abstract
Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
Description
- The present invention relates to structures and methods of facilitating fabricating semiconductor structures, and more particularly, to structures and methods of fabricating defect-free semiconductor structure, for use, in fabrication of integrated circuits.
- A semiconductor device fabrication, such as transistor fabrication, typically involves deposition of dielectric layers within high aspect ratio openings, associated with various circuit features, for instance, intermetal dielectric (IMD) features, pre-metal dielectric (PMD) features or isolation features, including shallow trench isolation regions. As the size of technology nodes continues to decrease, significant challenges continues to arise due, in part, to limitations of available fabrication techniques, including issues related to planarity and defects within the dielectric layers.
- The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method which includes, for instance: providing a dielectric layer, the dielectric layer including at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
- In a further aspect, a semiconductor structure is provided which includes: an interlayer structure, the interlayer structure including: at least one first dielectric layer disposed above a semiconductor substrate, one first dielectric layer of the at least one first dielectric layer having a first elemental composition, wherein the first elemental composition includes at least one replacement consumable material; and a second dielectric layer disposed above the at least one first dielectric layer, the second dielectric layer having a second elemental composition, wherein the second elemental composition includes at least one consumable material.
- Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
- One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 is a cross-sectional elevational view of one embodiment of an intermediate semiconductor structure, which includes a dielectric layer disposed over semiconductor substrate, and is obtained during semiconductor fabrication process, in accordance with one or more aspects of the present invention; -
FIG. 2 depicts the semiconductor structure ofFIG. 1 , after selectively removing a portion of the dielectric layer, leaving, in part, a depleted region, in accordance with one or more aspects of the present invention; -
FIG. 3 depicts the semiconductor structure ofFIG. 2 , after subjecting the depleted region to a treatment process, in accordance with one or more aspects of the present invention; -
FIG. 4 depicts the intermediate semiconductor structure ofFIG. 3 , after creating a substantially planar, defect-free semiconductor structure, in accordance with one or more aspects of the present invention; -
FIG. 5 depicts the intermediate semiconductor structure of FIG. - 4, with gate structures having been exposed, in accordance with one or more aspects of the present invention; and
-
FIG. 6 depicts the intermediate semiconductor structure ofFIG. 5 after removal of exposed gate structures, in accordance with one or more aspects of the present invention. - Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
- One aspect of integrated circuit fabrication (also referred to as herein semiconductor device fabrication) typically involves deposition of dielectric layer within high aspect ratio openings, associated with various circuit features, for instance, intermetal dielectric (IMD) features, pre-metal dielectric (PMD) features or isolation features, including shallow trench isolation regions. In one example, dielectric layers may include doped or undoped silicon-based high aspect ratio oxides such as, for instance, High-Density-Plasma silicon dioxide (HDP-SiO2), High Aspect Ratio Process (HARP) oxide or ozone-tetraethylorthosilicate (O3-TEOS) oxide.
- By way of example, in a conventional semiconductor device fabrication, dielectric layer including, for instance, doped High-Density-Plasma (HDP) silicon dioxide, may generally be deposited using thermal chemical vapor deposition (CVD) or plasma enhanced chemical vapor depostion (PECVD) processes, for instance, by treating an oxygen-containing source such as oxygen (O2) or ozone (O3), with a silicon-containing source. As integration density of transistors continues to increase, the area available for providing a substantially planar, defect-free dielectric layer within the high aspect ratio openings continues to decrease. This decrease in available footprint area within the high aspect ratio openings often results in a multi-step processing technique being employed, in one or more iterations, to provide the dielectric layer. In one example, the multi-step processing technique includes, for instance, deposition, etching and deposition technique (also referred to herein as “dep/etch/dep” processing), wherein a portion of dielectric layer is etched using a suitable etching process, for instance, fluorine-based etching process, followed by deposition of a second layer of dielectric layer. However, this multi-step processing technique will often result in creating defects between the respective dielectric layers, for instance, due to the loss of dopants during the etching processes, thereby resulting in layering (referred to herein as “layering effect”) of the respective dielectric layers, and in turn, propagating defects within the semiconductor structure.
- Generally stated, disclosed herein, in one aspect, is a method of facilitating fabrication of substantially planar, defect-free semiconductor structure. The method includes: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
- In one embodiment, the dielectric layer includes, for example, a silicon-based high aspect ratio oxide having an initial elemental composition. The silicon-based high aspect ratio oxide having the initial elemental composition may include the at least one consumable material such as, for instance, a doped material. By way of example, the doped material may include at least one of nitrogen and phosphorus. In such a case, the selectively removing consumes, in part, a remaining portion of the at least one consumable material, for instance, a doped material, from within the initial elemental composition of the remaining portion of the dielectric layer, leaving, the depleted region within the remaining portion of the dielectric layer. The subjecting the depleted region further includes restoring the depleted region, for instance, of the remaining portion of the dielectric layer, to the initial elemental composition with the at least one replacement consumable material.
- Further, in one embodiment, the remaining portion of the at least one consumable material consumed within the depleted region and the at least one replacement consumable material restored within the depleted region include a same material, for example, nitrogen, phosphorus and undoped silicon.
- In one implementation, the treatment process includes facilitating an interaction between the depleted region and at least one source of the at least one replacement consumable material, the interaction restoring the depleted region with the at least one replacement consumable material. The at least one source of the at least one replacement consumable material, for instance, includes at least one of nitrogen source such as, ammonia gas; phosphorus source such as, phosphine gas; and undoped silicon source such as silane gas.
- In another implementation, the treatment process includes implanting the depleted region with the at least one replacement consumable material to restore the portion of the consumed at least one consumable material, for instance, the at least one replacement consumable material including at least one of doped material and undoped silicon. By way of example, the doped material includes at least one of nitrogen and phosphorus. Selectively removing the portion of the dielectric layer includes selectively etching the portion of the dielectric layer using nitrogen trifluoride plasma.
- In a further embodiment, the method includes repeating sequentially, in at least one or more iterations, the providing a dielectric layer, the selectively removing the portion of the dielectric layer, and the subjecting the depleted region to the treatment process, to achieve the defect-free semiconductor structure. Repeating sequentially further includes providing a plurality of dielectric layer, the providing facilitates minimizing the layering effect between the plurality of dielectric layers, and creating substantially planar, defect-free interlayer structure of the plurality of dielectric layers.
- Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
- By way of example,
FIGS. 1-6 depict one detailed embodiment of a method of facilitating fabrication of a defect-free semiconductor structure, for instance, by creating substantially planar, defect-free dielectric layer for use, in fabrication of integrated circuits, in accordance with one or more aspects of the present invention. -
FIG. 1 illustrates anintermediate semiconductor structure 100, attained during fabrication of one or more interlayer structures, in accordance with one or more aspects of the present invention. In the example shown,intermediate structure 100 includes asemiconductor substrate 102, such as a bulk semiconductor material, for example, a bulk silicon wafer. In one example,semiconductor substrate 102 may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI), or silicon-on-replacement (SRI) substrates and the like.Semiconductor substrate 102 may in addition or instead include various isolations, dopings, and/or device features. The semiconductor substrate may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, or GaInAsP or combinations thereof. - Although not critical to the invention,
intermediate semiconductor structure 100 may include a plurality ofgate structures isolation features 110, for instance, shallow trench isolation features (STI). One skilled in the art will know that, the formation of isolation regions, such as, shallow trench isolation may include, for instance, forming a recess within the semiconductor substrate and filling the recess with a dielectric material, for instance, high-density-plasma (HDP) silicon dioxide or TEOS (tetraethylorthosilicate) based silicon oxide, silicon nitride and the like. Although not critical to the invention,gate structures - Although not critical to the invention,
intermediate semiconductor structure 100 may further include source and drain regions (also referred to as active region 112) is provided oversemiconductor substrate 102.Active region 112 may be formed using any suitable techniques, for instance, ion implantation, epitaxial growth of the embedded source/drain materials and activation anneals. -
Intermediate structure 100 may further include a protectivehard mask 114, which disposed along the sidewalls and the upper surfaces ofrespective gate structures hard mask 114 may be deposited using conventional deposition processes, such as, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure CVD, or plasma-enhanced CVD (PE-CVD). In one example, protectivehard mask 114 may have conventional thickness and may include or be fabricated of a material such as, for example, silicon nitride. - A
dielectric layer 116 is disposed between and overgate structures Dielectric layer 116 may include or be fabricated of a dielectric material such as, for example, silicon-based high aspect ratio oxide. By way of example, the silicon-based high aspect ratio oxide may include but are not limited to, High-Density-Plasma (HDP) silicon dioxide, high aspect ratio process (HARP) oxide, and may be conformally deposited using conventional deposition processes such as, chemical vapor deposition (CVD), high-density-plasma CVD (HDP-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) processes and the like. - In accordance with one aspect of the present invention, silicon-based high aspect ratio oxide may include undoped silicon dioxide, with a predetermined initial elemental composition of silicon dioxide (SiO2). In one example, undoped silicon dioxide may be deposited, by employing high-density-plasma CVD (HDP-CVD) process using process gases that include silicon-containing source (e.g., silane (SiH4), disilane (Si2H6), etc.,), an oxygen-containing source (e.g., oxygen (O2), ozone (O3), etc.,) and an inert gas (e.g., argon(Ar), helium (He), etc.,). In another aspect, silicon-based high aspect ratio oxide may also include doped silicon dioxide, with a predetermined initial elemental composition of stoichiometric silicon dioxide (SiO2) compositions with dopant concentrations in the range of about 0.01 to 10 atomic percent (at. wt. %), the dopants being consumable materials. In one example, the dopants employed may include but are not limited to, n-type dopants. Note that as used herein, n-type dopant refers to the addition of impurities to, for instance, an intrinsic dielectric material/layer, which contribute more electrons to an intrinsic material, and may include (for instance) nitrogen, phosphorus and the like. In one example, nitrogen-doped silicon dioxide or phosphorus-doped silicon dioxide (also referred to herein as phosphorus silica glass (PSG)) may be deposited, by employing high-density-plasma CVD (HDP-CVD) process using process gases that include silicon-containing source (e.g., silane (SiH4), disilane (Si2H6), etc.,), an oxygen-containing source (e.g., oxygen (O2), ozone (O3), etc.,) and an inert gas (e.g., argon(Ar), helium (He), etc.,) along with suitable dopant precursors such as, for example, ammonia (NH3), phosphine (PH3) respectively. Although the
dielectric layer 116 may have conventional suitable thickness, the thickness ofdielectric layer 116, in one example, may vary according to the processing node in which the semiconductor device is being fabricated. In one example, the thickness ofdielectric layer 116 may be in the range of about 0.1 to 50 nanometers. - Prior to the present invention, deposition processes employed to provide the dielectric layer between
gate structures FIG.1 , disadvantageously often result in a non-uniform deposition of the dielectric layer within the high aspect ratio openings, thereby resulting in voids or defects within the dielectric layer. Consequently, according to the present invention a portion of dielectric layer may be selectively removed, as depicted inFIG. 2 , by employing suitable fluorine-containing etching chemistries. One suitable example of fluorine-containing etchants include nitrogen trifluoride (NF3). In one example, a controlled etching process may be employed using nitrogen trifluoride (NF3) as a process gas, at a flow rate of about 100 sccm to about 1000 sccm and at temperature ranging from about 300° C. to about 500° C. This controlled etching process results in removing a portion of dielectric layer, leaving a remaining portion ofdielectric layer 116, betweenrespective gate structures dielectric layer 116. This consumption of a portion of the consumable material results in depletedregion 118, within the remaining portion ofdielectric layer 116, the depleted region having a loss of, at least a portion of, dopants. In one example, the portion of dopant, for example, nitrogen or phosphorus, consumed within depletedregion 118 of the remaining portion ofdielectric layer 116 results in the loss of dopant in the range of about 0.01 to 5 atomic percent % (at. wt. %). As understood, “controlled” in this context means that the conventional process conditions, such as, for instance, flow rate, time, for which the etching process is etched, is typically controlled and limited to the desired portion of the consumable dopant consumed within the depleted region. -
FIG. 3 depicts the semiconductor structure ofFIG. 2 after subjecting depleted region 118 (seeFIG. 2 ) of remaining portion ofdielectric layer 116 to a treatment process, in accordance with one or more aspects of the present invention. This treatment process advantageously results in restoring depleted region 118 (seeFIG. 2 ) of the remaining portion ofdielectric layer 116, to the same initial elemental composition of the original dielectric layer deposited betweengate structures FIG. 1 . Note that depleted region 118 (seeFIG. 2 ) of the remaining portion ofdielectric layer 116 may be restored to the same initial elemental composition with a replacement consumable material, for instance, dopants such as, nitrogen or phosphorus. One skilled in the art will note that, the dopant of the replacement consumable material restored within depletedregion 118 will be substantially similar to the consumable material, for instance, dopant consumed within the depleted region. In a specific example, if the dopant consumed within depletedregion 118 were to be nitrogen, depletedregion 118 of the remaining portion ofdielectric layer 116 may be subjected to a treatment process using process gas, such as ammonia (NH3). In another specific example, if the dopant consumed within depletedregion 118 were to be phosphorus, depletedregion 118 of the remaining portion ofdielectric layer 116 may be subjected to a treatment process using, for instance, phosphine as a process gas. - By way of an example, the treatment process may be accomplished by facilitating an interaction between depleted region 118 (see
FIG. 2 ) of the remaining portion ofdielectric layer 116 and at least one source of the replacement consumable material, for instance, having an n-type dopant such as, nitrogen or phosphorus. An interaction between depleted region 118 (seeFIG. 2 ) and the source of the replacement consumable material may be facilitated using conventional processing techniques, including but are not limited to, ion implantation, chemical reaction and the like., using a plasma processing chamber. In one example,dielectric layer 116, for instance, containing nitrogen-doped silicon dioxide or phosphorus-doped silicon dioxide (also referred to herein as phosphorus silica glass (PSG)) with depleted region 118 (seeFIG. 2 ) having a loss of dopants such as, for example, nitrogen or phosphorus, in the range of about 0.01 to about 5 atomic percent % (at.wt. %), is treated with nitrogen-containing source (e.g., ammonia (NH3)) or phosphorus-containing source (e.g., phosphine (PH3)) respectively, either in presence of or without the presence of undoped silicon-containing source (e.g., silane (SiH4), disilane (Si2H6), etc.,), an oxygen-containing source (e.g., oxygen (O2), ozone (O3), etc.,) and an inert gas (e.g., argon(Ar), helium (He), etc.,) using high-density-plasma CVD (HDP-CVD) process. In an alternate example,dielectric layer 116, for instance, containing nitrogen-doped silicon dioxide or phosphorus-doped silicon dioxide, having a depletedregion 118 may be implanted with at least one replacement consumable material, having a dopant such as, nitrogen or phosphorus, either in presence of or without the presence of undoped silicon, to restore the portion of the consumable material consumed within the depleted region of the remaining portion of the dielectric layer. -
FIG. 4 depicts the intermediate semiconductor structure ofFIG. 3 , after repeating the process steps depicted inFIGS. 1-3 , sequentially in one or more iterations, as discussed above, in accordance with one or more aspects of the present invention. This sequential repetition of process steps, in the order discussed above, advantageously facilitates in providing a plurality of dielectric layers, for instance,second layer 120 of dielectric layer/material with at least one consumable material such as dopant over afirst layer 116 of dielectric layer/material having at least one replacement consumable material. Although not discussed in detail for the sake of brevity, in one specific example, the multi-step processing technique includes, for instance, deposition (step ofFIG. 1 ), etching (step ofFIG. 2 ), treating (step ofFIG. 3 ) and deposition techniques (repeating the step ofFIG. 1 ), the multi-step processing technique also being referred to herein as “dep/etch/treat/dep” processing technique. By way of example, this multi-step processing technique proceeds by providing a dielectric layer, for instance, a silicon-based high aspect ratio oxide having a predetermined initial elemental composition of doped silicon dioxide, with at least one consumable doping material or undoped silicon dioxide over layer of dielectric material/layer 116, having a replacement consumable doping material or replacement consumable undoped material. A portion ofsecond layer 120 of dielectric material/layer may be selectively removed using controlled selective etching process in presence of fluorine-containing etching chemistries, leaving a depleted region within the remaining portion ofsecond layer 120 of dielectric material/layer. The depleted region of second layer of dielectric material/layer is then subjected to a treatment process, for instance, ion implantation, to restore the depleted region of the remaining portion ofsecond layer 120 of dielectric layer to the same initial elemental composition with a replacement consumable doping material. Note that thedielectric layers - When or after the intermediate semiconductor structure shown in
FIG. 4 has been obtained, such structure may be further processed as shown inFIGS. 5 and 6 , as further discussed, for example, herein to achieve intermediate semiconductor structure as shown inFIG. 6 . -
FIG. 5 depicts the structure ofFIG. 4 after further processing to recess protective hard masks 114 (seeFIG. 4 ) protecting theunderlying gate structures gate structures gate structures - As illustrated in
FIG. 6 , the exposed gate structures, holding the gate positions for subsequent metal gate structures to be formed, may selectively be removed using any suitable conventional etching process(es). In one example, the exposed gate structures may be removed using a conventional anisotropic dry etching process or an isotropic wet etching process. In one example, isotropic wet etching may be performed using wet etchants such as, for example, ammonium hydroxide or HF:Nitric acid:Acetic acid solution (also HNA etch). In an alternate example, reactive ion etching or plasma etching may also be employed to remove the exposed adjacent gate structures. - The multi-step processing technique, for instance “dep/etch/treat/dep” technique, described in the present invention facilitates in restoring the depleted region of the dielectric layer to the initial elemental composition with a replacement consumable material such as, for example, nitrogen or phosphorus, resulting in eliminating or minimizing the layering effect, that would otherwise be caused by the loss of consumable doping materials, during the etching process. This elimination or minimization of layering effect of respective dielectric layers, advantageously, results in creating a substantially planar, defect-free interlayer structure, for example, of one or more dielectric layers, which in turn, facilitates in fabricating a defect-free semiconductor structure. The resultant deposited structure minimizes or eliminates distinguishable layers yielding a uniform defect minimized or free semiconductor structure.
- Advantageously, the fabrication processing described herein may be employed in providing a defect-free interlayer structure of one or more dielectric layers, within other high aspect ratio openings, associated with various circuit features, for instance, intermetal dielectric (IMD) features, pre-metal dielectric (PMD) features or isolation features, including shallow trench isolation regions, across the semiconductor wafer, and thereby facilitating fabricating a defect-free semiconductor structure.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (7)
1-14. (canceled)
15. A semiconductor structure comprising:
an interlayer structure, the interlayer structure comprising:
at least one first dielectric layer disposed above a semiconductor substrate, one first dielectric layer of the at least one first dielectric layer having a first elemental composition, wherein the first elemental composition comprises at least one implanted replacement consumable material, wherein said at least one implanted replacement consumable material comprises at least one of: (i) doping or dopant material and (ii) undoped silicon; and
a second dielectric layer disposed above the at least one first dielectric layer, the second dielectric layer having a second elemental composition, wherein the second elemental composition comprises at least one consumable material.
16. The semiconductor structure of claim 15 , wherein the at least one consumable material of the second dielectric layer and the at least one implanted replacement consumable material of the at least one first dielectric layer comprise a same material, the same material comprising at least one of: (i) nitrogen, (ii) phosphorus and (iii) undoped silicon.
17. The semiconductor structure of claim 15 , wherein the second dielectric layer having the second elemental composition and the one first dielectric layer of the at least one first dielectric layer having the first elemental composition comprise a same material.
18. The semiconductor structure of claim 17 , wherein the same material comprises at least one of: (i) a silicon-based high aspect ratio oxide and (ii) a doping or dopant material.
19. The semiconductor structure of claim 18 , wherein the doping or dopant material comprises at least one of: (i) nitrogen and (ii) phosphorus.
20. The semiconductor structure of claim 15 , wherein the semiconductor structure further comprises a substantially planar, defect-free semiconductor structure, wherein the interlayer structure of the substantially planar, defect-free semiconductor structure comprises the one first dielectric layer of the at least one first dielectric layer, and the second dielectric layer disposed over the one first dielectric layer of the at least one first dielectric layer.
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US6218268B1 (en) * | 1998-05-05 | 2001-04-17 | Applied Materials, Inc. | Two-step borophosphosilicate glass deposition process and related devices and apparatus |
US6444593B1 (en) * | 1998-12-02 | 2002-09-03 | Advanced Micro Devices, Inc. | Surface treatment of low-K SiOF to prevent metal interaction |
US6348706B1 (en) * | 2000-03-20 | 2002-02-19 | Micron Technology, Inc. | Method to form etch and/or CMP stop layers |
US6444136B1 (en) * | 2000-04-25 | 2002-09-03 | Newport Fab, Llc | Fabrication of improved low-k dielectric structures |
US7001854B1 (en) * | 2001-08-03 | 2006-02-21 | Novellus Systems, Inc. | Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures |
US7972968B2 (en) * | 2008-08-18 | 2011-07-05 | Applied Materials, Inc. | High density plasma gapfill deposition-etch-deposition process etchant |
US8497211B2 (en) * | 2011-06-24 | 2013-07-30 | Applied Materials, Inc. | Integrated process modulation for PSG gapfill |
US8916429B2 (en) * | 2012-04-30 | 2014-12-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Aqueous cleaning techniques and compositions for use in semiconductor device manufacturing |
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US6787469B2 (en) * | 2001-12-28 | 2004-09-07 | Texas Instruments Incorporated | Double pattern and etch of poly with hard mask |
US6942958B2 (en) * | 2002-01-04 | 2005-09-13 | Intel Corporation | Modifying circuitry features in radiation sensitive layers with active secondary exposure masks |
US7598174B1 (en) * | 2008-05-27 | 2009-10-06 | Infineon Technologies Ag | Feature patterning methods |
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