US20150333764A1 - Digital-to-analog converter circuit for use in a power converter - Google Patents
Digital-to-analog converter circuit for use in a power converter Download PDFInfo
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- US20150333764A1 US20150333764A1 US14/276,834 US201414276834A US2015333764A1 US 20150333764 A1 US20150333764 A1 US 20150333764A1 US 201414276834 A US201414276834 A US 201414276834A US 2015333764 A1 US2015333764 A1 US 2015333764A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/745—Simultaneous conversion using current sources as quantisation value generators with weighted currents
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/82—Digital/analogue converters with intermediate conversion to time interval
- H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation
- H03M1/825—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation by comparing the input signal with a digital ramp signal
Definitions
- the present invention relates generally to power supplies, and more specifically, the invention relates to switch mode power supplies.
- Switch mode power converters also referred to as switch mode power supplies, are commonly used due to their high efficiency, small size, and low weight to convert the high voltage ac power to a regulated dc power.
- switch mode power converters are used to provide regulated power to light emitting diode (LED) devices.
- a switch mode power converter One important consideration for a switch mode power converter is the shape and the phase of the input current drawn from the power source relative to the ac input voltage.
- the shape of the ac input voltage is typically sinusoidal but because a switching power converter presents itself as a non-linear load, the shape of the input current drawn from the power source may become distorted (non-sinusoidal) and/or out of phase with ac input voltage. This results in increased power loss in the power distribution systems.
- the power factor may be defined as the ratio of the average power over a cycle to the product of the root mean square (rms) voltage and the rms current. That is, the power factor may represent the ratio of the amount of usable power to the amount of total power delivered to the load. As such, the power factor may have a value between zero and one, with unity power factor being the optimal. If the input current is sinusoidal and perfectly in-phase with the input voltage, the power factor of the power supply is one, and none of the energy delivered to the load is returned to the power source.
- the switch mode power supply distorts the wave shape of the input current and/or introduces a phase shift with respect to the input voltage, the power factor decreases.
- Several regulatory agencies have set tight standards that typically stipulate for greater power factors and/or lower harmonic content of the input current.
- switch mode power supplies may be required to perform PFC is power conversion systems that are used in light emitting diode (LED) lighting. Since the brightness of light provided by LED lamps is a function of the current through LEDs, the power supply used in such a system may also regulate the current provided to LEDs at the output of the power supply. In other words, the power supply may provide both output current regulation and PFC.
- LED light emitting diode
- Output current regulation is typically achieved by a power supply controller by sensing the current provided to the LEDs.
- a feedback signal is used to represent a current through the LEDs.
- the power supply controller controls the transfer of energy from an input to an output of the power supply in response to the feedback signal.
- Switch mode power supplies typically respond very quickly to fluctuations in the feedback signal by adjusting the energy transfer to regulate the LED current at a desired level. However, making rapid changes to the energy transfer can compromise the PFC performance and cause the input current to be non-sinusoidal and/or out of phase with the input voltage, resulting in a reduced power factor.
- a switch mode power supply may use a controller to control the switching (i.e., the turning on and turning off) of a power switch to provide a desired output to a load.
- the controller may regulate the output at a desired level in response to a feedback signal representative of the output of the power supply.
- Some controllers may use a digital control signal to adjust the operating condition (e.g., on-time, switching frequency) of the power switch in response to the feedback signal.
- Such a controller may employ a digital-to-analog converter (DAC) to convert the binary values of the control signal to corresponding discrete levels of an analog signal that may be used to set the operating condition of the power switch.
- DAC digital-to-analog converter
- DACs such as binary-weighted DACs
- the number of the bits of the control signal is increased, the number of different operating conditions to which the power switch can be set is increased.
- the area on the silicon occupied by the DAC components such as current sources, resistors, etc., may grow and make such an implementation impractical.
- FIG. 1A shows a schematic diagram illustrating an example switch mode power converter including a controller with a state selector circuit and a driver circuit in accordance with the teachings of the present invention.
- FIG. 1B shows examples of relationships of switching frequency with respect to a state signal of an example switch mode power converter including a controller in accordance with the teachings of the present invention.
- FIG. 2A shows a circuit diagram illustrating one example of the state selector circuit of the controller in FIG. 1A in accordance with the teachings of the present invention.
- FIG. 2B shows a circuit diagram illustrating another example of the state selector circuit of the controller in FIG. 1A in accordance with the teachings of the present invention.
- FIG. 2C shows a circuit diagram illustrating yet another example of the state selector circuit of the controller in FIG. 1A in accordance with the teachings of the present invention.
- FIG. 3A shows an example set of waveforms illustrating the operation of the controller in FIG. 1A in accordance with the teachings of the present invention.
- FIG. 3B shows another example set of waveforms illustrating the operation of the controller in FIG. 1A in accordance with the teachings of the present invention.
- FIG. 3C shows yet another example set of waveforms illustrating the operation of the controller in FIG. 1A in accordance with the teachings of the present invention.
- FIG. 4A shows a flow diagram illustrating an example process for adjusting the operating condition of a switch of a power supply in accordance with the teachings of the present invention.
- FIG. 4B shows a flow diagram illustrating one example of detailed steps of one the process blocks of the process shown in FIG. 4A in accordance with the teachings of the present invention.
- FIG. 4C shows a flow diagram illustrating one example of detailed steps of another one of the process blocks of the process shown in FIG. 4A in accordance with the teachings of the present invention.
- FIG. 5 shows a circuit diagram illustrating an example driver circuit including one example of a modulated DAC in accordance with the teachings of the present invention.
- FIG. 6 shows a table illustrating different values of an example digital signal received as an input by the driver circuit in FIG. 5 and a timing diagram illustrating waveforms for various signals that are associated with the example modulated DAC in accordance with the teachings of the present invention.
- FIG. 7 shows a collection of signal levels illustrating example average values for the output of the modulated DAC of FIG. 5 in accordance with the teachings of the present invention.
- FIG. 8 shows a circuit diagram illustrating another example of a driver circuit in accordance with the teachings of the present invention.
- FIG. 9 shows a flow diagram illustrating an example process for generating an analog signal having discrete levels in response to a digital signal in one example of a power supply controller in accordance with the teachings of the present invention.
- an example power converter in accordance with the teachings of the present invention includes a controller with a state selector circuit that generates multiple count signals in response to comparisons of a feedback signal of the power converter with different threshold signals.
- the state selector circuit generates two count signals, first count signal and second count signal, and outputs a state signal in response to these count signals.
- the state selector circuit may be coupled to change the state signal at a different rate depending on the values of first and second count signals.
- the controller of the example power converter includes a driver circuit that is coupled to generate a drive signal in response to the state signal to drive the switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter in accordance with the teachings of the present invention.
- FIG. 1A shows an example switch mode power converter 100 , also referred to as a switch mode power supply, with a controller 150 that includes a state selector circuit 154 and a driver circuit 156 in accordance with the teachings of the present invention.
- power supply 100 receives an input current T IN 113 and an input voltage V IN 102 to output a dc output voltage V O 120 and a dc output current I O 118 to a load 122 .
- Input voltage V IN 102 may be representative of an ac line voltage.
- Load 122 may include one or more LEDs.
- input voltage V IN 102 is a rectified and filtered ac voltage.
- input voltage V IN 102 is referenced to a ground terminal 104 , which may also be referred to as an input return terminal.
- Output voltage V O 120 is referenced to a ground terminal 105 , which may also be referred to as an output return terminal.
- input return terminal 104 represents the lowest potential or the lowest voltage against that all voltages on the input side of power supply 100 are measured or defined
- output return terminal 105 represents the lowest potential or the lowest voltage against that all voltages on the output side of power supply 100 are measured or defined.
- input return terminal 104 and output return terminal 105 may correspond to the same voltage or potential. In some other cases, input return terminal 104 and output return terminal 105 may correspond to the different voltages or potentials.
- power supply 100 may further include an energy transfer element T 1 124 , a power switch S 1 170 , a diode D 1 114 and a capacitor C 1 116 .
- energy transfer element T 1 124 is a coupled inductor, which is sometimes referred to as a transformer, with a primary winding 110 and a secondary winding 112 .
- primary winding 110 has one end coupled to the input voltage V IN 102 and the opposite end coupled to power switch S 1 170 .
- Secondary winding 112 has one end coupled to return terminal 104 and the opposite end coupled to diode D 1 114 .
- Diode D 1 114 is further coupled to capacitor C 1 116 , which is coupled between the output of power supply 100 and return terminal 104 . While the polarities of primary winding 110 and secondary winding 112 , which are indicated by the dots at one end of each winding (dotted ends have the same polarity), show that power supply 100 is configured as a flyback power supply, it should be appreciated that other power supply topologies may also be used in accordance with the teachings of the present invention.
- power switch S 1 170 represents the operation of a controlled semiconductor device such as for example a metal oxide semiconductor field effect transistor (MOSFET) or for example a bipolar junction transistor (BJT). As shown, power switch S 1 170 is coupled to energy transfer element T 1 124 at primary winding 110 and to the input of power supply 100 at return terminal 104 .
- MOSFET metal oxide semiconductor field effect transistor
- BJT bipolar junction transistor
- controller 150 may be coupled to control the switching of power switch S 1 170 to control the energy transfer from the input to the output of power supply 100 , thereby regulating an output quantity U O 153 (e.g., output voltage V O 120 , output current I O 118 , or the combination of the two) at a desired level.
- controller 150 may control the switching of power switch S 1 170 to provide input current T IN 113 that is in phase with and proportional to input voltage V IN 102 . That is, controller 150 may control the switching of power switch S 1 170 to provide PFC.
- controller 150 may provide a drive signal U DR 162 to power switch S 1 170 to control the switching (i.e., the turning ON and turning OFF) of power switch S 1 170 .
- power switch S 1 170 may be switched to a closed position, which is also referred to as being turned ON or being in an ON state, and in turn, may conduct current that is represented by a switch current I SW 126 .
- power switch S 1 170 may be switched to an open position, which is also referred to as being turned OFF or being in an OFF state, in which power switch S 1 170 may substantially prevent current conduction.
- a clamp circuit 106 is coupled across primary winding 110 of energy transfer element T 1 124 and is coupled to the input of power supply 100 .
- clamp circuit 106 operates to clamp turn-off spikes that result from leakage inductance from primary winding 110 across the switching device S 1 170 .
- controller 150 may be coupled to sense switch current I SW 126 as a sensed switch signal U SSW 144 .
- Any known technique to sense current such as for example receiving the voltage across a resistor conducting the current, or for example receiving a scaled current from a current transformer, or for example receiving the voltage across the on-resistance of a MOSFET that conducts the current, may be used to sense switch current I SW 126 and to provide sensed switch signal U SSW 144 to controller 150 in accordance with the teachings of the present invention.
- controller 150 may be further coupled to receive an input sense signal U INS 142 representative of input voltage V IN 102 and an output sense signal U OS 132 representative of output quantity U O 153 .
- power supply 100 may include an input sense circuit 140 coupled to sense input voltage V IN 102 and produce input sense signal U INS 142 in response to input voltage V IN 102 .
- power supply 100 may include an output sense circuit 130 coupled to sense output quantity U O 153 and produce output sense signal U OS 132 in response to output quantity U O 153 .
- controller 150 may be implemented as a monolithic integrated circuit, with discrete electrical components, or using a combination of discrete and integrated circuits.
- controller 150 and power switch S 1 170 may form a part of an integrated circuit that is manufactured as either a hybrid or a monolithic integrated circuit.
- controller 150 may include a feedback signal generator 152 , a state selector circuit 154 , and a driver circuit 156 .
- feedback signal generator 152 is coupled to receive input sense signal U INS 142 , output sense signal U OS 132 , and sensed switch signal U SSW 144 to produce a feedback signal U FB 158 that is representative of output current I O 118 (i.e., current in load 122 ).
- feedback signal generator 152 may be configured to generate feedback signal U FB 158 only in response to output sense signal U OS 132 .
- feedback signal generator 152 may be configured to generate feedback signal U FB 158 in response to input sense signal U INS 142 , output sense signal U OS 132 , and sensed switch signal U SSW 144 .
- state selector circuit 154 is coupled to receive feedback signal U FB 158 .
- state selector circuit 154 outputs an N bit digital signal illustrated as a state signal U ST 160 .
- state selector circuit 154 may also be coupled to receive input sense signal U INS 142 .
- state selector circuit 154 gathers information regarding certain properties of feedback signal U FB 158 , which may also be referred to as feedback information, at a sampling frequency for a feedback period and adjusts state signal U ST 160 in response to the feedback information at the end of the feedback period.
- the feedback period is several times greater than the period of a clock signal used to sample feedback signal U FB 158 .
- the feedback period may be several times greater than a sampling period of feedback signal U FB 158 .
- the feedback period can be half of the period of the ac line voltage (i.e., half line cycle) and feedback signal U FB 158 can be sampled 512 times during each feedback period. That is, the feedback period can be 512 times greater than the sampling period.
- the feedback period can be equal to the period of the ac line voltage.
- the feedback period may be several times greater than the switching period of power switch S 1 170 . That is, power switch S 1 170 may be switched between the ON state and the OFF state several times (e.g., 1000 times) during the feedback period.
- driver circuit 156 is coupled to receive state signal U ST 160 and output a drive signal U DR 162 to drive the switching of power switch S 1 170 such that an operating condition such as on-time and/or switching frequency of power switch S 1 170 is set according to an operational state indicated by state signal U ST 160 .
- each one of 2 N possible values of state signal U ST 160 may represent a different operational state (i.e., a different on-time and/or switching frequency) for power switch S 1 170 .
- state selector circuit 154 does not adjust state signal U ST 160 until the end of a feedback period.
- driver circuit 156 does not adjust drive signal U DR 162 until the end of the feedback period.
- the operational state (hence, the operating condition of power switch S 1 170 ) is maintained for the entire feedback period in one example in accordance with the teachings of the present invention.
- FIG. 1B shows examples of relationships of switching frequency of power switch S 1 170 with respect to state signal U ST 160 of FIG. 1A in accordance with the teachings of the present invention.
- the switching frequency of power switch S 1 170 varies with state signal U ST 160 .
- state signal U ST 160 shown in FIG. 1A may be a 10 bit digital signal ranging from 0 to 1023, and the switching frequency of power switch S 1 170 may increase (e.g., from 50 kHz to 130 kHz) as state signal U ST 160 increases (e.g., from 0 to 1023).
- the switching frequency of power switch S 1 170 may increase (e.g., from 50 kHz to 130 kHz) as state signal U ST 160 increases until reaching a certain value (e.g., until state signal U ST 160 reaches 512) and may remain at a constant switching frequency (e.g., 130 kHz) for greater values of state signal U ST 160 .
- FIG. 1B provides examples for explanation purposes and that other similar relationships may also exist between the on-time of power switch S 1 170 and state signal U ST 160 in accordance with the teachings of the present invention.
- the example state selector circuit 154 may adjust state signal U ST 160 by an amount that is based on an operation mode of state selector circuit 154 .
- the operation mode of state selector circuit 154 is determined according to the feedback information at the end of a feedback period. For instance, in response to the feedback information at the end of a feedback period, state selector circuit 154 may be operating in a coarse mode of operation. In this coarse mode, state selector circuit 154 may update the sixth bit of state signal U ST 160 in response to the feedback information.
- state selector circuit 154 may increase state signal U ST 160 by 32 (i.e., 0000100000 binary) if the feedback information indicates that state selector circuit 154 should increase state signal U ST 160 and decrease state signal U ST 160 by 32 (i.e., 0000100000 binary) if the feedback information indicates that state selector circuit 154 should decrease state signal U ST 160 .
- state selector circuit 154 may be operating in a fine mode of operation, and update the first bit, or least significant bit, of state signal U ST 160 .
- state selector circuit 154 may increase or decrease state signal U ST 160 by 1 (i.e., 0000000001 binary) in response to the feedback information.
- state selector circuit 154 may vary the resolution of changes made to state signal U ST 160 and thus, may vary the rate of change in power delivery over multiple feedback periods to load 122 in response to the feedback information in accordance with the teachings of the present invention. For example, if the feedback information indicates to state selector circuit 154 that the rate of change (i.e., rate of increase or rate of decrease) in power delivery over multiple feedback periods to load 122 should be greater, state selector circuit 154 may operate in the coarse mode and update state signal U ST 160 , which therefore updates the operating condition of power switch S 1 170 by a greater amount in accordance with the teachings of the present invention.
- the feedback information may include a first information that may represent a difference between a portion of a feedback period that feedback signal U FB 158 is less than a threshold value, and a portion of the feedback period that feedback signal U FB 158 is greater than the threshold value.
- the feedback information may also include a second information that may represent a difference between a portion of a feedback period that feedback signal U FB 158 is less than a lower limit and a portion of the feedback period that feedback signal U FB 158 is greater than an upper limit.
- the threshold value may represent a desired level of regulated output current I O 118 at the output of power supply 100 .
- the lower limit may represent a level of output current I O 118 that is below the desired level (e.g., 10% below the desired level) and the upper limit may represent a level of output current I O 118 that is above the desired level (e.g., 10% above the desired level).
- the first information may represent a difference between an estimated average value of feedback signal U FB 158 and the threshold value.
- state selector circuit 154 may use the first information and/or the second information to determine an operational state and hence, set an operating condition of power switch S 1 170 accordingly.
- state selector circuit 154 may determine that the power delivery to load 122 per unit time should be increased by a greater amount to more quickly bring output current I O 118 closer to the desired level. In this case, state selector circuit 154 may operate in the coarse mode.
- state selector circuit 154 may determine that changes to the power delivery to load 122 should be made with finer resolution. In this case, state selector circuit 154 may operate in the fine mode. In this way, controller 150 can be configured to respond more rapidly to larger transients and remain less responsive to smaller disturbances at the input and/or the output of power supply 100 in accordance with the teachings of the present invention.
- FIG. 2A shows a circuit diagram illustrating one example of the state selector circuit 154 of the controller 150 in FIG. 1A with increased detail in accordance with the teachings of the present invention.
- state selector circuit 154 includes a feedback signal processor 280 that is coupled to receive feedback signal U FB 158 , a sampling signal U SMP 272 , and a feedback period signal U PER 262 .
- feedback signal processor 280 outputs a first count signal U CN1 222 corresponding to the first information and a second count signal U CN2 232 corresponding to the second information.
- feedback signal processor 280 compares feedback signal U FB 158 with a threshold U TH 205 , an upper limit U UP 201 , and a lower limit U LO 203 at a sampling frequency that is determined by the frequency of sampling signal U SMP 272 .
- Feedback signal processor 280 updates first count signal U CN1 222 and second count signal U CN2 232 based on the results of the comparisons during the feedback period.
- threshold U TH 205 corresponds to the threshold value (i.e., desired value of output current I O 118 )
- lower limit U LO 203 corresponds to the lower limit
- upper limit U UP 201 corresponds to the upper limit.
- FIG. 2A shows state selector 154 including a feedback period signal generator 260 that generates feedback period signal U PER 262 and a sampling clock generator 270 that generates sampling signal U SMP 272 .
- feedback period signal generator 260 may output a pulse at set intervals (i.e., a periodic pulse with a certain period) as feedback period signal U PER 262 .
- Each one of the intervals i.e., the period of feedback period signal U PER 262
- feedback period signal U PER 262 can indicate the beginning and the end of a feedback period.
- the period of feedback period signal U PER 262 (i.e., the feedback period) may be equal to one half of the period the ac line voltage, which may be several times (e.g., 512 ) greater than the period of sampling signal U SMP 272 (i.e., the sampling period).
- feedback signal processor 280 may update first count signal U CN1 222 and second count signal U CN2 232 512 times during every feedback period. Additionally, feedback signal processor 280 may set first count signal U CN1 222 to a first initial value and second count signal U CN2 232 to a second initial value at the beginning of each feedback period.
- the first initial value and the second initial value may be the same and equal to zero. In some cases, the first initial value may be different from the second initial value.
- feedback signal processor 280 includes a first counter Counter 1 220 , a second counter Counter 2 230 , a logic circuit 210 , and comparators 202 , 204 , and 206 .
- First counter Counter 1 220 is coupled to receive sampling signal U SMP 272 at its CLK input, feedback period signal U PER 262 at its RESET input, an output 207 of comparator 206 at its UP/DN input.
- First counter Counter 1 220 is also coupled to output first count signal U CN1 222 . In operation, first counter Counter 1 220 updates first count signal U CN1 222 by counting up or down in response to output 207 during every sampling period.
- first counter Counter 1 220 counts up if output 207 is logic low and counts down if output 207 is logic high.
- Comparator 206 is coupled to receive feedback signal U FB 158 and set output 207 to logic high or logic low in response to a comparison of feedback signal U FB 158 with threshold U TH 205 .
- comparator 206 may set output 207 to logic high if feedback signal U FB 158 is greater than threshold U TH 205 , and set output 207 to logic low if feedback signal U FB 158 is less than threshold U TH 205 .
- First counter Counter 1 220 may increase first count signal U CN1 222 by counting up when feedback signal U FB 158 is less than threshold U TH 205 during a sampling period and similarly, may decrease first count signal U CN1 222 by counting down when feedback signal U FB 158 is greater than threshold U TH 205 during a sampling period. In this way, first counter Counter 1 220 may output as first count signal U CN1 222 a signal that may be representative of the difference between a portion of a feedback period that feedback signal U FB 158 is less than threshold U TH 205 and a portion of the feedback period that feedback signal U FB 158 is greater than threshold U TH 205 .
- second counter Counter 2 230 is coupled to receive sampling signal U SMP 272 at its CLK input, feedback period signal U PER 262 at its RESET input, output 207 of comparator 206 at its UP/DN input, an output 213 of logic circuit 210 at its EN input. Second counter Counter 2 230 is further coupled to output second count signal U CN2 232 . In operation, second counter Counter 2 230 updates second count signal U CN2 232 by counting up or down in response to output 207 during every sampling period if output 213 indicates that second counter 230 should be enabled, and maintains second count signal U CN2 232 at the same value if output 213 indicates that second counter Counter 2 230 should be disabled.
- logic circuit 210 may be a two-input XOR gate coupled to receive an output 211 of comparator 202 and an output 209 of comparator 204 as inputs.
- output 213 may be logic low indicating that second counter Counter 2 230 should be disabled when output 211 and 209 are both logic low or are both logic high.
- Output 213 may be logic high indicating that second counter Counter 2 230 should be enabled when only one of outputs 209 and 211 is logic high and the other one of outputs 209 and 211 is logic low.
- comparators 202 and 204 are coupled to receive feedback signal U FB 158 and set outputs 211 and 209 in response to the comparisons of feedback signal U FB 158 with upper limit U UP 201 and with lower limit U LO 203 , respectively.
- comparator 202 sets output 211 to logic high if feedback signal U FB 158 is less than upper limit U UP 201 and to logic low if feedback signal U FB 158 is greater than upper limit U UP 201 .
- comparator 204 sets output 209 to logic high if feedback signal U FB 158 is greater than lower limit U LO 203 and to logic low if feedback signal U FB 158 is less than lower limit U LO 203 .
- second counter Counter 2 230 is enabled to count up or down in response to output 207 when feedback signal U FB 158 is greater than upper limit U UP 201 or less than lower limit U LO 203 during a sampling period.
- second counter Counter 2 230 is disabled and keeps second count signal U CN2 232 constant.
- second counter Counter 2 230 when enabled, increases second count signal U CN2 232 by counting up if output 207 is logic low and decreases second count signal U CN2 232 by counting down if output 207 is logic high. That is, second counter Counter 2 230 counts up when feedback signal U FB 158 is less than lower limit U LO 203 during a sampling period. Second counter Counter 2 230 counts down when feedback signal U FB 158 is greater than upper limit U UP 201 during a sampling period.
- second counter Counter 2 230 may output as second count signal U CN2 232 a signal that may be representative of the difference between a portion of a feedback period that feedback signal U FB 158 is less than lower limit U LO 203 and a portion of the feedback period that feedback signal U FB 158 is greater than upper limit U UP 201 .
- both first counter Counter 1 220 and second counter Counter 2 230 are configured to have a maximum output count that is representative of a length of time corresponding to a feedback period. The magnitudes of first count signal U CN1 222 and second count signal U CN2 232 cannot exceed the maximum output count.
- state selector circuit 154 also includes a decision circuit 240 and a state counter 250 .
- Decision circuit 240 is coupled to receive first count signal U CN1 222 and second count signal U CN2 232 from feedback signal processor 280 and output a direction signal U DIR 244 and a mode signal U MD 242 .
- direction signal U DIR 244 may be a one-bit digital signal indicative of the direction of change in state signal U ST 160 and mode signal U MD 242 may be a two-bit digital signal indicative of an operation mode of state selector circuit 154 .
- decision circuit 240 may set direction signal U DIR 244 to zero or one in response to first count signal U CN1 222 , and mode signal U MD 242 to one of zero (i.e., 00 binary), one (i.e., 01 binary), and two (i.e., 10 binary) in response to both first count signal U CN1 222 and second count signal U CN2 232 .
- decision circuit 240 may set direction signal U DIR 244 to one indicating that state signal U ST 160 should be increased when first count signal U CN1 222 is positive and set direction signal U DIR 244 to zero indicating that state signal U ST 160 should be decreased when first count signal U CN1 222 is negative.
- decision circuit 240 may set mode signal U MD 242 to zero, which may correspond to a coarse mode as an operation mode if the magnitude of first count signal U CN1 222 is greater than a value X, the magnitude of second count signal U CN2 232 is greater than a value Y, and both first count signal U CN1 222 and second count signal U CN2 232 have the same sign (i.e., both signals are either positive or negative).
- Decision circuit 240 may set mode signal U MD 242 to one, which may correspond to a medium mode as an operation mode if the magnitude of first count signal U CN1 222 is greater than the value X, the magnitude of second count signal U CN2 232 is between the value Y and a value Z (less than the value Y), and both first count signal U CN1 222 and second count signal U CN2 232 have the same sign.
- Decision circuit 240 may set mode signal U MD 242 to two, which may correspond to a fine mode as an operation mode if the magnitude of first count signal U CN1 222 is less than the value X, or the magnitude of second count signal U CN2 232 is less than the value Z, or first count signal U CN1 222 and second count signal U CN2 232 have different signs.
- the value X represents a length of time that corresponds to 5% of a feedback period (i.e., the value X is equal to 5% of the maximum output count). In some cases, the value X may also correspond to 5% of the maximum value of the difference between an estimated average value of feedback signal U FB 158 and threshold U TH 205 .
- the value Y represents a length of time that corresponds to 20% of a feedback period (i.e., the value Y is equal to 20% of the maximum output count) and the value Z represents a length of time that corresponds to 10% of a feedback period (i.e., the value Z is equal to 10% of the maximum output count).
- state counter 250 is coupled to receive feedback period signal U PER 262 at its UPDATE input, direction signal U DIR 244 , mode signal U MD 242 , first count signal U CN1 222 , second count signal U CN2 232 .
- State counter is also coupled to output state signal U ST 160 .
- state counter 250 may update state signal U ST 160 in response to the values of direction signal U DIR 244 and mode signal U MD 242 at the time that a new pulse in feedback period signal U PER 262 is received, which is indicative of the end of a presently occurring feedback period (i.e., the beginning of a new feedback period).
- state selector circuit 154 when the value of mode signal U MD 242 at the end of a presently occurring feedback period is zero, state selector circuit 154 is set to operate in the coarse mode.
- state counter 250 may update (increase or decrease) the sixth bit of state signal U ST 160 (i.e., 0000100000 binary) in response to the value of direction signal U DIR 244 at the end of the presently occurring feedback period. That is, when state selector circuit 154 is operating in the coarse mode, state counter 250 may increase or decrease state signal U ST 160 by 32 for the next feedback period based on the value of direction signal U DIR 244 at the end of the presently occurring feedback period. In one example, state counter 250 increases state signal U ST 160 if direction signal U DIR 244 is one and decreases state signal U ST 160 if direction signal U DIR 244 is zero.
- state selector circuit 154 when the value of mode signal U MD 242 at the end of a presently occurring feedback period is one, state selector circuit 154 is set to operate in the medium mode.
- state counter 250 may update the fourth bit of state signal U ST 160 (i.e., 0000001000 binary) in response to the value of direction signal U DIR 244 at the end of the presently occurring feedback period. That is, when state selector circuit 154 is operating in the coarse mode, state counter 250 may increase or decrease state signal U ST 160 by eight for the next feedback period based on the value of direction signal U DIR 244 at the end of the presently occurring feedback period. In one example, state counter 250 increases state signal U ST 160 if direction signal U DIR 244 is one and decreases state signal U ST 160 if direction signal U DIR 244 is zero.
- state selector circuit 154 when the value of mode signal U MD 242 at the end of a presently occurring feedback period is two, state selector circuit 154 is set to operate in the fine mode. When state selector circuit 154 is in the fine mode, state counter 250 may update the first bit (least significant bit) of state signal U ST 160 (i.e., 0000000001 binary).
- state counter 250 when state selector circuit 154 is operating in the fine mode, state counter 250 is configured to update state signal U ST 160 only if direction signal U DIR 244 and mode signal U MD 242 maintain their values, and the final values of both first count signal U CN1 222 and second count signal U CN2 232 at the end of a feedback period are above a minimum threshold count (e.g., 3) for a certain number (e.g., 12) of consecutive feedback periods.
- a minimum threshold count e.g., 3
- state counter 250 increases state signal U ST 160 by one. If this set of conditions is met but direction signal U DIR 244 is zero, state counter 250 decreases state signal U ST 160 by one.
- state counter 250 keeps state signal U ST 160 unchanged.
- state counter 250 may include a counter that only operates when state selector circuit 154 is in the fine mode. The counter may be configured to start counting from one when state selector circuit 154 enters the fine mode and count up at the end of each feedback period if direction signal U DIR 244 maintains its value, and the final values of both first count signal U CN1 222 and second count signal U CN2 232 at the end of a feedback period are above the minimum threshold count.
- direction signal U DIR 244 changes its value and/or at least one of the final values of first count signal U CN1 222 and second count signal U CN2 232 drops below the minimum threshold count, then the counter is reset to one and state signal U ST 160 remains unchanged. If direction signal U DIR 244 maintains its value, and the final values of both first count signal U CN1 222 and second count signal U CN2 232 remain above the minimum threshold count for 12 consecutive feedback periods (i.e., if the counter output reaches 12), state counter 250 updates state signal U ST 160 based on the value of direction signal U DIR 244 and sets the counter output back to one.
- state selector circuit 154 can adjust the rate of change in the operating condition of power switch S 1 170 (hence, the rate of change in power delivery to load 122 ) in response to the feedback information in accordance with the teachings of the present invention.
- FIG. 2B shows a circuit diagram illustrating another example of the state selector circuit 154 of the controller 150 in FIG. 1A in accordance with the teachings of the present invention. It is noted that state selector circuit 154 in FIG. 2B shares similarities with state selector circuit 154 in FIG. 2A . It should be appreciated that similarly named and numbered elements referenced below are coupled and function as described above.
- One difference between state selector circuit 154 in FIG. 2B and state selector circuit 154 in FIG. 2A is that feedback period signal generator 260 in FIG. 2B includes a one-shot circuit 264 coupled to receive output 207 from comparator 206 , and is therefore coupled to generate feedback period signal U PER 262 in response to the comparison of feedback signal U FB 158 with threshold U TH 205 .
- One-shot circuit 264 is coupled to output a pulse in feedback period signal U PER 262 when output 207 transitions from logic high to logic low.
- feedback period signal generator 260 may output a pulse when feedback signal U FB 158 falls from a level above threshold U TH 205 to a level below threshold U TH 205 .
- each feedback period may correspond to a length of time between consecutive instances of feedback signal U FB 158 falling below threshold U TH 205 .
- feedback period signal generator 260 may be configured to output a pulse to terminate a feedback period if feedback signal U FB 158 does not fall below threshold U TH 205 within a certain length of time (e.g., a timeout period) from the start of the feedback period.
- feedback period signal generator 260 may output a pulse every timeout period to indicate that a presently occurring feedback period has ended and a new feedback period has begun. That is, each feedback period may be equal to the timeout period.
- FIG. 2C shows a circuit diagram illustrating yet another example of the state selector circuit 154 of the controller 150 in FIG. 1A in accordance with the teachings of the present invention. It is noted that selector circuit 154 in FIG. 2C shares similarities with state selector circuit 154 in FIG. 2A . It should be appreciated that similarly named and numbered elements referenced below are coupled and function as described above.
- One difference between state selector circuit 154 in FIG. 2C and state selector circuit 154 in FIG. 2A is that feedback period signal generator 260 in FIG. 2C includes a comparator 266 coupled to receive input sense signal U INS 142 and a one-shot circuit 264 coupled to comparator 266 to output feedback period signal U PER 262 in response to the output of comparator 266 .
- comparator 266 may compare input sense signal U INS 142 with a zero condition threshold U ZC , which may be representative of a zero crossing threshold for input voltage V IN 102 . In response, comparator 266 may output a logic high or logic low signal.
- One-shot circuit 264 may be coupled to output a pulse in feedback period signal U PER 262 when the signal at the output of comparator 266 transitions from logic high to logic low.
- comparator 266 outputs a logic high signal if input sense signal U INS 142 is greater than zero condition threshold U ZC and a logic low signal if input sense signal U INS 142 is less than or equal to zero condition threshold U ZC .
- each feedback period may correspond to a length of time between consecutive zero crossing events.
- FIG. 3A shows an example set of waveforms illustrating the operation of the controller 150 in FIG. 1A in accordance with the teachings of the present invention.
- waveform 302 is a rectified periodic signal with a period T P 310 and may be representative of input voltage V IN 102 .
- Waveform 313 is a periodic signal with period T P 310 and may be representative of input current I IN 113 . As shown in the example, waveform 313 is in phase with and proportional to waveform 302 .
- Waveform 358 is an example waveform representative of feedback signal U FB 158 . In one example, waveform 358 may be representative of output current I O 118 that is provided to load 122 of power supply 100 .
- waveform 358 is phase shifted with respect to waveform 313 . This could be due to output capacitor C 1 116 phase shifting output current I O 118 with respect to input current I IN 113 . It should be noted that despite being phase shifted, waveform 358 may still be periodic with a period T FB that is substantially equal to the period of waveform 302 (i.e., period T P 310 ).
- Waveform 362 may be representative of feedback period signal U PER 262 of FIGS. 2A-2C
- waveform 372 may be representative of sampling signal U SMP 272 of FIGS. 2A-2C
- waveform 362 includes pulses that are generated in response to waveform 358 falling from a level above a value 305 to a level below value 305 .
- Value 305 may correspond to threshold U TH 205 of FIGS. 2A-2C .
- the length of time between consecutive pulses in waveform 362 may correspond to a feedback period.
- time points t n , t n+1 , and t n+2 may be the start and end points of consecutive feedback periods, with time point t n indicating the start of the n th feedback period, time point t n+1 indicating the end of the n th feedback period and the start of the (n+1) th feedback period, and time point t n+2 indicating the end of the (n+1) th feedback period and the start of the (n+2) th feedback period.
- waveform 322 and 332 are representative of first count signal T CN1 222 and second count signal U CN2 232 of FIGS. 2A-2C , respectively, and may be updated every period of waveform 372 (i.e., every sampling period). Specifically, waveform 322 may be incremented if waveform 358 is less than value 305 , and may be decremented if waveform 358 is greater than or equal to waveform 305 .
- Waveform 332 may be incremented if waveform 358 is less than a value 303 , which is representative of lower limit U LO 203 , may be decremented if waveform 358 is greater than a value 301 , which is representative of upper limit U UP 201 , and may be kept unchanged if waveform 358 is between value 301 and value 303 .
- FIG. 3A also illustrates a waveform 360 , which may be representative of state signal U ST 160 .
- Final values of waveforms 322 and 332 at the end of a feedback period may be used to set the values of direction signal U DIR 244 and mode signal U MD 242 and in turn, update waveform 360 to adjust the operating condition of power switch S 1 170 for the next feedback period.
- waveform 360 may be updated by a different amount depending on the set of conditions that is met by the final values of waveforms 322 and 332 during a feedback period.
- waveforms 322 and 332 may be set to an initial value such as, for example, zero at the beginning of each feedback period (e.g., at time points t n , t n+1 , and t n+2 ). This ensures that the final values of waveforms 322 and 332 at the end of a feedback period reflect only the feedback information gathered during that feedback period.
- the final value of waveform 322 is positive and greater than the value X
- final value of waveform 332 is positive and greater than the value Y.
- direction signal U DIR 244 is set to one indicating that state signal U ST 160 should be increased
- mode signal U MD 242 is set to zero indicating that state selector circuit 154 should operate in the coarse mode.
- waveform 360 is increased by 32 from a value K to a value (K+32) for (n+1) th feedback period.
- waveform 360 is again increased by 32 from value (K+32) to (K+64) for the next feedback period starting at time point t n+2 .
- FIG. 3B shows another example set of waveforms illustrating the operation of controller 150 of FIG. 1A in accordance with the teachings of the present invention.
- One difference between waveform 358 in FIG. 3B and waveform 358 in FIG. 3A is that the final values of waveforms 322 and 332 in waveform 358 in FIG. 3B at the end of n th feedback period and (n+1) th feedback period satisfy a different set of conditions.
- the final value of waveform 322 is positive and greater than the value X
- the final value of waveform 332 is positive and between the value Y and the value Z.
- the value Z is less than the value Y.
- direction signal U DIR 244 is set to one indicating that state signal U ST 160 should be increased and mode signal U MD 242 is set to one indicating that state selector circuit 154 should operate in the medium mode.
- waveform 360 is increased by eight from value K to a value (K+8) for (n+1) th feedback period.
- the same set of conditions holds at the end of (n+1) th feedback period. Therefore, waveform 360 is again increased by eight from value (K+8) to a value (K+16) for the next feedback period starting at time point t n+2 .
- FIG. 3C shows yet another example set of waveforms illustrating the operation of controller 150 of FIG. 1A in accordance with the teachings of the present invention.
- waveform 358 of FIG. 3C and waveform 358 of FIG. 3A and FIG. 3B One difference between waveform 358 of FIG. 3C and waveform 358 of FIG. 3A and FIG. 3B is that the final values of waveforms 322 and 332 in FIG. 3C at the end of the feedback periods from the n th feedback period through (n+11) th feedback period (not shown) satisfy a different set of conditions. Specifically, at the end of the n th feedback period, the final value of waveform 322 is positive and less than the value X, and the final value of waveform 332 is positive and less than the value Z. Under these conditions, direction signal U DIR 244 is set to one indicating that state signal U ST 160 should be increased and mode signal U MD 242 is set to two indicating that state selector circuit 154 should operate in the fine mode.
- state selector circuit 154 when operating in the fine mode, updates state signal U ST 160 only if the values of direction signal U DIR 244 and mode signal U MD 242 remain the same, and both first count signal U CN1 222 and second count signal U CN2 232 are above the minimum threshold count for a certain number (e.g., 12) of consecutive feedback periods.
- the final values of waveforms 322 and 332 remain positive and below the value X and the value Z, respectively from n th feedback period through (n+11) th feedback period such that the values of direction signal U DIR 244 and mode signal U MD 242 remain at one and two, respectively for 12 consecutive feedback periods.
- first count signal U CN1 222 and second count signal U CN2 232 at the end of each feedback period remain above the minimum threshold count during this time.
- waveform 360 is increased by one from value K to a value (K+1) for (n+12) th feedback period starting at time point t n+12 .
- FIG. 4A shows a flow diagram illustrating an example process 400 for adjusting the operating condition of a switch of a power supply in accordance with the teachings of the present invention. It is noted that process 400 may be performed by a circuit similar or identical to example state selector circuit 154 in FIG. 2A , FIG. 2B and in FIG. 2C in accordance with the teachings of the present invention. In the depicted example, process 400 may begin at block 401 . At block 403 , a new feedback period may be started. In one example, the feedback period may be started in response to a pulse in an indicator signal (e.g., feedback period signal U PER 262 ).
- an indicator signal e.g., feedback period signal U PER 262
- feedback period signal generator 260 may output pulses at set intervals as the indicator signal and each pulse may indicate the start of a new feedback period.
- feedback period signal generator 260 may output a pulse in response to feedback signal U FB 158 falling below a threshold (e.g., threshold U TH 205 ).
- a first count signal e.g., first count signal U CN1 222
- a second count signal e.g., second count signal U CN2 232
- the first count signal may be representative of the difference between a portion of a feedback period that feedback signal U FB 158 is less than the threshold and a portion of the feedback period that feedback signal U FB 158 is greater than the threshold.
- the first count signal may be generated by a counter (e.g., first counter Counter 1 220 ).
- the second count signal may be representative of the difference between a portion of a feedback period that feedback signal U FB 158 is less than a lower limit (e.g., lower limit U LO 203 ) and a portion of the feedback period that feedback signal U FB 158 is greater than an upper limit (e.g., upper limit U UP 201 ).
- the second count signal may be generated by another counter (e.g., second counter Counter 2 230 ).
- the first and the second count signals may be set to the initial value when the counters are reset in response to a pulse in the indicator signal.
- a new feedback sample (i.e., a new sample of feedback signal U FB 158 ) may be obtained.
- each feedback sample may be representative of the value of feedback signal U FB 158 during a corresponding sampling period.
- Each sampling period may be equal to the period of a clock signal (e.g., sampling signal U SMP 272 ) generated by a clock generator (e.g., sampling clock generator).
- the period of the clock signal may be several times (e.g., 512) smaller than the feedback period.
- feedback signal U FB 158 may be sampled several times (e.g., 512) during a feedback period.
- the feedback sample may be compared with the threshold, the lower limit and the upper limit. Then, the first and the second count signals may be updated based on these comparisons. More particularly, the first count signal may be changed in response to the comparison of the feedback sample with the threshold and the second count signal may be changed in response to the comparisons of the feedback sample with both the upper limit and the lower limit.
- FIG. 4B shows a flow diagram illustrating one example of detailed steps that may occur in process block 409 in accordance with the teachings of the present invention. For instance, examples of these comparisons and the resulting changes in the first and the second signals discussed on process block 409 of FIG. 4A are shown in detail.
- the feedback sample is compared with the threshold. If the sample is greater than the threshold, process 409 proceeds to block 414 where the first count signal is decremented. In one example, first counter Counter 1 220 may decrement first count signal U CN1 222 by counting down. If the sample is not greater than the threshold, process 409 proceeds block 416 where the first count signal is incremented. In one example, first counter Counter 1 220 increments first count signal U CN1 222 by counting up.
- the feedback sample is compared with the upper limit. If the sample is greater than the upper limit, process 409 proceeds to block 422 where the second count signal is decremented. In one example, second counter Counter 2 230 decrements second count signal U CN2 232 by counting down. If the sample is not greater than the upper limit, process 409 proceeds to block 420 where the sample is compared with the lower limit. If the sample is less than the lower limit, process 409 proceeds to block 424 where the second count signal is incremented. In one example, second counter Counter 2 230 increments second count signal U CN2 232 by counting up. If the sample is not less than the lower limit, process 409 proceeds to block 426 where the second count signal is kept unchanged.
- the feedback period may end in response to a new pulse in the indicator signal. If the feedback period has not ended, process 400 returns to block 407 . Otherwise, if the feedback period has ended, process 400 proceeds to block 413 .
- values of a direction signal e.g., direction signal U DIR 244
- a mode signal e.g., mode signal U MD 242
- state selector circuit 154 may include a decision circuit (e.g., decision circuit 240 ) coupled to receive the first and the second count signals and set the values of direction signal and the mode signal in response to the final values of the first and the second count signals.
- FIG. 4C shows a flow diagram illustrating one example of detailed steps that may occur in process block 413 in accordance with the teachings of the present invention. For instance, various different conditions on the first and the second count signals, and the corresponding values of the direction signal and the mode signal are shown in detail. Referring now to FIG. 4C , at block 440 , it may be determined whether or not the magnitude of the first count signal is greater than the value X, whether or not the magnitude of the second count signal is greater than the value Y, and whether or not both signals have the same sign. If these conditions are met, process 413 proceeds to block 442 . If not, process 413 proceeds to block 444 .
- the direction signal is set in response to the sign of the first signal and the mode signal is set to a value that indicates the coarse mode as the operation mode of state selector circuit 154 .
- decision circuit 240 may set mode signal U MD 242 to zero and direction signal U DIR 244 to zero if the first signal is positive, and to one if the first signal is negative.
- process 413 proceeds to block 446 where the direction signal is set in response to the sign of the first signal and the mode signal is set to a value that indicates the medium mode as the operation mode of state selector circuit 154 . If the conditions at block 444 are not met, process 413 proceeds to block 448 where the direction signal is set in response to the sign of the first signal and the mode signal is set to a value that indicates the fine mode as the operation mode of state selector circuit 154 .
- the operating condition of a power switch may be adjusted in response to the direction signal, to the mode signal, and to at least one of the final values of the first count signal and the second count signal at the end of a feedback period.
- state selector circuit 154 may change state signal U ST 160 based on the values of direction signal U DIR 244 and mode signal U MD 242 . This may change a drive signal (e.g., drive signal U DR 162 ) coupled to drive switching of the power switch, thereby causing an operating condition of power switch S 1 170 such as switching frequency and/or on-time to change.
- state selector circuit 154 may change state signal U ST 160 by an amount that varies based on the operation mode of state selector circuit 154 . Therefore, state selector circuit 154 may vary the rate of change in the operating condition of power switch S 1 170 over multiple feedback periods. In addition, state selector circuit 154 may keep state signal U ST 160 unchanged based on direction signal U DIR 244 and at least one of the final value of the first count signal and the final value of the second count signal.
- state selector circuit 154 when state selector circuit 154 is operating in the fine mode, if direction signal U DIR 244 changes and/or at least one of the final value of the first count signal and the final value of the second count signal drops below the minimum threshold count during a certain number of consecutive feedback periods, state selector circuit 154 may keep state signal U ST 160 unchanged. In some cases, when state signal U ST 160 increases, switching frequency of power switch S 1 170 may increase resulting in more power to be delivered to load 122 and conversely, when state signal U ST 160 decreases, switching frequency of power switch S 1 170 may decrease resulting in less power to be delivered to load 122 .
- FIG. 5 is a schematic circuit diagram illustrating an example driver circuit including one example of a modulated DAC according to the teachings of the present invention.
- driver circuit 156 can be coupled to receive a digital input signal U IN 590 comprising (Q+P) bits, where Q and P are non-zero integers.
- Driver circuit 156 can be coupled to output drive signal U DR 162 in response to digital input signal U IN 590 to control the switching of power switch S 1 170 .
- digital input signal U IN 590 may correspond to state signal U ST 160 of the controller in FIG. 1A .
- upper Q bits of digital input signal U IN 590 i.e., bits B 1 through B Q
- baseline bits bit B Q being the most significant bit
- bit B 1 being the least significant bit
- lower P bits of digital input signal U IN 590 i.e., bits M 1 through M P
- modulation bits bit M P being the most significant bit and bit M 1 being the least significant bit.
- a modulated DAC 540 coupled to receive digital input signal U IN 590 and a clock signal U CLK 512 .
- clock signal U CLK 512 is generated by a clock signal generator 510 that is included in driver circuit 156 .
- clock signal U CLK 512 is a periodic signal with a fixed period.
- modulated DAC 540 outputs an adjust signal U ADJ 580 to a drive signal generator 520 .
- Modulated DAC 540 can include a modulator 530 coupled to receive clock signal U CLK 512 and the modulation bits. In response, modulator 530 generates a modulation period signal UMP 538 .
- modulation period signal UMP 538 is a periodic signal that alternates between logic high and logic low.
- the period of modulation period signal U MDP 538 may be proportional to the number of possible values (i.e., 2 P ) that can be represented by the modulation bits.
- modulator 530 includes a counter 532 and a comparator 535 .
- Counter 532 has an UPDATE input coupled to receive clock signal U CLK 512 .
- Comparator 535 is coupled to receive an output 534 of counter 532 and the modulation signal and in turn, output modulation period signal U MDP 538 .
- counter 532 is configured to continually count up every period of clock signal U CLK 512 .
- counter 532 increments output 534 by counting up every period of clock signal U CLK 512 until output 534 reaches the maximum value of the modulation bits (i.e., 2 P ⁇ 1).
- counter 532 In response to reaching the maximum value of the modulation bits, counter 532 sets output 534 back to zero and again counts up every period of clock signal U CLK 512 .
- the period of modulation period signal U MDP 538 may be equal to 2 P periods of clock signal U CLK 512 .
- comparator 535 can set modulation period signal U MDP 538 to logic high or logic low in response to comparing output 534 with the value of the modulation bits. In one example, comparator 535 can set modulation period signal U MDP 538 to logic high if output 534 is less than the value of the modulation bits and may set modulation period signal U MDP 538 to logic low if output 534 is greater than or equal to the value of the modulation bits.
- modulator 530 can adjust a portion of the period of modulation period signal U MDP 538 that modulation period signal U MDP 538 is logic high and a portion of the period that modulation period signal U MDP 538 is logic low in response to the value of the modulation bits. That is, modulator 530 can adjust the duty cycle of the modulation period signal U MDP 538 (i.e., the ratio of a portion of the period of modulation period signal U MDP 538 during which modulation period signal U MDP 538 is either logic high or logic low to the period of modulation period signal U MDP 538 ) in response to the value of the modulation bits.
- the duty cycle of modulation period signal U MDP 538 times the period of modulation period signal U MDP 538 may be referred to as a modulation time.
- the modulation time represents the portion of the period of modulation period signal U MDP 538 during which modulation period signal U MDP 538 is logic high.
- the value of the modulation bits determines the duty cycle of modulation period signal U MDP 538 .
- the period of modulation period signal U MDP 538 is eight (2 3 ) periods of clock signal U CLK 512 and the duty cycle of the modulation period signal U MDP 538 is 3 ⁇ 8.
- modulation period signal U MDP 538 may be set to logic high for three periods of clock signal U CLK 512 and to logic low for five periods of clock signal U CLK 512 during every period of modulation period signal U MDP 538 .
- modulated DAC 540 may include a DAC 577 comprising a group of switchable bit-to-analog circuitries 576 and a switchable modulation source 575 .
- the number of switchable bit-to-analog circuitries included in DAC 577 may be equal to the number of baseline bits (i.e., Q).
- Group of switchable bit-to-analog circuitries 576 and switchable modulation source 575 may be coupled between a voltage source VA and a summing block 586 .
- group of switchable bit-to-analog circuitries 576 is coupled to receive the baseline bits and provide to summing block 586 a base signal U BASE 584 , which is responsive to the baseline bits.
- each one of switchable bit-to-analog circuitries 564 to 570 includes a current source and a switch. Each one of switchable bit-to-analog circuitries 564 to 570 of the group can be switched in response to one of the baseline bits. Therefore, base signal U BASE 584 may be representative of the total sum of currents that is provided to summing block 586 from the group. It should be noted that, in other examples, each one of switchable bit-to-analog circuitries 564 to 570 may include other known circuit components such as a resistor, a capacitor in place of a current source. In one example, summing block 586 is a circuit node that is coupled to receive multiple currents and output a signal representative of the sum of these currents.
- DAC 577 is a binary weighted DAC. That is, each one of current sources 544 to 550 of the group of switchable bit-to-analog circuitries outputs a current that has a magnitude that is weighted by power of two relative to the current output by the current source of the switchable bit-to-analog circuitry that is responsive to the adjacent less-significant bit of the baseline bits.
- switchable bit-to-analog circuitry 564 is responsive to the least significant bit B 1 and current source 544 outputs a current with the lowest magnitude I B .
- Switchable bit-to-analog circuitry 566 is responsive to bit B 2 and current source 546 outputs a current that is twice as large as I B .
- the magnitude of the current output by each one of the current sources of the remaining switchable bit-to-analog circuitries successively doubles such that current source 550 of switchable bit-to-analog circuitry 570 responsive to the most significant bit B Q outputs a current that has magnitude 2 Q I B .
- switches 554 to 560 coupled to current sources 544 to 550 can be switched in response to one of the baseline bits.
- each one of switches 554 to 560 can be switched in response to the bit of the baseline bits to which the corresponding switchable bit-to-analog circuitry is responsive.
- switchable bit-to-analog circuitry 564 includes switch 554 that is coupled to current source 544 . Since switchable bit-to-analog circuitry 564 is responsive to the least significant bit B 1 of the baseline bits, switch 554 can be switched in response to the least significant bit B 1 .
- a high value for one of the digits of the baseline bits may close (i.e., enable) the respective switch to couple the corresponding current source to summing block 586 .
- a low value for one of the digits of the baseline bits may open (i.e., disable) the respective switch to prevent current from its respective current source from entering summing block 586 . Therefore, base signal U BASE 584 that enters summing block 586 is an analog signal representative of the value of the baseline bits.
- a low value for one of the baseline bits is a high value for the complement of that one of the baseline bits.
- a bar over the symbol for a bit of the baseline bits represents the complement of the bit.
- modulated DAC 540 may have multiple switches within each one of switchable bit-to-analog circuitries to direct current from current sources 544 to 550 to other nodes for other reasons, such as for calibration.
- switchable modulation source 575 is coupled to output a modulated signal U MOD 582 in response to modulation period signal U MDP 538 .
- Switchable modulation source 575 includes a current source 542 that outputs a current that has magnitude equal to that of the current source of the switchable bit-to-analog circuitry responsive to the least significant bit B 1 of the baseline bits. In other words, current source 542 outputs a current that has a magnitude of I B .
- Switchable modulation source 575 also includes a switch 552 coupled to current source 542 . Switch 552 can be switched in response to modulation period signal UMP 538 .
- switch 552 closes (i.e., is enabled) to couple current source 542 to summing block 586 and when modulation period signal UMP 538 is logic low, switch 552 opens (i.e., is disabled) to prevent current from current source 542 from entering summing block 586 . That is, in operation, switchable modulation source 575 may alternate modulated signal U MOD 582 between I B and zero in response to modulation period signal U MDP 538 . In such cases, modulated signal U MOD 582 is also a periodic signal with the same period as that of modulation period signal U MDP 538 (i.e., 2 P periods of clock signal U CLK 512 ).
- adjust signal U ADJ 580 output by modulated DAC 540 is the sum of currents that are received by summing block 586 , namely the sum of modulated signal U MOD 582 and base signal U BASE 584 .
- this means that adjust signal U ADJ 580 is a periodic signal with the same period as that of modulation period signal U MDP 538 and modulated signal U MOD 582 (i.e., 2 P periods of clock signal U CLK 512 ).
- switchable modulation source 575 can cause adjust signal U ADJ 580 to alternate between base signal U BASE 584 and base signal U BASE 584 plus I B during a period of adjust signal U ADJ 580 . Because the current source of the switchable bit-to-analog circuitry that is responsive to the least significant bit of the baseline bits outputs a current that has a magnitude of I B , the difference in base signal U BASE 584 for two adjacent values of the baseline bits is equal to I B .
- base signal U BASE 584 and base signal U BASE 584 plus I B may represent two adjacent discrete levels of adjust signal U ADJ 580 with base signal U BASE 564 corresponding to the lower level, which may also be referred to as the “base level.”
- adjust signal U ADJ 580 is an analog signal having discrete levels that are set in response to the value of the baseline bits and the value of the modulation bits.
- modulated DAC 540 may alternate adjust signal U ADJ 580 between two adjacent discrete levels in response to modulation period signal U MDP 538 .
- modulated DAC 540 may set a portion of the period of adjust signal U ADJ 580 that adjust signal U ADJ 580 is the greater of the adjacent levels in response to modulation period signal U MDP 538 .
- modulated DAC 540 may set adjust signal U ADJ 580 to the greater level when modulation period signal U MDP 538 is logic high and set adjust signal U ADJ 580 to the base level when modulation period signal U MDP 538 is logic low.
- Modulated DAC 540 may thus set the portion of the period of adjust signal U ADJ 580 during which adjust signal U ADJ 580 is the greater level to be equal to the modulation time.
- the average value of adjust signal U ADJ 580 may over time become equal to one of several additional levels that are equally spaced between the adjacent levels of adjust signal U ADJ 580 . More particularly, by changing the modulation time between zero and (2 P ⁇ 1) periods of clock signal U CLK 512 in response to the value of the modulation bits, modulated DAC 540 may output an adjust signal U ADJ 580 with an average value equal to one of (2 P ⁇ 1) equally spaced levels between any pair of adjacent levels. In this manner, modulated DAC 540 may generate a signal at its output with the equivalent number of discrete levels and hence with the same resolution that a conventional (P+Q) bit DAC can generate.
- Modulated DAC 540 can thus reduce the area required for implementing a DAC since modulated DAC 540 may need only Q circuit components (e.g., current sources) to achieve the same resolution as that of a (P+Q) bit DAC.
- Q circuit components e.g., current sources
- an averaging circuit such as a low pass filter, an integrator or the like can be used either in the modulated DAC or outside of the modulated DAC to generate the average value of adjust signal U ADJ 580 .
- modulator 530 operates in conjunction with a binary weighted DAC to alternate the output between adjacent levels.
- modulator 530 can operate in conjunction with other types of DACs (e.g., thermometer coded DAC, R ⁇ 2R ladder DAC) that are appropriately modified.
- modulated DAC 540 may include a DAC that generates two levels for the output in response to the baseline bits. One of the levels may correspond to the value of the baseline bits and the other one of the levels may correspond to one of the adjacent values of the baseline bits. In this example, the DAC may alternate the output between the two levels in response to modulation period signal U MDP 538 .
- one or more signals that alternate between adjacent digital levels can be received by a DAC.
- a multiplexer can output a digital signal that is set to a first level for a first period of time and to an adjacent second level for a second period of time within a period.
- the DAC can receive the digital signal at the output of the multiplexer and convert the alternating digital signal to an analog output as adjust signal U ADJ 580 .
- the first level may be determined, for example, based on the value of the baseline bits or the value of the digital input signal received by a modulated DAC.
- the first period of time and the second period of time can be determined, for example, based on the value of the modulation bits or in response to a separate signal that sets the duty cycle of modulation period signal U MDP 538 .
- the multiplexer would be acting as a modulator and its output would alternate between a higher digital level and a lower digital level.
- the digital signal may be output as adjust signal U ADJ 580 .
- drive signal generator 520 is coupled to receive adjust signal U ADJ 580 and in response, output drive signal U DR 162 .
- Drive signal U DR 162 may be a periodic signal that alternates between logic high and logic low.
- drive signal generator 520 can set certain properties of drive signal U DR 162 based on adjust signal U ADJ 580 . Examples of such properties of drive signal U DR 162 include period, ratio of logic high to logic low in a period, etc.
- drive signal generator 520 can set the operating condition of power switch S 1 170 .
- drive signal generator 520 may include switches, capacitors, and comparators (not shown in FIG. 5 ).
- Drive signal generator 520 can use the charging and discharging of those capacitors in response to adjust signal U ADJ 580 to set one or more properties of drive signal U DR 162 .
- drive signal generator 520 can include a circuit (e.g., a digital pulse width modulation circuit) to output a rectangular signal as drive signal U DR 162 .
- the circuit can be coupled to receive an alternating digital signal (e.g., the digital signal at the output of the multiplexer) and configured to set one or more properties of drive signal U DR 162 in response to the alternating digital signal.
- FIG. 6 shows a table illustrating different values of an example digital signal received as an input signal by driver circuit 156 and a timing diagram illustrating waveforms of various signals of modulated DAC 540 .
- the table includes nine rows from row A to row I where each row shows a different value of the input signal that, in one example, may be representative of input signal U IN 590 .
- the input signal includes a total of 13 bits with upper ten bits set aside as the baseline bits (i.e., Q equals ten) and lower three bits set aside as the modulation bits (i.e., P equals three).
- the portion of the input signal corresponding to the baseline bits is separated from the portion corresponding to the modulation bits by a solid line.
- waveform 612 is periodic waveform 612 with a period T CLK 614 and that alternates between logic high H and logic low L.
- waveform 612 is representative of clock signal U CLK 512 generated by clock signal generator 510 .
- FIG. 6 also includes a collection of example waveforms 620 for adjust signal U ADJ 580 . Each waveform of the collection corresponds to the input signal in the respective adjacent row of the table.
- the value of the modulation bits can be one of eight different values between zero and seven.
- Waveforms in collection 620 are periodic with a period T ADJ 616 which is equal to eight periods of waveform 612 (i.e., eight times period Tux 614 ).
- the base level of adjust signal U ADJ 580 is set in response to the value of baseline bits and the duty cycle of modulation period signal U MDP 538 is set in response to the value of the modulation bits.
- the input signal in row A indicates 513 for the value of the baseline bits and zero for the value of the modulation bits.
- modulated DAC 540 sets the base level of adjust signal U ADJ 580 to 513 I B and the duty cycle of modulation period signal U MDP 538 to zero. In other words, modulated DAC 540 sets modulation period signal U MDP 538 to logic low for the entire period of modulation period signal U MDP 538 . Accordingly, the corresponding waveform of group 620 is constant and equal to the base level of 513 I B . For rows B through I, the value of the baseline bits indicated by the respective input signal is the same and equal to 512 but the value of the modulation bits decreases from seven in row B to zero in row I.
- the base level of adjust signal U ADJ 580 is equal to 512 I B
- the greater of the adjacent levels of adjust signal U ADJ 580 is equal to 513 I B ( 512 I B +I B )
- the modulation time is equal to the value of the modulation bits times period Tux 614 .
- modulation period signal U MDP 538 is logic high for a length of time that is equal to the value of the modulation bits times period Tux 614 .
- each corresponding waveform of group 620 is set to the 513 I B for the corresponding modulation time during each period T ADJ 616 .
- the value of the modulation bits is seven
- the corresponding modulation time is seven times period T CLK 614 and the corresponding waveform of group 620 is set to 513 I B for seven times period T CLK 614 during each period T ADJ 616 .
- the value of the modulation bits is four
- the corresponding modulation time is four times period T CLK 614 and the corresponding waveform is set to 513 I B for four times period T CLK 614 during each period T ADJ 616 .
- FIG. 7 shows a collection of signal levels illustrating example average values for the output of the modulated DAC of FIG. 5 .
- each one of levels of collection 720 in FIG. 7 represents the average value of the corresponding waveform of collection 620 that is responsive to the input signal in the respective adjacent row of the table in FIG. 6 .
- FIG. 7 is an expanded view illustrating both the adjacent levels of 512 I B and 513 I B of adjust signal U ADJ 580 and the additional seven (2 3 ⁇ 1) equally spaced levels between these adjacent levels.
- the levels of collection 720 that correspond to the input signals in row A and I of the table in FIG. 6 are equal to 513 I B and 512 I B , respectively.
- the corresponding level of collection 720 decreases by steps of (1 ⁇ 8)I B .
- the average value of the waveform of collection 620 corresponding to row B is ( 512 I B +(7 ⁇ 8)I B )
- the average value of the waveform of collection 620 corresponding to row C is ( 512 I B +( 6/8)I B ) and so on.
- an adjust signal U ADJ 580 generated by using ten current sources in this manner may have the equivalent number of discrete levels and the same resolution as that of a signal generated by a 13 bit DAC that uses, for example, 13 current sources.
- FIG. 8 is a schematic circuit diagram illustrating another implementation of the driver circuit in FIG. 1A according to the teachings of the present invention.
- Driver circuit 156 in FIG. 8 differs from driver circuit 156 in FIG. 5 in that counter 832 is coupled to receive drive signal U DR 162 at its UPDATE input. Consequently, the periods of modulation period signal U MDP 838 , modulated signal U MOD 882 and adjust signal U ADJ 880 are all equal to 2 P times the period of drive signal U DR 162 .
- the periods of modulation period signal U MDP 838 , modulated signal U MOD 882 and adjust signal U ADJ 880 may also vary during the operation of controller 150 .
- FIG. 9 is a flow diagram illustrating an example process 900 according to the teachings of the present invention for generating an analog signal having discrete levels in response to a digital signal.
- process 900 may begin at block 905 .
- an N bit digital signal is received as an input.
- the base level of an output signal is set in response to upper Q bits of the input. More particularly, the base level may be proportional to the value of a digital signal represented by upper Q bits of the input. For example, Q may be chosen as ten and the digital signal represented by upper Q bits of the input may be equal to 512. In this case, the base level of the output signal may be equal to 512 times a current that has a magnitude of I B .
- a periodic signal is generated in response to lower P bits of the input.
- the periodic signal has a period proportional to the number of possible values that can be represented by lower P bits of the input (i.e., 2 P ).
- the period of the periodic signal may be eight (2 3 ) periods of a clock signal.
- the periodic signal may alternate between logic low and logic high during that period.
- the duty cycle of the periodic signal i.e., the ratio of either a logic high or logic low portion of the period of the periodic signal to the period of the periodic signal
- the duty cycle of the periodic signal times the period of the periodic signal may represent a modulation time.
- the portion of the period during which the periodic signal is set to logic high may be equal to the modulation time and hence, proportional to the value of lower P bits of the input.
- the value of lower P bits of the input may be equal to five.
- the duty cycle of the periodic signal may be 5 ⁇ 8
- the modulation time may be five periods of the clock signal
- the periodic signal may be logic high for five of eight periods of the clock signal.
- the output signal may be set to an adjacent level of the base level for the modulation time and to the base level for the remainder of the period of the periodic signal.
- the adjacent level corresponds to the greater of the two closest levels of the base level that can be generated in response to upper Q bits of the input.
- the base level of the output signal may increase or decrease in steps of value I B in response to upper Q bits of the input. In this case, when the base level is equal to 512 I B , the adjacent level becomes equal to 513 I B . Consequently, the output signal may be set to 513 I B for the modulation time and to 512 I B for the remainder of the period of the periodic signal.
- the average value of the output signal generated by process 900 may be equal to one of (2 P ⁇ 1) additional levels that are equally spaced between any pair of adjacent levels of the output signal.
- the output signal generated by using Q current sources according to process 900 can achieve the same resolution as that of a signal generated by a (Q+P) bit DAC that uses (Q+P) current sources.
- the illustrated process may be performed by a modulated DAC 540 or 840 .
- Modulated DAC 540 or 840 may perform process block 910 by receiving input signal U IN 590 or 890 as an N bit digital signal.
- the base level of an output signal e.g., adjust signal U ADJ 580 or 880
- group of switchable bit-to-analog circuitries 576 or 876 can set the base level of the output signal by outputting base signal U BASE 584 or 884 to summing block 566 or 866 .
- Generating a periodic signal in response to P lower bits of the digital signal in process block 930 can be performed by modulator 530 or 830 .
- Setting the duty cycle of the periodic signal (hence, the modulation time) in response to the value of lower P bits of the digital signal in process block 940 can also be performed by modulator 530 or 830 .
- Setting the output signal to an adjacent level of the base level for the modulation time and to the base level for the remainder of the period of the periodic signal in process block 950 can be performed by switchable modulation source 575 or 875 and group of switchable bit-to-analog circuitries 576 or 876 .
- switchable modulation source 575 or 875 can be configured to couple a current source (e.g., current source 542 or 842 ) to summing block 566 or 866 to provide an additional signal (e.g., modulated signal U MOD 582 or 882 ) in response to modulation period signal UMP 538 or 838 such that the output signal is set to the adjacent level of the base level for the modulation time.
- switchable modulation source 575 or 875 can be configured to prevent the current source from coupling to summing block 566 or 866 in response to modulation period signal U MDP 538 or 838 such that the output signal is set to the base level for the remainder of the period of the periodic signal.
Abstract
Description
- This application is related to U.S. patent application Ser. No. ______ of Pastore et al., filed May 13, 2014, entitled “MULTI-PACE CONTROLLER,” and assigned to the Assignee of the present application.
- 1. Field of the Disclosure
- The present invention relates generally to power supplies, and more specifically, the invention relates to switch mode power supplies.
- 2. Background
- Many electronic devices, such as cell phones, laptops, etc., are powered by a source of direct current (dc) power. Conventional wall outlets generally deliver a high voltage alternating current (ac) power that needs to be transformed to dc power in order to be used as a power source by most consumer electronic devices. Switch mode power converters, also referred to as switch mode power supplies, are commonly used due to their high efficiency, small size, and low weight to convert the high voltage ac power to a regulated dc power. In one example, switch mode power converters are used to provide regulated power to light emitting diode (LED) devices.
- One important consideration for a switch mode power converter is the shape and the phase of the input current drawn from the power source relative to the ac input voltage. The shape of the ac input voltage is typically sinusoidal but because a switching power converter presents itself as a non-linear load, the shape of the input current drawn from the power source may become distorted (non-sinusoidal) and/or out of phase with ac input voltage. This results in increased power loss in the power distribution systems.
- Correction of the input current waveform to reduce shape and/or phase mismatch with respect to input voltage is referred to as power factor correction (PFC). The power factor may be defined as the ratio of the average power over a cycle to the product of the root mean square (rms) voltage and the rms current. That is, the power factor may represent the ratio of the amount of usable power to the amount of total power delivered to the load. As such, the power factor may have a value between zero and one, with unity power factor being the optimal. If the input current is sinusoidal and perfectly in-phase with the input voltage, the power factor of the power supply is one, and none of the energy delivered to the load is returned to the power source. However, as the switch mode power supply distorts the wave shape of the input current and/or introduces a phase shift with respect to the input voltage, the power factor decreases. Several regulatory agencies have set tight standards that typically stipulate for greater power factors and/or lower harmonic content of the input current.
- One example application where switch mode power supplies may be required to perform PFC is power conversion systems that are used in light emitting diode (LED) lighting. Since the brightness of light provided by LED lamps is a function of the current through LEDs, the power supply used in such a system may also regulate the current provided to LEDs at the output of the power supply. In other words, the power supply may provide both output current regulation and PFC.
- Output current regulation is typically achieved by a power supply controller by sensing the current provided to the LEDs. A feedback signal is used to represent a current through the LEDs. The power supply controller controls the transfer of energy from an input to an output of the power supply in response to the feedback signal. Switch mode power supplies typically respond very quickly to fluctuations in the feedback signal by adjusting the energy transfer to regulate the LED current at a desired level. However, making rapid changes to the energy transfer can compromise the PFC performance and cause the input current to be non-sinusoidal and/or out of phase with the input voltage, resulting in a reduced power factor.
- A switch mode power supply may use a controller to control the switching (i.e., the turning on and turning off) of a power switch to provide a desired output to a load. The controller may regulate the output at a desired level in response to a feedback signal representative of the output of the power supply. Some controllers may use a digital control signal to adjust the operating condition (e.g., on-time, switching frequency) of the power switch in response to the feedback signal. Such a controller may employ a digital-to-analog converter (DAC) to convert the binary values of the control signal to corresponding discrete levels of an analog signal that may be used to set the operating condition of the power switch. For some types of DACs, such as binary-weighted DACs, as the number of the bits of the control signal is increased, the number of different operating conditions to which the power switch can be set is increased. As a result, the area on the silicon occupied by the DAC components such as current sources, resistors, etc., may grow and make such an implementation impractical.
- Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
-
FIG. 1A shows a schematic diagram illustrating an example switch mode power converter including a controller with a state selector circuit and a driver circuit in accordance with the teachings of the present invention. -
FIG. 1B shows examples of relationships of switching frequency with respect to a state signal of an example switch mode power converter including a controller in accordance with the teachings of the present invention. -
FIG. 2A shows a circuit diagram illustrating one example of the state selector circuit of the controller inFIG. 1A in accordance with the teachings of the present invention. -
FIG. 2B shows a circuit diagram illustrating another example of the state selector circuit of the controller inFIG. 1A in accordance with the teachings of the present invention. -
FIG. 2C shows a circuit diagram illustrating yet another example of the state selector circuit of the controller inFIG. 1A in accordance with the teachings of the present invention. -
FIG. 3A shows an example set of waveforms illustrating the operation of the controller inFIG. 1A in accordance with the teachings of the present invention. -
FIG. 3B shows another example set of waveforms illustrating the operation of the controller inFIG. 1A in accordance with the teachings of the present invention. -
FIG. 3C shows yet another example set of waveforms illustrating the operation of the controller inFIG. 1A in accordance with the teachings of the present invention. -
FIG. 4A shows a flow diagram illustrating an example process for adjusting the operating condition of a switch of a power supply in accordance with the teachings of the present invention. -
FIG. 4B shows a flow diagram illustrating one example of detailed steps of one the process blocks of the process shown inFIG. 4A in accordance with the teachings of the present invention. -
FIG. 4C shows a flow diagram illustrating one example of detailed steps of another one of the process blocks of the process shown inFIG. 4A in accordance with the teachings of the present invention. -
FIG. 5 shows a circuit diagram illustrating an example driver circuit including one example of a modulated DAC in accordance with the teachings of the present invention. -
FIG. 6 shows a table illustrating different values of an example digital signal received as an input by the driver circuit inFIG. 5 and a timing diagram illustrating waveforms for various signals that are associated with the example modulated DAC in accordance with the teachings of the present invention. -
FIG. 7 shows a collection of signal levels illustrating example average values for the output of the modulated DAC ofFIG. 5 in accordance with the teachings of the present invention. -
FIG. 8 shows a circuit diagram illustrating another example of a driver circuit in accordance with the teachings of the present invention. -
FIG. 9 shows a flow diagram illustrating an example process for generating an analog signal having discrete levels in response to a digital signal in one example of a power supply controller in accordance with the teachings of the present invention. - Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.
- In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.
- Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
- As will be discussed, an example power converter in accordance with the teachings of the present invention includes a controller with a state selector circuit that generates multiple count signals in response to comparisons of a feedback signal of the power converter with different threshold signals. In one example, the state selector circuit generates two count signals, first count signal and second count signal, and outputs a state signal in response to these count signals. In the example, the state selector circuit may be coupled to change the state signal at a different rate depending on the values of first and second count signals. In addition, the controller of the example power converter includes a driver circuit that is coupled to generate a drive signal in response to the state signal to drive the switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter in accordance with the teachings of the present invention.
- To illustrate,
FIG. 1A shows an example switchmode power converter 100, also referred to as a switch mode power supply, with acontroller 150 that includes astate selector circuit 154 and adriver circuit 156 in accordance with the teachings of the present invention. In the illustrated example,power supply 100 receives an inputcurrent T IN 113 and aninput voltage V IN 102 to output a dcoutput voltage V O 120 and a dc output current IO 118 to aload 122.Input voltage V IN 102 may be representative of an ac line voltage.Load 122 may include one or more LEDs. In one example,input voltage V IN 102 is a rectified and filtered ac voltage. As shown,input voltage V IN 102 is referenced to aground terminal 104, which may also be referred to as an input return terminal.Output voltage V O 120 is referenced to aground terminal 105, which may also be referred to as an output return terminal. In the example,input return terminal 104 represents the lowest potential or the lowest voltage against that all voltages on the input side ofpower supply 100 are measured or defined, andoutput return terminal 105 represents the lowest potential or the lowest voltage against that all voltages on the output side ofpower supply 100 are measured or defined. In some cases,input return terminal 104 andoutput return terminal 105 may correspond to the same voltage or potential. In some other cases,input return terminal 104 andoutput return terminal 105 may correspond to the different voltages or potentials. - As shown in the depicted example,
power supply 100 may further include an energytransfer element T1 124, apower switch S1 170, adiode D1 114 and acapacitor C1 116. In the illustrated example, energytransfer element T1 124 is a coupled inductor, which is sometimes referred to as a transformer, with a primary winding 110 and a secondary winding 112. In one example, primary winding 110 has one end coupled to theinput voltage V IN 102 and the opposite end coupled topower switch S1 170. Secondary winding 112 has one end coupled to return terminal 104 and the opposite end coupled todiode D1 114.Diode D1 114 is further coupled tocapacitor C1 116, which is coupled between the output ofpower supply 100 and return terminal 104. While the polarities of primary winding 110 and secondary winding 112, which are indicated by the dots at one end of each winding (dotted ends have the same polarity), show thatpower supply 100 is configured as a flyback power supply, it should be appreciated that other power supply topologies may also be used in accordance with the teachings of the present invention. In the depicted example,power switch S1 170 represents the operation of a controlled semiconductor device such as for example a metal oxide semiconductor field effect transistor (MOSFET) or for example a bipolar junction transistor (BJT). As shown,power switch S1 170 is coupled to energytransfer element T1 124 at primary winding 110 and to the input ofpower supply 100 atreturn terminal 104. - In one example,
controller 150 may be coupled to control the switching ofpower switch S1 170 to control the energy transfer from the input to the output ofpower supply 100, thereby regulating an output quantity UO 153 (e.g.,output voltage V O 120, output current IO 118, or the combination of the two) at a desired level. In addition,controller 150 may control the switching ofpower switch S1 170 to provide inputcurrent T IN 113 that is in phase with and proportional toinput voltage V IN 102. That is,controller 150 may control the switching ofpower switch S1 170 to provide PFC. In the illustrated example,controller 150 may provide adrive signal U DR 162 topower switch S1 170 to control the switching (i.e., the turning ON and turning OFF) ofpower switch S1 170. For example, in response to drivesignal U DR 162,power switch S1 170 may be switched to a closed position, which is also referred to as being turned ON or being in an ON state, and in turn, may conduct current that is represented by a switchcurrent I SW 126. Similarly, in response to drivesignal U DR 162,power switch S1 170 may be switched to an open position, which is also referred to as being turned OFF or being in an OFF state, in whichpower switch S1 170 may substantially prevent current conduction. - During the operation of
power supply 100, whenpower switch S1 170 is in the ON state, the voltage across primary winding 110 of energytransfer element T1 124 becomes substantially equal toinput voltage V IN 102 and causes current in primary winding 110 to increase linearly, which results in energy to be stored in energytransfer element T1 124. Whenpower switch S1 170 is in the OFF state, the energy stored in energytransfer element T1 124 whilepower switch S1 170 was conducting begins to transfer tooutput capacitor C1 116 andload 122. This energy transfer may produce a pulsating current indiode D1 114, which may be filtered byoutput capacitor C1 116 to produce a substantially constantoutput voltage V OUT 120. In one example, the switching ofpower switch S1 170 may produce a substantially constant output current IO 118 to be provided to load 122. - As shown in the example, a
clamp circuit 106 is coupled across primary winding 110 of energytransfer element T1 124 and is coupled to the input ofpower supply 100. In the example,clamp circuit 106 operates to clamp turn-off spikes that result from leakage inductance from primary winding 110 across theswitching device S1 170. - As further depicted in the example shown in
FIG. 1A ,controller 150 may be coupled to sense switch current ISW 126 as a sensedswitch signal U SSW 144. Any known technique to sense current, such as for example receiving the voltage across a resistor conducting the current, or for example receiving a scaled current from a current transformer, or for example receiving the voltage across the on-resistance of a MOSFET that conducts the current, may be used to sense switch current ISW 126 and to provide sensedswitch signal U SSW 144 tocontroller 150 in accordance with the teachings of the present invention. - In one example,
controller 150 may be further coupled to receive an inputsense signal U INS 142 representative ofinput voltage V IN 102 and an outputsense signal U OS 132 representative ofoutput quantity U O 153. In one example,power supply 100 may include aninput sense circuit 140 coupled to senseinput voltage V IN 102 and produce inputsense signal U INS 142 in response toinput voltage V IN 102. Similarly,power supply 100 may include anoutput sense circuit 130 coupled to senseoutput quantity U O 153 and produce outputsense signal U OS 132 in response tooutput quantity U O 153. - In one example,
controller 150 may be implemented as a monolithic integrated circuit, with discrete electrical components, or using a combination of discrete and integrated circuits. In addition,controller 150 andpower switch S1 170 may form a part of an integrated circuit that is manufactured as either a hybrid or a monolithic integrated circuit. - As further illustrated in the example depicted in
FIG. 1A ,controller 150 may include afeedback signal generator 152, astate selector circuit 154, and adriver circuit 156. In the illustrated example,feedback signal generator 152 is coupled to receive inputsense signal U INS 142, outputsense signal U OS 132, and sensedswitch signal U SSW 144 to produce afeedback signal U FB 158 that is representative of output current IO 118 (i.e., current in load 122). In some cases,feedback signal generator 152 may be configured to generatefeedback signal U FB 158 only in response to outputsense signal U OS 132. In some other cases,feedback signal generator 152 may be configured to generatefeedback signal U FB 158 in response to inputsense signal U INS 142, outputsense signal U OS 132, and sensedswitch signal U SSW 144. - In the illustrated example,
state selector circuit 154 is coupled to receivefeedback signal U FB 158. In response,state selector circuit 154 outputs an N bit digital signal illustrated as astate signal U ST 160. In some cases,state selector circuit 154 may also be coupled to receive inputsense signal U INS 142. In operation,state selector circuit 154 gathers information regarding certain properties offeedback signal U FB 158, which may also be referred to as feedback information, at a sampling frequency for a feedback period and adjustsstate signal U ST 160 in response to the feedback information at the end of the feedback period. In general, the feedback period is several times greater than the period of a clock signal used to samplefeedback signal U FB 158. In other words, the feedback period may be several times greater than a sampling period offeedback signal U FB 158. For instance, in one example, the feedback period can be half of the period of the ac line voltage (i.e., half line cycle) andfeedback signal U FB 158 can be sampled 512 times during each feedback period. That is, the feedback period can be 512 times greater than the sampling period. In another example, the feedback period can be equal to the period of the ac line voltage. Additionally, the feedback period may be several times greater than the switching period ofpower switch S1 170. That is,power switch S1 170 may be switched between the ON state and the OFF state several times (e.g., 1000 times) during the feedback period. - As shown in the example depicted in
FIG. 1A ,driver circuit 156 is coupled to receivestate signal U ST 160 and output adrive signal U DR 162 to drive the switching ofpower switch S1 170 such that an operating condition such as on-time and/or switching frequency ofpower switch S1 170 is set according to an operational state indicated bystate signal U ST 160. In one example, each one of 2N possible values ofstate signal U ST 160 may represent a different operational state (i.e., a different on-time and/or switching frequency) forpower switch S1 170. As previously mentioned, in one example,state selector circuit 154 does not adjuststate signal U ST 160 until the end of a feedback period. This also means thatdriver circuit 156 does not adjustdrive signal U DR 162 until the end of the feedback period. In other words, the operational state (hence, the operating condition of power switch S1 170) is maintained for the entire feedback period in one example in accordance with the teachings of the present invention. -
FIG. 1B shows examples of relationships of switching frequency ofpower switch S1 170 with respect tostate signal U ST 160 ofFIG. 1A in accordance with the teachings of the present invention. As shown inrelationship 174 depicted inFIG. 1B , the switching frequency ofpower switch S1 170 varies withstate signal U ST 160. Specifically,state signal U ST 160 shown inFIG. 1A may be a 10 bit digital signal ranging from 0 to 1023, and the switching frequency ofpower switch S1 170 may increase (e.g., from 50 kHz to 130 kHz) asstate signal U ST 160 increases (e.g., from 0 to 1023). In another example, as shown inrelationship 176, the switching frequency ofpower switch S1 170 may increase (e.g., from 50 kHz to 130 kHz) asstate signal U ST 160 increases until reaching a certain value (e.g., untilstate signal U ST 160 reaches 512) and may remain at a constant switching frequency (e.g., 130 kHz) for greater values ofstate signal U ST 160. It should be noted of course thatFIG. 1B provides examples for explanation purposes and that other similar relationships may also exist between the on-time ofpower switch S1 170 andstate signal U ST 160 in accordance with the teachings of the present invention. - Referring back to the
example controller 150 depicted inFIG. 1A , the examplestate selector circuit 154 may adjuststate signal U ST 160 by an amount that is based on an operation mode ofstate selector circuit 154. In the illustrated example, the operation mode ofstate selector circuit 154 is determined according to the feedback information at the end of a feedback period. For instance, in response to the feedback information at the end of a feedback period,state selector circuit 154 may be operating in a coarse mode of operation. In this coarse mode,state selector circuit 154 may update the sixth bit ofstate signal U ST 160 in response to the feedback information. That is, in the coarse mode,state selector circuit 154 may increasestate signal U ST 160 by 32 (i.e., 0000100000 binary) if the feedback information indicates thatstate selector circuit 154 should increasestate signal U ST 160 and decreasestate signal U ST 160 by 32 (i.e., 0000100000 binary) if the feedback information indicates thatstate selector circuit 154 should decreasestate signal U ST 160. - Similarly, in response to feedback information at the end of the feedback period,
state selector circuit 154 may be operating in a fine mode of operation, and update the first bit, or least significant bit, ofstate signal U ST 160. In other words, in the fine mode,state selector circuit 154 may increase or decreasestate signal U ST 160 by 1 (i.e., 0000000001 binary) in response to the feedback information. In one example, this means thatstate selector circuit 154 may adjuststate signal U ST 160 such that the rate of change in state signal UST 160 (hence, the rate of change in the operating condition of power switch S1 170) over multiple feedback periods in the fine mode of operation is less than the rate of change instate signal U ST 160 over multiple feedback periods in the coarse mode of operation. In this manner,state selector circuit 154 may vary the resolution of changes made tostate signal U ST 160 and thus, may vary the rate of change in power delivery over multiple feedback periods to load 122 in response to the feedback information in accordance with the teachings of the present invention. For example, if the feedback information indicates tostate selector circuit 154 that the rate of change (i.e., rate of increase or rate of decrease) in power delivery over multiple feedback periods to load 122 should be greater,state selector circuit 154 may operate in the coarse mode and updatestate signal U ST 160, which therefore updates the operating condition ofpower switch S1 170 by a greater amount in accordance with the teachings of the present invention. - In the depicted example, the feedback information may include a first information that may represent a difference between a portion of a feedback period that
feedback signal U FB 158 is less than a threshold value, and a portion of the feedback period thatfeedback signal U FB 158 is greater than the threshold value. The feedback information may also include a second information that may represent a difference between a portion of a feedback period thatfeedback signal U FB 158 is less than a lower limit and a portion of the feedback period thatfeedback signal U FB 158 is greater than an upper limit. In one example, the threshold value may represent a desired level of regulated output current IO 118 at the output ofpower supply 100. The lower limit may represent a level of output current IO 118 that is below the desired level (e.g., 10% below the desired level) and the upper limit may represent a level of output current IO 118 that is above the desired level (e.g., 10% above the desired level). In some applications, the first information may represent a difference between an estimated average value offeedback signal U FB 158 and the threshold value. In one example,state selector circuit 154 may use the first information and/or the second information to determine an operational state and hence, set an operating condition ofpower switch S1 170 accordingly. - For example, if the portion of a feedback period that
feedback signal U FB 158 is less than the threshold value is greater than the portion of the feedback period thatfeedback signal U FB 158 is greater than the threshold value by a certain amount,state selector circuit 154 may determine that the power delivery to load 122 per unit time should be increased by a greater amount to more quickly bring output current IO 118 closer to the desired level. In this case,state selector circuit 154 may operate in the coarse mode. However, once the portion of a feedback period thatfeedback signal U FB 158 is less than the threshold value approaches the portion of the feedback period thatfeedback signal U FB 158 is greater than the threshold value (e.g., the difference between the portion of a feedback period thatfeedback signal U FB 158 is less than the threshold value and the portion of the feedback period thatfeedback signal U FB 158 is greater than the threshold value falls within a certain range),state selector circuit 154 may determine that changes to the power delivery to load 122 should be made with finer resolution. In this case,state selector circuit 154 may operate in the fine mode. In this way,controller 150 can be configured to respond more rapidly to larger transients and remain less responsive to smaller disturbances at the input and/or the output ofpower supply 100 in accordance with the teachings of the present invention. -
FIG. 2A shows a circuit diagram illustrating one example of thestate selector circuit 154 of thecontroller 150 inFIG. 1A with increased detail in accordance with the teachings of the present invention. It should be appreciated that similarly named and numbered elements referenced below are coupled and function as described above. As shown,state selector circuit 154 includes afeedback signal processor 280 that is coupled to receivefeedback signal U FB 158, asampling signal U SMP 272, and a feedbackperiod signal U PER 262. In response,feedback signal processor 280 outputs a firstcount signal U CN1 222 corresponding to the first information and a secondcount signal U CN2 232 corresponding to the second information. - As will be shown, in one example, during a feedback period that is demarcated by feedback
period signal U PER 262,feedback signal processor 280 comparesfeedback signal U FB 158 with athreshold U TH 205, anupper limit U UP 201, and alower limit U LO 203 at a sampling frequency that is determined by the frequency ofsampling signal U SMP 272.Feedback signal processor 280 updates first countsignal U CN1 222 and secondcount signal U CN2 232 based on the results of the comparisons during the feedback period. In the illustrated example,threshold U TH 205 corresponds to the threshold value (i.e., desired value of output current IO 118),lower limit U LO 203 corresponds to the lower limit, andupper limit U UP 201 corresponds to the upper limit. - The example of
FIG. 2A showsstate selector 154 including a feedbackperiod signal generator 260 that generates feedbackperiod signal U PER 262 and asampling clock generator 270 that generatessampling signal U SMP 272. In one example, feedbackperiod signal generator 260 may output a pulse at set intervals (i.e., a periodic pulse with a certain period) as feedbackperiod signal U PER 262. Each one of the intervals (i.e., the period of feedback period signal UPER 262) demarcates a feedback period. Stated differently, feedbackperiod signal U PER 262 can indicate the beginning and the end of a feedback period. In one example, the period of feedback period signal UPER 262 (i.e., the feedback period) may be equal to one half of the period the ac line voltage, which may be several times (e.g., 512) greater than the period of sampling signal USMP 272 (i.e., the sampling period). In other words,feedback signal processor 280 may update firstcount signal U CN1 222 and secondcount signal U CN2 232 512 times during every feedback period. Additionally,feedback signal processor 280 may set firstcount signal U CN1 222 to a first initial value and secondcount signal U CN2 232 to a second initial value at the beginning of each feedback period. In the depicted example, the first initial value and the second initial value may be the same and equal to zero. In some cases, the first initial value may be different from the second initial value. - As further illustrated in the example depicted in
FIG. 2A ,feedback signal processor 280 includes afirst counter Counter1 220, asecond counter Counter2 230, alogic circuit 210, andcomparators Counter1 220 is coupled to receivesampling signal U SMP 272 at its CLK input, feedbackperiod signal U PER 262 at its RESET input, anoutput 207 ofcomparator 206 at its UP/DN input. First counterCounter1 220 is also coupled to output firstcount signal U CN1 222. In operation,first counter Counter1 220 updates first countsignal U CN1 222 by counting up or down in response tooutput 207 during every sampling period. In one example,first counter Counter1 220 counts up ifoutput 207 is logic low and counts down ifoutput 207 is logic high.Comparator 206 is coupled to receivefeedback signal U FB 158 and setoutput 207 to logic high or logic low in response to a comparison offeedback signal U FB 158 withthreshold U TH 205. In one example,comparator 206 may setoutput 207 to logic high iffeedback signal U FB 158 is greater thanthreshold U TH 205, and setoutput 207 to logic low iffeedback signal U FB 158 is less thanthreshold U TH 205. First counterCounter1 220 may increase firstcount signal U CN1 222 by counting up whenfeedback signal U FB 158 is less thanthreshold U TH 205 during a sampling period and similarly, may decrease firstcount signal U CN1 222 by counting down whenfeedback signal U FB 158 is greater thanthreshold U TH 205 during a sampling period. In this way,first counter Counter1 220 may output as first count signal UCN1 222 a signal that may be representative of the difference between a portion of a feedback period thatfeedback signal U FB 158 is less thanthreshold U TH 205 and a portion of the feedback period thatfeedback signal U FB 158 is greater thanthreshold U TH 205. - Continuing with the example depicted in
FIG. 2A ,second counter Counter2 230 is coupled to receivesampling signal U SMP 272 at its CLK input, feedbackperiod signal U PER 262 at its RESET input,output 207 ofcomparator 206 at its UP/DN input, anoutput 213 oflogic circuit 210 at its EN input.Second counter Counter2 230 is further coupled to output secondcount signal U CN2 232. In operation,second counter Counter2 230 updates secondcount signal U CN2 232 by counting up or down in response tooutput 207 during every sampling period ifoutput 213 indicates thatsecond counter 230 should be enabled, and maintains secondcount signal U CN2 232 at the same value ifoutput 213 indicates thatsecond counter Counter2 230 should be disabled. In one example,logic circuit 210 may be a two-input XOR gate coupled to receive anoutput 211 ofcomparator 202 and anoutput 209 ofcomparator 204 as inputs. As such,output 213 may be logic low indicating thatsecond counter Counter2 230 should be disabled whenoutput Output 213 may be logic high indicating thatsecond counter Counter2 230 should be enabled when only one ofoutputs outputs - In the depicted example,
comparators feedback signal U FB 158 and setoutputs feedback signal U FB 158 withupper limit U UP 201 and withlower limit U LO 203, respectively. Specifically,comparator 202 setsoutput 211 to logic high iffeedback signal U FB 158 is less thanupper limit U UP 201 and to logic low iffeedback signal U FB 158 is greater thanupper limit U UP 201. Similarly,comparator 204 setsoutput 209 to logic high iffeedback signal U FB 158 is greater thanlower limit U LO 203 and to logic low iffeedback signal U FB 158 is less thanlower limit U LO 203. In other words,second counter Counter2 230 is enabled to count up or down in response tooutput 207 whenfeedback signal U FB 158 is greater thanupper limit U UP 201 or less thanlower limit U LO 203 during a sampling period. Whenfeedback signal U FB 158 is betweenupper limit U UP 201 andlower limit U LO 203, however,second counter Counter2 230 is disabled and keeps secondcount signal U CN2 232 constant. - In the example, when enabled,
second counter Counter2 230 increases secondcount signal U CN2 232 by counting up ifoutput 207 is logic low and decreases secondcount signal U CN2 232 by counting down ifoutput 207 is logic high. That is,second counter Counter2 230 counts up whenfeedback signal U FB 158 is less thanlower limit U LO 203 during a sampling period.Second counter Counter2 230 counts down whenfeedback signal U FB 158 is greater thanupper limit U UP 201 during a sampling period. In this way,second counter Counter2 230 may output as second count signal UCN2 232 a signal that may be representative of the difference between a portion of a feedback period thatfeedback signal U FB 158 is less thanlower limit U LO 203 and a portion of the feedback period thatfeedback signal U FB 158 is greater thanupper limit U UP 201. In one example, bothfirst counter Counter1 220 andsecond counter Counter2 230 are configured to have a maximum output count that is representative of a length of time corresponding to a feedback period. The magnitudes of firstcount signal U CN1 222 and secondcount signal U CN2 232 cannot exceed the maximum output count. - As further shown,
state selector circuit 154 also includes adecision circuit 240 and astate counter 250.Decision circuit 240 is coupled to receive firstcount signal U CN1 222 and secondcount signal U CN2 232 fromfeedback signal processor 280 and output adirection signal U DIR 244 and amode signal U MD 242. In one example,direction signal U DIR 244 may be a one-bit digital signal indicative of the direction of change instate signal U ST 160 andmode signal U MD 242 may be a two-bit digital signal indicative of an operation mode ofstate selector circuit 154. In operation,decision circuit 240 may setdirection signal U DIR 244 to zero or one in response to firstcount signal U CN1 222, andmode signal U MD 242 to one of zero (i.e., 00 binary), one (i.e., 01 binary), and two (i.e., 10 binary) in response to both firstcount signal U CN1 222 and secondcount signal U CN2 232. In the illustrated example,decision circuit 240 may setdirection signal U DIR 244 to one indicating thatstate signal U ST 160 should be increased when firstcount signal U CN1 222 is positive and setdirection signal U DIR 244 to zero indicating thatstate signal U ST 160 should be decreased when firstcount signal U CN1 222 is negative. - Furthermore,
decision circuit 240 may setmode signal U MD 242 to zero, which may correspond to a coarse mode as an operation mode if the magnitude of firstcount signal U CN1 222 is greater than a value X, the magnitude of secondcount signal U CN2 232 is greater than a value Y, and both firstcount signal U CN1 222 and secondcount signal U CN2 232 have the same sign (i.e., both signals are either positive or negative).Decision circuit 240 may setmode signal U MD 242 to one, which may correspond to a medium mode as an operation mode if the magnitude of firstcount signal U CN1 222 is greater than the value X, the magnitude of secondcount signal U CN2 232 is between the value Y and a value Z (less than the value Y), and both firstcount signal U CN1 222 and secondcount signal U CN2 232 have the same sign.Decision circuit 240 may setmode signal U MD 242 to two, which may correspond to a fine mode as an operation mode if the magnitude of firstcount signal U CN1 222 is less than the value X, or the magnitude of secondcount signal U CN2 232 is less than the value Z, or firstcount signal U CN1 222 and secondcount signal U CN2 232 have different signs. In one example, the value X represents a length of time that corresponds to 5% of a feedback period (i.e., the value X is equal to 5% of the maximum output count). In some cases, the value X may also correspond to 5% of the maximum value of the difference between an estimated average value offeedback signal U FB 158 andthreshold U TH 205. The value Y represents a length of time that corresponds to 20% of a feedback period (i.e., the value Y is equal to 20% of the maximum output count) and the value Z represents a length of time that corresponds to 10% of a feedback period (i.e., the value Z is equal to 10% of the maximum output count). - As shown in the depicted example,
state counter 250 is coupled to receive feedbackperiod signal U PER 262 at its UPDATE input,direction signal U DIR 244,mode signal U MD 242, firstcount signal U CN1 222, secondcount signal U CN2 232. State counter is also coupled to outputstate signal U ST 160. In operation,state counter 250 may updatestate signal U ST 160 in response to the values ofdirection signal U DIR 244 andmode signal U MD 242 at the time that a new pulse in feedbackperiod signal U PER 262 is received, which is indicative of the end of a presently occurring feedback period (i.e., the beginning of a new feedback period). For example, when the value ofmode signal U MD 242 at the end of a presently occurring feedback period is zero,state selector circuit 154 is set to operate in the coarse mode. Whenstate selector circuit 154 is in the coarse mode,state counter 250 may update (increase or decrease) the sixth bit of state signal UST 160 (i.e., 0000100000 binary) in response to the value ofdirection signal U DIR 244 at the end of the presently occurring feedback period. That is, whenstate selector circuit 154 is operating in the coarse mode,state counter 250 may increase or decreasestate signal U ST 160 by 32 for the next feedback period based on the value ofdirection signal U DIR 244 at the end of the presently occurring feedback period. In one example,state counter 250 increasesstate signal U ST 160 ifdirection signal U DIR 244 is one and decreasesstate signal U ST 160 ifdirection signal U DIR 244 is zero. - In another example, when the value of
mode signal U MD 242 at the end of a presently occurring feedback period is one,state selector circuit 154 is set to operate in the medium mode. Whenstate selector circuit 154 is in the medium mode,state counter 250 may update the fourth bit of state signal UST 160 (i.e., 0000001000 binary) in response to the value ofdirection signal U DIR 244 at the end of the presently occurring feedback period. That is, whenstate selector circuit 154 is operating in the coarse mode,state counter 250 may increase or decreasestate signal U ST 160 by eight for the next feedback period based on the value ofdirection signal U DIR 244 at the end of the presently occurring feedback period. In one example,state counter 250 increasesstate signal U ST 160 ifdirection signal U DIR 244 is one and decreasesstate signal U ST 160 ifdirection signal U DIR 244 is zero. - In yet another example, when the value of
mode signal U MD 242 at the end of a presently occurring feedback period is two,state selector circuit 154 is set to operate in the fine mode. Whenstate selector circuit 154 is in the fine mode,state counter 250 may update the first bit (least significant bit) of state signal UST 160 (i.e., 0000000001 binary). In the depicted example, whenstate selector circuit 154 is operating in the fine mode,state counter 250 is configured to updatestate signal U ST 160 only ifdirection signal U DIR 244 andmode signal U MD 242 maintain their values, and the final values of both firstcount signal U CN1 222 and secondcount signal U CN2 232 at the end of a feedback period are above a minimum threshold count (e.g., 3) for a certain number (e.g., 12) of consecutive feedback periods. In one example, if this set of conditions is met and direction signalU DIR 244 is one,state counter 250 increasesstate signal U ST 160 by one. If this set of conditions is met butdirection signal U DIR 244 is zero,state counter 250 decreasesstate signal U ST 160 by one. Conversely, if this set of conditions is not met such thatdirection signal U DIR 244 changes and/or at least one of the final values of firstcount signal U CN1 222 and secondcount signal U CN2 232 drops below the minimum threshold count,state counter 250 keepsstate signal U ST 160 unchanged. For example,state counter 250 may include a counter that only operates whenstate selector circuit 154 is in the fine mode. The counter may be configured to start counting from one whenstate selector circuit 154 enters the fine mode and count up at the end of each feedback period ifdirection signal U DIR 244 maintains its value, and the final values of both firstcount signal U CN1 222 and secondcount signal U CN2 232 at the end of a feedback period are above the minimum threshold count. Ifdirection signal U DIR 244 changes its value and/or at least one of the final values of firstcount signal U CN1 222 and secondcount signal U CN2 232 drops below the minimum threshold count, then the counter is reset to one andstate signal U ST 160 remains unchanged. Ifdirection signal U DIR 244 maintains its value, and the final values of both firstcount signal U CN1 222 and secondcount signal U CN2 232 remain above the minimum threshold count for 12 consecutive feedback periods (i.e., if the counter output reaches 12),state counter 250 updatesstate signal U ST 160 based on the value ofdirection signal U DIR 244 and sets the counter output back to one. It is in this manner thatstate selector circuit 154 can adjust the rate of change in the operating condition of power switch S1 170 (hence, the rate of change in power delivery to load 122) in response to the feedback information in accordance with the teachings of the present invention. -
FIG. 2B shows a circuit diagram illustrating another example of thestate selector circuit 154 of thecontroller 150 inFIG. 1A in accordance with the teachings of the present invention. It is noted thatstate selector circuit 154 inFIG. 2B shares similarities withstate selector circuit 154 inFIG. 2A . It should be appreciated that similarly named and numbered elements referenced below are coupled and function as described above. One difference betweenstate selector circuit 154 inFIG. 2B andstate selector circuit 154 inFIG. 2A is that feedbackperiod signal generator 260 inFIG. 2B includes a one-shot circuit 264 coupled to receiveoutput 207 fromcomparator 206, and is therefore coupled to generate feedbackperiod signal U PER 262 in response to the comparison offeedback signal U FB 158 withthreshold U TH 205. One-shot circuit 264 is coupled to output a pulse in feedbackperiod signal U PER 262 whenoutput 207 transitions from logic high to logic low. In other words, feedbackperiod signal generator 260 may output a pulse whenfeedback signal U FB 158 falls from a level abovethreshold U TH 205 to a level belowthreshold U TH 205. As such, each feedback period may correspond to a length of time between consecutive instances offeedback signal U FB 158 falling belowthreshold U TH 205. Additionally, feedbackperiod signal generator 260 may be configured to output a pulse to terminate a feedback period iffeedback signal U FB 158 does not fall belowthreshold U TH 205 within a certain length of time (e.g., a timeout period) from the start of the feedback period. For example, during startup, energy at the output ofpower supply 100 may be at a level such thatfeedback signal U FB 158 is belowthreshold U TH 205. In this case, feedbackperiod signal generator 260 may output a pulse every timeout period to indicate that a presently occurring feedback period has ended and a new feedback period has begun. That is, each feedback period may be equal to the timeout period. -
FIG. 2C shows a circuit diagram illustrating yet another example of thestate selector circuit 154 of thecontroller 150 inFIG. 1A in accordance with the teachings of the present invention. It is noted thatselector circuit 154 inFIG. 2C shares similarities withstate selector circuit 154 inFIG. 2A . It should be appreciated that similarly named and numbered elements referenced below are coupled and function as described above. One difference betweenstate selector circuit 154 inFIG. 2C andstate selector circuit 154 inFIG. 2A is that feedbackperiod signal generator 260 inFIG. 2C includes acomparator 266 coupled to receive inputsense signal U INS 142 and a one-shot circuit 264 coupled tocomparator 266 to output feedbackperiod signal U PER 262 in response to the output ofcomparator 266. - Specifically, in one example,
comparator 266 may compare inputsense signal U INS 142 with a zero condition threshold UZC, which may be representative of a zero crossing threshold forinput voltage V IN 102. In response,comparator 266 may output a logic high or logic low signal. One-shot circuit 264 may be coupled to output a pulse in feedbackperiod signal U PER 262 when the signal at the output ofcomparator 266 transitions from logic high to logic low. In one example,comparator 266 outputs a logic high signal if inputsense signal U INS 142 is greater than zero condition threshold UZC and a logic low signal if inputsense signal U INS 142 is less than or equal to zero condition threshold UZC. In other words, feedbackperiod signal generator 260 inFIG. 2C may output a pulse in feedbackperiod signal U PER 262 when inputsense signal U INS 142 crosses zero condition threshold UZC from a level that is above the threshold to a level that is below the threshold, which may also be referred to as a zero crossing event. As such, each feedback period may correspond to a length of time between consecutive zero crossing events. -
FIG. 3A shows an example set of waveforms illustrating the operation of thecontroller 150 inFIG. 1A in accordance with the teachings of the present invention. In the illustrated example,waveform 302 is a rectified periodic signal with aperiod T P 310 and may be representative ofinput voltage V IN 102.Waveform 313 is a periodic signal withperiod T P 310 and may be representative of inputcurrent I IN 113. As shown in the example,waveform 313 is in phase with and proportional towaveform 302.Waveform 358 is an example waveform representative offeedback signal U FB 158. In one example,waveform 358 may be representative of output current IO 118 that is provided to load 122 ofpower supply 100. As illustrated,waveform 358 is phase shifted with respect towaveform 313. This could be due tooutput capacitor C1 116 phase shifting output current IO 118 with respect to inputcurrent I IN 113. It should be noted that despite being phase shifted,waveform 358 may still be periodic with a period TFB that is substantially equal to the period of waveform 302 (i.e., period TP 310). - Further illustrated in
FIG. 3A are waveform 362 andwaveform 372.Waveform 362 may be representative of feedbackperiod signal U PER 262 ofFIGS. 2A-2C , andwaveform 372 may be representative ofsampling signal U SMP 272 ofFIGS. 2A-2C . In the illustrated example,waveform 362 includes pulses that are generated in response towaveform 358 falling from a level above avalue 305 to a level belowvalue 305.Value 305 may correspond tothreshold U TH 205 ofFIGS. 2A-2C . Accordingly, in one example, the length of time between consecutive pulses inwaveform 362 may correspond to a feedback period. For example, time points tn, tn+1, and tn+2 may be the start and end points of consecutive feedback periods, with time point tn indicating the start of the nth feedback period, time point tn+1 indicating the end of the nth feedback period and the start of the (n+1)th feedback period, and time point tn+2 indicating the end of the (n+1)th feedback period and the start of the (n+2)th feedback period. - In the illustrated example,
waveform count signal T CN1 222 and secondcount signal U CN2 232 ofFIGS. 2A-2C , respectively, and may be updated every period of waveform 372 (i.e., every sampling period). Specifically,waveform 322 may be incremented ifwaveform 358 is less thanvalue 305, and may be decremented ifwaveform 358 is greater than or equal towaveform 305.Waveform 332 may be incremented ifwaveform 358 is less than avalue 303, which is representative oflower limit U LO 203, may be decremented ifwaveform 358 is greater than avalue 301, which is representative ofupper limit U UP 201, and may be kept unchanged ifwaveform 358 is betweenvalue 301 andvalue 303. -
FIG. 3A also illustrates awaveform 360, which may be representative ofstate signal U ST 160. Final values ofwaveforms direction signal U DIR 244 andmode signal U MD 242 and in turn, updatewaveform 360 to adjust the operating condition ofpower switch S1 170 for the next feedback period. For instance,waveform 360 may be updated by a different amount depending on the set of conditions that is met by the final values ofwaveforms waveforms waveforms - In the depicted example, at the end of the nth feedback period, the final value of
waveform 322 is positive and greater than the value X, and final value ofwaveform 332 is positive and greater than the value Y. Under these conditions, in one example,direction signal U DIR 244 is set to one indicating thatstate signal U ST 160 should be increased andmode signal U MD 242 is set to zero indicating thatstate selector circuit 154 should operate in the coarse mode. As a result,waveform 360 is increased by 32 from a value K to a value (K+32) for (n+1)th feedback period. In the depicted example, the same set of conditions is met bywaveforms waveform 360 is again increased by 32 from value (K+32) to (K+64) for the next feedback period starting at time point tn+2. -
FIG. 3B shows another example set of waveforms illustrating the operation ofcontroller 150 ofFIG. 1A in accordance with the teachings of the present invention. One difference betweenwaveform 358 inFIG. 3B andwaveform 358 inFIG. 3A is that the final values ofwaveforms waveform 358 inFIG. 3B at the end of nth feedback period and (n+1)th feedback period satisfy a different set of conditions. Specifically, as shown in the example depicted inFIG. 3B at the end of nth feedback period, the final value ofwaveform 322 is positive and greater than the value X, and the final value ofwaveform 332 is positive and between the value Y and the value Z. In one example, the value Z is less than the value Y. Under these conditions,direction signal U DIR 244 is set to one indicating thatstate signal U ST 160 should be increased andmode signal U MD 242 is set to one indicating thatstate selector circuit 154 should operate in the medium mode. As a result,waveform 360 is increased by eight from value K to a value (K+8) for (n+1)th feedback period. In the depicted example, the same set of conditions holds at the end of (n+1)th feedback period. Therefore,waveform 360 is again increased by eight from value (K+8) to a value (K+16) for the next feedback period starting at time point tn+2. -
FIG. 3C shows yet another example set of waveforms illustrating the operation ofcontroller 150 ofFIG. 1A in accordance with the teachings of the present invention. One difference betweenwaveform 358 ofFIG. 3C andwaveform 358 ofFIG. 3A andFIG. 3B is that the final values ofwaveforms FIG. 3C at the end of the feedback periods from the nth feedback period through (n+11)th feedback period (not shown) satisfy a different set of conditions. Specifically, at the end of the nth feedback period, the final value ofwaveform 322 is positive and less than the value X, and the final value ofwaveform 332 is positive and less than the value Z. Under these conditions,direction signal U DIR 244 is set to one indicating thatstate signal U ST 160 should be increased andmode signal U MD 242 is set to two indicating thatstate selector circuit 154 should operate in the fine mode. - In one example, when operating in the fine mode,
state selector circuit 154 updatesstate signal U ST 160 only if the values ofdirection signal U DIR 244 andmode signal U MD 242 remain the same, and both firstcount signal U CN1 222 and secondcount signal U CN2 232 are above the minimum threshold count for a certain number (e.g., 12) of consecutive feedback periods. In the illustrated example, the final values ofwaveforms direction signal U DIR 244 andmode signal U MD 242 remain at one and two, respectively for 12 consecutive feedback periods. Additionally, the values of firstcount signal U CN1 222 and secondcount signal U CN2 232 at the end of each feedback period remain above the minimum threshold count during this time. As a result,waveform 360 is increased by one from value K to a value (K+1) for (n+12)th feedback period starting at time point tn+12. -
FIG. 4A shows a flow diagram illustrating anexample process 400 for adjusting the operating condition of a switch of a power supply in accordance with the teachings of the present invention. It is noted thatprocess 400 may be performed by a circuit similar or identical to examplestate selector circuit 154 inFIG. 2A ,FIG. 2B and inFIG. 2C in accordance with the teachings of the present invention. In the depicted example,process 400 may begin atblock 401. Atblock 403, a new feedback period may be started. In one example, the feedback period may be started in response to a pulse in an indicator signal (e.g., feedback period signal UPER 262). For example, feedbackperiod signal generator 260 may output pulses at set intervals as the indicator signal and each pulse may indicate the start of a new feedback period. Alternatively, feedbackperiod signal generator 260 may output a pulse in response tofeedback signal U FB 158 falling below a threshold (e.g., threshold UTH 205). Atblock 405, a first count signal (e.g., first count signal UCN1 222) and a second count signal (e.g., second count signal UCN2 232) may be set to an initial value (e.g., zero). In one example, the first count signal may be representative of the difference between a portion of a feedback period thatfeedback signal U FB 158 is less than the threshold and a portion of the feedback period thatfeedback signal U FB 158 is greater than the threshold. The first count signal may be generated by a counter (e.g., first counter Counter1 220). The second count signal may be representative of the difference between a portion of a feedback period thatfeedback signal U FB 158 is less than a lower limit (e.g., lower limit ULO 203) and a portion of the feedback period thatfeedback signal U FB 158 is greater than an upper limit (e.g., upper limit UUP 201). The second count signal may be generated by another counter (e.g., second counter Counter2 230). The first and the second count signals may be set to the initial value when the counters are reset in response to a pulse in the indicator signal. - At
block 407, a new feedback sample (i.e., a new sample of feedback signal UFB 158) may be obtained. In one example, each feedback sample may be representative of the value offeedback signal U FB 158 during a corresponding sampling period. Each sampling period may be equal to the period of a clock signal (e.g., sampling signal USMP 272) generated by a clock generator (e.g., sampling clock generator). In one example, the period of the clock signal may be several times (e.g., 512) smaller than the feedback period. In other words,feedback signal U FB 158 may be sampled several times (e.g., 512) during a feedback period. - At
block 409, the feedback sample may be compared with the threshold, the lower limit and the upper limit. Then, the first and the second count signals may be updated based on these comparisons. More particularly, the first count signal may be changed in response to the comparison of the feedback sample with the threshold and the second count signal may be changed in response to the comparisons of the feedback sample with both the upper limit and the lower limit. -
FIG. 4B shows a flow diagram illustrating one example of detailed steps that may occur inprocess block 409 in accordance with the teachings of the present invention. For instance, examples of these comparisons and the resulting changes in the first and the second signals discussed on process block 409 ofFIG. 4A are shown in detail. Referring now toFIG. 4B , atblock 412, the feedback sample is compared with the threshold. If the sample is greater than the threshold,process 409 proceeds to block 414 where the first count signal is decremented. In one example,first counter Counter1 220 may decrement firstcount signal U CN1 222 by counting down. If the sample is not greater than the threshold,process 409 proceeds block 416 where the first count signal is incremented. In one example,first counter Counter1 220 increments firstcount signal U CN1 222 by counting up. - At
block 418, the feedback sample is compared with the upper limit. If the sample is greater than the upper limit,process 409 proceeds to block 422 where the second count signal is decremented. In one example,second counter Counter2 230 decrements secondcount signal U CN2 232 by counting down. If the sample is not greater than the upper limit,process 409 proceeds to block 420 where the sample is compared with the lower limit. If the sample is less than the lower limit,process 409 proceeds to block 424 where the second count signal is incremented. In one example,second counter Counter2 230 increments secondcount signal U CN2 232 by counting up. If the sample is not less than the lower limit,process 409 proceeds to block 426 where the second count signal is kept unchanged. - Referring now back to
FIG. 4A , atblock 411, it may be determined whether or not the feedback period has ended. In one example, the feedback period may end in response to a new pulse in the indicator signal. If the feedback period has not ended,process 400 returns to block 407. Otherwise, if the feedback period has ended,process 400 proceeds to block 413. - At
block 413, values of a direction signal (e.g., direction signal UDIR 244) and a mode signal (e.g., mode signal UMD 242) are set in response to the final values of the first and the second count signals at the end of the feedback period. In one example,state selector circuit 154 may include a decision circuit (e.g., decision circuit 240) coupled to receive the first and the second count signals and set the values of direction signal and the mode signal in response to the final values of the first and the second count signals. -
FIG. 4C shows a flow diagram illustrating one example of detailed steps that may occur inprocess block 413 in accordance with the teachings of the present invention. For instance, various different conditions on the first and the second count signals, and the corresponding values of the direction signal and the mode signal are shown in detail. Referring now toFIG. 4C , atblock 440, it may be determined whether or not the magnitude of the first count signal is greater than the value X, whether or not the magnitude of the second count signal is greater than the value Y, and whether or not both signals have the same sign. If these conditions are met,process 413 proceeds to block 442. If not,process 413 proceeds to block 444. - At
block 442, the direction signal is set in response to the sign of the first signal and the mode signal is set to a value that indicates the coarse mode as the operation mode ofstate selector circuit 154. For example,decision circuit 240 may setmode signal U MD 242 to zero and direction signalU DIR 244 to zero if the first signal is positive, and to one if the first signal is negative. - At
block 444, it may be determined whether or not the magnitude of the first signal is greater than the value X, whether or not the magnitude of the second signal is less than the value Y but greater than the value Z, and whether or not both signals have the same sign. If these conditions are met,process 413 proceeds to block 446 where the direction signal is set in response to the sign of the first signal and the mode signal is set to a value that indicates the medium mode as the operation mode ofstate selector circuit 154. If the conditions atblock 444 are not met,process 413 proceeds to block 448 where the direction signal is set in response to the sign of the first signal and the mode signal is set to a value that indicates the fine mode as the operation mode ofstate selector circuit 154. - Referring now back to
FIG. 4A , atblock 415, the operating condition of a power switch (e.g., power switch S1 170) of a switched-mode power supply may be adjusted in response to the direction signal, to the mode signal, and to at least one of the final values of the first count signal and the second count signal at the end of a feedback period. For example,state selector circuit 154 may changestate signal U ST 160 based on the values ofdirection signal U DIR 244 andmode signal U MD 242. This may change a drive signal (e.g., drive signal UDR 162) coupled to drive switching of the power switch, thereby causing an operating condition ofpower switch S1 170 such as switching frequency and/or on-time to change. As previously mentioned,state selector circuit 154 may changestate signal U ST 160 by an amount that varies based on the operation mode ofstate selector circuit 154. Therefore,state selector circuit 154 may vary the rate of change in the operating condition ofpower switch S1 170 over multiple feedback periods. In addition,state selector circuit 154 may keepstate signal U ST 160 unchanged based ondirection signal U DIR 244 and at least one of the final value of the first count signal and the final value of the second count signal. For example, whenstate selector circuit 154 is operating in the fine mode, ifdirection signal U DIR 244 changes and/or at least one of the final value of the first count signal and the final value of the second count signal drops below the minimum threshold count during a certain number of consecutive feedback periods,state selector circuit 154 may keepstate signal U ST 160 unchanged. In some cases, whenstate signal U ST 160 increases, switching frequency ofpower switch S1 170 may increase resulting in more power to be delivered to load 122 and conversely, whenstate signal U ST 160 decreases, switching frequency ofpower switch S1 170 may decrease resulting in less power to be delivered to load 122. -
FIG. 5 is a schematic circuit diagram illustrating an example driver circuit including one example of a modulated DAC according to the teachings of the present invention. As shown,driver circuit 156 can be coupled to receive a digitalinput signal U IN 590 comprising (Q+P) bits, where Q and P are non-zero integers.Driver circuit 156 can be coupled to outputdrive signal U DR 162 in response to digitalinput signal U IN 590 to control the switching ofpower switch S1 170. In one example, digitalinput signal U IN 590 may correspond tostate signal U ST 160 of the controller inFIG. 1A . In this disclosure, upper Q bits of digital input signal UIN 590 (i.e., bits B1 through BQ) are referred to as “baseline bits” with bit BQ being the most significant bit and bit B1 being the least significant bit. Lower P bits of digital input signal UIN 590 (i.e., bits M1 through MP) are referred to as “modulation bits” with bit MP being the most significant bit and bit M1 being the least significant bit. - Further illustrated in the example driver circuit is a modulated
DAC 540 coupled to receive digitalinput signal U IN 590 and aclock signal U CLK 512. In the illustrated example,clock signal U CLK 512 is generated by aclock signal generator 510 that is included indriver circuit 156. In one example,clock signal U CLK 512 is a periodic signal with a fixed period. In response to digitalinput signal U IN 590 andclock signal U CLK 512, modulatedDAC 540 outputs an adjustsignal U ADJ 580 to adrive signal generator 520.Modulated DAC 540 can include amodulator 530 coupled to receiveclock signal U CLK 512 and the modulation bits. In response,modulator 530 generates a modulationperiod signal UMP 538. In one example, modulationperiod signal UMP 538 is a periodic signal that alternates between logic high and logic low. The period of modulationperiod signal U MDP 538 may be proportional to the number of possible values (i.e., 2P) that can be represented by the modulation bits. - In the depicted example,
modulator 530 includes acounter 532 and acomparator 535.Counter 532 has an UPDATE input coupled to receiveclock signal U CLK 512.Comparator 535 is coupled to receive anoutput 534 ofcounter 532 and the modulation signal and in turn, output modulationperiod signal U MDP 538. In one example,counter 532 is configured to continually count up every period ofclock signal U CLK 512. Specifically, counter 532increments output 534 by counting up every period ofclock signal U CLK 512 untiloutput 534 reaches the maximum value of the modulation bits (i.e., 2P−1). In response to reaching the maximum value of the modulation bits, counter 532 setsoutput 534 back to zero and again counts up every period ofclock signal U CLK 512. In one example, the period of modulationperiod signal U MDP 538 may be equal to 2P periods ofclock signal U CLK 512. In operation,comparator 535 can set modulationperiod signal U MDP 538 to logic high or logic low in response to comparingoutput 534 with the value of the modulation bits. In one example,comparator 535 can set modulationperiod signal U MDP 538 to logic high ifoutput 534 is less than the value of the modulation bits and may set modulationperiod signal U MDP 538 to logic low ifoutput 534 is greater than or equal to the value of the modulation bits. In other words,modulator 530 can adjust a portion of the period of modulationperiod signal U MDP 538 that modulationperiod signal U MDP 538 is logic high and a portion of the period that modulationperiod signal U MDP 538 is logic low in response to the value of the modulation bits. That is,modulator 530 can adjust the duty cycle of the modulation period signal UMDP 538 (i.e., the ratio of a portion of the period of modulationperiod signal U MDP 538 during which modulationperiod signal U MDP 538 is either logic high or logic low to the period of modulation period signal UMDP 538) in response to the value of the modulation bits. The duty cycle of modulationperiod signal U MDP 538 times the period of modulationperiod signal U MDP 538 may be referred to as a modulation time. As such, in one example, the modulation time represents the portion of the period of modulationperiod signal U MDP 538 during which modulationperiod signal U MDP 538 is logic high. - In one example, the value of the modulation bits determines the duty cycle of modulation
period signal U MDP 538. For example, if there are three modulation bits and the value of the modulation bits is equal to three (i.e., 011 binary), the period of modulationperiod signal U MDP 538 is eight (23) periods ofclock signal U CLK 512 and the duty cycle of the modulationperiod signal U MDP 538 is ⅜. Accordingly, modulationperiod signal U MDP 538 may be set to logic high for three periods ofclock signal U CLK 512 and to logic low for five periods ofclock signal U CLK 512 during every period of modulationperiod signal U MDP 538. - As further illustrated, modulated
DAC 540 may include aDAC 577 comprising a group of switchable bit-to-analog circuitries 576 and aswitchable modulation source 575. The number of switchable bit-to-analog circuitries included inDAC 577 may be equal to the number of baseline bits (i.e., Q). Group of switchable bit-to-analog circuitries 576 andswitchable modulation source 575 may be coupled between a voltage source VA and a summingblock 586. In the depicted example, group of switchable bit-to-analog circuitries 576 is coupled to receive the baseline bits and provide to summing block 586 abase signal U BASE 584, which is responsive to the baseline bits. In one example, each one of switchable bit-to-analog circuitries 564 to 570 includes a current source and a switch. Each one of switchable bit-to-analog circuitries 564 to 570 of the group can be switched in response to one of the baseline bits. Therefore,base signal U BASE 584 may be representative of the total sum of currents that is provided to summing block 586 from the group. It should be noted that, in other examples, each one of switchable bit-to-analog circuitries 564 to 570 may include other known circuit components such as a resistor, a capacitor in place of a current source. In one example, summingblock 586 is a circuit node that is coupled to receive multiple currents and output a signal representative of the sum of these currents. - Furthermore, in the example modulated
DAC 540,DAC 577 is a binary weighted DAC. That is, each one ofcurrent sources 544 to 550 of the group of switchable bit-to-analog circuitries outputs a current that has a magnitude that is weighted by power of two relative to the current output by the current source of the switchable bit-to-analog circuitry that is responsive to the adjacent less-significant bit of the baseline bits. In other words, switchable bit-to-analog circuitry 564 is responsive to the least significant bit B1 andcurrent source 544 outputs a current with the lowest magnitude IB. Switchable bit-to-analog circuitry 566 is responsive to bit B2 andcurrent source 546 outputs a current that is twice as large as IB. The magnitude of the current output by each one of the current sources of the remaining switchable bit-to-analog circuitries successively doubles such thatcurrent source 550 of switchable bit-to-analog circuitry 570 responsive to the most significant bit BQ outputs a current that has magnitude 2QIB. - As further shown, switches 554 to 560 coupled to
current sources 544 to 550, respectively, can be switched in response to one of the baseline bits. Specifically, each one ofswitches 554 to 560 can be switched in response to the bit of the baseline bits to which the corresponding switchable bit-to-analog circuitry is responsive. For example, switchable bit-to-analog circuitry 564 includesswitch 554 that is coupled tocurrent source 544. Since switchable bit-to-analog circuitry 564 is responsive to the least significant bit B1 of the baseline bits, switch 554 can be switched in response to the least significant bit B1. In the depicted example, a high value for one of the digits of the baseline bits may close (i.e., enable) the respective switch to couple the corresponding current source to summingblock 586. Conversely, a low value for one of the digits of the baseline bits may open (i.e., disable) the respective switch to prevent current from its respective current source from entering summingblock 586. Therefore,base signal U BASE 584 that enters summingblock 586 is an analog signal representative of the value of the baseline bits. In the example ofFIG. 5 , a low value for one of the baseline bits is a high value for the complement of that one of the baseline bits. As illustrated, a bar over the symbol for a bit of the baseline bits represents the complement of the bit. - It should be noted that other examples of modulated
DAC 540 may have multiple switches within each one of switchable bit-to-analog circuitries to direct current fromcurrent sources 544 to 550 to other nodes for other reasons, such as for calibration. - In the
example DAC 577,switchable modulation source 575 is coupled to output a modulatedsignal U MOD 582 in response to modulationperiod signal U MDP 538.Switchable modulation source 575 includes acurrent source 542 that outputs a current that has magnitude equal to that of the current source of the switchable bit-to-analog circuitry responsive to the least significant bit B1 of the baseline bits. In other words,current source 542 outputs a current that has a magnitude of IB.Switchable modulation source 575 also includes aswitch 552 coupled tocurrent source 542. Switch 552 can be switched in response to modulationperiod signal UMP 538. In one example, when modulationperiod signal U MDP 538 is logic high,switch 552 closes (i.e., is enabled) to couplecurrent source 542 to summing block 586 and when modulationperiod signal UMP 538 is logic low,switch 552 opens (i.e., is disabled) to prevent current fromcurrent source 542 from entering summingblock 586. That is, in operation,switchable modulation source 575 may alternate modulatedsignal U MOD 582 between IB and zero in response to modulationperiod signal U MDP 538. In such cases, modulatedsignal U MOD 582 is also a periodic signal with the same period as that of modulation period signal UMDP 538 (i.e., 2P periods of clock signal UCLK 512). - As depicted in the example in
FIG. 5 , adjustsignal U ADJ 580 output by modulatedDAC 540 is the sum of currents that are received by summingblock 586, namely the sum of modulatedsignal U MOD 582 andbase signal U BASE 584. In one example, this means that adjustsignal U ADJ 580 is a periodic signal with the same period as that of modulationperiod signal U MDP 538 and modulated signal UMOD 582 (i.e., 2P periods of clock signal UCLK 512). In operation, by alternating modulatedsignal U MOD 582 between IB and zero in response to modulationperiod signal U MDP 538,switchable modulation source 575 can cause adjustsignal U ADJ 580 to alternate betweenbase signal U BASE 584 andbase signal U BASE 584 plus IB during a period of adjustsignal U ADJ 580. Because the current source of the switchable bit-to-analog circuitry that is responsive to the least significant bit of the baseline bits outputs a current that has a magnitude of IB, the difference inbase signal U BASE 584 for two adjacent values of the baseline bits is equal to IB. Therefore,base signal U BASE 584 andbase signal U BASE 584 plus IB may represent two adjacent discrete levels of adjustsignal U ADJ 580 withbase signal U BASE 564 corresponding to the lower level, which may also be referred to as the “base level.” In this case, adjustsignal U ADJ 580 is an analog signal having discrete levels that are set in response to the value of the baseline bits and the value of the modulation bits. - As previously mentioned, modulated
DAC 540 may alternate adjustsignal U ADJ 580 between two adjacent discrete levels in response to modulationperiod signal U MDP 538. Specifically, modulatedDAC 540 may set a portion of the period of adjustsignal U ADJ 580 that adjustsignal U ADJ 580 is the greater of the adjacent levels in response to modulationperiod signal U MDP 538. For example, modulatedDAC 540 may set adjustsignal U ADJ 580 to the greater level when modulationperiod signal U MDP 538 is logic high and set adjustsignal U ADJ 580 to the base level when modulationperiod signal U MDP 538 is logic low.Modulated DAC 540 may thus set the portion of the period of adjustsignal U ADJ 580 during which adjustsignal U ADJ 580 is the greater level to be equal to the modulation time. - In the depicted example, the average value of adjust
signal U ADJ 580 may over time become equal to one of several additional levels that are equally spaced between the adjacent levels of adjustsignal U ADJ 580. More particularly, by changing the modulation time between zero and (2P−1) periods ofclock signal U CLK 512 in response to the value of the modulation bits, modulatedDAC 540 may output an adjustsignal U ADJ 580 with an average value equal to one of (2P−1) equally spaced levels between any pair of adjacent levels. In this manner, modulatedDAC 540 may generate a signal at its output with the equivalent number of discrete levels and hence with the same resolution that a conventional (P+Q) bit DAC can generate. -
Modulated DAC 540 can thus reduce the area required for implementing a DAC since modulatedDAC 540 may need only Q circuit components (e.g., current sources) to achieve the same resolution as that of a (P+Q) bit DAC. Although the example modulated DAC ofFIG. 5 provides higher resolution by alternating the output between adjacent levels, in other examples, an averaging circuit such as a low pass filter, an integrator or the like can be used either in the modulated DAC or outside of the modulated DAC to generate the average value of adjustsignal U ADJ 580. - In the illustrated modulated
DAC 540,modulator 530 operates in conjunction with a binary weighted DAC to alternate the output between adjacent levels. In other cases,modulator 530 can operate in conjunction with other types of DACs (e.g., thermometer coded DAC, R−2R ladder DAC) that are appropriately modified. For example, modulatedDAC 540 may include a DAC that generates two levels for the output in response to the baseline bits. One of the levels may correspond to the value of the baseline bits and the other one of the levels may correspond to one of the adjacent values of the baseline bits. In this example, the DAC may alternate the output between the two levels in response to modulationperiod signal U MDP 538. - In some implementations, rather than generating a modulation signal that alternates between a logic high level and a logic low level, one or more signals that alternate between adjacent digital levels can be received by a DAC. For example, a multiplexer can output a digital signal that is set to a first level for a first period of time and to an adjacent second level for a second period of time within a period. The DAC can receive the digital signal at the output of the multiplexer and convert the alternating digital signal to an analog output as adjust
signal U ADJ 580. The first level may be determined, for example, based on the value of the baseline bits or the value of the digital input signal received by a modulated DAC. The first period of time and the second period of time can be determined, for example, based on the value of the modulation bits or in response to a separate signal that sets the duty cycle of modulationperiod signal U MDP 538. In this case, the multiplexer would be acting as a modulator and its output would alternate between a higher digital level and a lower digital level. In yet another implementation, rather than converting the digital signal at the output of the multiplexer to an analog output, the digital signal may be output as adjustsignal U ADJ 580. - In the
example driver circuit 156,drive signal generator 520 is coupled to receive adjustsignal U ADJ 580 and in response, outputdrive signal U DR 162.Drive signal U DR 162 may be a periodic signal that alternates between logic high and logic low. In operation, drivesignal generator 520 can set certain properties ofdrive signal U DR 162 based on adjustsignal U ADJ 580. Examples of such properties ofdrive signal U DR 162 include period, ratio of logic high to logic low in a period, etc. By setting the properties ofdrive signal U DR 162,drive signal generator 520 can set the operating condition ofpower switch S1 170. In one example, drivesignal generator 520 may include switches, capacitors, and comparators (not shown inFIG. 5 ). Drivesignal generator 520 can use the charging and discharging of those capacitors in response to adjustsignal U ADJ 580 to set one or more properties ofdrive signal U DR 162. In another example, drivesignal generator 520 can include a circuit (e.g., a digital pulse width modulation circuit) to output a rectangular signal asdrive signal U DR 162. The circuit can be coupled to receive an alternating digital signal (e.g., the digital signal at the output of the multiplexer) and configured to set one or more properties ofdrive signal U DR 162 in response to the alternating digital signal. -
FIG. 6 shows a table illustrating different values of an example digital signal received as an input signal bydriver circuit 156 and a timing diagram illustrating waveforms of various signals of modulatedDAC 540. In the illustrated example, the table includes nine rows from row A to row I where each row shows a different value of the input signal that, in one example, may be representative ofinput signal U IN 590. Specifically, the input signal includes a total of 13 bits with upper ten bits set aside as the baseline bits (i.e., Q equals ten) and lower three bits set aside as the modulation bits (i.e., P equals three). As shown, in each row of the table, the portion of the input signal corresponding to the baseline bits is separated from the portion corresponding to the modulation bits by a solid line. Further illustrated inFIG. 6 isperiodic waveform 612 with aperiod T CLK 614 and that alternates between logic high H and logic low L. In one example,waveform 612 is representative ofclock signal U CLK 512 generated byclock signal generator 510.FIG. 6 also includes a collection ofexample waveforms 620 for adjustsignal U ADJ 580. Each waveform of the collection corresponds to the input signal in the respective adjacent row of the table. - In the depicted example, since there are three bits used as modulation bits, the value of the modulation bits can be one of eight different values between zero and seven. Waveforms in
collection 620 are periodic with aperiod T ADJ 616 which is equal to eight periods of waveform 612 (i.e., eight times period Tux 614). As previously mentioned, the base level of adjustsignal U ADJ 580 is set in response to the value of baseline bits and the duty cycle of modulationperiod signal U MDP 538 is set in response to the value of the modulation bits. In the example, the input signal in row A indicates 513 for the value of the baseline bits and zero for the value of the modulation bits. In response to receiving this input signal, modulatedDAC 540 sets the base level of adjustsignal U ADJ 580 to 513IB and the duty cycle of modulationperiod signal U MDP 538 to zero. In other words, modulatedDAC 540 sets modulationperiod signal U MDP 538 to logic low for the entire period of modulationperiod signal U MDP 538. Accordingly, the corresponding waveform ofgroup 620 is constant and equal to the base level of 513IB. For rows B through I, the value of the baseline bits indicated by the respective input signal is the same and equal to 512 but the value of the modulation bits decreases from seven in row B to zero in row I. Thus, for rows B through I, the base level of adjustsignal U ADJ 580 is equal to 512IB, the greater of the adjacent levels of adjustsignal U ADJ 580 is equal to 513IB (512IB+IB) and the modulation time is equal to the value of the modulation bitstimes period Tux 614. In other words, modulationperiod signal U MDP 538 is logic high for a length of time that is equal to the value of the modulation bitstimes period Tux 614. As a result, for rows B through I, each corresponding waveform ofgroup 620 is set to the 513IB for the corresponding modulation time during eachperiod T ADJ 616. For example, in row B, the value of the modulation bits is seven, the corresponding modulation time is seventimes period T CLK 614 and the corresponding waveform ofgroup 620 is set to 513IB for seventimes period T CLK 614 during eachperiod T ADJ 616. Similarly, in row E, the value of the modulation bits is four, the corresponding modulation time is fourtimes period T CLK 614 and the corresponding waveform is set to 513IB for fourtimes period T CLK 614 during eachperiod T ADJ 616. -
FIG. 7 shows a collection of signal levels illustrating example average values for the output of the modulated DAC ofFIG. 5 . Specifically, each one of levels ofcollection 720 inFIG. 7 represents the average value of the corresponding waveform ofcollection 620 that is responsive to the input signal in the respective adjacent row of the table inFIG. 6 . In other words,FIG. 7 is an expanded view illustrating both the adjacent levels of 512IB and 513IB of adjustsignal U ADJ 580 and the additional seven (23−1) equally spaced levels between these adjacent levels. As shown, the levels ofcollection 720 that correspond to the input signals in row A and I of the table inFIG. 6 are equal to 513IB and 512IB, respectively. As the modulation time decreases from seventimes period T CLK 614 in row B to onetimes period T CLK 614 in row H, the corresponding level of collection 720 (i.e., the average value of adjust signal UADJ 580) decreases by steps of (⅛)IB. For example, the average value of the waveform ofcollection 620 corresponding to row B is (512IB+(⅞)IB), the average value of the waveform ofcollection 620 corresponding to row C is (512IB+( 6/8)IB) and so on. It should be noted that even though the example waveforms and levels inFIG. 6 andFIG. 7 only illustrate this behavior for one pair of adjacent levels of adjust signal UADJ 580 (i.e., 512IB and 513IB), the same behavior can be seen for any pair of adjacent levels. Therefore, an adjustsignal U ADJ 580 generated by using ten current sources in this manner may have the equivalent number of discrete levels and the same resolution as that of a signal generated by a 13 bit DAC that uses, for example, 13 current sources. -
FIG. 8 is a schematic circuit diagram illustrating another implementation of the driver circuit inFIG. 1A according to the teachings of the present invention.Driver circuit 156 inFIG. 8 differs fromdriver circuit 156 inFIG. 5 in thatcounter 832 is coupled to receivedrive signal U DR 162 at its UPDATE input. Consequently, the periods of modulationperiod signal U MDP 838, modulatedsignal U MOD 882 and adjustsignal U ADJ 880 are all equal to 2P times the period ofdrive signal U DR 162. In the example driver circuit, since the period ofdrive signal U DR 162 may vary in response to adjustsignal U ADJ 880, the periods of modulationperiod signal U MDP 838, modulatedsignal U MOD 882 and adjustsignal U ADJ 880 may also vary during the operation ofcontroller 150. -
FIG. 9 is a flow diagram illustrating anexample process 900 according to the teachings of the present invention for generating an analog signal having discrete levels in response to a digital signal. In the depicted example,process 900 may begin atblock 905. Atblock 910, an N bit digital signal is received as an input. Atblock 920, the base level of an output signal is set in response to upper Q bits of the input. More particularly, the base level may be proportional to the value of a digital signal represented by upper Q bits of the input. For example, Q may be chosen as ten and the digital signal represented by upper Q bits of the input may be equal to 512. In this case, the base level of the output signal may be equal to 512 times a current that has a magnitude of IB. - At
block 930, a periodic signal is generated in response to lower P bits of the input. In one example, the periodic signal has a period proportional to the number of possible values that can be represented by lower P bits of the input (i.e., 2 P). For example, when P is chosen as three, the period of the periodic signal may be eight (23) periods of a clock signal. The periodic signal may alternate between logic low and logic high during that period. Atblock 940, the duty cycle of the periodic signal (i.e., the ratio of either a logic high or logic low portion of the period of the periodic signal to the period of the periodic signal) is set in response to the value of lower P bits of the input. The duty cycle of the periodic signal times the period of the periodic signal may represent a modulation time. Thus, in one example, the portion of the period during which the periodic signal is set to logic high may be equal to the modulation time and hence, proportional to the value of lower P bits of the input. For example, the value of lower P bits of the input may be equal to five. In this case, the duty cycle of the periodic signal may be ⅝, the modulation time may be five periods of the clock signal and the periodic signal may be logic high for five of eight periods of the clock signal. - At
block 950, the output signal may be set to an adjacent level of the base level for the modulation time and to the base level for the remainder of the period of the periodic signal. In one example, the adjacent level corresponds to the greater of the two closest levels of the base level that can be generated in response to upper Q bits of the input. For example, the base level of the output signal may increase or decrease in steps of value IB in response to upper Q bits of the input. In this case, when the base level is equal to 512IB, the adjacent level becomes equal to 513IB. Consequently, the output signal may be set to 513IB for the modulation time and to 512IB for the remainder of the period of the periodic signal. - In this manner, the average value of the output signal generated by
process 900 may be equal to one of (2P−1) additional levels that are equally spaced between any pair of adjacent levels of the output signal. As such, the output signal generated by using Q current sources according toprocess 900 can achieve the same resolution as that of a signal generated by a (Q+P) bit DAC that uses (Q+P) current sources. - In one example, the illustrated process may be performed by a modulated
DAC Modulated DAC input signal U analog circuitries process block 920, the base level of an output signal (e.g., adjustsignal U ADJ 580 or 880) is set in response to upper Q bits of the digital signal. In one example, group of switchable bit-to-analog circuitries base signal U period signal U MDP 538 or 838) in response to P lower bits of the digital signal in process block 930 can be performed bymodulator modulator switchable modulation source analog circuitries switchable modulation source current source 542 or 842) to summing block 566 or 866 to provide an additional signal (e.g., modulatedsignal U MOD 582 or 882) in response to modulationperiod signal UMP switchable modulation source period signal U - The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.
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