US20150295172A1 - RRAM Cell with Bottom Electrode - Google Patents
RRAM Cell with Bottom Electrode Download PDFInfo
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- US20150295172A1 US20150295172A1 US14/252,111 US201414252111A US2015295172A1 US 20150295172 A1 US20150295172 A1 US 20150295172A1 US 201414252111 A US201414252111 A US 201414252111A US 2015295172 A1 US2015295172 A1 US 2015295172A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
-
- H01L45/1253—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H01L45/16—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- RRAM Resistive random access memory
- An RRAM cell includes a dielectric data storage layer having a variable resistance, which is placed between two electrodes disposed within back-end-of-the-line (BEOL) metallization layers.
- FIG. 1 illustrates a cross-sectional view of some embodiments of resistive random access memory (RRAM) cell having a bottom electrode with a flat top surface that provides for a low leakage current.
- RRAM resistive random access memory
- FIG. 2 illustrates a cross-sectional view of some embodiments of RRAM cell having a bottom electrode disposed within a bottom dielectric layer.
- FIG. 3 illustrates a cross-sectional view of some embodiments of RRAM cell having a bottom electrode disposed within a lower metal interconnect layer.
- FIG. 4 illustrates a flow diagram of some embodiments of a method of forming a RRAM cell having a bottom electrode comprising a flat top surface connected to a bottom surface by way of curved sidewalls.
- FIG. 5 illustrates a flow diagram of some alternative embodiments of a method of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer.
- FIGS. 6-13 illustrate cross-sectional views of some alternative embodiments showing a method of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer.
- FIG. 14 illustrates a flow diagram of some alternative embodiments of a method of forming a RRAM cell having a bottom electrode disposed within a lower metal interconnect layer.
- FIGS. 15-24 illustrate cross-sectional views of some alternative embodiments showing a method of forming a RRAM cell having a bottom electrode disposed within a lower metal interconnect layer.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Resistive random access memory (RRAM) cells have a bottom electrode that is separated from an overlying top electrode by a dielectric data storage layer having a variable resistance.
- RRAM cells are separated from an underlying metal layer by a bottom dielectric layer comprising an opening that provides for contact between the bottom electrode and the underlying metal interconnect layer.
- the bottom electrode is formed over the opening, causing the bottom electrode to have a ‘U’ shape that extends from within the opening to a position overlying the bottom dielectric layer.
- a bottom electrode having such a U shape can cause a number of problems in an RRAM cell.
- the distance between extensions of the bottom electrode overlying the bottom dielectric layer and the top electrode is relatively small and can cause to leakage currents between the bottom electrode and the top electrode, which lead to degradation of the RRAM cell.
- the top electrode is typically flanked by insulating sidewall spacers that increase a leakage path distance (i.e., a distance through which a leakage current will travel) between the top electrode and the extension of the bottom electrode.
- insulating sidewall spacers increase the height and width of the RRAM cell making integration into advanced technology nodes (e.g., 28 nm node, 20 nm node, etc.) more difficult.
- advanced technology nodes e.g., 28 nm node, 20 nm node, etc.
- the U shape can lead to micro-trenching in an underlying metal interconnect layer, which over many cycles (e.g., 10,000 cycles) can lead to RRAM failure.
- the present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode with a flat top surface that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation.
- the RRAM cell comprises a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer.
- a bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer.
- a dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom electrode and the top electrode, and thereby provides for low leakage current for the RRAM cell without using sidewall spacers that increase the size of the RRAM cell.
- FIG. 1 illustrates a cross-sectional view of a resistive random access memory (RRAM) cell 100 having a bottom electrode 102 with a flat top surface that provides for a low leakage current.
- RRAM resistive random access memory
- the RRAM cell 100 comprises a bottom electrode 102 disposed over a lower metal interconnect layer 108 surrounded by a lower inter-level dielectric (ILD) layer 110 .
- the bottom electrode 102 comprises a top surface 102 b and a bottom surface 102 a.
- the top surface 102 b may comprise a flat surface connected to the bottom surface 102 a by way of curved sidewalls 102 s (i.e., sidewalls having a slope that changes as a function of height).
- the bottom surface 102 a may also be curved, such that the sidewalls 102 s and the bottom surface 102 a form a continuous curved surface that extends between opposing sides of the top surface 102 b.
- a bottom dielectric layer 112 is disposed above the lower metal interconnect layer 108 and/or the lower inter-level dielectric (ILD) layer 110 .
- a variable resistance dielectric data storage layer 104 which is configured to store a data state depending on an applied voltage, is located over the top surface 102 b of the bottom electrode 102 and the bottom dielectric layer 112 .
- a top electrode 106 is disposed over the variable resistance dielectric data storage layer 104 .
- Placement of the variable resistance dielectric data storage layer 104 onto the bottom dielectric layer 112 provides for a relatively large leakage path distance d I (i.e., a distance through which a leakage current will travel) between the bottom electrode 102 and the top electrode 106 , thereby providing for low leakage current of the RRAM cell 100 .
- a top dielectric layer 114 is disposed over the top electrode 106 .
- the top dielectric layer 114 continuously extends from a position overlying the top electrode 106 to positions abutting sidewalls of the top electrode 106 and the variable resistance dielectric data storage layer 104 .
- the top dielectric layer 114 separates the top electrode 106 and the variable resistance dielectric data storage layer 104 from an upper inter-level dielectric (ILD) layer 120 surrounding an upper metal interconnect layer 117 having an upper metal via 116 and an upper metal wire 118 .
- ILD inter-level dielectric
- FIG. 2 illustrates a cross-sectional view of some embodiments of RRAM cell 200 having a bottom electrode 206 disposed within a bottom dielectric layer 208 .
- RRAM cell 200 comprises a bottom electrode 206 disposed onto a lower metal interconnect layer 202 surrounded by lower inter-level dielectric (ILD) layer 204 within a BEOL metallization stack.
- the lower metal interconnect layer 202 may comprise one of a plurality of metal interconnect layers disposed between the bottom electrode 206 and an underlying semiconductor substrate (not shown).
- the bottom electrode 206 comprises a flat top surface that is connected to a bottom surface by way of curved sidewalls.
- the curved sidewalls abut a surrounding bottom dielectric layer 208 .
- the flat top surface of the bottom electrode 206 and a top surface of the surrounding bottom dielectric layer 208 are aligned along a planar surface 207 .
- the bottom electrode 206 may comprise a first bottom electrode layer 206 a and a second bottom electrode layer 206 b.
- the first bottom electrode layer 206 a comprises a ‘U’ shaped layer that abuts the lower metal interconnect layer 202 and the bottom dielectric layer 208 .
- the second bottom electrode layer 206 b is nested within the opening of the ‘U’ shape of the first bottom electrode layer 206 a.
- the first and second bottom electrode layers, 206 a and 206 b, have flat top surfaces disposed along the planar surface 207 .
- a dielectric data storage layer 210 having a variable resistance is disposed onto the top surface of the bottom electrode 206 and the bottom dielectric layer 208 .
- the dielectric data storage layer 210 will undergo a reversible change between a high resistance state associated with a first data state (e.g., a ‘0’) and a low resistance state associated with a second data state (e.g., a ‘1’).
- a voltage applied to the dielectric data storage layer 210 will induce conductive paths (e.g., oxygen vacancies) to form across the dielectric data storage layer 210 , thereby reducing the resistance of the dielectric data storage layer 210 .
- the dielectric data storage layer 210 has a width that is greater than the width of the bottom electrode, so that the dielectric data storage layer 210 extends beyond the bottom electrode 206 on opposing sides.
- a capping layer 212 may be disposed over the dielectric data storage layer 210 .
- the capping layer 212 is configured to store oxygen, which can facilitate resistance changes within the dielectric data storage layer 210 .
- the capping layer 212 may comprise a metal or a metal oxide that is relatively low in oxygen concentration.
- a top electrode 214 is disposed over the capping layer 212 .
- the top electrode 214 , the capping layer 212 , and the dielectric data storage layer 210 comprise sidewalls that are laterally aligned with one another (i.e., along a vertical plane). Since the dielectric data storage layer 210 extends beyond the bottom electrode 206 on opposing sides, the top electrode 214 is separated from the bottom electrode 206 by a relatively large leakage path distance d I .
- the relatively large leakage path distance d I reduces the leakage current in the RRAM cell 200 without using sidewall spacers, thereby allowing for RRAM cell 200 to have a smaller size than RRAM cells using sidewall spacers.
- a masking layer 216 (e.g., a hard mask layer) is disposed over the top electrode 214 at positions abutting opposite sidewalls of an upper metal via 222 .
- the masking layer 216 has sidewalls 216 a that are aligned with sidewalls of the top electrode 214 .
- the masking layer 216 may comprise a silicon oxy-nitride (SiON) hard mask layer or a silicon dioxide (SiO 2 ) hard mask layer.
- the masking layer 216 may comprise a hard mask layer that is substantially devoid of oxygen.
- the masking layer 216 may comprise a silicon carbide (SiC) hard mask layer, a silicon-nitride (SiN) hard mask layer, or a composite dielectric film that is substantially devoid of oxygen.
- SiC silicon carbide
- SiN silicon-nitride
- the use of a masking layer 216 that is substantially devoid of oxygen is described in relation to the RRAM cell of FIG. 2 , it will be appreciated that the use of a masking layer 216 that is substantially devoid of oxygen is not limited to such a RRAM cell structure. Rather, the use of a masking layer 216 that is substantially devoid of oxygen may be used with any RRAM cell structure (e.g., an RRAM cell having any shape of bottom electrode, RRAM cell having bottom electrodes that extends over bottom dielectric layer 208 , etc.).
- a top dielectric layer 218 is disposed onto the masking layer 216 .
- the top dielectric layer 218 continuously extends along sidewalls of the dielectric data storage layer 210 , the capping layer 212 , the top electrode 214 , and the masking layer 216 , from a first position abutting a top surface of the masking layer 216 to a second position abutting a top surface of the bottom dielectric layer 208 .
- the top dielectric layer 218 separates the dielectric data storage layer 210 , the capping layer 212 , the top electrode 214 , and the masking layer 216 from an upper inter-level dielectric (ILD) layer 220 .
- ILD inter-level dielectric
- the upper ILD layer 220 surrounds an upper metal interconnect layer 221 disposed onto the top electrode 214 .
- the upper metal interconnect layer 221 comprises the upper metal via 222 , which extends from the top electrode 214 , through the masking layer 216 and the top dielectric layer 218 , to an upper metal wire 118 .
- FIG. 3 illustrates a cross-sectional view of some embodiments of RRAM cell 300 having a bottom electrode 304 disposed within a lower metal interconnect layer 302 .
- RRAM cell 300 comprises a bottom electrode 304 disposed within a lower metal interconnect layer 302 surrounded by lower inter-level dielectric (ILD) layer 204 .
- the bottom electrode 304 comprises a flat top surface that is connected to a curved bottom surface by way of curved sidewalls, such that the sidewalls and the bottom surface form a continuous curved surface that extends between opposing sides of the flat top surface.
- the bottom surface of the bottom electrode 304 has a convex curvature that abuts a concave top surface of the lower metal interconnect layer 302 .
- the flat top surface of the bottom electrode 304 is aligned with a top surface of the lower ILD layer 204 along a planar surface 305 .
- the bottom electrode 304 may comprise a first bottom electrode layer 304 a having a ‘U’ shaped layer that is disposed onto the lower metal interconnect layer 302 , and a second bottom electrode layer 304 b is nested within the opening of the U shape of the first bottom electrode layer 304 a.
- the first and second bottom electrode layers, 304 a and 304 b, have flat top surfaces disposed along the planar surface 305 .
- a bottom dielectric layer 306 is disposed over the lower ILD layer 204 and the bottom electrode 304 .
- the bottom dielectric layer 306 comprises an opening that provides for contact between the bottom electrode 304 and a dielectric data storage layer 308 .
- the dielectric data storage layer 308 is disposed over the opening, causing the dielectric data storage layer 308 to have a non-planar topography that extends from within the opening to a position overlying the bottom dielectric layer 306 .
- a capping layer 310 having a non-planar topography is disposed over the dielectric data storage layer 308
- a top electrode 312 having a non-planar topography is disposed over the dielectric data storage layer 308 .
- the top electrode 312 is separated from the bottom electrode 304 by a relatively large leakage path distance d I .
- the relatively large leakage path distance d I reduces the leakage current in the RRAM cell 300 without using sidewall spacers, thereby allowing for RRAM cell 300 to have a smaller size than RRAM cells using sidewall spacers.
- a masking layer 314 having a non-planar topography is disposed over the top electrode 312 .
- the masking layer 314 may comprise a hard mask layer that is substantially devoid of oxygen.
- a top dielectric layer 316 continuously extends from a first position abutting a top surface of the masking layer 314 to a second position abutting a top surface of the bottom dielectric layer 306 .
- the top dielectric layer 316 has a first side that abuts the dielectric data storage layer 308 , the capping layer 310 , the top electrode 312 , and the masking layer 314 , and a second side that abuts an upper inter-level dielectric (ILD) layer 318 .
- the upper ILD layer 318 surrounds an upper metal interconnect layer 319 comprising an upper metal via 320 configured to extend from the top electrode 312 , through the masking layer 314 and the top dielectric layer 316 , to an upper metal wire 118 .
- FIG. 4 illustrates a flow diagram of some embodiments of a method 400 of forming a RRAM cell having a bottom electrode with a flat top that provides for a low leakage current.
- a bottom electrode is formed over a lower metal interconnect layer comprised within a lower inter-level dielectric (ILD) layer.
- the bottom electrode may comprise a flat top surface connected to a bottom surface by way of curved sidewalls.
- a bottom dielectric layer is formed over the lower metal interconnect layer or the lower ILD layer.
- a dielectric data storage layer having a variable resistance is formed above the bottom dielectric layer and the bottom electrode.
- the dielectric data storage layer may be formed onto and in direct contact with the bottom dielectric layer and the bottom electrode.
- a top electrode is formed over dielectric data storage layer.
- an upper metal interconnect layer is formed over the top electrode.
- FIG. 5 illustrates a flow diagram of some embodiments of a method 500 of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer.
- a lower metal interconnect layer is formed within a lower inter-level dielectric (ILD) layer disposed over a semiconductor substrate.
- ILD inter-level dielectric
- a bottom dielectric layer is formed over the lower metal interconnect layer and/or the lower ILD layer.
- the bottom dielectric layer is selectively etched to form an opening that extends through the bottom dielectric layer to expose the lower metal interconnect layer.
- a first bottom electrode layer having curved sidewalls is formed within the opening.
- the first bottom electrode layer may comprise a first material.
- a second bottom electrode layer may be formed within the opening at a position overlying the first bottom electrode layer, in some embodiments.
- the second bottom electrode layer is nested within the first bottom electrode layer and also has curved sidewalls.
- the second bottom electrode layer may comprise a second material different than the first material.
- a planarization process is performed to remove excess material from the first bottom electrode layer and the second bottom electrode layer.
- the planarization process forms a bottom electrode having a flat top surface that is located along a plane aligned with a top surface of the bottom dielectric layer.
- a stack is formed over the bottom electrode layer and the bottom dielectric layer.
- the stack comprises a planar dielectric data storage layer, a planar capping layer disposed onto the planar dielectric data storage layer, a planar top electrode layer disposed onto the planar capping layer, and a planar masking layer disposed onto the planar top electrode.
- the stack is selectively patterned according to the planar masking layer to form a patterned stack having a dielectric data storage layer that abuts top surfaces of the bottom electrode and the bottom dielectric layer.
- a top dielectric layer is formed over the patterned stack.
- the top dielectric layer continuously extends from position abutting planar masking layer to position abutting bottom dielectric layer.
- an upper inter-level dielectric (ILD) layer is formed over the top dielectric layer.
- ILD inter-level dielectric
- an upper metal interconnect layer is formed onto the top electrode.
- the upper metal interconnect layer comprises an upper metal via formed at a position in contact with the top electrode, and an upper metal wire formed in contact with the upper metal via.
- FIGS. 6-13 illustrate some embodiments of cross-sectional views showing a method of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer.
- FIGS. 6-13 are described in relation to method 500 , it will be appreciated that the structures disclosed in FIGS. 6-13 are not limited to such a method, but instead may stand alone as structures independent of the method.
- FIG. 6 illustrates some embodiments of a cross-sectional view 600 corresponding to acts 502 - 504 .
- a lower metal interconnect layer 202 is formed within a lower inter-level dielectric (ILD) layer 204 .
- the lower metal interconnect layer 202 may be formed by selectively etching the lower ILD layer 204 (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric) to form an opening in the lower ILD layer 204 .
- a metal e.g., copper, aluminum, etc.
- a planarization process is performed to remove excess metal to form the lower metal interconnect layer 202 .
- a bottom dielectric layer 602 is formed onto the lower metal interconnect layer 202 and/or the lower ILD layer 204 .
- the bottom dielectric layer 602 may comprise silicon-nitride (SiN), silicon-carbide (SiC), or a similar composite dielectric film.
- the bottom dielectric layer 602 may be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.).
- FIG. 7 illustrates some embodiments of a cross-sectional view 700 corresponding to act 506 .
- a first masking layer 704 is formed over the bottom dielectric layer 702 .
- the bottom dielectric layer 702 is the selectively exposed to an etchant 706 (e.g., a dry etchant) in areas not covered by the first masking layer 704 .
- the etchant 706 forms an opening 708 in the bottom dielectric layer 702 , which extends through the bottom dielectric layer 702 to the lower metal interconnect layer 202 .
- the opening 708 may have curved sidewalls 702 s (i.e., sidewalls having a slope that changes as a function of height).
- FIG. 8 illustrates some embodiments of a cross-sectional view 800 corresponding to acts 508 - 510 .
- a first bottom electrode layer 802 is formed within the opening 708 .
- the first bottom electrode layer 802 extends from within the opening 708 to a position overlying the bottom dielectric layer 702 .
- the first bottom electrode layer 802 may comprise tantalum (Ta) or tantalum nitride (TaN), for example.
- a second bottom electrode layer 804 is formed within the opening at a position overlying the first bottom electrode layer 802 .
- the second bottom electrode layer 804 extends from within the opening 708 to a position overlying the bottom dielectric layer 702 .
- the second bottom electrode layer 804 may comprise titanium (Ti) or titanium nitride (TiN), for example.
- FIG. 9 illustrates some embodiments of a cross-sectional view 900 corresponding to act 512 .
- a planarization process is performed to form a flat surface along line 902 by removing excess materials from the first and second bottom electrode layers, 206 a and 206 b.
- the planarization process results in a bottom electrode 206 having a flat top surface connected to the bottom surface by way of curved sidewalls.
- the flat top surface of the bottom electrode 206 is aligned with the top surface of the bottom dielectric layer 702 .
- the planarization process may comprise a chemical mechanical polishing (CMP) process.
- FIG. 10 illustrates some embodiments of a cross-sectional view 1000 corresponding to act 514 .
- a stack 1001 is formed over the bottom electrode 206 and the bottom dielectric layer 702 .
- the stack 1001 comprises a planar dielectric data storage layer 1002 , a planar capping layer 1004 overlying the planar dielectric data storage layer 1002 , a planar top electrode layer 1006 overlying the planar capping layer 1004 , and a planar masking layer 1008 overlying the planar top electrode layer 1006 .
- the planar masking layer 1008 is configured to define a top electrode of the RRAM cell.
- the different layers of the stack 1001 may be deposited by way of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.).
- the planar dielectric data storage layer 1002 may comprise a high-k dielectric material having a variable resistance.
- the planar dielectric data storage layer 1002 may comprise hafnium oxide (HfO x ), zirconium oxide (ZrO x ), aluminum oxide (AlO x ), nickel oxide (NiO x ), tantalum oxide (TaO x ), or titanium oxide (TiO x ).
- the planar capping layer 1004 may comprise a metal such as titanium (Ti), hafnium (Hf), platinum (Pt), ruthenium (Ru), and/or aluminum (Al).
- the planar capping layer 1004 may comprise a metal oxide such as titanium oxide (TiO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), germanium oxide (GeO x ), cesium oxide (CeO x )
- the planar top electrode layer 1006 may comprise a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or a metal (e.g., titanium (Ti) or tantalum (Ta)).
- the planar masking layer 1008 may comprise an oxygen containing hard mask layer, such as silicon-oxide (SiO 2 ) or silicon-oxynitride (SiON).
- the planar masking layer 1008 may comprise a hard mask layer that is substantially devoid of oxygen, such as silicon-nitride (SiN) silicon-carbide (SiC), or a composite dielectric film that is substantially devoid of oxygen.
- FIG. 11 illustrates some embodiments of a cross-sectional view 1100 corresponding to act 516 .
- the stack 1001 is patterned according to the planar masking layer 1104 .
- the stack 1001 may be patterned to form a patterned stack 1001 ′ by selectively exposing the stack 1001 to an etchant 1102 in areas not covered by the planar masking layer 1104 .
- the patterned stack 1001 ′ has a dielectric data storage layer 210 that abuts top surfaces of the bottom electrode 206 and the bottom dielectric layer 208 .
- the etchant 1102 may comprise a dry etchant.
- a planar masking layer 1008 that is substantially devoid of oxygen can increase yield of an associated RRAM cell. This is because during patterning of the stack 1001 , the etchant 1102 may dissociate oxygen radicals from an oxygen containing masking layer (e.g., such as SiO 2 or SiON). The dissociated oxygen radicals can subsequently be implanted into the top electrode 214 , the capping layer 212 , and/or the dielectric layer 210 , where the oxygen radicals lead to device failure (e.g., disturb formation of RRAM filament and resetting the RRAM filament). Using a planar masking layer 1008 that is substantially devoid of oxygen eliminates such oxygen radicals during patterning of the stack 1001 , leading to a yield increase (e.g., of up to 30% or more).
- a yield increase e.g., of up to 30% or more.
- planar masking layer 1008 that is substantially devoid of substantially oxygen is described with relation to FIGS. 10-11 , it will be appreciated that the use of a planar masking layer 1008 that is substantially devoid of oxygen (e.g., to pattern a top electrode and/or a bottom electrode) is not limited to such a method or to such a RRAM cell structures. Rather, the use of a planar masking layer 1008 that is substantially devoid may be used with any method of RRAM formation and/or with any RRAM cell structures.
- FIG. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to acts 518 - 520 .
- a top dielectric layer 1202 is formed over patterned stack 1001 ′.
- An upper inter-level dielectric (ILD) layer 1204 is disposed over the top dielectric layer 1202 .
- the top dielectric layer 1202 has a first side that abuts the dielectric data storage layer 210 , the capping layer 212 , the top electrode 214 , and the masking layer 1104 , and a second side that abuts the upper ILD layer 1204 .
- FIG. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to act 522 .
- an upper metal interconnect layer 221 is formed at a position abutting the top electrode 214 .
- the upper metal interconnect layer 221 comprises an upper metal via 222 and an upper metal wire 118 .
- the upper metal interconnect layer 221 may be formed by etching the upper ILD layer 220 to form an opening that extends through the top dielectric layer 218 and the masking layer 216 to the top electrode 214 . The opening is then filed with a metal to form an upper metal via 222 , which extends from a top surface of the top electrode 214 to the upper metal wire 118 .
- FIG. 14 illustrates a flow diagram of some alternative embodiments of a method 1400 of forming a RRAM cell having a bottom electrode disposed within a lower metal interconnect layer.
- a metal is deposited within an opening in a lower inter-level dielectric (ILD) layer overlying a semiconductor substrate.
- ILD inter-level dielectric
- a first planarization process is performed to remove excess metal to form a lower metal interconnect layer.
- the first planarization process forms a dished recess within a top surface of the lower metal interconnect layer.
- a first bottom electrode layer is formed within the dished recess.
- the first bottom electrode layer may comprise a first material.
- a second bottom electrode layer may be formed within the dished recess at a position overlying the first bottom electrode layer, in some embodiments.
- the second bottom electrode layer is nested within the first bottom electrode layer.
- the second bottom electrode layer may comprise a second material different than the first material.
- a second planarization process is performed to remove excess material from the first bottom electrode layer and the second bottom electrode layer.
- the planarization process forms a bottom electrode having a flat top surface that is located along a plane aligned with a top surface of the lower ILD layer.
- a bottom dielectric layer is formed over the bottom electrode and/or the lower ILD layer.
- the bottom dielectric layer is selectively etched to form opening that extends through the bottom dielectric layer to expose the bottom electrode.
- a stack is formed over the opening in the bottom dielectric layer.
- the stack comprises a non-planar dielectric data storage layer, a non-planar capping layer disposed onto the non-planar dielectric data storage layer, a non-planar top electrode layer disposed onto the non-planar capping layer, and a non-planar masking layer disposed onto the non-planar top electrode.
- the stack is selectively patterned according to the non-planar masking layer to form a patterned stack having a dielectric data storage layer that abuts top surfaces of the bottom electrode and the bottom dielectric layer.
- a top dielectric layer is formed over the stack.
- the top dielectric layer continuously extends from position abutting masking non-planar layer to position abutting bottom dielectric layer.
- an upper inter-level dielectric (ILD) layer is formed over the top dielectric layer.
- ILD inter-level dielectric
- an upper metal interconnect layer is formed onto the top electrode.
- the upper metal interconnect layer comprises an upper metal via formed at a position in contact with the top electrode, and an upper metal wire formed in contact with the upper metal via.
- FIGS. 15-24 illustrate some embodiments of cross-sectional views showing a method of forming a RRAM cell disposed within a lower metal interconnect layer.
- FIGS. 15-24 are described in relation to method 1400 , it will be appreciated that the structures disclosed in FIGS. 15-24 are not limited to such a method, but instead may stand alone as structures independent of the method.
- FIG. 15 illustrates some embodiments of a cross-sectional view 1500 corresponding to act 1402 .
- a metal 1502 (e.g., copper) is deposited within an opening 1504 in a lower inter-level dielectric (ILD) layer 204 (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric).
- ILD inter-level dielectric
- the opening 1504 in the lower ILD layer 204 may be formed by selectively etching the lower ILD layer 204 .
- the metal 1502 is deposited to a thickness that causes the metal 1502 within the opening 1504 to be recessed a distance d below a top surface 203 of the lower ILD layer 204 .
- FIG. 16 illustrates some embodiments of a cross-sectional view 1600 corresponding to act 1404 .
- a first planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed to remove excess metal 1502 to form a planar surface along line 1602 .
- the first planarization process results in the formation of a lower metal interconnect layer 302 . Because the metal 1502 was recessed below the top surface 203 of the lower ILD layer 204 , the planarization process results in a dished recess 1604 having a curved bottom surface abutting a top surface of the lower metal interconnect layer 302 .
- CMP chemical mechanical polishing
- FIG. 17 illustrates some embodiments of a cross-sectional view 1700 corresponding to acts 1406 - 1408 .
- a first bottom electrode layer 1702 is formed within the dished recess 1604 .
- the first bottom electrode layer 1702 extends from within the dished recess 1604 to a position overlying the lower ILD layer 204 .
- the bottom surface of the first bottom electrode layer 1702 has a convex curvature that abuts a concave top surface of the lower metal interconnect layer 302 .
- the first bottom electrode layer 1702 may comprise a first material (e.g., Ta, TaN).
- a second bottom electrode layer 1704 is formed within the dished recess 1604 a position overlying the first bottom electrode layer 1702 .
- the second bottom electrode layer 1704 extends from within the dished recess 1604 to a position overlying the lower ILD layer 204 .
- the second bottom electrode layer 1704 may comprise a first material (e.g., Ti, TiN) different than the first material.
- FIG. 18 illustrates some embodiments of a cross-sectional view 1800 corresponding to act 1410 .
- a second planarization process (e.g., a CMP process) is performed to form a planar surface along line 1802 by removing excess materials from the first and second bottom electrode layers, 304 a and 304 b.
- the second planarization process results in a bottom electrode 304 having a flat top surface connected to the bottom surface by way of curved sidewalls.
- the flat top surface of the bottom electrode 304 is aligned with the top surface of the lower ILD layer 204 .
- FIG. 19 illustrates some embodiments of a cross-sectional view 1900 corresponding to act 1412 .
- a bottom dielectric layer 1902 is formed onto the bottom electrode 304 and the lower ILD layer 204 .
- the bottom dielectric layer 1902 may comprise a silicon nitride or a silicon carbide layer formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.).
- FIG. 20 illustrates some embodiments of a cross-sectional view 2000 corresponding to act 1414 .
- a first masking layer 2004 is formed over the bottom dielectric layer 2002 .
- the bottom dielectric layer 2002 is the selectively exposed to an etchant 2006 in areas not covered by the first masking layer 2004 .
- the etchant 2006 forms an opening 2008 in the bottom dielectric layer 2002 , which extends through the bottom dielectric layer 2002 to the bottom electrode 304 .
- the opening 2008 has curved sidewalls 2002 s.
- FIG. 21 illustrates some embodiments of a cross-sectional view 2100 corresponding to act 1416 .
- a stack 2101 is formed over the bottom electrode 304 and the bottom dielectric layer 1902 .
- the stack 2101 comprises a non-planar dielectric data storage layer 2102 having a variable resistance, a non-planar capping layer 2104 overlying the non-planar dielectric data storage layer 2102 , a non-planar top electrode layer 2106 overlying the non-planar capping layer 2104 , and a non-planar masking layer 2108 overlying the non-planar top electrode layer 2106 .
- the non-planar masking layer 2108 is configured to define a top electrode of the RRAM cell.
- the non-planar masking layer 2108 may comprise an oxygen containing hard mask layer, such as silicon-oxide (SiO 2 ) or silicon-oxynitride (SiON).
- the non-planar masking layer 2108 may comprise a material that is substantially devoid of oxygen, such as silicon-nitride (SiN), silicon-carbide (SiC) or a composite dielectric film that is substantially devoid of oxygen.
- the different layers of the stack 2101 may be deposited by way of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.).
- FIG. 22 illustrates some embodiments of a cross-sectional view 2200 corresponding to act 1418 .
- the stack 2101 is patterned according to the non-planar masking layer 2204 .
- the stack 2101 may be patterned to form a patterned stack 2101 ′ by selectively exposing the stack 2101 to an etchant 2202 in areas not covered by the non-planar masking layer 2204 .
- the patterned stack 2101 ′ has a dielectric data storage layer 308 that abuts top surfaces of the bottom electrode 304 and the bottom dielectric layer 306 .
- FIG. 23 illustrates some embodiments of a cross-sectional view 2300 corresponding to acts 1420 - 1422 .
- a top dielectric layer 2302 is formed over patterned stack 2101 ′.
- An upper inter-level dielectric (ILD) layer 2304 is disposed over the top dielectric layer 2302 .
- the top dielectric layer 2302 has a first side that abuts the dielectric data storage layer 308 , the capping layer 310 , the top electrode 312 , and the masking layer 314 , and a second side that abuts the upper ILD layer 2304 .
- FIG. 24 illustrates some embodiments of a cross-sectional view 2400 corresponding to act 1424 .
- an upper metal interconnect layer 319 is formed at a position abutting the top electrode 312 .
- the upper metal interconnect layer 319 comprises an upper metal via 320 and an upper metal wire 118 .
- the upper metal interconnect layer 319 may be formed by etching the upper ILD layer 318 to form an opening that extends through the top dielectric layer 316 and the planar masking layer 314 to the top electrode 312 . The opening is then filed to form an upper metal via 320 , which extends from a top surface of the top electrode 312 to the upper metal wire 118 .
- the present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode with a flat top that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation.
- RRAM resistive random access memory
- the present disclosure relates to a resistive random access memory (RRAM) cell.
- the RRAM cell comprises a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer, and a bottom dielectric layer disposed over the lower metal interconnect layer or the lower ILD layer.
- the RRAM cell further comprises a dielectric data storage layer having a variable resistance and a top electrode disposed over the dielectric data storage layer. A bottom surface of the dielectric data storage layer abuts top surfaces of the bottom dielectric layer and the bottom electrode.
- the present disclosure relates to a resistive random access memory (RRAM) cell.
- the RRAM cell comprises a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer.
- a bottom dielectric layer is disposed over the lower metal interconnect layer or the lower ILD layer.
- a dielectric data storage layer having a variable resistance is located over the bottom electrode, and a top electrode is disposed over the dielectric data storage layer.
- the present disclosure relates to a method of forming a resistive random access memory (RRAM) cell.
- the method comprises forming a bottom electrode over a lower metal interconnect layer comprised within a lower inter-level dielectric (ILD) layer, and forming a bottom dielectric layer over the lower metal interconnect layer or the lower ILD layer.
- the method further comprises forming a dielectric data storage layer having a variable resistance above the bottom dielectric layer and the bottom electrode, and forming a top electrode over the dielectric data storage layer.
Abstract
Description
- Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data while it is powered, while non-volatile memory is able to store data when power is removed. Resistive random access memory (RRAM) is one promising candidate for next generation non-volatile memory technology due to its simple structure and CMOS logic compatible process technology that is involved. An RRAM cell includes a dielectric data storage layer having a variable resistance, which is placed between two electrodes disposed within back-end-of-the-line (BEOL) metallization layers.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a cross-sectional view of some embodiments of resistive random access memory (RRAM) cell having a bottom electrode with a flat top surface that provides for a low leakage current. -
FIG. 2 illustrates a cross-sectional view of some embodiments of RRAM cell having a bottom electrode disposed within a bottom dielectric layer. -
FIG. 3 illustrates a cross-sectional view of some embodiments of RRAM cell having a bottom electrode disposed within a lower metal interconnect layer. -
FIG. 4 illustrates a flow diagram of some embodiments of a method of forming a RRAM cell having a bottom electrode comprising a flat top surface connected to a bottom surface by way of curved sidewalls. -
FIG. 5 illustrates a flow diagram of some alternative embodiments of a method of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer. -
FIGS. 6-13 illustrate cross-sectional views of some alternative embodiments showing a method of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer. -
FIG. 14 illustrates a flow diagram of some alternative embodiments of a method of forming a RRAM cell having a bottom electrode disposed within a lower metal interconnect layer. -
FIGS. 15-24 illustrate cross-sectional views of some alternative embodiments showing a method of forming a RRAM cell having a bottom electrode disposed within a lower metal interconnect layer. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Resistive random access memory (RRAM) cells have a bottom electrode that is separated from an overlying top electrode by a dielectric data storage layer having a variable resistance. Typically, RRAM cells are separated from an underlying metal layer by a bottom dielectric layer comprising an opening that provides for contact between the bottom electrode and the underlying metal interconnect layer. The bottom electrode is formed over the opening, causing the bottom electrode to have a ‘U’ shape that extends from within the opening to a position overlying the bottom dielectric layer.
- A bottom electrode having such a U shape can cause a number of problems in an RRAM cell. For example, the distance between extensions of the bottom electrode overlying the bottom dielectric layer and the top electrode is relatively small and can cause to leakage currents between the bottom electrode and the top electrode, which lead to degradation of the RRAM cell. To reduce leakage currents within an RRAM cell, the top electrode is typically flanked by insulating sidewall spacers that increase a leakage path distance (i.e., a distance through which a leakage current will travel) between the top electrode and the extension of the bottom electrode. However, insulating sidewall spacers increase the height and width of the RRAM cell making integration into advanced technology nodes (e.g., 28 nm node, 20 nm node, etc.) more difficult. Also, the U shape can lead to micro-trenching in an underlying metal interconnect layer, which over many cycles (e.g., 10,000 cycles) can lead to RRAM failure.
- Accordingly, the present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode with a flat top surface that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell comprises a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom electrode and the top electrode, and thereby provides for low leakage current for the RRAM cell without using sidewall spacers that increase the size of the RRAM cell.
-
FIG. 1 illustrates a cross-sectional view of a resistive random access memory (RRAM)cell 100 having abottom electrode 102 with a flat top surface that provides for a low leakage current. - The
RRAM cell 100 comprises abottom electrode 102 disposed over a lowermetal interconnect layer 108 surrounded by a lower inter-level dielectric (ILD)layer 110. Thebottom electrode 102 comprises atop surface 102 b and abottom surface 102 a. In some embodiments, thetop surface 102 b may comprise a flat surface connected to thebottom surface 102 a by way ofcurved sidewalls 102 s (i.e., sidewalls having a slope that changes as a function of height). In some embodiments, thebottom surface 102 a may also be curved, such that thesidewalls 102 s and thebottom surface 102 a form a continuous curved surface that extends between opposing sides of thetop surface 102 b. - A bottom
dielectric layer 112 is disposed above the lowermetal interconnect layer 108 and/or the lower inter-level dielectric (ILD)layer 110. A variable resistance dielectricdata storage layer 104, which is configured to store a data state depending on an applied voltage, is located over thetop surface 102 b of thebottom electrode 102 and the bottomdielectric layer 112. Atop electrode 106 is disposed over the variable resistance dielectricdata storage layer 104. Placement of the variable resistance dielectricdata storage layer 104 onto the bottomdielectric layer 112 provides for a relatively large leakage path distance dI (i.e., a distance through which a leakage current will travel) between thebottom electrode 102 and thetop electrode 106, thereby providing for low leakage current of theRRAM cell 100. - In some embodiments, a top
dielectric layer 114 is disposed over thetop electrode 106. The topdielectric layer 114 continuously extends from a position overlying thetop electrode 106 to positions abutting sidewalls of thetop electrode 106 and the variable resistance dielectricdata storage layer 104. The topdielectric layer 114 separates thetop electrode 106 and the variable resistance dielectricdata storage layer 104 from an upper inter-level dielectric (ILD)layer 120 surrounding an upper metal interconnect layer 117 having an upper metal via 116 and anupper metal wire 118. -
FIG. 2 illustrates a cross-sectional view of some embodiments ofRRAM cell 200 having abottom electrode 206 disposed within a bottomdielectric layer 208. -
RRAM cell 200 comprises abottom electrode 206 disposed onto a lowermetal interconnect layer 202 surrounded by lower inter-level dielectric (ILD)layer 204 within a BEOL metallization stack. In some embodiments, the lowermetal interconnect layer 202 may comprise one of a plurality of metal interconnect layers disposed between thebottom electrode 206 and an underlying semiconductor substrate (not shown). - The
bottom electrode 206 comprises a flat top surface that is connected to a bottom surface by way of curved sidewalls. The curved sidewalls abut a surrounding bottomdielectric layer 208. The flat top surface of thebottom electrode 206 and a top surface of the surrounding bottomdielectric layer 208 are aligned along aplanar surface 207. In some embodiments, thebottom electrode 206 may comprise a firstbottom electrode layer 206 a and a secondbottom electrode layer 206 b. The firstbottom electrode layer 206 a comprises a ‘U’ shaped layer that abuts the lowermetal interconnect layer 202 and the bottomdielectric layer 208. The secondbottom electrode layer 206 b is nested within the opening of the ‘U’ shape of the firstbottom electrode layer 206 a. The first and second bottom electrode layers, 206 a and 206 b, have flat top surfaces disposed along theplanar surface 207. - A dielectric
data storage layer 210 having a variable resistance is disposed onto the top surface of thebottom electrode 206 and the bottomdielectric layer 208. Depending on an applied voltage, the dielectricdata storage layer 210 will undergo a reversible change between a high resistance state associated with a first data state (e.g., a ‘0’) and a low resistance state associated with a second data state (e.g., a ‘1’). For example, a voltage applied to the dielectricdata storage layer 210 will induce conductive paths (e.g., oxygen vacancies) to form across the dielectricdata storage layer 210, thereby reducing the resistance of the dielectricdata storage layer 210. The dielectricdata storage layer 210 has a width that is greater than the width of the bottom electrode, so that the dielectricdata storage layer 210 extends beyond thebottom electrode 206 on opposing sides. - In some embodiments, a
capping layer 212 may be disposed over the dielectricdata storage layer 210. Thecapping layer 212 is configured to store oxygen, which can facilitate resistance changes within the dielectricdata storage layer 210. In some embodiments, thecapping layer 212 may comprise a metal or a metal oxide that is relatively low in oxygen concentration. - A
top electrode 214 is disposed over thecapping layer 212. Thetop electrode 214, thecapping layer 212, and the dielectricdata storage layer 210 comprise sidewalls that are laterally aligned with one another (i.e., along a vertical plane). Since the dielectricdata storage layer 210 extends beyond thebottom electrode 206 on opposing sides, thetop electrode 214 is separated from thebottom electrode 206 by a relatively large leakage path distance dI. The relatively large leakage path distance dI reduces the leakage current in theRRAM cell 200 without using sidewall spacers, thereby allowing forRRAM cell 200 to have a smaller size than RRAM cells using sidewall spacers. - A masking layer 216 (e.g., a hard mask layer) is disposed over the
top electrode 214 at positions abutting opposite sidewalls of an upper metal via 222. Themasking layer 216 has sidewalls 216 a that are aligned with sidewalls of thetop electrode 214. In some embodiments, themasking layer 216 may comprise a silicon oxy-nitride (SiON) hard mask layer or a silicon dioxide (SiO2) hard mask layer. In other embodiments, themasking layer 216 may comprise a hard mask layer that is substantially devoid of oxygen. For example, themasking layer 216 may comprise a silicon carbide (SiC) hard mask layer, a silicon-nitride (SiN) hard mask layer, or a composite dielectric film that is substantially devoid of oxygen. Although the use of amasking layer 216 that is substantially devoid of oxygen is described in relation to the RRAM cell ofFIG. 2 , it will be appreciated that the use of amasking layer 216 that is substantially devoid of oxygen is not limited to such a RRAM cell structure. Rather, the use of amasking layer 216 that is substantially devoid of oxygen may be used with any RRAM cell structure (e.g., an RRAM cell having any shape of bottom electrode, RRAM cell having bottom electrodes that extends overbottom dielectric layer 208, etc.). - A
top dielectric layer 218 is disposed onto themasking layer 216. Thetop dielectric layer 218 continuously extends along sidewalls of the dielectricdata storage layer 210, thecapping layer 212, thetop electrode 214, and themasking layer 216, from a first position abutting a top surface of themasking layer 216 to a second position abutting a top surface of thebottom dielectric layer 208. Thetop dielectric layer 218 separates the dielectricdata storage layer 210, thecapping layer 212, thetop electrode 214, and themasking layer 216 from an upper inter-level dielectric (ILD)layer 220. Theupper ILD layer 220 surrounds an uppermetal interconnect layer 221 disposed onto thetop electrode 214. The uppermetal interconnect layer 221 comprises the upper metal via 222, which extends from thetop electrode 214, through themasking layer 216 and thetop dielectric layer 218, to anupper metal wire 118. -
FIG. 3 illustrates a cross-sectional view of some embodiments ofRRAM cell 300 having abottom electrode 304 disposed within a lowermetal interconnect layer 302. -
RRAM cell 300 comprises abottom electrode 304 disposed within a lowermetal interconnect layer 302 surrounded by lower inter-level dielectric (ILD)layer 204. Thebottom electrode 304 comprises a flat top surface that is connected to a curved bottom surface by way of curved sidewalls, such that the sidewalls and the bottom surface form a continuous curved surface that extends between opposing sides of the flat top surface. The bottom surface of thebottom electrode 304 has a convex curvature that abuts a concave top surface of the lowermetal interconnect layer 302. The flat top surface of thebottom electrode 304 is aligned with a top surface of thelower ILD layer 204 along aplanar surface 305. In some embodiments, thebottom electrode 304 may comprise a firstbottom electrode layer 304 a having a ‘U’ shaped layer that is disposed onto the lowermetal interconnect layer 302, and a secondbottom electrode layer 304 b is nested within the opening of the U shape of the firstbottom electrode layer 304 a. The first and second bottom electrode layers, 304 a and 304 b, have flat top surfaces disposed along theplanar surface 305. - A
bottom dielectric layer 306 is disposed over thelower ILD layer 204 and thebottom electrode 304. Thebottom dielectric layer 306 comprises an opening that provides for contact between thebottom electrode 304 and a dielectricdata storage layer 308. The dielectricdata storage layer 308 is disposed over the opening, causing the dielectricdata storage layer 308 to have a non-planar topography that extends from within the opening to a position overlying thebottom dielectric layer 306. Acapping layer 310 having a non-planar topography is disposed over the dielectricdata storage layer 308, and atop electrode 312 having a non-planar topography is disposed over the dielectricdata storage layer 308. Since thebottom dielectric layer 306 is disposed between thetop electrode 312 and thebottom electrode 304, thetop electrode 312 is separated from thebottom electrode 304 by a relatively large leakage path distance dI. The relatively large leakage path distance dI reduces the leakage current in theRRAM cell 300 without using sidewall spacers, thereby allowing forRRAM cell 300 to have a smaller size than RRAM cells using sidewall spacers. - A
masking layer 314 having a non-planar topography is disposed over thetop electrode 312. In some embodiments, themasking layer 314 may comprise a hard mask layer that is substantially devoid of oxygen. Atop dielectric layer 316 continuously extends from a first position abutting a top surface of themasking layer 314 to a second position abutting a top surface of thebottom dielectric layer 306. Thetop dielectric layer 316 has a first side that abuts the dielectricdata storage layer 308, thecapping layer 310, thetop electrode 312, and themasking layer 314, and a second side that abuts an upper inter-level dielectric (ILD)layer 318. Theupper ILD layer 318 surrounds an uppermetal interconnect layer 319 comprising an upper metal via 320 configured to extend from thetop electrode 312, through themasking layer 314 and thetop dielectric layer 316, to anupper metal wire 118. -
FIG. 4 illustrates a flow diagram of some embodiments of amethod 400 of forming a RRAM cell having a bottom electrode with a flat top that provides for a low leakage current. - At 402, a bottom electrode is formed over a lower metal interconnect layer comprised within a lower inter-level dielectric (ILD) layer. In some embodiments, the bottom electrode may comprise a flat top surface connected to a bottom surface by way of curved sidewalls.
- At 404, a bottom dielectric layer is formed over the lower metal interconnect layer or the lower ILD layer.
- At 406, a dielectric data storage layer having a variable resistance is formed above the bottom dielectric layer and the bottom electrode. In some embodiments, the dielectric data storage layer may be formed onto and in direct contact with the bottom dielectric layer and the bottom electrode.
- At 408, a top electrode is formed over dielectric data storage layer.
- At 410, an upper metal interconnect layer is formed over the top electrode.
-
FIG. 5 illustrates a flow diagram of some embodiments of amethod 500 of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer. - While disclosed methods (e.g.,
methods - At 502, a lower metal interconnect layer is formed within a lower inter-level dielectric (ILD) layer disposed over a semiconductor substrate.
- At 504, a bottom dielectric layer is formed over the lower metal interconnect layer and/or the lower ILD layer.
- At 506, the bottom dielectric layer is selectively etched to form an opening that extends through the bottom dielectric layer to expose the lower metal interconnect layer.
- At 508, a first bottom electrode layer having curved sidewalls is formed within the opening. In some embodiments, the first bottom electrode layer may comprise a first material.
- At 510, a second bottom electrode layer may be formed within the opening at a position overlying the first bottom electrode layer, in some embodiments. The second bottom electrode layer is nested within the first bottom electrode layer and also has curved sidewalls. In some embodiments, the second bottom electrode layer may comprise a second material different than the first material.
- At 512, a planarization process is performed to remove excess material from the first bottom electrode layer and the second bottom electrode layer. The planarization process forms a bottom electrode having a flat top surface that is located along a plane aligned with a top surface of the bottom dielectric layer.
- At 514, a stack is formed over the bottom electrode layer and the bottom dielectric layer. The stack comprises a planar dielectric data storage layer, a planar capping layer disposed onto the planar dielectric data storage layer, a planar top electrode layer disposed onto the planar capping layer, and a planar masking layer disposed onto the planar top electrode.
- At 516, the stack is selectively patterned according to the planar masking layer to form a patterned stack having a dielectric data storage layer that abuts top surfaces of the bottom electrode and the bottom dielectric layer.
- At 518, a top dielectric layer is formed over the patterned stack. The top dielectric layer continuously extends from position abutting planar masking layer to position abutting bottom dielectric layer.
- At 520, an upper inter-level dielectric (ILD) layer is formed over the top dielectric layer.
- At 522, an upper metal interconnect layer is formed onto the top electrode. The upper metal interconnect layer comprises an upper metal via formed at a position in contact with the top electrode, and an upper metal wire formed in contact with the upper metal via.
-
FIGS. 6-13 illustrate some embodiments of cross-sectional views showing a method of forming a RRAM cell having a bottom electrode disposed within a bottom dielectric layer. AlthoughFIGS. 6-13 are described in relation tomethod 500, it will be appreciated that the structures disclosed inFIGS. 6-13 are not limited to such a method, but instead may stand alone as structures independent of the method. -
FIG. 6 illustrates some embodiments of across-sectional view 600 corresponding to acts 502-504. - As shown in
cross-sectional view 600, a lowermetal interconnect layer 202 is formed within a lower inter-level dielectric (ILD)layer 204. In some embodiments, the lowermetal interconnect layer 202 may be formed by selectively etching the lower ILD layer 204 (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric) to form an opening in thelower ILD layer 204. A metal (e.g., copper, aluminum, etc.) is then deposited to fill the opening, and a planarization process is performed to remove excess metal to form the lowermetal interconnect layer 202. - A bottom dielectric layer 602 is formed onto the lower
metal interconnect layer 202 and/or thelower ILD layer 204. In some embodiments, the bottom dielectric layer 602 may comprise silicon-nitride (SiN), silicon-carbide (SiC), or a similar composite dielectric film. In some embodiments, the bottom dielectric layer 602 may be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.). -
FIG. 7 illustrates some embodiments of across-sectional view 700 corresponding to act 506. - As shown in
cross-sectional view 700, afirst masking layer 704 is formed over thebottom dielectric layer 702. Thebottom dielectric layer 702 is the selectively exposed to an etchant 706 (e.g., a dry etchant) in areas not covered by thefirst masking layer 704. Theetchant 706 forms anopening 708 in thebottom dielectric layer 702, which extends through thebottom dielectric layer 702 to the lowermetal interconnect layer 202. Theopening 708 may havecurved sidewalls 702 s (i.e., sidewalls having a slope that changes as a function of height). -
FIG. 8 illustrates some embodiments of across-sectional view 800 corresponding to acts 508-510. - As shown in
cross-sectional view 700, a firstbottom electrode layer 802 is formed within theopening 708. The firstbottom electrode layer 802 extends from within theopening 708 to a position overlying thebottom dielectric layer 702. In some embodiments, the firstbottom electrode layer 802 may comprise tantalum (Ta) or tantalum nitride (TaN), for example. A secondbottom electrode layer 804 is formed within the opening at a position overlying the firstbottom electrode layer 802. The secondbottom electrode layer 804 extends from within theopening 708 to a position overlying thebottom dielectric layer 702. In some embodiments, the secondbottom electrode layer 804 may comprise titanium (Ti) or titanium nitride (TiN), for example. -
FIG. 9 illustrates some embodiments of across-sectional view 900 corresponding to act 512. - As shown in
cross-sectional view 900, a planarization process is performed to form a flat surface alongline 902 by removing excess materials from the first and second bottom electrode layers, 206 a and 206 b. The planarization process results in abottom electrode 206 having a flat top surface connected to the bottom surface by way of curved sidewalls. The flat top surface of thebottom electrode 206 is aligned with the top surface of thebottom dielectric layer 702. In some embodiments, the planarization process may comprise a chemical mechanical polishing (CMP) process. -
FIG. 10 illustrates some embodiments of across-sectional view 1000 corresponding to act 514. - As shown in
cross-sectional view 1000, astack 1001 is formed over thebottom electrode 206 and thebottom dielectric layer 702. Thestack 1001 comprises a planar dielectric data storage layer 1002, a planar capping layer 1004 overlying the planar dielectric data storage layer 1002, a planartop electrode layer 1006 overlying the planar capping layer 1004, and aplanar masking layer 1008 overlying the planartop electrode layer 1006. Theplanar masking layer 1008 is configured to define a top electrode of the RRAM cell. In some embodiments, the different layers of thestack 1001 may be deposited by way of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.). - In some embodiments, the planar dielectric data storage layer 1002 may comprise a high-k dielectric material having a variable resistance. For example, in some embodiments, the planar dielectric data storage layer 1002 may comprise hafnium oxide (HfOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), nickel oxide (NiOx), tantalum oxide (TaOx), or titanium oxide (TiOx). In some embodiments, the planar capping layer 1004 may comprise a metal such as titanium (Ti), hafnium (Hf), platinum (Pt), ruthenium (Ru), and/or aluminum (Al). In other embodiments, the planar capping layer 1004 may comprise a metal oxide such as titanium oxide (TiOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), germanium oxide (GeOx), cesium oxide (CeOx) In various embodiments, the planar
top electrode layer 1006 may comprise a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or a metal (e.g., titanium (Ti) or tantalum (Ta)). In some embodiments, theplanar masking layer 1008 may comprise an oxygen containing hard mask layer, such as silicon-oxide (SiO2) or silicon-oxynitride (SiON). In other embodiments, theplanar masking layer 1008 may comprise a hard mask layer that is substantially devoid of oxygen, such as silicon-nitride (SiN) silicon-carbide (SiC), or a composite dielectric film that is substantially devoid of oxygen. -
FIG. 11 illustrates some embodiments of across-sectional view 1100 corresponding to act 516. - As shown in
cross-sectional view 1100, thestack 1001 is patterned according to theplanar masking layer 1104. Thestack 1001 may be patterned to form apatterned stack 1001′ by selectively exposing thestack 1001 to an etchant 1102 in areas not covered by theplanar masking layer 1104. The patternedstack 1001′ has a dielectricdata storage layer 210 that abuts top surfaces of thebottom electrode 206 and thebottom dielectric layer 208. In some embodiments, the etchant 1102 may comprise a dry etchant. - It has been appreciated that using a
planar masking layer 1008 that is substantially devoid of oxygen can increase yield of an associated RRAM cell. This is because during patterning of thestack 1001, the etchant 1102 may dissociate oxygen radicals from an oxygen containing masking layer (e.g., such as SiO2 or SiON). The dissociated oxygen radicals can subsequently be implanted into thetop electrode 214, thecapping layer 212, and/or thedielectric layer 210, where the oxygen radicals lead to device failure (e.g., disturb formation of RRAM filament and resetting the RRAM filament). Using aplanar masking layer 1008 that is substantially devoid of oxygen eliminates such oxygen radicals during patterning of thestack 1001, leading to a yield increase (e.g., of up to 30% or more). - Although, the use of a
planar masking layer 1008 that is substantially devoid of substantially oxygen is described with relation toFIGS. 10-11 , it will be appreciated that the use of aplanar masking layer 1008 that is substantially devoid of oxygen (e.g., to pattern a top electrode and/or a bottom electrode) is not limited to such a method or to such a RRAM cell structures. Rather, the use of aplanar masking layer 1008 that is substantially devoid may be used with any method of RRAM formation and/or with any RRAM cell structures. -
FIG. 12 illustrates some embodiments of across-sectional view 1200 corresponding to acts 518-520. - As shown in
cross-sectional view 1200, atop dielectric layer 1202 is formed over patternedstack 1001′. An upper inter-level dielectric (ILD)layer 1204 is disposed over thetop dielectric layer 1202. Thetop dielectric layer 1202 has a first side that abuts the dielectricdata storage layer 210, thecapping layer 212, thetop electrode 214, and themasking layer 1104, and a second side that abuts theupper ILD layer 1204. -
FIG. 13 illustrates some embodiments of across-sectional view 1300 corresponding to act 522. - As shown in
cross-sectional view 1300, an uppermetal interconnect layer 221 is formed at a position abutting thetop electrode 214. In some embodiments, the uppermetal interconnect layer 221 comprises an upper metal via 222 and anupper metal wire 118. In some embodiments, the uppermetal interconnect layer 221 may be formed by etching theupper ILD layer 220 to form an opening that extends through thetop dielectric layer 218 and themasking layer 216 to thetop electrode 214. The opening is then filed with a metal to form an upper metal via 222, which extends from a top surface of thetop electrode 214 to theupper metal wire 118. -
FIG. 14 illustrates a flow diagram of some alternative embodiments of amethod 1400 of forming a RRAM cell having a bottom electrode disposed within a lower metal interconnect layer. - At 1402, a metal is deposited within an opening in a lower inter-level dielectric (ILD) layer overlying a semiconductor substrate.
- At 1404, a first planarization process is performed to remove excess metal to form a lower metal interconnect layer. The first planarization process forms a dished recess within a top surface of the lower metal interconnect layer.
- At 1406, a first bottom electrode layer is formed within the dished recess. In some embodiments, the first bottom electrode layer may comprise a first material.
- At 1408, a second bottom electrode layer may be formed within the dished recess at a position overlying the first bottom electrode layer, in some embodiments. The second bottom electrode layer is nested within the first bottom electrode layer. In some embodiments, the second bottom electrode layer may comprise a second material different than the first material.
- At 1410, a second planarization process is performed to remove excess material from the first bottom electrode layer and the second bottom electrode layer. The planarization process forms a bottom electrode having a flat top surface that is located along a plane aligned with a top surface of the lower ILD layer.
- At 1412, a bottom dielectric layer is formed over the bottom electrode and/or the lower ILD layer.
- At 1414, the bottom dielectric layer is selectively etched to form opening that extends through the bottom dielectric layer to expose the bottom electrode.
- At 1416, a stack is formed over the opening in the bottom dielectric layer. The stack comprises a non-planar dielectric data storage layer, a non-planar capping layer disposed onto the non-planar dielectric data storage layer, a non-planar top electrode layer disposed onto the non-planar capping layer, and a non-planar masking layer disposed onto the non-planar top electrode.
- At 1418, the stack is selectively patterned according to the non-planar masking layer to form a patterned stack having a dielectric data storage layer that abuts top surfaces of the bottom electrode and the bottom dielectric layer.
- At 1420, a top dielectric layer is formed over the stack. The top dielectric layer continuously extends from position abutting masking non-planar layer to position abutting bottom dielectric layer.
- At 1422, an upper inter-level dielectric (ILD) layer is formed over the top dielectric layer.
- At 1424, an upper metal interconnect layer is formed onto the top electrode. The upper metal interconnect layer comprises an upper metal via formed at a position in contact with the top electrode, and an upper metal wire formed in contact with the upper metal via.
-
FIGS. 15-24 illustrate some embodiments of cross-sectional views showing a method of forming a RRAM cell disposed within a lower metal interconnect layer. AlthoughFIGS. 15-24 are described in relation tomethod 1400, it will be appreciated that the structures disclosed inFIGS. 15-24 are not limited to such a method, but instead may stand alone as structures independent of the method. -
FIG. 15 illustrates some embodiments of a cross-sectional view 1500 corresponding to act 1402. - As shown in cross-sectional view 1500, a metal 1502 (e.g., copper) is deposited within an opening 1504 in a lower inter-level dielectric (ILD) layer 204 (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric). The opening 1504 in the
lower ILD layer 204 may be formed by selectively etching thelower ILD layer 204. The metal 1502 is deposited to a thickness that causes the metal 1502 within the opening 1504 to be recessed a distance d below a top surface 203 of thelower ILD layer 204. -
FIG. 16 illustrates some embodiments of a cross-sectional view 1600 corresponding to act 1404. - As shown in cross-sectional view 1600, a first planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed to remove excess metal 1502 to form a planar surface along line 1602. The first planarization process results in the formation of a lower
metal interconnect layer 302. Because the metal 1502 was recessed below the top surface 203 of thelower ILD layer 204, the planarization process results in a dished recess 1604 having a curved bottom surface abutting a top surface of the lowermetal interconnect layer 302. -
FIG. 17 illustrates some embodiments of a cross-sectional view 1700 corresponding to acts 1406-1408. - As shown in
cross-sectional view 700, a first bottom electrode layer 1702 is formed within the dished recess 1604. The first bottom electrode layer 1702 extends from within the dished recess 1604 to a position overlying thelower ILD layer 204. The bottom surface of the first bottom electrode layer 1702 has a convex curvature that abuts a concave top surface of the lowermetal interconnect layer 302. In some embodiments, the first bottom electrode layer 1702 may comprise a first material (e.g., Ta, TaN). A second bottom electrode layer 1704 is formed within the dished recess 1604 a position overlying the first bottom electrode layer 1702. The second bottom electrode layer 1704 extends from within the dished recess 1604 to a position overlying thelower ILD layer 204. In some embodiments, the second bottom electrode layer 1704 may comprise a first material (e.g., Ti, TiN) different than the first material. -
FIG. 18 illustrates some embodiments of across-sectional view 1800 corresponding to act 1410. - As shown in
cross-sectional view 1800, a second planarization process (e.g., a CMP process) is performed to form a planar surface alongline 1802 by removing excess materials from the first and second bottom electrode layers, 304 a and 304 b. The second planarization process results in abottom electrode 304 having a flat top surface connected to the bottom surface by way of curved sidewalls. The flat top surface of thebottom electrode 304 is aligned with the top surface of thelower ILD layer 204. -
FIG. 19 illustrates some embodiments of across-sectional view 1900 corresponding to act 1412. - As shown in
cross-sectional view 900, abottom dielectric layer 1902 is formed onto thebottom electrode 304 and thelower ILD layer 204. In some embodiments, thebottom dielectric layer 1902 may comprise a silicon nitride or a silicon carbide layer formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.). -
FIG. 20 illustrates some embodiments of across-sectional view 2000 corresponding to act 1414. - As shown in
cross-sectional view 2000, afirst masking layer 2004 is formed over thebottom dielectric layer 2002. Thebottom dielectric layer 2002 is the selectively exposed to anetchant 2006 in areas not covered by thefirst masking layer 2004. Theetchant 2006 forms anopening 2008 in thebottom dielectric layer 2002, which extends through thebottom dielectric layer 2002 to thebottom electrode 304. Theopening 2008 hascurved sidewalls 2002 s. -
FIG. 21 illustrates some embodiments of across-sectional view 2100 corresponding to act 1416. - As shown in
cross-sectional view 2100, astack 2101 is formed over thebottom electrode 304 and thebottom dielectric layer 1902. Thestack 2101 comprises a non-planar dielectricdata storage layer 2102 having a variable resistance, anon-planar capping layer 2104 overlying the non-planar dielectricdata storage layer 2102, a non-planartop electrode layer 2106 overlying thenon-planar capping layer 2104, and anon-planar masking layer 2108 overlying the non-planartop electrode layer 2106. Thenon-planar masking layer 2108 is configured to define a top electrode of the RRAM cell. In some embodiments, thenon-planar masking layer 2108 may comprise an oxygen containing hard mask layer, such as silicon-oxide (SiO2) or silicon-oxynitride (SiON). In other embodiments, thenon-planar masking layer 2108 may comprise a material that is substantially devoid of oxygen, such as silicon-nitride (SiN), silicon-carbide (SiC) or a composite dielectric film that is substantially devoid of oxygen. In some embodiments, the different layers of thestack 2101 may be deposited by way of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.). -
FIG. 22 illustrates some embodiments of across-sectional view 2200 corresponding to act 1418. - As shown in
cross-sectional view 2200, thestack 2101 is patterned according to thenon-planar masking layer 2204. Thestack 2101 may be patterned to form apatterned stack 2101′ by selectively exposing thestack 2101 to anetchant 2202 in areas not covered by thenon-planar masking layer 2204. The patternedstack 2101′ has a dielectricdata storage layer 308 that abuts top surfaces of thebottom electrode 304 and thebottom dielectric layer 306. -
FIG. 23 illustrates some embodiments of across-sectional view 2300 corresponding to acts 1420-1422. - As shown in
cross-sectional view 2300, atop dielectric layer 2302 is formed over patternedstack 2101′. An upper inter-level dielectric (ILD)layer 2304 is disposed over thetop dielectric layer 2302. Thetop dielectric layer 2302 has a first side that abuts the dielectricdata storage layer 308, thecapping layer 310, thetop electrode 312, and themasking layer 314, and a second side that abuts theupper ILD layer 2304. -
FIG. 24 illustrates some embodiments of across-sectional view 2400 corresponding to act 1424. - As shown in
cross-sectional view 2400, an uppermetal interconnect layer 319 is formed at a position abutting thetop electrode 312. In some embodiments, the uppermetal interconnect layer 319 comprises an upper metal via 320 and anupper metal wire 118. In some embodiments, the uppermetal interconnect layer 319 may be formed by etching theupper ILD layer 318 to form an opening that extends through thetop dielectric layer 316 and theplanar masking layer 314 to thetop electrode 312. The opening is then filed to form an upper metal via 320, which extends from a top surface of thetop electrode 312 to theupper metal wire 118. - Therefore, the present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode with a flat top that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation.
- In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) cell. The RRAM cell comprises a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer, and a bottom dielectric layer disposed over the lower metal interconnect layer or the lower ILD layer. The RRAM cell further comprises a dielectric data storage layer having a variable resistance and a top electrode disposed over the dielectric data storage layer. A bottom surface of the dielectric data storage layer abuts top surfaces of the bottom dielectric layer and the bottom electrode.
- In other embodiments, the present disclosure relates to a resistive random access memory (RRAM) cell. The RRAM cell comprises a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer or the lower ILD layer. A dielectric data storage layer having a variable resistance is located over the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. A masking layer that is substantially devoid of oxygen disposed over the top electrode. The masking layer has sidewalls that are vertically aligned with sidewalls of the top electrode.
- In yet other embodiments, the present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method comprises forming a bottom electrode over a lower metal interconnect layer comprised within a lower inter-level dielectric (ILD) layer, and forming a bottom dielectric layer over the lower metal interconnect layer or the lower ILD layer. The method further comprises forming a dielectric data storage layer having a variable resistance above the bottom dielectric layer and the bottom electrode, and forming a top electrode over the dielectric data storage layer.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (23)
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