US20150287595A1 - Devices and methods of forming fins at tight fin pitches - Google Patents
Devices and methods of forming fins at tight fin pitches Download PDFInfo
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- US20150287595A1 US20150287595A1 US14/725,430 US201514725430A US2015287595A1 US 20150287595 A1 US20150287595 A1 US 20150287595A1 US 201514725430 A US201514725430 A US 201514725430A US 2015287595 A1 US2015287595 A1 US 2015287595A1
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- 239000011295 pitch Substances 0.000 title abstract description 13
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Definitions
- the fin hard masks are tall relative to the ever decreasing fin pitch, which was previously between 48 nm and 60 nm, is currently between 36 nm and 42 nm, and is moving towards sub-30 nm, while the fin width is not scaling at the same rate, and fundamentally cannot scale below 8-10 nm during patterning. If the hard masks are scaled, material selectivity between the oxide, nitride, and silicon may occur. In addition, the current height of the hard masks may result in pullback during hard mask removal. Thus, a thinner hard mask is needed to prevent pullback and improve the fin cut accuracy.
- the currently used nitride hard mask material has a fundamental etch selectivity limitation between the poly, oxide, and nitride preventing it from being used as a hard mask in a thinner layer.
- a method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material.
- the intermediate semiconductor device including, for instance, a substrate with at least one n-well region and at least one p-well region.
- FIG. 1 depicts one embodiment of a process for fabricating, for instance, FinFET devices with tight fin pitches, in accordance with one or more aspects of the present invention
- FIG. 2 depicts another embodiment of a process for fabricating, for instance, FinFET devices with tight fin pitches, in accordance with one or more aspects of the present invention
- FIG. 3 depicts a cross section of a portion of one embodiment of an intermediate structure of a semiconductor device with an n-well region and a p-well region formed in a substrate, in accordance with one or more aspects of the present invention
- FIG. 4 depicts a cross section of a portion of the intermediate structure of FIG. 3 after formation of a doped layer, an epi layer, an oxide layer, a dielectric material, and a sacrificial lithography stack, in accordance with one or more aspects of the present invention
- FIG. 5 depicts a cross section of a portion of the intermediate structure of FIG. 4 after etching of the sacrificial lithography stack and application of a spacer material, in accordance with one or more aspects of the present invention
- FIG. 7 depicts a cross section of a portion of the intermediate structure of FIG. 6 after removal of the sacrificial mandrel material between the spacers, in accordance with one or more aspects of the present invention
- FIG. 8 depicts a cross section of a portion of the intermediate structure of FIG. 7 after etching of the dielectric layer, in accordance with one or more aspects of the present invention
- FIG. 9 depicts a cross section of a portion of the intermediate structure of FIG. 8 after removal of the spacers, in accordance with one or more aspects of the present invention.
- FIG. 10 depicts a cross section of a portion of another embodiment of an intermediate structure of FIG. 3 after formation of a doped layer, an epi layer, a first oxide layer, a dielectric material, a second oxide layer, and a sacrificial lithography stack, in accordance with one or more aspects of the present invention
- FIG. 11 depicts a cross section of a portion of the intermediate structure of FIG. 10 after etching of the sacrificial lithography stack and application of a spacer material, in accordance with one or more aspects of the present invention
- FIG. 12 depicts a cross section of a portion of the intermediate structure of FIG. 11 after etching the spacer material and the sacrificial layer, in accordance with one or more aspects of the present invention
- FIG. 13 depicts a cross section of a portion of the intermediate structure of FIG. 12 after removal of the sacrificial mandrel material between the spacers, in accordance with one or more aspects of the present invention
- FIG. 14 depicts a cross section of a portion of the intermediate structure of FIG. 13 after etching the second oxide layer, in accordance with one or more aspects of the present invention
- FIG. 15 depicts a cross section of a portion of the intermediate structure of FIG. 14 after application of a spacer material over the second oxide layer, in accordance with one or more aspects of the present invention
- FIG. 16 depicts a cross section of a portion of the intermediate structure of FIG. 15 after etching the spacer material, in accordance with one or more aspects of the present invention
- FIG. 17 depicts a cross section of a portion of the intermediate structure of FIG. 16 after removal of the second oxide material between the spacers, in accordance with one or more aspects of the present invention
- FIG. 18 depicts a cross section of a portion of one embodiment of an intermediate structure of FIG. 3 after formation of a doped layer, an epi layer, a first oxide layer, a dielectric material, and a second oxide layer, in accordance with one or more aspects of the present invention
- FIG. 19 depicts a cross section of a portion of the intermediate structure of FIG. 18 after a first etch, in accordance with one or more aspects of the present invention
- FIG. 20 depicts a cross section of a portion of the intermediate structure of FIG. 19 after a second etch, in accordance with one or more aspects of the present invention
- FIG. 21 depicts a cross section of a portion of the intermediate structure of FIG. 20 after deposition and etching of a spacer material, in accordance with one or more aspects of the present invention
- FIG. 22 depicts a cross section of a portion of the intermediate structure of FIG. 21 after removal of the sacrificial mandrel material between the spacers, in accordance with one or more aspects of the present invention
- FIG. 23 depicts a cross section in a first plane of a portion of the intermediate structure of FIG. 9 after application of a tri-layer mask stack and performing lithography for a fin cut mask, in accordance with one or more aspects of the present invention
- FIG. 24 depicts a cross section in the first plane of a portion of the intermediate structure of FIG. 23 after etching into the tri-layer mask stack over the fin cut mask, in accordance with one or more aspects of the present invention
- FIG. 25 depicts a cross section in a second plane of a portion of the intermediate structure of FIG. 23 after performing lithography for a fin preserving mask, in accordance with one or more aspects of the present invention
- FIG. 26 depicts a cross section in the second plane of a portion of the intermediate structure of FIG. 24 after etching over the fin preserving mask, in accordance with one or more aspects of the present invention
- FIG. 27 depicts a cross section in a first plane of a portion of the intermediate structure of FIG. 8 after application of a tri-layer mask stack and performing lithography for a fin cut mask, in accordance with one or more aspects of the present invention
- FIG. 28 depicts a cross section in the first plane of a portion of the intermediate structure of FIG. 27 after etching into the tri-layer mask stack over the fin cut mask, in accordance with one or more aspects of the present invention
- FIG. 29 depicts a cross section in a second plane of a portion of the intermediate structure of FIG. 27 after performing lithography for a fin preserving mask, in accordance with one or more aspects of the present invention
- FIG. 30 depicts a cross section in the second plane of a portion of the intermediate structure of FIG. 28 after etching over the fin preserving mask, in accordance with one or more aspects of the present invention
- FIG. 31 depicts a cross section in the second plane of a portion of the intermediate structure of FIG. 30 after revealing the dielectric masks, in accordance with one or more aspects of the present invention
- FIG. 32 depicts a cross section of a portion of the intermediate structure of FIG. 31 after etching at least one fin, in accordance with one or more aspects of the present invention
- FIG. 33 depicts a cross section of a portion of the intermediate structure of FIG. 32 after removing the dielectric material and performing a second fin etch, in accordance with one or more aspects of the present invention
- FIG. 34 depicts a cross section of a portion of the intermediate structure of FIG. 33 after application of an oxide gapfill, in accordance with one or more aspects of the present invention.
- FIG. 35 depicts a cross section of a portion of the intermediate structure of FIG. 34 after etching to reveal a portion of the at least one fin, in accordance with one or more aspects of the present invention.
- FinFET device fabrication processes disclosed herein provide for FinFET devices with tight fin pitches, for example, fin pitches of approximately 25 nm and above.
- FinFET device formation in accordance with one or more aspects of the present invention may include, for instance: obtaining an intermediate semiconductor device 100 ; growing an epi layer on the semiconductor device 110 ; depositing a doped layer below the epi layer 120 ; depositing a first oxide layer on the epi layer 130 ; applying a dielectric material on the first oxide layer 140 ; and depositing a lithography stack on the dielectric material 150 .
- the process shown in FIG. 1 is inherent in the more detailed FinFET structure formation process shown in FIG. 2 .
- the process of FIG. 1 is inherent in obtaining an intermediate semiconductor device 200 of FIG. 2 .
- the FinFET formation process of FIG. 2 is in accordance with one or more aspects of the present invention and may include, for instance: obtaining an intermediate semiconductor device after lithography stack deposition 200 ; etching the lithography stack 210 ; depositing a spacer material on the etched lithography stack 220 ; etching to form spacers 230 ; removing the sacrificial layer and sacrificial mandrel material 240 ; etching the dielectric layer 250 ; removing the spacer material 260 ; and forming at least one fin for the semiconductor device 270 .
- FIGS. 3-9 depict, by way of example only, one detailed embodiment of a portion of a FinFET device formation process, and a portion of an intermediate FinFET structure, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements.
- a semiconductor device structure 300 is schematically illustrated in FIG. 3 and may have been processed through, for example, shallow trench isolation (STI), n/p well formation, and other initial device processing steps in accordance with the design of the semiconductor device being fabricated.
- the semiconductor structure 300 may include a substrate 302 which may be made of, for example, a semiconductor material.
- the semiconductor material may include, e.g., silicon (Si), germanium (Ge), a compound semiconductor material, and a layered semiconductor material.
- the semiconductor structure 300 may also include at least one n-well region 304 and at least one p-well region 306 .
- the n-well region 304 may be made of, for example, an n-well material and the p-well region 306 may be made of, for example, a p-well material.
- the semiconductor structure 300 may then be sent for additional fabrication processing, for example, where an intermediate semiconductor device structure 400 , as shown in FIG. 4 , may be formed.
- the intermediate device 400 may include, for example, a doped layer 402 formed over the n-well region 304 and the p-well region 306 .
- the doped layer 402 may be, for example, a carbon doped layer.
- the device 400 may also include, for example, an epi layer 404 grown over the n-well and p-well regions 304 , 306 .
- the epi layer 404 may be, for example, an undoped silicon layer, SiGe layer, or another channel material that will grow on the substrate 302 .
- the epi layer 404 may correspond, for example, to the fin height for the device 400 .
- the doped layer 402 may be approximately 5 nm and may be formed by insitu-doping the Si epi layer 404 with high levels of carbon directly in the epitaxy after the epi layer 404 is formed.
- the intermediate device 400 may include, for example, a first oxide layer 406 deposited onto the epi layer 404 .
- the first oxide layer 406 may alternatively be a nitride layer.
- the intermediate device 400 may also have a dielectric material 408 deposited on the first oxide layer 406 .
- the intermediate device 400 may further include a sacrificial lithography stack 410 applied onto the dielectric material 408 .
- the sacrificial lithography stack 410 may include, for example, a sacrificial mandrel material 412 and a sacrificial layer 414 .
- the sacrificial mandrel material 412 may be, for example, an amorphous carbon
- the sacrificial layer 414 may be, for example, a SiON material.
- the lithography stack 410 may be etched to form at least one mandrel 416 .
- the spacing and size of the mandrels 416 may correlate to the fin pitch during the fin formation process.
- the mandrels 416 may include, for example, a sacrificial mandrel material 412 and a sacrificial layer 414 .
- a spacer material 418 may be applied over the exposed dielectric material 408 and the mandrels 416 , by for example, atomic layer deposition (ALD), such as, sidewall image transfer (SIT) ALD.
- ALD atomic layer deposition
- SIT sidewall image transfer
- the spacer material 418 may be made of, for example, SiN.
- the intermediate device 400 may be etched to remove a portion of the spacer material 418 and the sacrificial layer 414 .
- the portion of the spacer material 418 that may be removed during etching may include, for example, the horizontal spacer material 418 , leaving vertical sidewall spacers 420 on each side of the mandrels 416 , as shown in FIG. 6 .
- the etch may be, for example, a nitrogen etch which will remove the sacrificial layer 414 made of, for example, SiON, as well as etch away the spacer material 418 without etching into the dielectric material 408 .
- the mandrel material 412 may be removed by for example a mandrel ashing, as shown in FIG. 7 .
- the position of the remaining sidewall spacers 420 may correspond to the position of the fins that may be formed on the device 400 .
- the device 400 may then be etched to remove any of the dielectric layer 408 not masked by the sidewall spacers 420 to form masks 422 under the spacers 420 .
- Etching the dielectric layer 408 may be done with, for example, a chlorine based material that is highly selective to nitrogen and/or oxygen.
- the dielectric masks 422 are etched from the dielectric layer 408 , thus may be, for example, a high-k material, such as, HfO 2 , Al 2 O 3 , HfAlO 2 , ZrO 2 , ZrO, etc.
- a high-k material such as, HfO 2 , Al 2 O 3 , HfAlO 2 , ZrO 2 , ZrO, etc.
- the remaining material 418 of the spacers 420 may be stripped to expose the masks 422 .
- the masks 422 may be a thin transfer layer that is cut to place the fins in the desired position prior to etching.
- the dielectric masks 422 may be, for example, approximately 1 nm to 4 nm thick.
- the material 418 of the spacers 420 will remain over the masks 422 during the fin cutting process. Then the device 400 may be processed to form the fins, as described in greater detail below with reference to FIGS. 23-35 .
- the intermediate device 500 may include the semiconductor structure 300 as described above with reference to FIG. 3 . As shown in FIG. 10 , the device 500 may also include a doped layer 502 over the n-well region 304 and p-well region 306 . The doped layer 502 may be of the type described above with reference to doped layer 402 , which for brevity sake will not be described again here. The device may also include an epi layer 504 above the doped layer 502 , which may be, for example, an undoped Si layer, an undoped SiGe layer with varying percentages of germanium, another material from, for example, Groups III-V that can be grown defect free, or a combination thereof.
- the thickness of the epi layer 504 may correspond to the height of the fins.
- a first oxide layer 506 may be deposited over the epi layer 504 and a dielectric material 508 may be deposited over the first oxide layer 506 .
- the first oxide layer 506 may alternatively be a nitride layer.
- the dielectric material 508 may be a high-k material, for example, HfO 2 , Al 2 O 3 , HfAlO 2 , ZrO 2 , and the like.
- a second oxide layer 510 may then be deposited over the dielectric material 508 .
- a sacrificial lithography stack 512 may be formed on the second oxide layer 510 .
- the lithography stack 512 may include a sacrificial mandrel material 514 and a sacrificial layer 516 as described above with reference to the lithography stack 410 , which will not be described again here for brevity sake.
- the lithography stack 512 may be etched to form at least one mandrel 518 , which may include at least a portion of the sacrificial mandrel material 514 and a portion of the sacrificial layer 516 .
- a first spacer material 520 may be applied over the device 500 including the mandrels 518 .
- the spacer material 520 may be of the type described above with reference to spacer material 418 , and will not be described again here for brevity sake.
- the intermediate device 500 may be etched to remove a portion of the spacer material 520 and the sacrificial layer 516 , as shown in FIG. 12 .
- the etching may remove, for example, at least part of the horizontal portions of the spacer material 520 to form sidewall spacers 522 on the vertical side of the mandrels 518 .
- the mandrel material 514 may be removed leaving the sidewall spacers, as shown in FIG. 13 .
- the device 500 may then be etched using the sidewall spacers 522 as a mask over the second oxide layer 510 to form oxide mandrels 524 .
- a second spacer material 526 may then be applied over the oxide mandrels 524 , as shown in FIG. 15 .
- an etch may be performed to remove a portion of the second spacer material 526 and form sidewall spacers 528 on either side of the oxide mandrels 524 , as shown in FIG. 16 .
- the spacers 522 , 528 may be of the type described above with reference to spacers 420 .
- the oxide mandrels 524 may be removed, as shown in FIG. 17 .
- the remaining sidewall spacers 528 may correspond to the position where the fins will be formed on the device 500 .
- the device 500 may proceed to the fabrication processes as described above with reference to FIGS. 8 and 9 , which include etching the dielectric material 508 to form dielectric masks 422 .
- the device 500 may then be stripped to remove the spacer material 526 and expose the masks 422 , if an indirect alignment will be used to cut the device 500 .
- the spacer material 526 of the spacers 528 will remain over the masks 422 during the fin cutting process.
- the device 500 may be processed to form the fins, as described in greater detail below with reference to FIGS. 23-35 .
- FIGS. 18-22 show another embodiment intermediate semiconductor device 600 .
- the intermediate device 600 may include the semiconductor structure 300 , as described above with reference to FIG. 3 .
- the device 600 may also include a doped layer 602 over the n-well and p-well regions 304 , 306 .
- the doped layer 602 may be of the type described above with reference to doped layer 402 , which for brevity sake will not be described again here.
- the device may also include an epi layer 604 over the doped layer 602 , which may be, for example, an undoped Si or SiGe layer. The thickness of the epi layer 604 may correspond to the height of the exposed fins.
- a first oxide layer 606 may be deposited over the epi layer 604 and a dielectric material 608 may be deposited over the first oxide layer 606 .
- the first oxide layer 606 may alternatively be a nitride layer.
- the dielectric material 608 may be a high-k material, for example, HfO 2 , Al 2 O 3 , HfAlO 2 , ZrO, and the like.
- a second oxide layer 610 may then be deposited over the dielectric material 608 .
- a first lithography etch may be performed on the second oxide layer 610 of the device 600 to form a first set of oxide mandrels 612 .
- a second lithography etch may be performed to remove at least a portion of the first set of oxide mandrels 612 to form a second set of oxide mandrels 614 .
- the first and second lithography etches may be, for example, negative tone development (NTD) subtractive etches, although other types of etches are also contemplated.
- a spacer material may be deposited over the device 600 covering the second set of oxide mandrels 614 and the revealed portion of the dielectric material 608 .
- the spacer material may be of the type described above with reference to spacer material 418 .
- An etch may then be performed to remove a portion of the spacer material to form sidewall spacers 616 on the sides of the oxide mandrels 614 , as shown in FIG. 21 .
- the sidewall spacers 616 may be of the type described above with reference to sidewall spacers 420 .
- the oxide mandrels 614 may be removed, as shown in FIG. 22 .
- the oxide mandrels 614 may be removed by, for example, an oxide mandrel strip using a diluted hydrofluoric acid (dHF) which is selective to the dielectric material 608 and the sidewall spacers 616 .
- dHF diluted hydrofluoric acid
- the device 600 may proceed to the fabrication processes as described above with reference to FIGS. 8 and 9 which include etching the dielectric material 608 to form dielectric masks 422 . As described above with reference to FIG. 9 , the device 600 will then be stripped to remove the sidewall spacers 616 and expose the masks 422 , if an indirect alignment will be used to cut the device 600 . Alternatively, if a direct alignment technique will be used to cut the device 600 , the spacer material of the spacers 616 will remain over the masks 422 during the fin cutting process. Next, the device 600 may be processed to form the device fins, as described in greater detail below with reference to FIGS. 23-35 .
- the devices 400 , 500 and 600 may be passed to the fin formation processes.
- the fin formation processes may include, for example, super steep retrograde well (SSRW) processes, self-aligned quadruple pattering (SAQP) processes, litho-etch-litho-etch (LELE) self-aligned double patterning (SADP) processes, and the like.
- SSRW super steep retrograde well
- SAQP self-aligned quadruple pattering
- LELE litho-etch-litho-etch
- SADP self-aligned double patterning
- a mask stack 700 may be applied on the device 400 of FIG. 9 over the masks 422 formed of the dielectric material 408 .
- the mask stack 700 may include, for example, an organic planarization layer (OPL) 702 , a silicon containing anti-reflective coating (SiARC) layer 704 , and a photoresist layer 706 .
- OPL organic planarization layer
- SiARC silicon containing anti-reflective coating
- a first pattern for cutting the device 400 based on the location of the masks 422 may be transferred to the photoresist layer 706 by, for example, lithography, as shown in FIG. 23 .
- a first etch may be performed to remove a portion of the SiARC layer 704 , the OPL layer 702 , and portions of the dielectric material 408 creating at least one first cut mask 708 for making a first cut, as shown in FIG. 24 .
- the first pattern and first etch shown in FIGS. 23-24 , may be performed in a first direction.
- a second pattern and second etch are performed in a second direction.
- FIG. 25 shows a second pattern for cutting the device 400 transferred to the photoresist layer 706 by, for example, lithography.
- the second etch is then performed to remove portions of the SiARC layer 704 , the OPL layer 702 , and portions of the dielectric material 408 forming at least one second cut mask 716 for making a second cut, as shown in FIG. 26 .
- pull back of the OPL layer 702 may occur, but it does not clip the masks 422 because they may be formed thin enough to prevent removal of a portion of the masks 422 .
- the OPL layer 702 may then be removed.
- the spacers 420 may be left over the masks 422 to form tall masks made of, for example, the spacers 420 and masks 422 , for direct alignment of the device 400 during the fin fabrication process.
- a mask stack 700 for example, the tri-layer mask stack described in greater detail above with reference to FIG. 23 and which will not be described here again for brevity sake, may be applied on the device 400 of FIG. 8 over the tall masks 420 , 422 .
- a first pattern for cutting the device 400 based on the location of the spacers 420 and masks 422 may be transferred to the photoresist layer 706 by, for example, lithography, as shown in FIG. 27 .
- a first etch may be performed to remove a portion of the SiARC layer 704 , the OPL layer 702 , the spacer material 418 , and the dielectric material 408 to form at least one first cut mask 708 for making a first cut, as shown in FIG. 28 .
- a second pattern and second etch may be performed. The second pattern for cutting the device 400 is then transferred to the photoresist layer 706 by, for example, lithography, as shown in FIG. 29 .
- the second etch is then performed to remove at least a portion of the SiARC layer 704 and portions of the OPL layer 702 , the spacers 420 , and the masks 422 forming at least one second cut mask 716 for making a second cut, as shown in FIG. 30 .
- portions of the spacers 420 may be removed, however the dielectric masks 422 will not be revealed if portions of the spacers 420 are removed.
- any remaining portions of the SiARC layer 704 and the OPL layer 702 may be removed.
- the remaining spacers 420 may be removed to reveal the masks 422 , as shown in FIG. 31 .
- a fin etch may then be performed over the masks 422 to expose a portion of the fins 710 , as shown in FIG. 32 .
- At least a portion of the first oxide layer 406 may be removed during the fin etch to enable removal of a portion of the epi layer 404 to form fins 710 .
- the dielectric masks 422 act as a transfer layer for the oxide open and the etched portion of the oxide layer 406 becomes the hard masks for the fin etching.
- the device 400 may include a thick oxide layer 406 and a thinner dielectric layer 408 .
- the dielectric masks 422 are the hard masks for the fin etching process and the first oxide layer 406 acts as a patterning stop.
- the device 400 may include a thinner oxide layer 406 and a thicker dielectric layer 408 .
- the masks 422 may have a thickness of, for example, approximately 1 nm to 4 nm, and the remaining portions of the etched oxide layer 406 may have a thickness of, for example, approximately 20 nm to 40 nm.
- the device 400 may then be etched to remove the dielectric layer 408 and to etch the rest of the fins 710 .
- a Cl-etch may be used to remove the dielectric masks 422 from the device 400 .
- an oxide material 712 may then be applied over the device 400 to create a stress buffer, as shown in FIG. 34 .
- a flowable oxide may be applied over the device 400 by, for example, flowable chemical vapor deposition (FCVD).
- FCVD flowable chemical vapor deposition
- the oxide may then be planarized and etched to reveal the exposed fin 714 at a desired height.
- the etching may remove the oxide layer 406 from the top surface of the fins 710 , as shown in FIG. 35 .
- the device 400 may be cut along the first and second cut masks to form the resultant semiconductor device.
- a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements.
- a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features.
- a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
Abstract
Description
- This application is a divisional of U.S. application Ser. No. 14/064,840 filed Oct. 28, 2013, which is hereby incorporated herein by reference in its entirety.
- The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to fins at a tight fin pitch and methods of fabricating semiconductor devices having fins at a tight fin pitch.
- As fin pitch scales down, it is more difficult to etch away the sacrificial fin hard masks used to guarantee active fin accuracy. In addition, as fins are formed there are non-idealities in terms of critical dimension variations, overlay variations, and resist pull-back during hard mask etch and post lithography expose. Uncut or partially cut fins can cause failures such as gate shorts, epi shorts, or isolation shorts. Currently, fin hard masks are typically made of oxide and SiN bilayers and have a height of approximately 70-120 nm at the time of cutting. Thus, the fin hard masks are tall relative to the ever decreasing fin pitch, which was previously between 48 nm and 60 nm, is currently between 36 nm and 42 nm, and is moving towards sub-30 nm, while the fin width is not scaling at the same rate, and fundamentally cannot scale below 8-10 nm during patterning. If the hard masks are scaled, material selectivity between the oxide, nitride, and silicon may occur. In addition, the current height of the hard masks may result in pullback during hard mask removal. Thus, a thinner hard mask is needed to prevent pullback and improve the fin cut accuracy. However, the currently used nitride hard mask material has a fundamental etch selectivity limitation between the poly, oxide, and nitride preventing it from being used as a hard mask in a thinner layer.
- Thus, the fabrication of FinFET devices with tight pitches can be problematic with existing substrates and designs and improved substrates and FinFET device designs are needed for forming FinFET devices with tight fin pitches that maintain the current electrical performance of the resultant semiconductor devices.
- The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, a method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. The intermediate semiconductor device including, for instance, a substrate with at least one n-well region and at least one p-well region.
- In another aspect, an intermediate semiconductor device which includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.
- Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
- One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 depicts one embodiment of a process for fabricating, for instance, FinFET devices with tight fin pitches, in accordance with one or more aspects of the present invention; -
FIG. 2 depicts another embodiment of a process for fabricating, for instance, FinFET devices with tight fin pitches, in accordance with one or more aspects of the present invention; -
FIG. 3 depicts a cross section of a portion of one embodiment of an intermediate structure of a semiconductor device with an n-well region and a p-well region formed in a substrate, in accordance with one or more aspects of the present invention; -
FIG. 4 depicts a cross section of a portion of the intermediate structure ofFIG. 3 after formation of a doped layer, an epi layer, an oxide layer, a dielectric material, and a sacrificial lithography stack, in accordance with one or more aspects of the present invention; -
FIG. 5 depicts a cross section of a portion of the intermediate structure ofFIG. 4 after etching of the sacrificial lithography stack and application of a spacer material, in accordance with one or more aspects of the present invention; -
FIG. 6 depicts a cross section of a portion of the intermediate structure ofFIG. 5 after etching of the spacer material and sacrificial layer, in accordance with one or more aspects of the present invention; -
FIG. 7 depicts a cross section of a portion of the intermediate structure ofFIG. 6 after removal of the sacrificial mandrel material between the spacers, in accordance with one or more aspects of the present invention; -
FIG. 8 depicts a cross section of a portion of the intermediate structure ofFIG. 7 after etching of the dielectric layer, in accordance with one or more aspects of the present invention; -
FIG. 9 depicts a cross section of a portion of the intermediate structure ofFIG. 8 after removal of the spacers, in accordance with one or more aspects of the present invention; -
FIG. 10 depicts a cross section of a portion of another embodiment of an intermediate structure ofFIG. 3 after formation of a doped layer, an epi layer, a first oxide layer, a dielectric material, a second oxide layer, and a sacrificial lithography stack, in accordance with one or more aspects of the present invention; -
FIG. 11 depicts a cross section of a portion of the intermediate structure ofFIG. 10 after etching of the sacrificial lithography stack and application of a spacer material, in accordance with one or more aspects of the present invention; -
FIG. 12 depicts a cross section of a portion of the intermediate structure ofFIG. 11 after etching the spacer material and the sacrificial layer, in accordance with one or more aspects of the present invention; -
FIG. 13 depicts a cross section of a portion of the intermediate structure ofFIG. 12 after removal of the sacrificial mandrel material between the spacers, in accordance with one or more aspects of the present invention; -
FIG. 14 depicts a cross section of a portion of the intermediate structure ofFIG. 13 after etching the second oxide layer, in accordance with one or more aspects of the present invention; -
FIG. 15 depicts a cross section of a portion of the intermediate structure ofFIG. 14 after application of a spacer material over the second oxide layer, in accordance with one or more aspects of the present invention; -
FIG. 16 depicts a cross section of a portion of the intermediate structure ofFIG. 15 after etching the spacer material, in accordance with one or more aspects of the present invention; -
FIG. 17 depicts a cross section of a portion of the intermediate structure ofFIG. 16 after removal of the second oxide material between the spacers, in accordance with one or more aspects of the present invention; -
FIG. 18 depicts a cross section of a portion of one embodiment of an intermediate structure ofFIG. 3 after formation of a doped layer, an epi layer, a first oxide layer, a dielectric material, and a second oxide layer, in accordance with one or more aspects of the present invention; -
FIG. 19 depicts a cross section of a portion of the intermediate structure ofFIG. 18 after a first etch, in accordance with one or more aspects of the present invention; -
FIG. 20 depicts a cross section of a portion of the intermediate structure ofFIG. 19 after a second etch, in accordance with one or more aspects of the present invention; -
FIG. 21 depicts a cross section of a portion of the intermediate structure ofFIG. 20 after deposition and etching of a spacer material, in accordance with one or more aspects of the present invention; -
FIG. 22 depicts a cross section of a portion of the intermediate structure ofFIG. 21 after removal of the sacrificial mandrel material between the spacers, in accordance with one or more aspects of the present invention; -
FIG. 23 depicts a cross section in a first plane of a portion of the intermediate structure ofFIG. 9 after application of a tri-layer mask stack and performing lithography for a fin cut mask, in accordance with one or more aspects of the present invention; -
FIG. 24 depicts a cross section in the first plane of a portion of the intermediate structure ofFIG. 23 after etching into the tri-layer mask stack over the fin cut mask, in accordance with one or more aspects of the present invention; -
FIG. 25 depicts a cross section in a second plane of a portion of the intermediate structure ofFIG. 23 after performing lithography for a fin preserving mask, in accordance with one or more aspects of the present invention; -
FIG. 26 depicts a cross section in the second plane of a portion of the intermediate structure ofFIG. 24 after etching over the fin preserving mask, in accordance with one or more aspects of the present invention; -
FIG. 27 depicts a cross section in a first plane of a portion of the intermediate structure ofFIG. 8 after application of a tri-layer mask stack and performing lithography for a fin cut mask, in accordance with one or more aspects of the present invention; -
FIG. 28 depicts a cross section in the first plane of a portion of the intermediate structure ofFIG. 27 after etching into the tri-layer mask stack over the fin cut mask, in accordance with one or more aspects of the present invention; -
FIG. 29 depicts a cross section in a second plane of a portion of the intermediate structure ofFIG. 27 after performing lithography for a fin preserving mask, in accordance with one or more aspects of the present invention; -
FIG. 30 depicts a cross section in the second plane of a portion of the intermediate structure ofFIG. 28 after etching over the fin preserving mask, in accordance with one or more aspects of the present invention; -
FIG. 31 depicts a cross section in the second plane of a portion of the intermediate structure ofFIG. 30 after revealing the dielectric masks, in accordance with one or more aspects of the present invention; -
FIG. 32 depicts a cross section of a portion of the intermediate structure ofFIG. 31 after etching at least one fin, in accordance with one or more aspects of the present invention; -
FIG. 33 depicts a cross section of a portion of the intermediate structure ofFIG. 32 after removing the dielectric material and performing a second fin etch, in accordance with one or more aspects of the present invention; -
FIG. 34 depicts a cross section of a portion of the intermediate structure ofFIG. 33 after application of an oxide gapfill, in accordance with one or more aspects of the present invention; and -
FIG. 35 depicts a cross section of a portion of the intermediate structure ofFIG. 34 after etching to reveal a portion of the at least one fin, in accordance with one or more aspects of the present invention. - Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
- Generally stated, disclosed herein are certain novel FinFET device formation methods and FinFET structures, which provide advantages over the above noted, existing FinFET device fabrication processes and structures. Advantageously, the FinFET device fabrication processes disclosed herein provide for FinFET devices with tight fin pitches, for example, fin pitches of approximately 25 nm and above.
- In one aspect, in one embodiment, as shown in
FIG. 1 , FinFET device formation in accordance with one or more aspects of the present invention may include, for instance: obtaining anintermediate semiconductor device 100; growing an epi layer on thesemiconductor device 110; depositing a doped layer below theepi layer 120; depositing a first oxide layer on theepi layer 130; applying a dielectric material on thefirst oxide layer 140; and depositing a lithography stack on thedielectric material 150. - The process shown in
FIG. 1 is inherent in the more detailed FinFET structure formation process shown inFIG. 2 . Specifically, the process ofFIG. 1 is inherent in obtaining anintermediate semiconductor device 200 ofFIG. 2 . The FinFET formation process ofFIG. 2 is in accordance with one or more aspects of the present invention and may include, for instance: obtaining an intermediate semiconductor device afterlithography stack deposition 200; etching thelithography stack 210; depositing a spacer material on the etchedlithography stack 220; etching to formspacers 230; removing the sacrificial layer andsacrificial mandrel material 240; etching thedielectric layer 250; removing thespacer material 260; and forming at least one fin for thesemiconductor device 270. -
FIGS. 3-9 depict, by way of example only, one detailed embodiment of a portion of a FinFET device formation process, and a portion of an intermediate FinFET structure, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements. - A
semiconductor device structure 300 is schematically illustrated inFIG. 3 and may have been processed through, for example, shallow trench isolation (STI), n/p well formation, and other initial device processing steps in accordance with the design of the semiconductor device being fabricated. As depicted inFIG. 3 , thesemiconductor structure 300 may include asubstrate 302 which may be made of, for example, a semiconductor material. The semiconductor material may include, e.g., silicon (Si), germanium (Ge), a compound semiconductor material, and a layered semiconductor material. Thesemiconductor structure 300 may also include at least one n-well region 304 and at least one p-well region 306. The n-well region 304 may be made of, for example, an n-well material and the p-well region 306 may be made of, for example, a p-well material. - The
semiconductor structure 300 may then be sent for additional fabrication processing, for example, where an intermediatesemiconductor device structure 400, as shown inFIG. 4 , may be formed. Theintermediate device 400 may include, for example, adoped layer 402 formed over the n-well region 304 and the p-well region 306. The dopedlayer 402 may be, for example, a carbon doped layer. Thedevice 400 may also include, for example, anepi layer 404 grown over the n-well and p-well regions epi layer 404 may be, for example, an undoped silicon layer, SiGe layer, or another channel material that will grow on thesubstrate 302. Theepi layer 404 may correspond, for example, to the fin height for thedevice 400. By way of specific example, the dopedlayer 402 may be approximately 5 nm and may be formed by insitu-doping theSi epi layer 404 with high levels of carbon directly in the epitaxy after theepi layer 404 is formed. In addition, theintermediate device 400 may include, for example, afirst oxide layer 406 deposited onto theepi layer 404. Thefirst oxide layer 406 may alternatively be a nitride layer. Theintermediate device 400 may also have adielectric material 408 deposited on thefirst oxide layer 406. Theintermediate device 400 may further include asacrificial lithography stack 410 applied onto thedielectric material 408. Thesacrificial lithography stack 410 may include, for example, asacrificial mandrel material 412 and asacrificial layer 414. In an embodiment, thesacrificial mandrel material 412 may be, for example, an amorphous carbon, and thesacrificial layer 414 may be, for example, a SiON material. - As shown in
FIG. 5 , thelithography stack 410 may be etched to form at least onemandrel 416. The spacing and size of themandrels 416 may correlate to the fin pitch during the fin formation process. Themandrels 416 may include, for example, asacrificial mandrel material 412 and asacrificial layer 414. Next aspacer material 418 may be applied over the exposeddielectric material 408 and themandrels 416, by for example, atomic layer deposition (ALD), such as, sidewall image transfer (SIT) ALD. Thespacer material 418 may be made of, for example, SiN. - After the
spacer material 418 is applied, theintermediate device 400 may be etched to remove a portion of thespacer material 418 and thesacrificial layer 414. The portion of thespacer material 418 that may be removed during etching may include, for example, thehorizontal spacer material 418, leavingvertical sidewall spacers 420 on each side of themandrels 416, as shown inFIG. 6 . The etch may be, for example, a nitrogen etch which will remove thesacrificial layer 414 made of, for example, SiON, as well as etch away thespacer material 418 without etching into thedielectric material 408. Next themandrel material 412 may be removed by for example a mandrel ashing, as shown inFIG. 7 . Once themandrel material 412 is removed, the position of the remainingsidewall spacers 420 may correspond to the position of the fins that may be formed on thedevice 400. - As shown in
FIG. 8 , thedevice 400 may then be etched to remove any of thedielectric layer 408 not masked by thesidewall spacers 420 to formmasks 422 under thespacers 420. Etching thedielectric layer 408 may be done with, for example, a chlorine based material that is highly selective to nitrogen and/or oxygen. Thedielectric masks 422 are etched from thedielectric layer 408, thus may be, for example, a high-k material, such as, HfO2, Al2O3, HfAlO2, ZrO2, ZrO, etc. Next, as shown inFIG. 9 , if an indirect alignment will be used to cut thedevice 400, the remainingmaterial 418 of thespacers 420 may be stripped to expose themasks 422. Themasks 422 may be a thin transfer layer that is cut to place the fins in the desired position prior to etching. Thedielectric masks 422 may be, for example, approximately 1 nm to 4 nm thick. Alternatively, if a direct alignment technique will be used to cut thedevice 400, thematerial 418 of thespacers 420 will remain over themasks 422 during the fin cutting process. Then thedevice 400 may be processed to form the fins, as described in greater detail below with reference toFIGS. 23-35 . - Another embodiment
intermediate semiconductor device 500 is shown inFIGS. 10-17 . Theintermediate device 500 may include thesemiconductor structure 300 as described above with reference toFIG. 3 . As shown inFIG. 10 , thedevice 500 may also include adoped layer 502 over the n-well region 304 and p-well region 306. The dopedlayer 502 may be of the type described above with reference to dopedlayer 402, which for brevity sake will not be described again here. The device may also include anepi layer 504 above the dopedlayer 502, which may be, for example, an undoped Si layer, an undoped SiGe layer with varying percentages of germanium, another material from, for example, Groups III-V that can be grown defect free, or a combination thereof. The thickness of theepi layer 504 may correspond to the height of the fins. Afirst oxide layer 506 may be deposited over theepi layer 504 and adielectric material 508 may be deposited over thefirst oxide layer 506. Thefirst oxide layer 506 may alternatively be a nitride layer. Thedielectric material 508 may be a high-k material, for example, HfO2, Al2O3, HfAlO2, ZrO2, and the like. Asecond oxide layer 510 may then be deposited over thedielectric material 508. Next asacrificial lithography stack 512 may be formed on thesecond oxide layer 510. Thelithography stack 512 may include asacrificial mandrel material 514 and asacrificial layer 516 as described above with reference to thelithography stack 410, which will not be described again here for brevity sake. - As shown in
FIG. 11 , thelithography stack 512 may be etched to form at least onemandrel 518, which may include at least a portion of thesacrificial mandrel material 514 and a portion of thesacrificial layer 516. After themandrels 518 are formed, afirst spacer material 520 may be applied over thedevice 500 including themandrels 518. Thespacer material 520 may be of the type described above with reference tospacer material 418, and will not be described again here for brevity sake. - After applying the
spacer material 520, theintermediate device 500 may be etched to remove a portion of thespacer material 520 and thesacrificial layer 516, as shown inFIG. 12 . The etching may remove, for example, at least part of the horizontal portions of thespacer material 520 to formsidewall spacers 522 on the vertical side of themandrels 518. Next, themandrel material 514 may be removed leaving the sidewall spacers, as shown inFIG. 13 . - As shown in
FIG. 14 , thedevice 500 may then be etched using thesidewall spacers 522 as a mask over thesecond oxide layer 510 to formoxide mandrels 524. Asecond spacer material 526 may then be applied over theoxide mandrels 524, as shown inFIG. 15 . Next, an etch may be performed to remove a portion of thesecond spacer material 526 andform sidewall spacers 528 on either side of theoxide mandrels 524, as shown inFIG. 16 . Thespacers spacers 420. Following thespacer 528 formation, theoxide mandrels 524 may be removed, as shown inFIG. 17 . The remainingsidewall spacers 528 may correspond to the position where the fins will be formed on thedevice 500. After thespacers 528 are formed thedevice 500 may proceed to the fabrication processes as described above with reference toFIGS. 8 and 9 , which include etching thedielectric material 508 to formdielectric masks 422. As described above with reference toFIG. 9 , thedevice 500 may then be stripped to remove thespacer material 526 and expose themasks 422, if an indirect alignment will be used to cut thedevice 500. Alternatively, if a direct alignment technique will be used to cut thedevice 500, thespacer material 526 of thespacers 528 will remain over themasks 422 during the fin cutting process. Next, thedevice 500 may be processed to form the fins, as described in greater detail below with reference toFIGS. 23-35 . -
FIGS. 18-22 show another embodimentintermediate semiconductor device 600. Theintermediate device 600 may include thesemiconductor structure 300, as described above with reference toFIG. 3 . As shown inFIG. 18 , thedevice 600 may also include adoped layer 602 over the n-well and p-well regions layer 602 may be of the type described above with reference to dopedlayer 402, which for brevity sake will not be described again here. The device may also include anepi layer 604 over the dopedlayer 602, which may be, for example, an undoped Si or SiGe layer. The thickness of theepi layer 604 may correspond to the height of the exposed fins. Afirst oxide layer 606 may be deposited over theepi layer 604 and adielectric material 608 may be deposited over thefirst oxide layer 606. Thefirst oxide layer 606 may alternatively be a nitride layer. Thedielectric material 608 may be a high-k material, for example, HfO2, Al2O3, HfAlO2, ZrO, and the like. Asecond oxide layer 610 may then be deposited over thedielectric material 608. - As shown in
FIG. 19 , a first lithography etch may be performed on thesecond oxide layer 610 of thedevice 600 to form a first set ofoxide mandrels 612. Next, as shown inFIG. 20 , a second lithography etch may be performed to remove at least a portion of the first set ofoxide mandrels 612 to form a second set ofoxide mandrels 614. The first and second lithography etches may be, for example, negative tone development (NTD) subtractive etches, although other types of etches are also contemplated. - Once the second set of
oxide mandrels 614 is formed a spacer material may be deposited over thedevice 600 covering the second set ofoxide mandrels 614 and the revealed portion of thedielectric material 608. The spacer material may be of the type described above with reference tospacer material 418. An etch may then be performed to remove a portion of the spacer material to formsidewall spacers 616 on the sides of theoxide mandrels 614, as shown inFIG. 21 . The sidewall spacers 616 may be of the type described above with reference tosidewall spacers 420. After thesidewall spacers 616 are formed theoxide mandrels 614 may be removed, as shown inFIG. 22 . Theoxide mandrels 614 may be removed by, for example, an oxide mandrel strip using a diluted hydrofluoric acid (dHF) which is selective to thedielectric material 608 and thesidewall spacers 616. - After the
sidewall spacers 616 are formed thedevice 600 may proceed to the fabrication processes as described above with reference toFIGS. 8 and 9 which include etching thedielectric material 608 to formdielectric masks 422. As described above with reference toFIG. 9 , thedevice 600 will then be stripped to remove thesidewall spacers 616 and expose themasks 422, if an indirect alignment will be used to cut thedevice 600. Alternatively, if a direct alignment technique will be used to cut thedevice 600, the spacer material of thespacers 616 will remain over themasks 422 during the fin cutting process. Next, thedevice 600 may be processed to form the device fins, as described in greater detail below with reference toFIGS. 23-35 . - As shown in
FIGS. 23-35 , after formation of themasks 422, thedevices device 400 will be used to describe the fin formation processes shown inFIGS. 23-35 . It will be understood by one skilled in the art thatdevices device 400 inFIGS. 23-35 for the fin formation processes. As shown inFIG. 23 , amask stack 700, for example, a tri-layer mask stack, may be applied on thedevice 400 ofFIG. 9 over themasks 422 formed of thedielectric material 408. Themask stack 700 may include, for example, an organic planarization layer (OPL) 702, a silicon containing anti-reflective coating (SiARC)layer 704, and aphotoresist layer 706. - After the
mask stack 700 is formed, a first pattern for cutting thedevice 400 based on the location of themasks 422 may be transferred to thephotoresist layer 706 by, for example, lithography, as shown inFIG. 23 . Next a first etch may be performed to remove a portion of theSiARC layer 704, theOPL layer 702, and portions of thedielectric material 408 creating at least onefirst cut mask 708 for making a first cut, as shown inFIG. 24 . The first pattern and first etch, shown inFIGS. 23-24 , may be performed in a first direction. Then, as shown inFIGS. 25-26 , a second pattern and second etch are performed in a second direction.FIG. 25 shows a second pattern for cutting thedevice 400 transferred to thephotoresist layer 706 by, for example, lithography. The second etch is then performed to remove portions of theSiARC layer 704, theOPL layer 702, and portions of thedielectric material 408 forming at least onesecond cut mask 716 for making a second cut, as shown inFIG. 26 . During the etching of thedevice 400, pull back of theOPL layer 702 may occur, but it does not clip themasks 422 because they may be formed thin enough to prevent removal of a portion of themasks 422. After the second etching is performed to remove portions of thedielectric material 408, theOPL layer 702 may then be removed. - Alternatively, the
spacers 420 may be left over themasks 422 to form tall masks made of, for example, thespacers 420 andmasks 422, for direct alignment of thedevice 400 during the fin fabrication process. As shown inFIG. 27 , amask stack 700, for example, the tri-layer mask stack described in greater detail above with reference toFIG. 23 and which will not be described here again for brevity sake, may be applied on thedevice 400 ofFIG. 8 over thetall masks device 400 based on the location of thespacers 420 andmasks 422 may be transferred to thephotoresist layer 706 by, for example, lithography, as shown inFIG. 27 . Then a first etch may be performed to remove a portion of theSiARC layer 704, theOPL layer 702, thespacer material 418, and thedielectric material 408 to form at least onefirst cut mask 708 for making a first cut, as shown inFIG. 28 . Then, as shown inFIGS. 29-30 , a second pattern and second etch may be performed. The second pattern for cutting thedevice 400 is then transferred to thephotoresist layer 706 by, for example, lithography, as shown inFIG. 29 . The second etch is then performed to remove at least a portion of theSiARC layer 704 and portions of theOPL layer 702, thespacers 420, and themasks 422 forming at least onesecond cut mask 716 for making a second cut, as shown inFIG. 30 . During the second etch, portions of thespacers 420 may be removed, however thedielectric masks 422 will not be revealed if portions of thespacers 420 are removed. After the second etching is performed to remove portions of thespacers 420 and themasks 422, then any remaining portions of theSiARC layer 704 and theOPL layer 702 may be removed. In addition, the remainingspacers 420 may be removed to reveal themasks 422, as shown inFIG. 31 . - In both the indirect alignment and direct alignment fabrication processes, a fin etch may then be performed over the
masks 422 to expose a portion of thefins 710, as shown inFIG. 32 . At least a portion of thefirst oxide layer 406 may be removed during the fin etch to enable removal of a portion of theepi layer 404 to formfins 710. By way of specific example, if a Cl-based fin etch is used, thedielectric masks 422 act as a transfer layer for the oxide open and the etched portion of theoxide layer 406 becomes the hard masks for the fin etching. With a Cl-based fin etch, thedevice 400 may include athick oxide layer 406 and a thinnerdielectric layer 408. In another embodiment, by way of specific example, if a F-based fin etch is used, thedielectric masks 422 are the hard masks for the fin etching process and thefirst oxide layer 406 acts as a patterning stop. With an F-based fin etch, thedevice 400 may include athinner oxide layer 406 and a thickerdielectric layer 408. Themasks 422 may have a thickness of, for example, approximately 1 nm to 4 nm, and the remaining portions of the etchedoxide layer 406 may have a thickness of, for example, approximately 20 nm to 40 nm. - As shown in
FIG. 33 , thedevice 400 may then be etched to remove thedielectric layer 408 and to etch the rest of thefins 710. A Cl-etch may be used to remove thedielectric masks 422 from thedevice 400. Once thefins 710 are formed, anoxide material 712 may then be applied over thedevice 400 to create a stress buffer, as shown inFIG. 34 . In addition, a flowable oxide may be applied over thedevice 400 by, for example, flowable chemical vapor deposition (FCVD). The oxide may then be planarized and etched to reveal the exposedfin 714 at a desired height. The etching may remove theoxide layer 406 from the top surface of thefins 710, as shown inFIG. 35 . Finally, thedevice 400 may be cut along the first and second cut masks to form the resultant semiconductor device. - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (12)
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US14/725,430 US20150287595A1 (en) | 2013-10-28 | 2015-05-29 | Devices and methods of forming fins at tight fin pitches |
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US14/064,840 US9105478B2 (en) | 2013-10-28 | 2013-10-28 | Devices and methods of forming fins at tight fin pitches |
US14/725,430 US20150287595A1 (en) | 2013-10-28 | 2015-05-29 | Devices and methods of forming fins at tight fin pitches |
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US9431265B2 (en) * | 2014-09-29 | 2016-08-30 | International Business Machines Corporation | Fin cut for tight fin pitch by two different sit hard mask materials on fin |
US9595475B2 (en) * | 2014-12-01 | 2017-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stage fin formation methods and structures thereof |
KR102323251B1 (en) * | 2015-01-21 | 2021-11-09 | 삼성전자주식회사 | Semiconductor device and method for manufacturing semiconductor device |
US9704974B2 (en) * | 2015-04-16 | 2017-07-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process of manufacturing Fin-FET device |
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US9508560B1 (en) | 2015-06-18 | 2016-11-29 | International Business Machines Corporation | SiARC removal with plasma etch and fluorinated wet chemical solution combination |
US9735063B2 (en) | 2015-08-19 | 2017-08-15 | Globalfoundries Inc. | Methods for forming fin structures |
US9397006B1 (en) | 2015-12-04 | 2016-07-19 | International Business Machines Corporation | Co-integration of different fin pitches for logic and analog devices |
US9466690B1 (en) | 2016-01-13 | 2016-10-11 | International Business Machines Corporation | Precisely controlling III-V height |
US9852917B2 (en) | 2016-03-22 | 2017-12-26 | International Business Machines Corporation | Methods of fabricating semiconductor fins by double sidewall image transfer patterning through localized oxidation enhancement of sacrificial mandrel sidewalls |
US10573528B2 (en) | 2017-12-14 | 2020-02-25 | Tessera, Inc. | Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic |
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