US20150270272A1

US20150270272A1 - Finfet Drive Strength Modification

Info

Publication number: US20150270272A1
Application number: US14/727,294
Authority: US
Inventors: Thomas MERELLE; Gerben Doornbos; Robert James Lander; Yi-Tzi Liu
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2008-06-11
Filing date: 2015-06-01
Publication date: 2015-09-24
Also published as: US8283231B2; US20140319609A1; US20100006945A1; US20130026567A1; US9048122B2; US8779527B2

Abstract

A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET.

One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Description

CROSS REFERENCE

The present application is a continuation application of U.S. application Ser. No. 14/329,587, filed Jul. 11, 2014, which is a continuation of U.S. application Ser. No. 13/647,091, filed Oct. 8, 2012, issued as U.S. Pat. No. 8,779,527, which is a divisional application of U.S. application Ser. No. 12/483,133, filed Jun. 11, 2009, now U.S. Pat. No. 8,283,231, which claims priority to European patent application number 08104375.4, filed Jun. 11, 2008, each of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present invention relates to the selective modification of the drive strength of a finFET (Fin Field Effect Transistor). In particular the invention provides methods for forming finFETs with a selectively modified drive strength and to circuits resulting from the application of those methods to the fabrication of integrated circuits. The present invention is particularly suited to, but not limited to, use in a Static Random Access Memory (SRAM) cell.
CMOS (Complementary Metal Oxide Semi-conductor) technology is widely used today in integrated circuits used in, for example, microprocessors, microcontrollers, memory circuits and other digital logic circuits, as well as in a wide variety of analog circuits. CMOS technology relies on MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) to amplify or to switch signals.
It is desirable to be able to differentiate the drive strengths of transistors within a CMOS circuit. For example one area in which it has been found to be advantageous to differentiate the drive strengths of transistors is within a Static Random Access Memory (SRAM) cell. A typical SRAM cell circuit with 6 transistors (6-T SRAM cell) is shown in FIG. 1, and a typical implementation of such a cell in conventional planar CMOS technology is shown in FIG. 2.
The exemplary 6-T SRAM cell shown in FIG. 1 comprises first and second cross-coupled inverters 2, 4 each inverter 2, 4 comprising a respective P-MOS Pull-Up (PU) transistor 6,8 and a N-MOS Pull-down (PD) transistor 10,12 coupled in series between the power source Vdd and ground Gnd. A first respective N-MOS Pass-gate (PG) transistor 14 is coupled between a bit-line 16 and an internal node 18 connecting the first pull-up transistor 6 and the first pull-down transistor 10. A second respective N-MOS pass-gate transistor 20 is coupled between an inverted bit-line 22 and an internal node 24 connecting the second pull-up transistor 8 and the second pull-down transistor 12. As will be apparent to a skilled person, corresponding inverted values are held by the internal nodes 18, 24.
The exemplary 6-T SRAM cell stores one bit and has two stable states, in which either internal node 18 or internal node 24 are asserted, which are used to denote a 1 or 0 for the bit. Access to the exemplary 6-T SRAM cell during both a read operation and a write operation is enabled by the word line WL, which turns on the first and second pass-gate transistors 14, 20 thus coupling the internal nodes 18, 24 to the bit lines 16, 22 respectively. For example, during a read operation, the bit lines 16 and 22 are both pre-charged to logic 1, before asserting the word line WL to turn on first and second pass-gate transistors 14, 20. Thereafter, the bit line corresponding to whichever of the internal node 18 or 24 started at logic 0 will discharge into the cell via the respective pass-gate transistor 14, 20 and the respective pull- down transistor 10,12. A detailed discussion of the read and write operation of a 6-T SRAM cell will be omitted since a skilled person will be familiar with the layout and operation of 6-T SRAM cell.
As is well known, the performance of a SRAM cell is dependent on the relative drive strengths of the transistors making up the SRAM cell. In this context, the term drive strength of a transistor is intended to mean the magnitude of the current flowing through the transistor when the transistor is switched on.
Conventionally designers of SRAM cells have been able to adjust all the major performance metrics of a SRAM cell, such as access time, static noise margin and write margin, by adjusting the transistor widths and lengths in planar CMOS technology to control the drive strengths of the respective transistors. Thus, for example in a SRAM cell implemented in conventional planar bulk CMOS technology the source and drain regions of the pull-down transistor can be made wider than the source and drain regions of the corresponding pass-gate transistor, thus increasing the drive strength of the pull-down transistor relative to the drive strength of the pass-gate transistor. The read time of the cell can therefore be improved.
A typical implementation of the SRAM cell of FIG. 1 in conventional planar CMOS technology showing the differentiation of the transistor dimensions is shown in FIG. 2. In FIG. 2 the same reference numerals as the reference numerals for the corresponding features in FIG. 1 have been used. In addition, interconnection 26 interconnects the gate of pull-up transistor 8; the gate of pull-down transistor 12; the drain of pull-up transistor 6; the drain of pull-down transistor 10 and the internal node side of the pass-gate transistor 14, and thus represents the internal node 18. An interconnection 28 interconnects the gate of pull-up transistor 6; the gate of pull-down transistor 10; the source of the pull-up transistor 8; the drain of pull-down transistor 12 and the internal node side of pass-gate transistor 20, and thus represents the internal node 24. As can be seen, the widths of the pull- down transistors 10, 12 are greater than the widths of the corresponding pass-gate transistors 14, 20, giving the pull- down transistors 10, 12 greater drive strength and thus improving the performance of the SRAM cell. It is noted that the pull- up transistors 6, 8 are P-MOS transistors, while the other transistors are N-MOS transistors.
However, due to increasing variability, it is becoming increasingly difficult to manufacture a SRAM array of several Mbits in planar CMOS technology with an acceptable yield as the density of the integrated circuits is increased. In addition, as the size of the individual MOSFETS is reduced, the performance of the MOSFETS degrades, in particular due to so-called short channel effects. At the present it is expected that conventional planar MOSFETs will reach the limit of miniaturisation by 2010, concurrent with the widespread adoption of 32 nm technologies.
FinFETs have been suggested as potential replacements for conventional planar MOSFETS. The distinguishing characteristic of the finFET is that the conducting channel is wrapped around a thin silicon “fin” which forms the body of the device. One or more gate electrodes are formed adjacent the fin. In a dual-gate device, one gate electrode on each side of the fin is formed. In a tri-ate device, one gate electrode on each side of the fin and one gate electrode at the top of the fin are formed. These arrangements enable good gate control over the channel, resulting in improved short channel immunity and improved ratio between the channel current when the transistor is switched on and the channel current when the transistor is switched off. The structure of a typical finFET will be described with reference to FIGS. 3-5.
FIG. 3 is a plan view of a typical finFET structure. FIG. 4 is a longitudinal cross-section through the line A-A in FIG. 1. FIG. 5 is a perspective view of a typical finFET structure showing the fin and the gate structures. In FIG. 5 the drain region and the source region of the finFET have been omitted for clarity.
The finFET 30 is provided with a narrow and relatively high fin 32 upstanding from the surface of the substrate 34 (seen best in FIGS. 4 and 5). The fin 32 is typically formed from Silicon on a buried Oxide (BOX) layer of a Silicon (SOI) substrate 34 or on a silicon substrate and has a width W_finand a Height H_fin. One or more gate electrodes 36 having a gate length L_gateare disposed over the top and sides of the fin 32 and spaced apart from the fin 32 by a spacer 38. Typical dimensions for the fin 32 and gate electrodes 36 for the 32 nm CMOS node would be L_gate=20-50 nm; W_fin=5-20 nm; H_fin=20-100 nm. Adjacent each end of the fin 32 are formed two high density doped (HDD) regions forming a source HDD region 40 and a drain HDD region 42 of the finFET 30. In addition, typically, low density doped (LDD) extension regions, forming source LDD extension region 44 and drain LDD extension region 46, are formed within the channel extending from the source HDD region 40 and drain HDD region 42 respectively towards the gate electrode(s) 36.
It is known to omit the drain LDD extension region of a finFET in order to reduce Gate Induced Drain leakage (GIDL) current within the channel of a finFET, as for example discussed in the article “GIDL (Gate-Induced Drain Leakage) and Parasitic Schottky barrier Leakage Elimination in aggressively scaled HfO₂/TiN FinFET devices” Hoffmann et al, Electron Devices Meeting, 2005 IEDM Technical Digest. IEEE International Dec. 5, 2005, Piscataway, N.J., USA.
Many of the performance metrics of a finFET, for example the drive strength of the finFET, are determined by the effective channel width of a finFET which in turn depends upon the dimensions of the fin. In particular, the effective channel width of a finFET is given by 2×H_fin(for a dual gate FinFET) and 2×H_fin+W_fin(for a tri-gate finFET). The person skilled in the art will be familiar with the principles of operation of a Field Effect Transistor (FET) and therefore a detailed description of the operation of the finFET will be omitted.
An exemplary implementation of the SRAM cell of FIG. 1 using finFETs is shown in FIG. 6. In FIG. 6 reference numerals corresponding to reference numerals used in FIG. 2 are used for the corresponding features. As can be seen from a consideration of FIG. 6, in this exemplary silicon layout implementation, the finFET pass-gate transistor 114 shares a common fin with the finFET pull-down transistor 110 and the finFET pass-gate transistor 120 shares a common fin with the finFET pull-down transistor 112. As a result, the drive strengths of the transistors in the SRAM cell implementation shown in FIG. 6, in particular the pass-gate transistors 114,120 and the pull- down transistors 110,112 cannot easily be altered independently.
Previously several different methods have been suggested to increase the drive strength of a finFET. In a first method disclosed for example in U.S. Pat. No. 6,706,571 an additional fin parallel to the fin common with the pass-gate transistor is provided for each pull-down transistor in a SRAM cell. However, the addition of the extra fin results in an undesirable increase in area used by the SRAM cell. In a second method disclosed for example in H. Kawasaki et al “Embedded Bulk FinFET SRAM cell Technology with planar FET peripheral circuit for hp32nm node and beyond”, Symposium on VLSI Technology digest of Technical papers, 2006, the fin height of adjacent finFETs in a cell built on bulk Si is adjusted to alter the drive strength of the finFETs. However, it is difficult to apply this technique to the mass fabrication of integrated circuits and especially difficult to apply this technique to finFETs built on a SOI substrate. In a third method proposed in Z. Guo et al., “FinFET-based SRAM Design”, Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ISPLED'05), pp 2-7, 2005, the pull-down transistors are rotated by 45 degrees so that the channels are formed in the [100] plane, resulting in an improvement in the Signal Noise Margin (SNM) owing to the improved electron mobility in the [100] plane compared with the conventional [110]. However, again this technique is complex and it is difficult to apply this technique to the mass fabrication of integrated circuits.
The present inventors have realised it would be desirable to be able to selectively modify the drive strength of a finFET in a CMOS circuit or to differentiate the drive strengths of two or more finFETs in a CMOS circuit.

SUMMARY

In accordance with one aspect of the present invention, there is provided a method of fabricating a fin Field Effect Transistor (finFET), the finFET being formed on a substrate and comprising a fin formed on the substrate, a first high density doped (HDD) region and a second high density doped (HDD) region formed in the substrate at longitudinal ends of the fin and at least one gate region formed adjacent the fin, the method comprising the steps of: determining whether the finFET should have a maximum drive strength or a relatively lower drive strength; and fabricating the finFET with a first low density doped (LDD) extension region in the substrate extending from the first high density doped (HDD) region toward the gate region and a second low density doped (LDD) extension region in the substrate extending from the second high density doped (HDD) region toward the gate region where a maximum drive strength is determined; and fabricating the finFET without one or both of said LDD extension regions in the substrate when a relatively lower drive strength is determined.
In accordance with another aspect of the invention, there is provided a method of forming a circuit comprising at least a first fin Field Effect Transistor (finFET) and a second finFET, the at least first and second finFETs being formed on a substrate and comprising a fin formed on the substrate, a first high density doped (HDD) region and a second high density doped (HDD) region formed in the substrate at longitudinal ends of the fin and at least one gate region formed adjacent the fin, where the drive strength of the first finFET is selected to be higher than the drive strength of the second finFET, by forming the first finFET with at least one of a first low density doped (LDD) extension region in the substrate extending from the first HDD region toward the gate region and a second low density doped (LDD) extension region in the substrate extending from the second HDD region toward the gate region; and the drive strength of the second finFET is selected to be lower than the drive strength of the first finFET by forming the second finFET with no LDD extension regions in the substrate or with only one of said first LDD extension region or said second LDD extension region.
In accordance with a further aspect of the invention there is provided a circuit comprising at least a first and second fin Field Effect Transistors (finFET), the at least first and second finFETs being formed on a substrate and comprising a fin formed on the substrate, a first high density doped (HDD) region and a second high density doped (HDD) region formed in the substrate at longitudinal ends of the fin and at least one gate region formed adjacent the fin, wherein the first finFET has at least one of a first low density doped (LDD) extension region in the substrate extending from the first HDD region toward the gate region and a second low density doped (LDD) extension region in the substrate extending from the second HDD region toward the gate region; and the second finFET has no LDD extension regions in the substrate or has only one of said first LDD extension region or said second LDD extension region such that the drive strength of the second finFET is reduced relative to the drive strength of the first finFET.
The first FinFET may be selected or determined to have maximum drive strength and be formed with a first LDD extension region and a second LDD extension region in the substrate. The first LDD extension region may be formed in the source region of the finFET and the second LDD extension region may be formed in the drain region of the finFET.
The second FinFET may be selected or determined to have a first drive strength lower than the maximum drive strength and be formed with only a second LDD extension region in the substrate. Alternatively, the second FinFET may be selected or determined to have a second drive strength lower than the maximum drive strength and be formed with a first LDD extension region in the substrate. Further, the second FinFET may be selected or determined to have a minimum drive strength and be formed with no LDD extension regions in the substrate.
In this context it will be understood that the terms “minimum drive strength” and “maximum drive strength”, and the “first drive strength” and “second drive strength” intermediate the maximum and minimum drive strengths, are intended to refer to the variation in drive strength of a finFET achievable in accordance with the omission of the source and/or drain LDD extensions in a finFET. It is not necessary that absolute values of the drive strength of the finFET are known: instead it is intended that the drive strength of at least one finFET can be selectively modified relative to either the maximum available drive strength of a finFET having the same dimensions, or relative to another finFET in the circuit.
Advantageously the invention may be applied to finFETs sharing a common fin, such as the pass-gate and pull-down finFETs in a SRAM.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic drawing showing a typical SRAM cell circuit with 6 transistors (6-T SRAM cell);

FIG. 2 illustrates a typical implementation of the circuit shown in FIG. 1 in conventional planar CMOS technology;

FIG. 3 is a plan view of a typical finFET structure;

FIG. 4 is a longitudinal cross-section through the line A-A in FIG. 3;

FIG. 5 is a partial perspective view of the typical finFET structure shown in FIGS. 3 and 4;

FIG. 6 illustrates an exemplary implementation of the circuit of FIG. 1 using finFETS;

FIG. 7 is a plan view of a finFET structure in accordance with one embodiment of the invention;

FIG. 8 is a longitudinal cross-section through the line A-A in FIG. 7;

FIGS. 9 a) to 9 c) show the variation of drive strength of a finFET;

FIG. 10 compares simulated butterfly curves of a prior art SRAM cell and a SRAM cell implementing the present invention;

FIG. 11 shows masks showing doping layer areas up to the first metal layer (M1) overlaid on a typical 6-T SRAM layout as shown in FIG. 6;

FIG. 12 illustrates the essential steps in a typical FinFET CMOS process flow using the masks shown in FIG. 11

FIG. 13 shows masks showing doping layer areas up to the first metal layer (M1) overlaid on a typical 6-T SRAM layout as shown in FIG. 6;

FIG. 14 illustrates the essential steps in a typical FinFET CMOS process flow using the masks shown in FIG. 13

FIG. 15 shows masks showing doping layer areas up to the first metal layer (M1) overlaid on a typical 6-T SRAM layout as shown in FIG. 6;

FIG. 16 illustrates the essential steps in a typical FinFET CMOS process flow using the masks shown in FIG. 15.

DETAILED DESCRIPTION

In accordance with the invention the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension region formation in the source and/or in the drain of the finFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from finFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.
The invention will now be explained with reference to FIG. 7, which shows a plan view of a finFET structure in accordance with one embodiment of the invention, and FIG. 8, which is a longitudinal cross-section through the line A-A in FIG. 7. Corresponding reference numerals have been used for features corresponding to FIGS. 3 and 4.
In this embodiment of the invention adjacent each end of the fin are formed two high density doped (HDD) regions forming a source HDD region 140 and a drain HDD region 144 of the finFET. The source LDD extension regions 132 have been formed in the channel, extending from the source HDD region 140 towards the gate electrode(s) 136 but drain LDD extension regions have not been formed.
As indicated above, in embodiments of the invention the drain LDD extension regions or the source LDD extension regions or both may be omitted, depending upon the desired extent of the reduction in the drive strength of the transistor required. Typical reductions in the drive strength that may be obtained in an NMOS finFET by omitting the drain LDD extension region, the source LDD extension region and both the source LDD extension region and the drain LDD extension region are shown in FIGS. 9 a to 9 c respectively.
FIGS. 9 a to 9 c show a plot of the drive strength of a single fin finFET, i.e. the current flowing through the fin of the finFET, against the gate 36 voltage applied to the finFET for a drain to source voltage equal to 1 Volt. In each of FIGS. 9 a to 9 c the line 50 shows the drive strength of a first finFET having both a source LDD extension region and a drain LDD extension, for example the finFET 30 shown in FIG. 3. Therefore line 50 shows the maximum drive strength that can be obtained without changing the dimensions of the fin.
In FIG. 9 a the line 52 shows the drive strength of a finFET in accordance with an exemplary embodiment having a source LDD extension region formed therein but no drain LDD extension region formed therein, for example the finFET 130 according to the exemplary embodiment shown in FIGS. 7 and 8. As can be seen, the drive current of the finFET in this embodiment shown by line 52 is reduced with respect to the maximum drive strength shown by line 50 by up to 27%.
In FIG. 9 b the line 54 shows the drive strength of a finFET in accordance with an exemplary embodiment having a drain LDD extension region formed therein but no source LDD extension region formed therein (not shown). As can be seen, the drive current of the finFET in this embodiment shown by line 54 is reduced with respect to the maximum drive strength shown by line 50 by up to 47%.
In FIG. 9 c the line 56 shows the drive strength of a finFET in accordance with an exemplary embodiment having no source LDD extension region or drain LDD extension region formed therein(not shown). As can be seen, the drive current of the finFET in this embodiment shown by line 56 is reduced with respect to the maximum drive strength shown by line 50 by up to 63%. Line 56 shows the minimum drive strength that can be obtained without changing the dimensions of the fin.
As will be appreciated by a skilled person, the invention may be applied to any situation in which it is desired to selectively modify the drive current of a finFET transistor. Thus it can be determined during a design process whether a finFET should have a maximum drive strength or should have a relatively lower drive strength. The finFET can then be designed, and then fabricated, with or without an LDD extension region for the source and/or the drain, according to the determined relative drive strength.
The invention is particularly suitable where a differentiation between the drive currents of two or more finFET transistors within a circuit is required. In this case, the drive strength of a first finFET of a circuit can be selected to be higher that a second finFET of the circuit, and the second finFET can be formed having fewer LDD extension regions than the first finFET, and thus having a lower drive strength.
One situation in which the invention can be applied is in a SRAM cell, and therefore embodiments of the invention will now be described with reference to a SRAM cell. However a skilled person will appreciate that the invention is not limited to application in a SRAM cell.
In the exemplary embodiment of the invention applied to a SRAM cell, the drive strength of the pass-gate transistors are modified by omitting source LDD extension regions or drain LDD extension regions, in order to reduce the drive strength of the pass-gate transistor. It should be noted that in the pass-gate transistor of an SRAM, the source and drain change role depending on the state of the cell (read/write/standby), therefore we will refer to the bit line side LDD extension regions or the internal node side LDD extension regions for the pass-gate transistors instead of source and drain LDD extension regions. However, the skilled person will understand that the principles of omitting one or both of the LDD extension regions on the finFET may be applied equally to this situation.
The static noise margin is given by the drive strength ratio of the pass-gate and the pull-down transistors. In the exemplary embodiment of the invention applied to a SRAM cell, the modification of the drive strength of the pass-gate transistors by omitting the bit line side LDD extension regions or the internal node side LDD extension regions as described above and as shown in FIGS. 9 a) to 9 c) will improve the static noise margin of the cell.
The static noise margin can be illustrated by means of a SRAM cell butterfly curve. FIG. 10 shows simulated butterfly curves of a first cell with internal node LDD extension regions in the pass-gate transistors (line 62) and a second cell without internal node LDD extension regions in the pass-gate transistors (line 64). Each cell has the same pull-up, pull-down and pass-gate transistor dimensions (L_gate=50 nm; W_fin=10 nm, H_fin=60 nm). V_ddis equal to 1.
The Static Noise Margin can be represented visually by the size of the biggest square that can be inserted in the “eyes” of the butterfly curve. As is clear from FIG. 10, the static noise margin of the second cell, represented by square 66, is larger than the static noise margin of the first cell, represented by square 68.
Thus it will be apparent to a skilled person that if the drive strength of the pass-gate transistor is designed to be weaker than the drive strength of the pull-down transistor by application of the principles of the invention, the read operation of a SRAM cell will be easier and the static noise margin will increase. A skilled person can select whether or not bit line side LDD extension regions and/or the internal node side LDD extension regions for the pass-gate transistors are implanted in order to achieve the desired drive strength decrease required for the pass gate transistor. In this context it should be noted that the drive strength of the pass-gate transistor should not be made too weak. In particular, a weak pass-gate finFET drive strength will also result firstly in a degraded write margin, since the write margin is reduced if the pass gate transistor drive strength decreases with respect to the pull-up transistor, and secondly in reduced read current I_read, since the read current I_readis improved if the drive strength of both pass-gate transistor and pull-down transistor is increased.
As indicated above, the present invention is not limited to use in finFET SRAM cells, and may be applied to a wide variety of circuits using finFETs.
An exemplary finFET CMOS process flow will now be described with reference to FIGS. 11 and 12.
FIG. 11 shows masks showing doping layer areas up to the first metal layer (M1) overlaid on a typical 6-T SRAM layout as shown in FIG. 6, and FIG. 12 illustrates the essential steps in a typical finFET CMOS process flow using the masks shown in FIG. 11.
The person skilled in the art will appreciate that additional or alternative steps can also be used to effect fabrication of a CMOS circuit and such additional or alternative steps have accordingly not been discussed in detail. In particular, well and halo (pocket) implantation steps are not present in the illustrated process flow, nor are intermediate thermal anneal steps and epitaxial growth steps after spacer formation to form a raised source or drain. Typically fins are undoped so that well implantations are not necessary: however they can be added as additional mask layers.
FIG. 11 shows the mask layers used in the CMOS process flow shown in FIG. 12. Mask layer ACTIVE 70, defines the fins; mask layer POLY 72, defines the gate stack; mask layer NPLUS 74 defines the areas to be N-doped; mask layer PPLUS 76 defines the areas to be P-doped; mask layer METAL 78 defines areas of metal interconnect; and mask layer CONTACT 80 defines contact areas. It should be noted that the mask layers ACTIVE 70, POLY 72, METAL 78 and CONTACT 80 shown in FIG. 11 are positive masks, i.e. the features remain where the mask is drawn. In contrast the NPLUS 74 and PPLUS 76 masks are negative, i.e. photo resist is removed where the mask is drawn such that underlying areas are open for the formation of doped layers, for example by ion implantation.
In the exemplary finFET CMOS process flow 1000 shown in FIG. 12, firstly a SOI silicon substrate is taken 1002, and the fins are formed 1004 using the ACTIVE mask 70. The fins are typically formed from silicon. Thereafter the associated gate stacks are formed 1006 on the substrate using the POLY mask 72, and a final gate etch step carried out 1008.
Then the LDD extensions are formed. Firstly the NPLUS mask, as shown in FIG. 11, is used in step 1010 to apply photo resist patterned to form the N-doped LDD extension regions, and then the N-LDD implant step 1012 is carried out. The N-LDD implant step 1012 may use, for example, Phosphorous (P) or arsenic (A) dopants. The photo resist is removed 1014. Next the PPLUS mask, as shown in FIG. 11, is used in step 1016 to apply photo resist patterned to form the P-doped LDD extension regions, and then P-LDD implant step is carried out 1018. The P-LDD implant step may use, for example, Boron (B) or Boron Fluorine (BF₂). Then again the photo resist is removed 1020.
After formation of a spacer 1022, the HDD extension regions are formed. Firstly the NPLUS mask, as shown in FIG. 11, is used in step 1024 to apply photo resist patterned to form the N-doped HDD regions. Then the N-HDD implant step 1026, which may be for example use Phosphorous (P) or arsenic (A), is carried out. The photo resist is removed, in step 1028. Then the PPLUS mask, as shown in FIG. 11, is used to apply photo resist patterned to form the P-doped HDD regions in step 1030. Then the P-HDD implant step 1032 is carried out. The N-HDD implant step 1032 may use, for example, Boron (B) or Boron Fluorine (BF₂). Once again the photo resist is removed in step 1034. A thermal anneal process in step 1036 completes the step of forming the LDD and HDD areas. Finally a salicidation step 1038 is carried out before the end of the process.
Modifications of the finFET process flow and/or process masks to fabricate a SRAM cell in accordance with exemplary embodiments of the invention will now be described with reference to FIGS. 13-16.
In a first embodiment illustrated with reference to FIGS. 13 and 14 a finFET transistor having asymmetric LDD extension regions, as described above with reference to FIGS. 7 and 8 is formed as a pass-gate transistor in a SRAM cell. As illustrated, the pass-gate transistors only have a LDD extension region on one side of the gate, in this case only the internal node side LDD extension regions are present and the bit line side LDD extension regions are omitted.
FIG. 13 shows masks showing doping layer areas up to the first metal layer (M1) overlaid on a typical 6-T SRAM layout. Reference numerals corresponding to reference numerals in FIGS. 7 and 8 have been added to FIG. 13. FIG. 14 illustrates the essential steps in a FinFET CMOS process flow 2000 using the masks shown in FIG. 13.
Again, the person skilled in the art will appreciate that additional or alternative steps can also be used to effect fabrication of a CMOS circuit and such additional or alternative steps have accordingly not been discussed in detail. In particular, well and halo (pocket) implantation steps are not present in the illustrated process flow, nor are intermediate thermal anneal steps and epitaxial growth steps after spacer formation to form a raised source or drain. Typically fins are undoped so that well implantations are not necessary: however they can be added as additional mask layers.
The LDD extension regions are typically formed by ion implantation of impurities, either vertically or under a tilt angle. Alternatively doping techniques such as plasma doping (PLAD) can also be applied. Also co-implantations with non-dopant impurities, e.g. Germanium (Ge) or Fluorine (F) or Hydrogen (H) or helium (He), may be made.
FIG. 13 shows the mask layers used in the CMOS process flow shown in FIG. 14. Mask layer ACTIVE 70, defines the fins; mask layer POLY 72, defines the gate stack; mask layer METAL 78 defines areas of metal interconnect; and mask layer CONTACT 80 defines contact areas correspond with the same mask layers described above with reference to FIG. 11, and have therefore been given the same reference numerals. New mask layer NLDD 82 defines the areas to be N-doped; and new mask layer PLDD 84 defines the areas to be P-doped.
Again it should be noted that the mask layers ACTIVE 70, POLY 72, METAL 78 and CONTACT 80 shown in FIG. 13 are positive masks, i.e. the features remain where the mask is drawn. In contrast the NLDD 82 and PLDD 84 masks are negative, i.e. photo resist is removed where the mask is drawn such that underlying areas are open for the formation of doped layers, for example by ion implantation.
In the finFET CMOS process flow 2000 in accordance with the embodiment of the invention shown in FIG. 14, firstly a SOI silicon substrate is taken 2002, and the fins are formed 2004 using the ACTIVE mask 70. The fins are typically formed from silicon. Thereafter the associated gate stacks are formed 2006 on the substrate using the POLY mask 72, and a final gate etch step carried out 2008.
Then the LDD extension regions are formed. Firstly the NLDD mask 82, as shown in FIG. 13, is used in step 2010 to apply photo resist patterned to form the N-doped LDD extension regions, and then the N-LDD implant step 2012 is carried out. The N-LDD implant step 2012 may use, for example, Phosphorous (P) or arsenic (A) dopants. The photo resist is removed in step 2014. Next the PLDD mask 84, as shown in FIG. 13, is used in step 2016 to apply photo resist patterned to form the P-doped LDD extension regions, and then P-LDD implant step is carried out 2018. The P-LDD implant step may use, for example, Boron (B) or Boron Fluorine (BF₂). Then again the photo resist is removed 2020.
After formation of a spacer 2022, the HDD regions are formed. Firstly the NPLUS mask 74, as shown in FIG. 11, is used in step 2024 to apply photo resist patterned to form the N-doped HDD regions. Then the N-HDD implant step 2026, which may be for example use Phosphorous (P) or arsenic (A), is carried out. The photo resist is removed, in step 2028. Then the PPLUS mask 76, as shown in FIG. 11, is used to apply photo resist patterned to form the P-doped HDD regions in step 2030. Then the P-HDD implant step 2032 is carried out. The N-HDD implant step 2032 may use, for example, Boron (B) or Boron Fluorine (BF₂). Once again the photo resist is removed in step 2034. A thermal anneal process in step 2036 completes the step of forming the LDD and HDD areas. Finally a salicidation step 2038 is carried out before the end of the process.
As will be apparent from the above description, in the embodiment of the invention described with reference to FIGS. 13 and 14 two additional masks NLDD 82 and PLDD 84 are needed in addition to the masks shown in FIG. 11, but no additional process steps are required. The new masks NLDD 82 and PLDD 84 do not contain small features, and are therefore relatively inexpensive.
In a second embodiment illustrated with reference to FIGS. 15 and 16 a finFET transistor having asymmetric LDD extension regions, as described above with reference to FIGS. 7 and 8, is formed as a pass-gate transistor in a SRAM cell. As illustrated the pass-gate transistors only have a LDD extension on one side of the gate, in this case only the internal node side LDD extensions are present and the bit line side LDD extensions are omitted.
FIG. 15 shows a hard mask to be used in addition to the masks shown in FIG. 11 in the FinFET CMOS process flow 3000 shown in FIG. 16. Reference numerals corresponding to reference numerals in FIGS. 7 and 8 have been added to FIG. 15.
Again, the person skilled in the art will appreciate that additional or alternative steps can also be used to effect fabrication of a CMOS circuit and such additional or alternative steps have accordingly not been discussed in detail. In particular, well and halo (pocket) implantation steps are not present in the illustrated process flow, nor are intermediate thermal anneal steps and epitaxial growth steps after spacer formation to form a raised source or drain. Typically fins are undoped so that well implantations are not necessary: however they can be added as additional mask layers.
The LDD extension regions are typically formed by ion implantation of impurities, either vertically or under a tilt angle. Alternatively doping techniques such as plasma doping (PLAD) can also be applied. Also co-implantations with non-dopant impurities, e.g. Germanium (Ge) or Fluorine (F) or Hydrogen (H) or helium (He), may be made.
FIG. 15 shows a blocking hard mask LDD 86. The LDD mask 86 is a negative mask, so that where the mask is drawn the hard mask will be removed and the LDD extension regions formed. In addition masks shown in FIG. 11 are also used in the CMOS process flow shown in FIG. 1. Process steps corresponding to the CMOS process described above with reference to FIG. 12 or 14 will be given corresponding reference numerals.
In the finFET CMOS process flow 3000 in accordance with the embodiment of the invention shown in FIG. 16, firstly a SOI silicon substrate is taken 3002, and the fins are formed 3004 using the ACTIVE mask 70. The fins are typically formed from silicon. Thereafter the associated gate stacks are formed 3006 on the substrate using the POLY mask 72, and a final gate etch step carried out 3008.
In this CMOS process flow, firstly a hard mask layer is applied in step 3050. The hard mask may be, for example, Silicon Nitride Si₃N₄or a TEOS layer or stack of layers. Next the LDD mask 86 is used in step 3052 to apply photo resist, and then the hard mask layer is etched in step 3054. Thereafter the photo resist is removed in step 3056. These steps result in a covering of hard mask preventing formation of LDD extension regions on the bit line side of the pass-gate transistors.
Then the LDD extension regions are formed. Firstly the NPLUS mask 74 is used in step 3010 to apply photo resist patterned to form the N-doped LDD extension regions, and then the N-LDD implant step 3012 is carried out. The N-LDD implant step 3012 may use, for example, Phosphorous (P) or arsenic (A) dopants. The photo resist is removed in step 3014. Next the PPLUS mask 76 is used in step 3016 to apply photo resist patterned to form the P-doped LDD extension regions, and then P-LDD implant step is carried out 3018. The P-LDD implant step may use, for example, Boron (B) or Boron Fluorine (BF₂). Then again the photo resist is removed in step 3020, and the hard mask removed in step 3058.
After formation of a spacer 3022, the HDD regions are formed. Firstly the NPLUS mask 74, as shown in FIG. 11, is used in step 3024 to apply photo resist patterned to form the N-doped HDD regions. Then the N-HDD implant step 3026, which may be for example use Phosphorous (P) or arsenic (A), is carried out. The photo resist is removed, in step 3028. Then the PPLUS mask 76, as shown in FIG. 11, is used to apply photo resist patterned to form the P-doped HDD regions in step 3030. Then the P-HDD implant step 3032 is carried out. The N-HDD implant step 3032 may use, for example, Boron (B) or Boron Fluorine (BF₂). Once again the photo resist is removed in step 3034. A thermal anneal process in step 3036 completes the step of forming the LDD and HDD areas. Finally a salicidation step 3038 is carried out before the end of the process.
As will be apparent from the above description, in the embodiment of the invention described with reference to FIGS. 15 and 16 only one additional mask namely the LDD mask 86 is needed in addition to the masks shown in FIG. 11, but additional process steps 3050-3058 are required. The new LDD mask 86 does not contain small features, and is therefore relatively inexpensive.
Thus in the embodiments of the invention described with reference to FIGS. 13-16 the LDD extension region is formed in the pass gate transistors only on the side in contact with the internal node. Clearly, in a first alternative the LDD extension region of the pass gate transistors on the side in contact with the bit line may be formed and the LDD extension region on the side in contact with the internal node may be omitted or in a second alternative both the LDD extension regions of the pass gate transistors on the side in contact with the bit line and on the side in contact with the internal node, may be omitted using suitable masks, depending on the required reduction in the drive strength of the transistor.
The skilled person will appreciate that the process flows described herein and the illustrated masks are illustrative only and changes may be made thereto without departing from the scope of the invention. In addition other methods of forming a finFET transistor without one or more LDD extensions are intended to be included within the scope of the invention.
Thus there is provided a method for the selective modification of the drive strength of a FinFET transistor, and in particular a method in which the drive strength of a finFET transistor can be selectively reduced, by omitting an LDD extension region formation in the source and/or in the drain of the FinFET.
One application of this method is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Claims

1. A device comprising:

a first transistor formed on a substrate, wherein the first transistor includes an active region; and

a second transistor formed on the substrate, wherein the first and second transistors share the active region, and

wherein the first transistor is without any low density doped (LDD) extension regions in the substrate and wherein the second transistor is associated with a first LDD extension region formed in the substrate such that a drive strength of the second transistor is greater relative to a drive strength of the first transistor.

2. The device of claim 1, further comprising a first high density doped (HDD) region associated with the second transistor and wherein the first LDD extension region extends from the first HDD region.

3. The device of claim 2, further comprising a second LDD extension region associated with the second transistor.

4. The device of claim 3, further comprising a second HDD region associated with the second transistor and wherein the second LLD extension region extends from the second HDD region.

5. The device of claim 1, wherein the first transistor is a pass gate transistor of a SRAM cell.

6. The device of claim 5, wherein the second transistor is a pull down transistor of the SRAM cell.

7. The device of claim 1, further comprising a third transistor formed on the substrate, wherein a drive strength of the third transistor is greater relative to the drive strength of the second transistor.

8. A device comprising:

a first transistor formed on a substrate, wherein the first transistor includes an active region;

a second transistor formed on the substrate, wherein the first transistor and the second transistor share the active region; and

a first high density doped (HDD) region and a second high density doped (HDD) region formed in the substrate, wherein the first transistor is without a first low density doped (LDD) extension region in the substrate extending from the first HDD region or a second LDD extension region in the substrate extending from the second HDD region toward the gate region such that such that a drive strength of the first transistor is reduced relative to a drive strength of the second transistor associated with at least one of the first and second LDD extension regions.

9. The device of claim 8, wherein the first transistor is without the first and second LDD extension regions.

10. The device of claim 8, wherein the first transistor is without any LDD extension regions.

11. The device of claim 8, wherein the second transistor is associated with both the first and second LDD extension regions.

12. The device of claim 8, wherein the device a complementary metal oxide semiconductor (CMOS) device.

13. The device of claim 8, wherein the first transistor is a pass gate transistor of a SRAM cell, and

wherein the second transistor is a pull down transistor of the SRAM cell.

14. The device of claim 8, further comprising a third transistor formed on the substrate, wherein a drive strength of the third transistor is greater relative to the drive strength of the second transistor.

15. A method comprising:

forming a high density doped (HDD) region in a semiconductor substrate;

forming a low density doped (LDD) extension region in the semiconductor substrate, wherein the LDD extension region interfaces with the HDD region;

forming a first transistor on the semiconductor substrate, wherein the first transistor includes an active region, and wherein the first transistor is without the LDD extension region in the semiconductor; and

forming a second transistor on the semiconductor substrate, wherein the first and second transistors share the active region, and wherein the second transistor is associated with the LDD extension region such that a drive strength of the second transistor is greater relative to a drive strength of the first transistor.

16. The method of claim 37, wherein the second transistor is not associated with any other LDD extension region.

17. The method of claim 15, further comprising forming another HDD region in the semiconductor substrate, and

forming another LDD extension region in the semiconductor substrate extending from the another HDD region toward the gate region, and

wherein the second transistor is associated with the another LDD extension region.

18. The method of claim 15, wherein the first transistor is a pass gate transistor of a SRAM cell, and

wherein the second transistor is a pull down transistor of the SRAM cell.

19. The method of claim 15, wherein the first transistor is without any LDD extension regions.

20. The method of claim 15, further comprising forming a third transistor on the substrate, wherein a drive strength of the third transistor is greater relative to the drive strength of the second transistor.