US20150251900A1 - Semiconductor arrangement with stress release configuration - Google Patents
Semiconductor arrangement with stress release configuration Download PDFInfo
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- US20150251900A1 US20150251900A1 US14/200,075 US201414200075A US2015251900A1 US 20150251900 A1 US20150251900 A1 US 20150251900A1 US 201414200075 A US201414200075 A US 201414200075A US 2015251900 A1 US2015251900 A1 US 2015251900A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0045—Packages or encapsulation for reducing stress inside of the package structure
- B81B7/0054—Packages or encapsulation for reducing stress inside of the package structure between other parts not provided for in B81B7/0048 - B81B7/0051
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
- B81B7/0019—Protection against thermal alteration or destruction
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00325—Processes for packaging MEMS devices for reducing stress inside of the package structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/008—MEMS characterised by an electronic circuit specially adapted for controlling or driving the same
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Definitions
- CMOS Complementary metal-oxide-semiconductor
- Many integrated circuits or semiconductor arrangements thus comprise CMOS wafers or at least one or more portions of a wafer whereon CMOS technology is implemented.
- Heat from a CMOS wafer can damage other portions of a semiconductor arrangement.
- a semiconductor arrangement can also be damaged from stress, such as printed circuit board stress. For example, stress-induced solder joint failure can occur from such stress.
- FIG. 1 is a flow diagram illustrating a method of forming a semiconductor arrangement, in accordance with some embodiments.
- FIG. 2 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 3 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 4 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 5 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 6 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 7 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 8 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 9 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 10A is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 10B is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 11 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- FIG. 12 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- FIG. 13 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- FIG. 14A is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- FIG. 14B is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- FIG. 14C is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- FIG. 14D is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- FIG. 14E is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments.
- MEMS microelectromechanical systems
- CMOS complementary metal-oxide-semiconductor
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a semiconductor arrangement comprises a cap wafer.
- the cap wafer comprises a first vacuum chamber and a second vacuum chamber.
- the second vacuum chamber is configured as a first spring structure.
- the semiconductor arrangement comprises a microelectromechanical systems (MEMS) wafer formed over the cap wafer.
- the MEMS wafer comprises a high vacuum chamber coupled to the first vacuum chamber.
- the high vacuum chamber is configured as a sensing gap.
- the semiconductor arrangement comprises a complementary metal-oxide-semiconductor (CMOS) wafer formed over the MEMS wafer.
- the CMOS wafer comprises an ambient pressure chamber connected to the second vacuum chamber through a second spring structure.
- the first spring structure and the second spring structure are operable based upon deformation of the sensing gap.
- at least one of the first spring structure or the second spring structure move, such as compress, to release stress that occurs from movement of the semiconductor arrangement, such as movement of a membrane of the MEMS wafer with respect to a poly layer of the MEMS wafer that deforms the sensing gap.
- movement and deformation occurs from a pressure difference between the high vacuum chamber, formed between the membrane and the poly layer, and the ambient pressure chamber connected to ambient air.
- the ambient pressure chamber is configured as a thermal insulation air gap to insulate the MEMS wafer from heat originating from the CMOS wafer. In this way, CMOS outgassing, stress, and thermal damage are mitigated for the semiconductor arrangement.
- a method 100 of forming a semiconductor arrangement is illustrated in FIG. 1 , and one or more semiconductor arrangements formed by such a methodology are illustrated in FIGS. 2-14E .
- a MEMS wafer 202 of a semiconductor arrangement 200 is formed, as illustrated in FIG. 2 .
- a silicon-on-insulator (SOI) wafer comprising a first silicon layer 204 , a first oxide layer 206 , and a second silicon layer 208 is used to form the MEMS wafer 202 , as illustrated in FIG. 2 .
- a second oxide layer 210 is deposited on the on the second silicon layer 208 .
- oxide seam trench formation is performed to form one or more trenches, such as a first trench 212 , a second trench 214 , a third trench 216 , a fourth trench 218 , or other trenches, into the second oxide layer 210 .
- a poly layer 302 is formed on the second oxide layer 210 of the MEMS wafer 202 , as illustrated in FIG. 3 .
- the poly layer 302 is formed by a deposition process.
- the poly layer 302 has a thickness between about 0.5 um and about 1.5 um.
- CMP chemical mechanical polishing
- the poly layer 302 is patterned to form one or more trenches, such as a first trench 304 , a second trench 306 , a third trench 308 , or other trenches.
- a third oxide layer 402 is formed on the poly layer 302 , as illustrated in FIG. 4 .
- the third oxide layer 402 is formed by an oxide deposition process.
- an annealing process is performed after the oxide deposition process.
- the oxide deposition process fills the first trench 304 , the second trench 306 , and the third trench 308 with poly.
- a cavity etch 512 is performed to create one or more cavities into the third oxide layer 402 , as illustrated in FIG. 5 .
- the cavity etch 512 forms a first cavity 502 , a second cavity 504 , a third cavity 506 , a fourth cavity 508 , a fifth cavity 510 , or other cavities into the third oxide layer 402 .
- the MEMS wafer 202 is bonded with a cap wafer 608 , as illustrated in FIG. 6 .
- a fusion bonding technique is performed to fuse the MEMS wafer 202 to the cap wafer 608 .
- an annealing process is performed after the fusion bonding technique.
- the cap wafer 608 comprises a silicon layer 606 .
- the cap wafer 608 comprises one or more trenches formed through the silicon layer 606 as vacuum chambers.
- a first vacuum chamber 604 is formed from a first trench.
- a second vacuum chamber 602 is formed from a second trench.
- the first vacuum chamber 604 has a first depth that is less than a second depth of the second vacuum chamber 602 .
- a first silicon etch such as a relatively slower etch using a relatively smaller opening, is performed to form one or more trenches having the first depth, such as the first trench formed as the first vacuum chamber 604 .
- a second silicon etch such as a relatively faster etch using a relatively larger opening, is performed to form one or more trenches having the second depth, such as the second trench formed as the second vacuum chamber 602 .
- the first silicon layer 204 is removed 702 from the MEMS wafer 202 , as illustrated in FIG. 7 .
- a grinding process is performed to remove the first silicon layer 204 .
- a back etching process is performed to remove the first silicon layer 204 .
- CMP is performed after the back etching process.
- One or more pattern release holes are formed through the first oxide layer 206 , the second silicon layer 208 , and the second oxide layer 210 , as illustrated in FIG. 8 .
- a pattern release hole comprises a sub-micrometer width release hole or trench that is etched to a depth suitable for controlling vHF processing time, such as to a depth where about a few micrometers of oxide layer remain below the pattern release hole.
- the first oxide layer 206 and a portion of the second oxide layer 210 are removed, as illustrated in FIG. 9 .
- an etch 902 such as a vapor hydrogen fluoride (VHF) release, a dry etch, or acid etch, is performed to remove the portion of the second oxide layer 210 to form a high vacuum chamber 906 .
- the etch 902 is performed to form a connection 910 between the high vacuum chamber 906 and the first vacuum chamber 604 .
- a portion of the poly layer 302 such as a poly layer 908 , is formed between the cap wafer 608 and the high vacuum chamber 906 .
- the poly layer 908 is formed between the third oxide layer 402 and the high vacuum chamber 906 .
- a portion of the second silicon layer 208 is formed as a membrane 904 over the poly layer 908 .
- the high vacuum chamber is formed between the membrane 904 and the poly layer 908 , such that the membrane can move with respect to the poly layer 908 .
- the first pattern release hole 810 , the second pattern release hole 812 , or other pattern release holes are filled with a metal, as illustrated in FIG. 10A .
- the first pattern release hole 810 is filled with metal to form a first metal structure 1002 .
- the second pattern release hole 812 is filled with metal to form a second metal structure 1004 .
- the high vacuum chamber 906 is sealed, such as from ambient air.
- the metal is sputtered onto the MEMS wafer 202 .
- the metal is aluminum.
- An etching process 1006 such as a photo etching process, is performed to remove a first side portion 1008 and a second side portion 1010 of the MEMS wafer 202 .
- the etching process 1006 is performed to remove the first side portion 1008 and the second side portion 1010 , and then a metal layer 1020 is formed over the MEMS wafer 202 , as illustrated in FIG. 10B .
- the high vacuum chamber 806 is sealed, such as from ambient air.
- the metal layer 1020 is deposited to a thickness between about 3.5 um to about 4.5 um.
- the metal layer 1020 is patterned to remove a portion of the metal layer 1020 , as illustrated in FIG. 11 .
- One or more stress release structures such as a first stress release structure 1102 and a second stress release structure 1104 , are formed through the metal layer 1020 , the poly layer 302 , and the third oxide layer 402 .
- a CMOS wafer 1202 is bonded to the MEMS wafer 202 , as illustrated in FIG. 12 .
- a eutectic bonding process is performed to bond the CMOS wafer 1202 to the MEMS wafer 202 .
- the eutectic bonding process utilizes pressure and temperature for bonding.
- a first metal structure 1210 of the CMOS wafer 1202 such as germanium metal over a tungsten plug, is bonded to a second metal structure 1208 of the MEMS wafer 202 , such as an aluminum structure.
- the CMOS wafer 1202 comprises a silicon layer 1206 .
- an ambient pressure chamber 1204 is formed between the CMOS wafer 1202 and the MEMS wafer 202 .
- a backside grinding process is performed to remove a portion of the silicon layer 606 of the cap wafer 608 .
- the backside grinding process is performed to control a thickness of the silicon layer 606 under the second chamber 602 , such as to a thickness between about 15 um to about 35 um.
- the thickness of silicon under the second chamber 602 affects a softness/hardness of a first spring structure for the semiconductor arrangement 200 that is to be formed by the second chamber 602 and the silicon under the second chamber 602 (e.g., a first spring structure 1406 of FIG. 14A ).
- a portion of the silicon layer 1206 of the CMOS wafer 1202 is removed, such as through a grinding process, for formation of a through-silicon via (TSV) structure 1306 on the CMOS wafer 1202 , as illustrated in FIG. 13 .
- TSV through-silicon via
- the TSV structure 1306 is connected to a metal connection 1304 , such as a solder ball.
- the second vacuum chamber 602 is configured as the first spring structure 1406 for the semiconductor arrangement 200 , as illustrated in FIG. 14A .
- an ambient air pressure channel 1402 is formed between the MEMS wafer 202 and the cap wafer 608 , as illustrated in FIG. 14A .
- an ambient air pressure channel 1422 is formed through the second vacuum chamber 602 to ambient air, as illustrated in FIG. 14B .
- a deep reactive-ion etching (DRIE) process is performed on the cap wafer 608 to form the ambient air pressure channel 1422 .
- a VHF release for oxide is performed through the ambient air pressure channel 1422 after the DRIE process.
- the ambient pressure chamber 1204 is connected, such as through the ambient air pressure channel 1402 of FIG. 14A or the ambient air pressure channel 1422 of FIG. 14B , to ambient air through a second spring structure 1404 .
- the second spring structure 1404 comprises a poly portion of the poly layer 302 and a metal portion of the metal layer 1020 .
- the ambient pressure chamber 1204 is configured as a thermal insulation air gap between the CMOS wafer 1202 and the MEMS wafer 202 . The thermal insulation air gap protects the MEMS wafer 202 from heat originating from the CMOS wafer 1202 .
- the high vacuum chamber 906 is configured as a sensing gap 1408 , as illustrated in FIG. 14A .
- the sensing gap 1408 is configured to deform based upon movement of the membrane 904 with respect to the poly layer 908 .
- a first sensing plate is coupled to the membrane 904 and the second sensing plate is coupled to the poly layer 908 .
- the first sensing plate and the second sensing plate are configured to provide capacitance information used to determine deformation of the sensing gap 1408 .
- the first spring structure 1406 and the second spring structure 1404 are configured to operate based upon deformation of the sensing gap 1408 . At least one of the first spring structure 1406 or the second spring structure 1404 move in response to deformation of the sensing gap 1408 to reduce stress resulting from movement of the membrane 904 with respect to the poly layer 908 .
- the first spring structure 1406 of the second vacuum chamber 602 is positioned in a default location within the cap wafer 608 based upon a default deformation constraint, as illustrated in FIGS. 14A and 14B . In some embodiments, the first spring structure 1406 of the second vacuum chamber 602 is positioned in a first constrained location within the cap wafer 608 based upon a first deformation constraint, as illustrated in FIG. 14C . In some embodiments, the first spring structure 1406 of the second vacuum chamber 602 is positioned in a second constrained location within the cap wafer 608 based upon a second deformation constraint, as illustrated in FIG. 14D .
- the first spring structure 1404 is formed between the high vacuum chamber 1204 and the second spring structure 1406 , as illustrated in FIG. 14D .
- the semiconductor arrangement 200 comprises a second spring structure 1404 a , as illustrated in FIG. 14E .
- the second spring structure 1404 a comprises at least one of a poly portion of the poly layer 302 , an oxide portion of the second oxide layer 210 , or a silicon portion of the second silicon layer 208 .
- At least one of the first spring structure 1406 of FIGS. 14A-14D , the second spring structure 1404 of FIGS. 14A-14D , or the second spring structure 1404 a of FIG. 14E mitigate stress due to movement of the membrane 904 with respect to the poly layer 908 .
- Such spring structures operate responsive to deformation of the sensing gap 1408 within the high vacuum chamber 906 .
- the ambient pressure chamber 1204 is configured as the thermal insulation air gap to protect the MEMS wafer 202 from heat originating from the CMOS wafer 1202 . In this way, CMOS outgassing, stress, and thermal damage are mitigated.
- layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments.
- etching techniques such as etching techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques such as magnetron or ion beam sputtering
- growth techniques such as thermal growth or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), for example.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- ALD atomic layer deposition
- first,” “second,” and/or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc.
- a first object and a second object generally correspond to object A and object B or two different or two identical objects or the same object.
- exemplary is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous.
- “or” is intended to mean an inclusive “or” rather than an exclusive “or”.
- “a” and “an” as used in this application are generally to be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form.
- at least one of A and B or the like generally means A or B or both A and B.
- a semiconductor arrangement comprising a cap wafer.
- the cap wafer comprises a first vacuum chamber and a second vacuum chamber.
- the second vacuum chamber is configured as a first spring structure.
- the semiconductor arrangement comprises a microelectromehcanimal systems (MEMS) wafer formed over the cap wafer.
- the MEMS wafer comprises a high vacuum chamber coupled to the first vacuum chamber.
- the high vacuum chamber is configured as a sensing gap.
- the semiconductor arrangement comprises a complementary metal-oxide-semiconductor (CMOS) wafer that is formed over the MEMS wafer.
- the CMOS wafer comprises an ambient pressure chamber connected to the second vacuum chamber through a second spring structure.
- the first spring structure and the second spring structure are operable based upon deformation of the sensing gap.
- a semiconductor arrangement comprising a cap wafer.
- the cap wafer comprises a first vacuum chamber and a second vacuum chamber.
- the second vacuum chamber is configured as a first spring structure.
- the semiconductor arrangement comprises a microelectromehcanimal systems (MEMS) wafer formed over the cap wafer.
- the MEMS wafer comprises a high vacuum chamber, a poly layer, an oxide layer, and a silicon layer.
- the high vacuum chamber is configured as a sensing gap.
- the semiconductor arrangement comprises a complementary metal-oxide-semiconductor (CMOS) wafer that is formed over the MEMS wafer.
- the CMOS wafer comprises an ambient pressure chamber connected to the second vacuum chamber through a second spring structure.
- the first spring structure and the second spring structure are operable based upon deformation of the sensing gap.
- the second spring structure comprises at least one of a poly portion of the poly layer, an oxide portion of the oxide layer, or a silicon portion of the silicon layer.
- a method for forming a semiconductor arrangement comprises forming a microelectromehcanimal systems (MEMS) wafer comprising a high vacuum chamber configured as a sensing gap.
- the MEMS wafer is bonded to a cap wafer comprising a first vacuum chamber and a second vacuum chamber.
- the second vacuum chamber is configured as a first spring structure.
- the high vacuum chamber is coupled to the first vacuum chamber.
- a complementary metal-oxide-semiconductor (CMOS) is bonded to the MEMS wafer.
- An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer.
- the ambient pressure chamber is connected to ambient air through a second spring structure.
- the first spring structure and the second spring structure are operable based upon deformation of the sensing gap.
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Abstract
Description
- Complementary metal-oxide-semiconductor (CMOS) is a technology used in constructing integrated circuits, such as image sensors, data converters, communication modules, etc. Many integrated circuits or semiconductor arrangements thus comprise CMOS wafers or at least one or more portions of a wafer whereon CMOS technology is implemented. Heat from a CMOS wafer, such as from outgassing, can damage other portions of a semiconductor arrangement. A semiconductor arrangement can also be damaged from stress, such as printed circuit board stress. For example, stress-induced solder joint failure can occur from such stress.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 is a flow diagram illustrating a method of forming a semiconductor arrangement, in accordance with some embodiments. -
FIG. 2 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments. -
FIG. 3 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments. -
FIG. 4 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments. -
FIG. 5 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer, in accordance with some embodiments. -
FIG. 6 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 7 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 8 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 9 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 10A is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 10B is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 11 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer, in accordance with some embodiments. -
FIG. 12 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. -
FIG. 13 is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. -
FIG. 14A is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. -
FIG. 14B is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. -
FIG. 14C is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. -
FIG. 14D is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. -
FIG. 14E is an illustration of a semiconductor arrangement comprising a microelectromechanical systems (MEMS) wafer bonded to a cap wafer and a complementary metal-oxide-semiconductor (CMOS) wafer, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. In some embodiments, a semiconductor arrangement comprises a cap wafer. The cap wafer comprises a first vacuum chamber and a second vacuum chamber. The second vacuum chamber is configured as a first spring structure. The semiconductor arrangement comprises a microelectromechanical systems (MEMS) wafer formed over the cap wafer. The MEMS wafer comprises a high vacuum chamber coupled to the first vacuum chamber. The high vacuum chamber is configured as a sensing gap. The semiconductor arrangement comprises a complementary metal-oxide-semiconductor (CMOS) wafer formed over the MEMS wafer. The CMOS wafer comprises an ambient pressure chamber connected to the second vacuum chamber through a second spring structure. The first spring structure and the second spring structure are operable based upon deformation of the sensing gap. In some embodiments, at least one of the first spring structure or the second spring structure move, such as compress, to release stress that occurs from movement of the semiconductor arrangement, such as movement of a membrane of the MEMS wafer with respect to a poly layer of the MEMS wafer that deforms the sensing gap. Such movement and deformation occurs from a pressure difference between the high vacuum chamber, formed between the membrane and the poly layer, and the ambient pressure chamber connected to ambient air. The ambient pressure chamber is configured as a thermal insulation air gap to insulate the MEMS wafer from heat originating from the CMOS wafer. In this way, CMOS outgassing, stress, and thermal damage are mitigated for the semiconductor arrangement.
- A
method 100 of forming a semiconductor arrangement is illustrated inFIG. 1 , and one or more semiconductor arrangements formed by such a methodology are illustrated inFIGS. 2-14E . At 102, a MEMS wafer 202 of asemiconductor arrangement 200 is formed, as illustrated inFIG. 2 . In some embodiments, a silicon-on-insulator (SOI) wafer comprising afirst silicon layer 204, afirst oxide layer 206, and asecond silicon layer 208 is used to form theMEMS wafer 202, as illustrated inFIG. 2 . Asecond oxide layer 210 is deposited on the on thesecond silicon layer 208. In some embodiments, oxide seam trench formation is performed to form one or more trenches, such as afirst trench 212, asecond trench 214, a third trench 216, afourth trench 218, or other trenches, into thesecond oxide layer 210. - A
poly layer 302 is formed on thesecond oxide layer 210 of theMEMS wafer 202, as illustrated inFIG. 3 . In some embodiments, thepoly layer 302 is formed by a deposition process. In some embodiments, thepoly layer 302 has a thickness between about 0.5 um and about 1.5 um. In some embodiments, chemical mechanical polishing (CMP) is performed on thepoly layer 302. In some embodiments, thepoly layer 302 is patterned to form one or more trenches, such as afirst trench 304, asecond trench 306, athird trench 308, or other trenches. - A
third oxide layer 402 is formed on thepoly layer 302, as illustrated inFIG. 4 . In some embodiments, thethird oxide layer 402 is formed by an oxide deposition process. In some embodiments, an annealing process is performed after the oxide deposition process. In some embodiments, the oxide deposition process fills thefirst trench 304, thesecond trench 306, and thethird trench 308 with poly. - A
cavity etch 512 is performed to create one or more cavities into thethird oxide layer 402, as illustrated inFIG. 5 . In some embodiment, thecavity etch 512 forms afirst cavity 502, asecond cavity 504, athird cavity 506, afourth cavity 508, afifth cavity 510, or other cavities into thethird oxide layer 402. - At 104, the
MEMS wafer 202 is bonded with acap wafer 608, as illustrated inFIG. 6 . In some embodiments, a fusion bonding technique is performed to fuse theMEMS wafer 202 to thecap wafer 608. In some embodiments, an annealing process is performed after the fusion bonding technique. Thecap wafer 608 comprises asilicon layer 606. Thecap wafer 608 comprises one or more trenches formed through thesilicon layer 606 as vacuum chambers. In some embodiments, afirst vacuum chamber 604 is formed from a first trench. Asecond vacuum chamber 602 is formed from a second trench. In some embodiments, thefirst vacuum chamber 604 has a first depth that is less than a second depth of thesecond vacuum chamber 602. In some embodiments, a first silicon etch, such as a relatively slower etch using a relatively smaller opening, is performed to form one or more trenches having the first depth, such as the first trench formed as thefirst vacuum chamber 604. A second silicon etch, such as a relatively faster etch using a relatively larger opening, is performed to form one or more trenches having the second depth, such as the second trench formed as thesecond vacuum chamber 602. - The
first silicon layer 204 is removed 702 from theMEMS wafer 202, as illustrated inFIG. 7 . In some embodiments, a grinding process is performed to remove thefirst silicon layer 204. In some embodiments, a back etching process is performed to remove thefirst silicon layer 204. In some embodiments, CMP is performed after the back etching process. - One or more pattern release holes, such as a first
pattern release hole 810 and a secondpattern release hole 812, are formed through thefirst oxide layer 206, thesecond silicon layer 208, and thesecond oxide layer 210, as illustrated inFIG. 8 . In some embodiments, a pattern release hole comprises a sub-micrometer width release hole or trench that is etched to a depth suitable for controlling vHF processing time, such as to a depth where about a few micrometers of oxide layer remain below the pattern release hole. - The
first oxide layer 206 and a portion of thesecond oxide layer 210 are removed, as illustrated inFIG. 9 . In some embodiments, anetch 902, such as a vapor hydrogen fluoride (VHF) release, a dry etch, or acid etch, is performed to remove the portion of thesecond oxide layer 210 to form ahigh vacuum chamber 906. Theetch 902 is performed to form aconnection 910 between thehigh vacuum chamber 906 and thefirst vacuum chamber 604. A portion of thepoly layer 302, such as apoly layer 908, is formed between thecap wafer 608 and thehigh vacuum chamber 906. In some embodiments, thepoly layer 908 is formed between thethird oxide layer 402 and thehigh vacuum chamber 906. A portion of thesecond silicon layer 208 is formed as amembrane 904 over thepoly layer 908. In some embodiments, the high vacuum chamber is formed between themembrane 904 and thepoly layer 908, such that the membrane can move with respect to thepoly layer 908. - In some embodiments, the first
pattern release hole 810, the secondpattern release hole 812, or other pattern release holes are filled with a metal, as illustrated inFIG. 10A . In some embodiments, the firstpattern release hole 810 is filled with metal to form afirst metal structure 1002. The secondpattern release hole 812 is filled with metal to form asecond metal structure 1004. In this way, thehigh vacuum chamber 906 is sealed, such as from ambient air. In some embodiments, the metal is sputtered onto theMEMS wafer 202. In some embodiments, the metal is aluminum. Anetching process 1006, such as a photo etching process, is performed to remove afirst side portion 1008 and asecond side portion 1010 of theMEMS wafer 202. - In some embodiments, the
etching process 1006 is performed to remove thefirst side portion 1008 and thesecond side portion 1010, and then ametal layer 1020 is formed over theMEMS wafer 202, as illustrated inFIG. 10B . In this way, the high vacuum chamber 806 is sealed, such as from ambient air. In some embodiments, themetal layer 1020 is deposited to a thickness between about 3.5 um to about 4.5 um. Themetal layer 1020 is patterned to remove a portion of themetal layer 1020, as illustrated inFIG. 11 . One or more stress release structures, such as a firststress release structure 1102 and a secondstress release structure 1104, are formed through themetal layer 1020, thepoly layer 302, and thethird oxide layer 402. - At 106, a
CMOS wafer 1202 is bonded to theMEMS wafer 202, as illustrated inFIG. 12 . In some embodiments, a eutectic bonding process is performed to bond theCMOS wafer 1202 to theMEMS wafer 202. In some embodiments, the eutectic bonding process utilizes pressure and temperature for bonding. In some embodiments, afirst metal structure 1210 of theCMOS wafer 1202, such as germanium metal over a tungsten plug, is bonded to asecond metal structure 1208 of theMEMS wafer 202, such as an aluminum structure. In some embodiments, theCMOS wafer 1202 comprises asilicon layer 1206. At 108, anambient pressure chamber 1204 is formed between theCMOS wafer 1202 and theMEMS wafer 202. In some embodiments, a backside grinding process is performed to remove a portion of thesilicon layer 606 of thecap wafer 608. In some embodiments, the backside grinding process is performed to control a thickness of thesilicon layer 606 under thesecond chamber 602, such as to a thickness between about 15 um to about 35 um. The thickness of silicon under thesecond chamber 602 affects a softness/hardness of a first spring structure for thesemiconductor arrangement 200 that is to be formed by thesecond chamber 602 and the silicon under the second chamber 602 (e.g., afirst spring structure 1406 ofFIG. 14A ). - In some embodiments, a portion of the
silicon layer 1206 of theCMOS wafer 1202 is removed, such as through a grinding process, for formation of a through-silicon via (TSV)structure 1306 on theCMOS wafer 1202, as illustrated inFIG. 13 . In some embodiments, theTSV structure 1306 is connected to ametal connection 1304, such as a solder ball. - In some embodiments, the
second vacuum chamber 602 is configured as thefirst spring structure 1406 for thesemiconductor arrangement 200, as illustrated inFIG. 14A . In some embodiments, an ambientair pressure channel 1402 is formed between theMEMS wafer 202 and thecap wafer 608, as illustrated inFIG. 14A . In some embodiments, an ambientair pressure channel 1422 is formed through thesecond vacuum chamber 602 to ambient air, as illustrated inFIG. 14B . In some embodiments, a deep reactive-ion etching (DRIE) process is performed on thecap wafer 608 to form the ambientair pressure channel 1422. In some embodiments, a VHF release for oxide is performed through the ambientair pressure channel 1422 after the DRIE process. - At 110, the
ambient pressure chamber 1204 is connected, such as through the ambientair pressure channel 1402 ofFIG. 14A or the ambientair pressure channel 1422 ofFIG. 14B , to ambient air through asecond spring structure 1404. In some embodiments, thesecond spring structure 1404 comprises a poly portion of thepoly layer 302 and a metal portion of themetal layer 1020. In some embodiments, theambient pressure chamber 1204 is configured as a thermal insulation air gap between theCMOS wafer 1202 and theMEMS wafer 202. The thermal insulation air gap protects theMEMS wafer 202 from heat originating from theCMOS wafer 1202. - The
high vacuum chamber 906 is configured as asensing gap 1408, as illustrated inFIG. 14A . In some embodiments, thesensing gap 1408 is configured to deform based upon movement of themembrane 904 with respect to thepoly layer 908. In some embodiments, a first sensing plate is coupled to themembrane 904 and the second sensing plate is coupled to thepoly layer 908. The first sensing plate and the second sensing plate are configured to provide capacitance information used to determine deformation of thesensing gap 1408. Thefirst spring structure 1406 and thesecond spring structure 1404 are configured to operate based upon deformation of thesensing gap 1408. At least one of thefirst spring structure 1406 or thesecond spring structure 1404 move in response to deformation of thesensing gap 1408 to reduce stress resulting from movement of themembrane 904 with respect to thepoly layer 908. - In some embodiments, the
first spring structure 1406 of thesecond vacuum chamber 602 is positioned in a default location within thecap wafer 608 based upon a default deformation constraint, as illustrated inFIGS. 14A and 14B . In some embodiments, thefirst spring structure 1406 of thesecond vacuum chamber 602 is positioned in a first constrained location within thecap wafer 608 based upon a first deformation constraint, as illustrated inFIG. 14C . In some embodiments, thefirst spring structure 1406 of thesecond vacuum chamber 602 is positioned in a second constrained location within thecap wafer 608 based upon a second deformation constraint, as illustrated inFIG. 14D . In some embodiments, thefirst spring structure 1404 is formed between thehigh vacuum chamber 1204 and thesecond spring structure 1406, as illustrated inFIG. 14D . In some embodiments, thesemiconductor arrangement 200 comprises asecond spring structure 1404 a, as illustrated inFIG. 14E . Thesecond spring structure 1404 a comprises at least one of a poly portion of thepoly layer 302, an oxide portion of thesecond oxide layer 210, or a silicon portion of thesecond silicon layer 208. - At least one of the
first spring structure 1406 ofFIGS. 14A-14D , thesecond spring structure 1404 ofFIGS. 14A-14D , or thesecond spring structure 1404 a ofFIG. 14E mitigate stress due to movement of themembrane 904 with respect to thepoly layer 908. Such spring structures operate responsive to deformation of thesensing gap 1408 within thehigh vacuum chamber 906. Theambient pressure chamber 1204 is configured as the thermal insulation air gap to protect theMEMS wafer 202 from heat originating from theCMOS wafer 1202. In this way, CMOS outgassing, stress, and thermal damage are mitigated. - Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated by one skilled in the art having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments.
- It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers features, elements, etc. mentioned herein, such as etching techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques such as magnetron or ion beam sputtering, growth techniques, such as thermal growth or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), for example.
- Further, unless specified otherwise, “first,” “second,” and/or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first object and a second object generally correspond to object A and object B or two different or two identical objects or the same object.
- Moreover, “exemplary” is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. As used herein, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application are generally to be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B or the like generally means A or B or both A and B. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to “comprising”.
- Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.
- According to an aspect of the instant disclosure, a semiconductor arrangement is provided. The semiconductor arrangement comprises a cap wafer. The cap wafer comprises a first vacuum chamber and a second vacuum chamber. The second vacuum chamber is configured as a first spring structure. The semiconductor arrangement comprises a microelectromehcanimal systems (MEMS) wafer formed over the cap wafer. The MEMS wafer comprises a high vacuum chamber coupled to the first vacuum chamber. The high vacuum chamber is configured as a sensing gap. The semiconductor arrangement comprises a complementary metal-oxide-semiconductor (CMOS) wafer that is formed over the MEMS wafer. The CMOS wafer comprises an ambient pressure chamber connected to the second vacuum chamber through a second spring structure. The first spring structure and the second spring structure are operable based upon deformation of the sensing gap.
- According to an aspect of the instant disclosure, a semiconductor arrangement is provided. The semiconductor arrangement comprises a cap wafer. The cap wafer comprises a first vacuum chamber and a second vacuum chamber. The second vacuum chamber is configured as a first spring structure. The semiconductor arrangement comprises a microelectromehcanimal systems (MEMS) wafer formed over the cap wafer. The MEMS wafer comprises a high vacuum chamber, a poly layer, an oxide layer, and a silicon layer. The high vacuum chamber is configured as a sensing gap. The semiconductor arrangement comprises a complementary metal-oxide-semiconductor (CMOS) wafer that is formed over the MEMS wafer. The CMOS wafer comprises an ambient pressure chamber connected to the second vacuum chamber through a second spring structure. The first spring structure and the second spring structure are operable based upon deformation of the sensing gap. The second spring structure comprises at least one of a poly portion of the poly layer, an oxide portion of the oxide layer, or a silicon portion of the silicon layer.
- According to an aspect of the instant disclosure, a method for forming a semiconductor arrangement is provided. The method comprises forming a microelectromehcanimal systems (MEMS) wafer comprising a high vacuum chamber configured as a sensing gap. The MEMS wafer is bonded to a cap wafer comprising a first vacuum chamber and a second vacuum chamber. The second vacuum chamber is configured as a first spring structure. The high vacuum chamber is coupled to the first vacuum chamber. A complementary metal-oxide-semiconductor (CMOS) is bonded to the MEMS wafer. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer. The ambient pressure chamber is connected to ambient air through a second spring structure. The first spring structure and the second spring structure are operable based upon deformation of the sensing gap.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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ITUB20161080A1 (en) * | 2016-02-25 | 2017-08-25 | St Microelectronics Srl | PRESSURE SENSOR DEVICE OF MICRO-ELECTRO-MECHANICAL TYPE WITH REDUCED TEMPERATURE SENSITIVITY |
ITUA20162174A1 (en) | 2016-03-31 | 2017-10-01 | St Microelectronics Srl | PROCESS OF MANUFACTURE OF A MEMS PRESSURE SENSOR AND RELATIVE MEMS PRESSURE SENSOR |
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US20110165717A1 (en) * | 2008-09-03 | 2011-07-07 | Solid State System Co., Ltd. | Method for forming micro-electro-mechanical system (mems) package |
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