US20150236709A1 - Protection for analog to digital converters - Google Patents
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- US20150236709A1 US20150236709A1 US14/183,159 US201414183159A US2015236709A1 US 20150236709 A1 US20150236709 A1 US 20150236709A1 US 201414183159 A US201414183159 A US 201414183159A US 2015236709 A1 US2015236709 A1 US 2015236709A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1028—Calibration at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Definitions
- Embodiments disclosed herein are related to protecting an analog-to-digital converter from excessive signals.
- Analog-to-digital converters are important in modern electronics, as they may be used to convert a continuous physical quantity represented by an analog signal to a digital representation that may approximate the amplitude of the analog signal.
- ADCs may typically convert the analog signal by periodically sampling and quantizing the analog signal to produce a sequence of digital values that correspond to a discrete-time and discrete-amplitude digital signal.
- One type of ADC is a pipeline or pipelined ADC, which uses multiple steps of conversion in successive stages to produce a digital signal.
- ADCs may be specified to work within a particular input signal range, referred to as the full scale range, and a system having an ADC may include automatic gain control (AGC) to control the input signal to be within this range.
- AGC automatic gain control
- SNR signal-to-noise ratio
- the AGC may be typically set so that the input signal is very close to the full scale range of the ADC to improve the SNR.
- the AGC is typically not fast enough to control the input signal such that the ADC receives an input signal that exceeds the full scale range.
- receiving an input signal that is an input voltage that exceeds the full scale range can cause problems.
- the internal voltages of the ADC may exceed the limits permitted by the manufacturing process and may cause transistors of the ADC to experience a hot carrier effect, which may damage and eventually destroy the transistors of the ADC.
- a hot carrier effect which may damage and eventually destroy the transistors of the ADC.
- the high input voltage may be propagated to subsequent stages, and can damage more than just the first or initial stage.
- ADCs may use an external input clamping buffer to limit or “clamp” the input signal to be close to the maximum full scale signal.
- external clamping buffers have some drawbacks. For example, extra cost and die space is required to add the extra integrated circuit required for the external clamping buffer.
- the external clamping buffer may also add in additional noise or additional distortion to the input signal, resulting in noise or distortion propagating through the ADC.
- the full scale signal of the ADC will vary based on such factors as temperature and component matching, the external clamping buffer may have to adjust the clamping level, which may lead to a reduced level of the input signal compared to the full scale signal and, consequently, a reduced SNR.
- FIG. 1 is a diagram illustrating an ADC, according to some embodiments.
- FIG. 2 is a diagram illustrating a conventional stage of a pipeline ADC.
- FIG. 3 is a graph illustrating a plot of a residue voltage V RES produced based on a input voltage V IN for a conventional stage of a pipeline ADC.
- FIG. 4 is a diagram illustrating a stage of an ADC, according to some embodiments.
- FIG. 5 is a diagram illustrating an ADC circuit of a flash ADC, consistent with some embodiments.
- FIG. 6 is a graph illustrating a plot of a residue voltage V RES produced based on input voltage V IN for the stage of an ADC shown in FIG. 4 having the ADC circuit shown in FIG. 5 .
- FIG. 7 is a diagram illustrating an ADC circuit of a flash ADC, consistent with some embodiments.
- FIG. 8 is a graph illustrating a plot of a residue voltage V RES produced based on input voltage V IN for the stage of an ADC shown in FIG. 4 having the ADC circuit shown in FIG. 7 .
- FIG. 9 is a flowchart illustrating a process for protecting an ADC from excessive voltage, consistent with some embodiments.
- a method for protecting an analog-to-digital converter includes steps of comparing an input voltage to a reference voltage, outputting at least one maximum signal when the input voltage exceeds the reference voltage, outputting a reset signal when a predetermined number of maximum signals are received, and entering a protection mode when the reset signal is received, wherein the ADC does not output a signal in the protection mode.
- the pipeline analog-to-digital converter includes at least one stage receiving an input voltage and producing outputs of a residue voltage and a digital signal.
- the at least one stage includes a first circuit receiving the input voltage and producing an output of the digital signal and one or more maximum signal when the input voltage exceeds a reference voltage, a decoder coupled to the first circuit, the decoder configured to output a reset signal when a predetermined number of maximum signals are received, and a second circuit coupled to the decoder and the first circuit, the second circuit receiving the input voltage, the digital signal, and the reset signal when output, and configured to output the residue voltage, wherein the second circuit is configured to not output the residue voltage when the reset signal is output and received.
- Embodiments consistent with this disclosure may provide improved protection for ADCs including pipeline ADCs.
- embodiments consistent with this disclosure may provide improved protection for ADCs by determining when an signal exceeding a full scale signal level is being received at a first stage of the ADC, and not propagating the excessive signal as well as information corresponding to the excessive signal.
- embodiments consistent with this disclosure may provide protection while continuing to allow ADC to operate at or near a full scale voltage level, thereby providing improved SNR.
- FIG. 1 is a diagram illustrating an ADC 100 according to some embodiments.
- ADC 100 may include a first stage 102 , an nth stage 104 , and an ith stage 106 , wherein nth stage 104 may be any intermediate stage and ith stage 106 may be the final stage of ADC 100 .
- ADC 100 may be a pipeline ADC.
- first stage 102 may receive an input voltage V IN and output a digital signal N 1 and an output voltage V OUT1 which may be a first residue voltage V RES1 .
- digital signal N 1 may have a predetermined amount of bits, such as m bits.
- Intermediate nth stage 104 may receive an input voltage that is a residue voltage from a previous stage, such as V RESn-1 and output a digital signal N n and an output voltage V OUTn which may be an nth residue voltage V RESn .
- Final ith stage 106 may receive an input voltage that is a residue voltage from a previous stage, such as V RESn and output a digital signal N i , which is the final digital signal produced by ADC 100 .
- FIG. 2 is a diagram illustrating a conventional stage 200 of ADC 100 .
- Stage 200 may correspond to first stage 102 or intermediate nth stage 104 .
- Stage 200 may also correspond to final ith stage 106 but would not include an output voltage.
- stage 200 may include a flash ADC 202 and a multiplying digital-to-analog converter (MDAC) 204 .
- Flash ADC 202 may measure input voltage V IN to produce an output digital signal NBITS OUT and to configure MDAC 204 to generate a residue voltage V RES that will be propagated to a subsequent stage.
- Flash ADC 202 may include a sample and hold circuit 206 capable of sampling and holding input voltage V IN and then periodically passing input voltage V IN to an ADC circuit 208 .
- ADC circuit 208 may be capable of converting input voltage V IN into output digital signal NBITS OUT.
- MDAC 204 may include a DAC circuit 210 capable of converting output digital signal NBITS OUT to an analog signal which is passed to difference circuit 212 .
- MDAC 204 may also include a sample and hold circuit 214 capable of sampling and holding input voltage V IN and periodically passing input voltage V IN to difference circuit 212 .
- Difference circuit 212 may be capable of determining a difference between voltage input V IN to the analog signal output by DAC circuit 210 . The determined difference may then be input into an amplifier 216 which may amplify the difference by a predetermined gain to produce an output voltage V OUT corresponding to residue voltage V RES .
- FIG. 3 is a graph 300 illustrating a plot of residue voltage V RES produced based on input voltage V IN for stage 200 of ADC 100 .
- ADC 100 may be a 4-bit ADC.
- the produced residue voltage V RES is within a maximum output.
- the produced residue voltage V RES may exceed a maximum output and produce output stresses 302 and 304 , which may be propagated to subsequent stages and cause transistors of the circuits in the subsequent stages to experience a hot carrier effect, which may damage and eventually destroy the transistors of the circuits of those stages.
- FIG. 4 is a diagram illustrating a stage 400 of ADC 100 , according to some embodiment.
- stage 400 may correspond to first stage 102 , but in other embodiments, stage 400 may correspond to intermediate nth stage 104 or final ith stage 106 .
- stage 400 may include a flash ADC 402 and a multiplying digital-to-analog converter (MDAC) 404 .
- Flash ADC 402 may measure input voltage V IN to produce an output digital signal NBITS OUT and to configure MDAC 404 to generate a residue voltage V RES that will be propagated to a subsequent stage.
- MDAC multiplying digital-to-analog converter
- Flash ADC 402 may include a sample and hold circuit 406 capable of sampling and holding input voltage V IN and then periodically passing input voltage V IN to an ADC circuit 408 .
- ADC circuit 208 may be capable of converting input voltage V IN into output digital signal NBITS OUT that is passed to DAC circuit 410 of MDAC 404 and decoder 411 .
- decoder 411 may be capable of receiving one or more maximum signals from flash ADC 402 and, when a predetermined number of maximum signals are received from flash ADC 402 , produce a reset signal RESET that is sent to MDAC 404 .
- flash ADC when reset signal RESET is sent to MDAC 404 , flash ADC may also produce a protection but that may be indicative that ADC is in a protection mode that may be used to inform a user that ADC is in a protection mode.
- the one or more maximum signals may be digital signals and may be 1-bits signals.
- the one or more maximum signals may be generated by Flash ADC 402 when input voltage V IN is greater than a predetermined reference voltage, such as a full scale voltage for ADC 100 .
- MDAC 404 may include a DAC circuit 410 capable of converting output digital signal NBITS OUT to an analog signal which is passed to difference circuit 412 .
- MDAC 404 may also include a sample and hold circuit 414 capable of sampling and holding input voltage V IN and periodically passing input voltage V IN to difference circuit 412 .
- Difference circuit 412 may be capable of determining a difference between voltage input V IN and the analog signal output by DAC circuit 410 . The determined difference may then be input into an amplifier 416 which may amplify the difference by a predetermined gain to produce an output voltage V OUT corresponding to residue voltage V RES .
- Amplifier 416 may also be capable of receiving reset signal RESET from decoder 411 when produced by decoder 411 in response to decoder 411 receiving a predetermined number of maximum signals.
- reset signal RESET when amplifier 416 receives reset signal RESET may amplifier will not produce output voltage V OUT which may correspond to residue voltage V RES . Consequently, when input voltage V IN exceeds a full scale voltage range, flash ADC 402 may generate the predetermined amount of maximum signals which, when received by decoder 411 , trigger decoder 411 to produce reset signal RESET and send it to amplifier 416 which will not produce residue voltage V RES and propagate a residue voltage V RES that may exceed a full scale voltage range and potentially damage circuits in subsequent stages.
- reset signal RESET may effectively place MDAC in a reset mode, that enables ADC 100 to be in a protection mode or clamping mode.
- reset signal RESET may trigger amplifier to amplify a signal input from difference circuit 412 at a gain of zero such that no residue voltage V RES is output from amplifier 416 .
- FIG. 5 is a diagram illustrating ADC circuit 408 of flash ADC 402 , consistent with some embodiments.
- ADC circuit 408 may include a series of n resistors 502 - 1 - 502 - n (referred to collectively as resistors 502 ) having a resistance R or R/2 receiving a positive component of a reference voltage +V REF and a negative component of a reference voltage ⁇ V REF from a reference voltage generator (not shown).
- a first resistor 502 - 1 and a last resistor 502 - n may have a resistance of R/2.
- ADC circuit 408 also includes m comparators 504 - 1 - 504 - m (referred to collectively as comparators 504 ) capable of receiving a reference voltage, which may be positive component of reference voltage +V REF and negative component of reference voltage ⁇ V REF through one or more resistors 502 and receiving input voltage V IN .
- ADC circuit 408 may have m comparators, wherein m is the number of bits ADC circuit 408 produces based on the received analog signal.
- comparators 504 may be capable of comparing the received input voltage V IN to the received reference voltage and outputting a maximum signal when the received input voltage V IN exceeds the received reference voltage. Otherwise, comparators may output digital output signal NBITS OUT.
- the maximum signal may then be transmitted to decoder 411 which, when a predetermined number of maximum signals are received, will produce reset signal RESET to place ADC 100 in a protection mode.
- ADC 100 may still output digital signal NBITS OUT when ADC 100 is in a protection mode as well as one or more bits protection bit indicative that ADC is in a protection mode that may be used to inform a user that ADC is in a protection mode.
- first comparator 504 - 1 and last comparator 504 - m may be configured to produce a maximum signal when the received input voltage V IN exceeds a received reference voltage.
- decoder 411 may produce reset signal RESET when a maximum signal is received from first comparator 504 - 1 and last comparator 504 - m . Consequently, ADC 100 having stage 400 may improve the internal robustness of ADC 100 . Further, by not propagating excessive voltages, ADC 100 having stage 400 may be capable of maintaining at or near full scale voltage range of operation during and after an excessive voltage event. In addition, ADC 100 may continue to be calibrated by background calibrations during and after an excessive voltage event because the calibration data will not be skewed by the propagation of the excessive voltage.
- FIG. 6 is a graph 600 illustrating a plot of residue voltage V RES produced based on input voltage V IN for stage 400 of ADC 100 .
- ADC 100 may be a 4 bit ADC.
- the produced residue voltage V RES is within a maximum output.
- decoder 411 may produce one or more maximum signals that will be sent to decoder 411 and, if enough maximum signals are received by decoder 411 , decoder 411 may produce a reset signal RESET that will be sent to amplifier 416 of DAC 404 to place DAC 404 in a reset mode corresponding to a protection mode for ADC 100 such that a residue voltage V RES is not produced or propagated from stage 400 .
- ADC 100 enters a protection mode at the beginning and end of the input range of input voltage V IN , such that no residue voltage V RES is produced.
- the input range of input voltage V IN is effectively reduced from the full scale voltage.
- the input range of input voltage V IN may be reduced by 20
- the full range of the input range will be 2 4 (16), such that the full range includes 16 sawtooth patterns, which may be considered to be subranges of the full range.
- the full range is shown in FIG. 3 , which includes 16 subranges.
- the input range has been reduced to having only 15 (2 4 ⁇ 1) subranges due to the loss of half of a subrange at either end. Consequently, the reduction of the input range for ADC 100 having flash ADC 408 may be 20
- FIG. 7 is a diagram illustrating ADC circuit 700 , consistent with some embodiments.
- ADC circuit 700 may be used in ADC 100 as a replacement for ADC circuit 408 .
- ADC circuit 700 may include a series of n resistors 702 - 1 - 702 - n (referred to collectively as resistors 702 ) having a resistance R or R/2 receiving a positive component of a reference voltage +V REF and a negative component of a reference voltage ⁇ V RES .
- a first resistor 702 - 1 and a last resistor 702 - n may have a resistance of R/2.
- ADC circuit 700 also includes m comparators 704 - 1 - 704 - m (referred to collectively as comparators 704 ) capable of receiving a reference voltage, which may be positive component of reference voltage +V REF and negative component of reference voltage ⁇ V REF through one or more resistors 702 and receiving input voltage V IN .
- ADC circuit 700 may be similar to ADC circuit 408 shown in FIG. 5 except that ADC circuit 700 includes comparators 706 and 708 which respectively receive the positive and negative components of the reference voltage that have not been through resistors 702 as well as input voltage V IN .
- comparators 706 and 708 may be capable of comparing the received input voltage V IN to the received reference voltage and outputting a maximum signal when the received input voltage V IN exceeds the received reference voltage. The maximum signal may then be transmitted to decoder 411 which, when maximum signals are received from comparators 706 and 708 are received, will produce reset signal RESET to place ADC 100 in a protection mode. Since the extra two comparators 706 and 708 are not receiving a reference voltage attenuated by a resistance, the reference voltage may be set to the maximum permitted input and full scale voltage range for ADC 100 and provide a better and improved comparison.
- FIG. 8 is a graph 800 illustrating a plot of residue voltage V RES produced based on input voltage V IN for stage 400 of ADC 100 having ADC circuit 808 in flash ADC 402 .
- ADC 100 may be a 4 bit ADC.
- the produced residue voltage V RES is within a maximum output.
- decoder 411 may produce maximum signals that will be sent to decoder 411 and, when maximum signals are received from comparator 706 and 708 by decoder 411 , decoder 411 may produce a reset signal RESET that will be sent to amplifier 416 of DAC 404 to place DAC 404 in a reset mode corresponding to a protection mode for ADC 100 such that a residue voltage V RES is not produced or propagated from stage 400 .
- ADC 100 enters a protection mode at the beginning and end of the input range of input voltage V IN , such that no residue voltage V RES is produced, and no voltages outside of the maximum permitted input are produced outside of the full scale voltage range.
- FIG. 8 ADC 100 enters a protection mode at the beginning and end of the input range of input voltage V IN , such that no residue voltage V RES is produced, and no voltages outside of the maximum permitted input are produced outside of the full scale voltage range.
- FIG. 8 ADC 100 enters a protection mode at the beginning and end of the input range of input
- the reference voltage may be set to more closely match, if not exactly match, the full scale voltage permitted by ADC 100 such that ADC 100 may still operate near or at the full scale voltage range.
- FIG. 9 is a flowchart illustrating a process 900 for protecting an ADC from excessive voltage, consistent with some embodiments.
- process 900 may be described with reference to one or more of FIGS. 1 and 4 - 8 .
- process 900 may include comparing an input voltage to a reference voltage ( 902 ).
- step 902 may be performed by one or more comparators 504 of ADC circuit 408 of ADC 100 .
- step 902 may be performed by comparators 704 - 708 of ADC circuit 700 of ADC 100 .
- the input voltage may correspond to V IN and the reference voltage may correspond to the positive component of reference voltage +V REF and the negative component of reference voltage ⁇ V REF through one or more resistances R or R/2 such as shown in FIG. 5 , or unattenuated such as shown in FIG. 7 .
- a maximum signal may be output by comparators 504 or 704 - 708 ( 906 ).
- decoder 411 of stage 400 of ADC 100 receives a predetermined number of maximum signals ( 908 )
- decoder 411 may produce and output a reset signal ( 910 ).
- the predetermined number of maximum signals may correspond to two maximum signals, and may further correspond to maximum signals received from first comparator 504 - 1 and last comparator 504 - m in ADC circuit 408 or from comparators 706 and 708 in ADC circuit 700 .
- the reset signal may be reset signal RESET and may be provided to amplifier 416 of MDAC 404 .
- ADC 100 may enter a protection mode ( 912 ).
- entering a protection mode may correspond to amplifier 416 entering a reset mode such that amplifier 416 and, as a result, stage 400 does not produce or propagate a residue voltage V RES .
- a gain of amplifier 416 may be set to zero.
- stage 400 which may correspond to first stage 102 of ADC, will not propagate an input voltage that may exceed a full scale voltage to prevent the excessive voltage from damaging intermediate ith stage 104 and final nth stage 106 . Consequently, ADC 100 performing process 900 may improve the internal robustness of ADC 100 .
- ADC 100 performing process 900 may be capable of maintaining at or near full scale voltage range of operation during and after an excessive voltage event.
- ADC 100 may continue to be calibrated by background calibrations during and after an excessive voltage event because the calibration data will not be skewed by the propagation of the excessive voltage.
- Embodiments consistent with this disclosure may provide improved protection for ADCs including pipeline ADCs.
- embodiments consistent with this disclosure may provide improved protection for ADCs by determining when an signal exceeding a full scale signal level is being received at a first stage of the ADC, and not propagating the excessive signal as well as information corresponding to the excessive signal.
- embodiments consistent with this disclosure may provide protection while continuing to allow ADC to operate at or near a full scale voltage level, thereby providing improved SNR.
- the examples provided above are exemplary only and are not intended to be limiting.
- One skilled in the art may readily devise other systems consistent with the disclosed embodiments which are intended to be within the scope of this disclosure. As such, the application is limited only by the following claims.
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Abstract
Description
- 1. Technical Field
- Embodiments disclosed herein are related to protecting an analog-to-digital converter from excessive signals.
- 2. Related Art
- Analog-to-digital converters (ADCs) are important in modern electronics, as they may be used to convert a continuous physical quantity represented by an analog signal to a digital representation that may approximate the amplitude of the analog signal. ADCs may typically convert the analog signal by periodically sampling and quantizing the analog signal to produce a sequence of digital values that correspond to a discrete-time and discrete-amplitude digital signal. One type of ADC is a pipeline or pipelined ADC, which uses multiple steps of conversion in successive stages to produce a digital signal.
- Most ADCs may be specified to work within a particular input signal range, referred to as the full scale range, and a system having an ADC may include automatic gain control (AGC) to control the input signal to be within this range. Since the sensitivity of the ADC may be closely related to the signal-to-noise ratio (SNR), the AGC may be typically set so that the input signal is very close to the full scale range of the ADC to improve the SNR. However, when the input signal increases suddenly, such as may occur when a system including the ADC is first powered on, the AGC is typically not fast enough to control the input signal such that the ADC receives an input signal that exceeds the full scale range. For applications where the ADC is used to convert an input voltage, receiving an input signal that is an input voltage that exceeds the full scale range can cause problems.
- For example, when the input signal, which may be an input voltage, exceeds the full scale range, the internal voltages of the ADC may exceed the limits permitted by the manufacturing process and may cause transistors of the ADC to experience a hot carrier effect, which may damage and eventually destroy the transistors of the ADC. For most modern submicron manufacturing processes, this is particularly problematic because robustness and protection is sacrificed for increased speed. Moreover, for pipeline or pipelined ADCs, the high input voltage may be propagated to subsequent stages, and can damage more than just the first or initial stage. As another example, when an ADC recovers from a saturation state, calibration information used to calibrate the ADC during the saturation state is skewed such that the ADC is improperly calibrated after the recovery as long as the skewed calibration information determined during the saturation state are propagated. For pipeline or pipelined ADCs, errors due to skewed calibration information may be further propagated to other stages of the ADC, resulting in further errors.
- Conventional ADCs may use an external input clamping buffer to limit or “clamp” the input signal to be close to the maximum full scale signal. However, such external clamping buffers have some drawbacks. For example, extra cost and die space is required to add the extra integrated circuit required for the external clamping buffer. The external clamping buffer may also add in additional noise or additional distortion to the input signal, resulting in noise or distortion propagating through the ADC. In addition, because the full scale signal of the ADC will vary based on such factors as temperature and component matching, the external clamping buffer may have to adjust the clamping level, which may lead to a reduced level of the input signal compared to the full scale signal and, consequently, a reduced SNR.
-
FIG. 1 is a diagram illustrating an ADC, according to some embodiments. -
FIG. 2 is a diagram illustrating a conventional stage of a pipeline ADC. -
FIG. 3 is a graph illustrating a plot of a residue voltage VRES produced based on a input voltage VIN for a conventional stage of a pipeline ADC. -
FIG. 4 is a diagram illustrating a stage of an ADC, according to some embodiments. -
FIG. 5 is a diagram illustrating an ADC circuit of a flash ADC, consistent with some embodiments. -
FIG. 6 is a graph illustrating a plot of a residue voltage VRES produced based on input voltage VIN for the stage of an ADC shown inFIG. 4 having the ADC circuit shown inFIG. 5 . -
FIG. 7 is a diagram illustrating an ADC circuit of a flash ADC, consistent with some embodiments. -
FIG. 8 is a graph illustrating a plot of a residue voltage VRES produced based on input voltage VIN for the stage of an ADC shown inFIG. 4 having the ADC circuit shown inFIG. 7 . -
FIG. 9 is a flowchart illustrating a process for protecting an ADC from excessive voltage, consistent with some embodiments. - In the following description specific details are set forth describing certain embodiments. It will be apparent, however, to one skilled in the art that the disclosed embodiments may be practiced without some or all of these specific details. The specific embodiments presented are meant to be illustrative, but not limiting. One skilled in the art may realize other material that, although not specifically described herein, is within the scope and spirit of this disclosure.
- There is a need for an ADC having improved protection from input signals exceeding a full scale signal level that provides improved SNR over the conventional external clamping buffer.
- Consistent with some embodiments, there is provided a method for protecting an analog-to-digital converter (ADC). The method includes steps of comparing an input voltage to a reference voltage, outputting at least one maximum signal when the input voltage exceeds the reference voltage, outputting a reset signal when a predetermined number of maximum signals are received, and entering a protection mode when the reset signal is received, wherein the ADC does not output a signal in the protection mode.
- Consistent with some embodiments, there is also provided a pipeline analog-to-digital converter. The pipeline analog-to-digital converter includes at least one stage receiving an input voltage and producing outputs of a residue voltage and a digital signal. The at least one stage includes a first circuit receiving the input voltage and producing an output of the digital signal and one or more maximum signal when the input voltage exceeds a reference voltage, a decoder coupled to the first circuit, the decoder configured to output a reset signal when a predetermined number of maximum signals are received, and a second circuit coupled to the decoder and the first circuit, the second circuit receiving the input voltage, the digital signal, and the reset signal when output, and configured to output the residue voltage, wherein the second circuit is configured to not output the residue voltage when the reset signal is output and received.
- Embodiments consistent with this disclosure may provide improved protection for ADCs including pipeline ADCs. In particular, embodiments consistent with this disclosure may provide improved protection for ADCs by determining when an signal exceeding a full scale signal level is being received at a first stage of the ADC, and not propagating the excessive signal as well as information corresponding to the excessive signal. Moreover, embodiments consistent with this disclosure may provide protection while continuing to allow ADC to operate at or near a full scale voltage level, thereby providing improved SNR.
-
FIG. 1 is a diagram illustrating anADC 100 according to some embodiments. ADC 100 may include afirst stage 102, annth stage 104, and anith stage 106, whereinnth stage 104 may be any intermediate stage and ithstage 106 may be the final stage ofADC 100. In some embodiments, ADC 100 may be a pipeline ADC. As shown inFIG. 1 ,first stage 102 may receive an input voltage VIN and output a digital signal N1 and an output voltage VOUT1 which may be a first residue voltage VRES1. In some embodiments, digital signal N1 may have a predetermined amount of bits, such as m bits.Intermediate nth stage 104 may receive an input voltage that is a residue voltage from a previous stage, such as VRESn-1 and output a digital signal Nn and an output voltage VOUTn which may be an nth residue voltage VRESn.Final ith stage 106 may receive an input voltage that is a residue voltage from a previous stage, such as VRESn and output a digital signal Ni, which is the final digital signal produced byADC 100. -
FIG. 2 is a diagram illustrating aconventional stage 200 ofADC 100.Stage 200 may correspond tofirst stage 102 orintermediate nth stage 104.Stage 200 may also correspond tofinal ith stage 106 but would not include an output voltage. As shown inFIG. 2 ,stage 200 may include a flash ADC 202 and a multiplying digital-to-analog converter (MDAC) 204. Flash ADC 202 may measure input voltage VIN to produce an output digital signal NBITS OUT and to configureMDAC 204 to generate a residue voltage VRES that will be propagated to a subsequent stage. Flash ADC 202 may include a sample and holdcircuit 206 capable of sampling and holding input voltage VIN and then periodically passing input voltage VIN to anADC circuit 208.ADC circuit 208 may be capable of converting input voltage VIN into output digital signal NBITS OUT. - MDAC 204 may include a
DAC circuit 210 capable of converting output digital signal NBITS OUT to an analog signal which is passed todifference circuit 212. MDAC 204 may also include a sample and holdcircuit 214 capable of sampling and holding input voltage VIN and periodically passing input voltage VIN todifference circuit 212.Difference circuit 212 may be capable of determining a difference between voltage input VIN to the analog signal output byDAC circuit 210. The determined difference may then be input into anamplifier 216 which may amplify the difference by a predetermined gain to produce an output voltage VOUT corresponding to residue voltage VRES. -
FIG. 3 is agraph 300 illustrating a plot of residue voltage VRES produced based on input voltage VIN forstage 200 ofADC 100. For the example graph shown inFIG. 3 , ADC 100 may be a 4-bit ADC. As shown inFIG. 3 , for an input range of input voltage VIN that is within the full scale (FS) voltage range ofADC 100 includingstage 200, the produced residue voltage VRES is within a maximum output. However, when input voltage VIN exceeds the full scale voltage range, the produced residue voltage VRES may exceed a maximum output and produce output stresses 302 and 304, which may be propagated to subsequent stages and cause transistors of the circuits in the subsequent stages to experience a hot carrier effect, which may damage and eventually destroy the transistors of the circuits of those stages. -
FIG. 4 is a diagram illustrating astage 400 ofADC 100, according to some embodiment. In some embodiments,stage 400 may correspond tofirst stage 102, but in other embodiments,stage 400 may correspond to intermediatenth stage 104 orfinal ith stage 106. As shown inFIG. 4 ,stage 400 may include aflash ADC 402 and a multiplying digital-to-analog converter (MDAC) 404.Flash ADC 402 may measure input voltage VIN to produce an output digital signal NBITS OUT and to configureMDAC 404 to generate a residue voltage VRES that will be propagated to a subsequent stage.Flash ADC 402 may include a sample and holdcircuit 406 capable of sampling and holding input voltage VIN and then periodically passing input voltage VIN to anADC circuit 408.ADC circuit 208 may be capable of converting input voltage VIN into output digital signal NBITS OUT that is passed toDAC circuit 410 ofMDAC 404 anddecoder 411. In some embodiments,decoder 411 may be capable of receiving one or more maximum signals fromflash ADC 402 and, when a predetermined number of maximum signals are received fromflash ADC 402, produce a reset signal RESET that is sent toMDAC 404. In some embodiments, when reset signal RESET is sent toMDAC 404, flash ADC may also produce a protection but that may be indicative that ADC is in a protection mode that may be used to inform a user that ADC is in a protection mode. The one or more maximum signals may be digital signals and may be 1-bits signals. The one or more maximum signals may be generated byFlash ADC 402 when input voltage VIN is greater than a predetermined reference voltage, such as a full scale voltage forADC 100. -
MDAC 404 may include aDAC circuit 410 capable of converting output digital signal NBITS OUT to an analog signal which is passed todifference circuit 412.MDAC 404 may also include a sample and holdcircuit 414 capable of sampling and holding input voltage VIN and periodically passing input voltage VIN todifference circuit 412.Difference circuit 412 may be capable of determining a difference between voltage input VIN and the analog signal output byDAC circuit 410. The determined difference may then be input into anamplifier 416 which may amplify the difference by a predetermined gain to produce an output voltage VOUT corresponding to residue voltage VRES. -
Amplifier 416 may also be capable of receiving reset signal RESET fromdecoder 411 when produced bydecoder 411 in response todecoder 411 receiving a predetermined number of maximum signals. In some embodiments, whenamplifier 416 receives reset signal RESET may amplifier will not produce output voltage VOUT which may correspond to residue voltage VRES. Consequently, when input voltage VIN exceeds a full scale voltage range,flash ADC 402 may generate the predetermined amount of maximum signals which, when received bydecoder 411,trigger decoder 411 to produce reset signal RESET and send it to amplifier 416 which will not produce residue voltage VRES and propagate a residue voltage VRES that may exceed a full scale voltage range and potentially damage circuits in subsequent stages. In some embodiments, reset signal RESET may effectively place MDAC in a reset mode, that enablesADC 100 to be in a protection mode or clamping mode. In some embodiments, reset signal RESET may trigger amplifier to amplify a signal input fromdifference circuit 412 at a gain of zero such that no residue voltage VRES is output fromamplifier 416. -
FIG. 5 is a diagram illustratingADC circuit 408 offlash ADC 402, consistent with some embodiments. As shown inFIG. 5 ,ADC circuit 408 may include a series of n resistors 502-1-502-n (referred to collectively as resistors 502) having a resistance R or R/2 receiving a positive component of a reference voltage +VREF and a negative component of a reference voltage −VREF from a reference voltage generator (not shown). In some embodiments, a first resistor 502-1 and a last resistor 502-n may have a resistance of R/2.ADC circuit 408 also includes m comparators 504-1-504-m (referred to collectively as comparators 504) capable of receiving a reference voltage, which may be positive component of reference voltage +VREF and negative component of reference voltage −VREF through one or more resistors 502 and receiving input voltage VIN. In some embodiments,ADC circuit 408 may have m comparators, wherein m is the number ofbits ADC circuit 408 produces based on the received analog signal. In some embodiments, comparators 504 may be capable of comparing the received input voltage VIN to the received reference voltage and outputting a maximum signal when the received input voltage VIN exceeds the received reference voltage. Otherwise, comparators may output digital output signal NBITS OUT. The maximum signal may then be transmitted todecoder 411 which, when a predetermined number of maximum signals are received, will produce reset signal RESET to placeADC 100 in a protection mode. In some embodiments,ADC 100 may still output digital signal NBITS OUT whenADC 100 is in a protection mode as well as one or more bits protection bit indicative that ADC is in a protection mode that may be used to inform a user that ADC is in a protection mode. In some embodiments, first comparator 504-1 and last comparator 504-m may be configured to produce a maximum signal when the received input voltage VIN exceeds a received reference voltage. In such embodiments,decoder 411 may produce reset signal RESET when a maximum signal is received from first comparator 504-1 and last comparator 504-m. Consequently,ADC 100 havingstage 400 may improve the internal robustness ofADC 100. Further, by not propagating excessive voltages,ADC 100 havingstage 400 may be capable of maintaining at or near full scale voltage range of operation during and after an excessive voltage event. In addition,ADC 100 may continue to be calibrated by background calibrations during and after an excessive voltage event because the calibration data will not be skewed by the propagation of the excessive voltage. -
FIG. 6 is agraph 600 illustrating a plot of residue voltage VRES produced based on input voltage VIN forstage 400 ofADC 100. For the example graph shown inFIG. 6 ,ADC 100 may be a 4 bit ADC. As shown inFIG. 6 , for an input range of input voltage VIN the produced residue voltage VRES is within a maximum output. However, when input voltage VIN exceeds a full scale voltage,ADC circuit 408 shown inFIG. 5 may produce one or more maximum signals that will be sent todecoder 411 and, if enough maximum signals are received bydecoder 411,decoder 411 may produce a reset signal RESET that will be sent toamplifier 416 ofDAC 404 to placeDAC 404 in a reset mode corresponding to a protection mode forADC 100 such that a residue voltage VRES is not produced or propagated fromstage 400. As shown inFIG. 6 ,ADC 100 enters a protection mode at the beginning and end of the input range of input voltage VIN, such that no residue voltage VRES is produced. - However, as also shown in
FIG. 6 , whenADC 100 enters a protection mode, the input range of input voltage VIN is effectively reduced from the full scale voltage. The input range of input voltage VIN may be reduced by 20 -
- For a 4-bit ADC, the full range of the input range will be 24 (16), such that the full range includes 16 sawtooth patterns, which may be considered to be subranges of the full range. The full range is shown in
FIG. 3 , which includes 16 subranges. However, as shown inFIG. 6 , the input range has been reduced to having only 15 (24−1) subranges due to the loss of half of a subrange at either end. Consequently, the reduction of the input range forADC 100 havingflash ADC 408 may be 20 -
- which is a reduction of about 0.56 dB from the full scale voltage range. While such a reduction may be fine for most applications, certain applications that require resolution may require the input range of input voltage VIN to be as close to the full scale voltage range as possible.
-
FIG. 7 is a diagram illustratingADC circuit 700, consistent with some embodiments.ADC circuit 700 may be used inADC 100 as a replacement forADC circuit 408. As shown inFIG. 7 ,ADC circuit 700 may include a series of n resistors 702-1-702-n (referred to collectively as resistors 702) having a resistance R or R/2 receiving a positive component of a reference voltage +VREF and a negative component of a reference voltage −VRES. In some embodiments, a first resistor 702-1 and a last resistor 702-n may have a resistance of R/2.ADC circuit 700 also includes m comparators 704-1-704-m (referred to collectively as comparators 704) capable of receiving a reference voltage, which may be positive component of reference voltage +VREF and negative component of reference voltage −VREF through one ormore resistors 702 and receiving input voltage VIN. ADC circuit 700 may be similar toADC circuit 408 shown inFIG. 5 except thatADC circuit 700 includescomparators resistors 702 as well as input voltage VIN. - In some embodiments,
comparators decoder 411 which, when maximum signals are received fromcomparators ADC 100 in a protection mode. Since the extra twocomparators ADC 100 and provide a better and improved comparison. -
FIG. 8 is agraph 800 illustrating a plot of residue voltage VRES produced based on input voltage VIN forstage 400 ofADC 100 having ADC circuit 808 inflash ADC 402. For the example graph shown inFIG. 8 ,ADC 100 may be a 4 bit ADC. As shown inFIG. 8 , for an input range of input voltage VIN the produced residue voltage VRES is within a maximum output. However, when input voltage VIN exceeds a full scale voltage,comparators ADC circuit 700 shown inFIG. 7 may produce maximum signals that will be sent todecoder 411 and, when maximum signals are received fromcomparator decoder 411,decoder 411 may produce a reset signal RESET that will be sent toamplifier 416 ofDAC 404 to placeDAC 404 in a reset mode corresponding to a protection mode forADC 100 such that a residue voltage VRES is not produced or propagated fromstage 400. As shown inFIG. 8 ,ADC 100 enters a protection mode at the beginning and end of the input range of input voltage VIN, such that no residue voltage VRES is produced, and no voltages outside of the maximum permitted input are produced outside of the full scale voltage range. However, as also shown inFIG. 8 , by addingextra comparators ADC circuit 700 offlash ADC 402, the reference voltage may be set to more closely match, if not exactly match, the full scale voltage permitted byADC 100 such thatADC 100 may still operate near or at the full scale voltage range. -
FIG. 9 is a flowchart illustrating aprocess 900 for protecting an ADC from excessive voltage, consistent with some embodiments. For the purpose of illustration,process 900 may be described with reference to one or more of FIGS. 1 and 4-8. As shown inFIG. 9 ,process 900 may include comparing an input voltage to a reference voltage (902). In some embodiments step 902 may be performed by one or more comparators 504 ofADC circuit 408 ofADC 100. In other embodiments,step 902 may be performed by comparators 704-708 ofADC circuit 700 ofADC 100. Moreover, in some embodiments, the input voltage may correspond to VIN and the reference voltage may correspond to the positive component of reference voltage +VREF and the negative component of reference voltage −VREF through one or more resistances R or R/2 such as shown inFIG. 5 , or unattenuated such as shown inFIG. 7 . - When the input voltage exceeds the reference voltage (904) a maximum signal may be output by comparators 504 or 704-708 (906). When
decoder 411 ofstage 400 ofADC 100 receives a predetermined number of maximum signals (908),decoder 411 may produce and output a reset signal (910). In some embodiments, the predetermined number of maximum signals may correspond to two maximum signals, and may further correspond to maximum signals received from first comparator 504-1 and last comparator 504-m inADC circuit 408 or fromcomparators ADC circuit 700. Moreover, the reset signal may be reset signal RESET and may be provided toamplifier 416 ofMDAC 404. WhenMDAC 404 receives the reset signal,ADC 100 may enter a protection mode (912). In some embodiments, entering a protection mode may correspond toamplifier 416 entering a reset mode such thatamplifier 416 and, as a result,stage 400 does not produce or propagate a residue voltage VRES. Moreover, whenamplifier 416 enters a reset mode, a gain ofamplifier 416 may be set to zero. WhenADC 100 enters a protection mode,stage 400, which may correspond tofirst stage 102 of ADC, will not propagate an input voltage that may exceed a full scale voltage to prevent the excessive voltage from damagingintermediate ith stage 104 and finalnth stage 106. Consequently,ADC 100 performingprocess 900 may improve the internal robustness ofADC 100. Further, by not propagating excessive voltages,ADC 100 performingprocess 900 may be capable of maintaining at or near full scale voltage range of operation during and after an excessive voltage event. In addition,ADC 100 may continue to be calibrated by background calibrations during and after an excessive voltage event because the calibration data will not be skewed by the propagation of the excessive voltage. - Embodiments consistent with this disclosure may provide improved protection for ADCs including pipeline ADCs. In particular, embodiments consistent with this disclosure may provide improved protection for ADCs by determining when an signal exceeding a full scale signal level is being received at a first stage of the ADC, and not propagating the excessive signal as well as information corresponding to the excessive signal. Moreover, embodiments consistent with this disclosure may provide protection while continuing to allow ADC to operate at or near a full scale voltage level, thereby providing improved SNR. The examples provided above are exemplary only and are not intended to be limiting. One skilled in the art may readily devise other systems consistent with the disclosed embodiments which are intended to be within the scope of this disclosure. As such, the application is limited only by the following claims.
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