US20150236034A1 - Novel compact charge trap multi-time programmable memory - Google Patents
Novel compact charge trap multi-time programmable memory Download PDFInfo
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- US20150236034A1 US20150236034A1 US14/704,004 US201514704004A US2015236034A1 US 20150236034 A1 US20150236034 A1 US 20150236034A1 US 201514704004 A US201514704004 A US 201514704004A US 2015236034 A1 US2015236034 A1 US 2015236034A1
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- 125000006850 spacer group Chemical group 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000010410 layer Substances 0.000 claims description 62
- 238000000034 method Methods 0.000 claims description 25
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 5
- 229910052746 lanthanum Inorganic materials 0.000 claims description 5
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000007935 neutral effect Effects 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- -1 TiAlN Chemical compound 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/772—Field effect transistors
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Abstract
A memory device requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a charge-trapping (CT) spacer on each tunnel oxide liner.
Description
- This application is a Divisional application of U.S. patent application Ser. No. 13/587,072, filed Aug. 16, 2012, the entirety of which is incorporated herein by reference.
- The present disclosure relates to fabrication of semiconductor memory cells. The present disclosure is particularly applicable to fabrication of multiple-time programmable (MTP) non-volatile memory (NVM).
- Non-volatile memory is utilized in a variety of devices, such as televisions, mobile devices, and computer memory, to store information. One-time programmable (OTP) memory devices have been employed, for example using a floating gate as a storage medium, since they require no additional mask and therefore have minimal cost. However, OTP cells require a large footprint due to gate-to-gate limitations and overlay tolerance, and allow for only a single programming, such that device updates are not possible. An example of an MTP memory uses merged nitride spacers as a storage medium. This structure requires no additional mask, allows for multiple programming, and has minimal cost, but requires a large footprint due to the addition of a select transistor. For a more compact structure, a split-gate memory has been employed, which allows for multiple programming and has a small footprint, but it requires an additional mask for a control gate, which complicates the manufacture thereof and increases cost. Thus, traditional memory devices require additional masks for fabrication, have a high cost of production, require a large footprint, and/or are limited to a single-time programming, thereby limiting the size, cost, and manufacturability of fabricated products employing the memory devices, particularly in low cost, small size products, such as portable electronics.
- A need therefore exists for methodology enabling fabrication of low cost MTP memory requiring no or minimal additional mask and having a small footprint, and the resulting device.
- An aspect of the present disclosure is a method of fabricating semiconductor memory including, inter alia, forming a tunnel oxide liner on side surfaces of gate stack and on the substrate on each side of the gate stack and forming a charge-trapping (CT) spacer on each tunnel oxide liner.
- An additional aspect of the present disclosure is a method of configuring, inter alia, the CT spacer on the drain side of the gate stack to: store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact; remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and determine a current or gate threshold voltage when a read voltage is applied on the second contact and a low voltage is applied to the first contact.
- Another aspect of the present disclosure is a device having, inter alia, a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a CT spacer on each tunnel oxide liner.
- Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
- According to the present disclosure, some technical effects may be achieved in part by a method including: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a CT spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.
- Some aspects include forming an interlayer dielectric (ILD) over an upper surface of the substrate surrounding the gate stack and the CT spacers, after forming the source and drain. Further aspects include: forming, through the ILD over the drain, a first contact at least partially abutting the CT spacer or separated from the CT spacer by a block oxide liner; and forming, through the ILD over the source, a second contact. Some aspects include: forming each CT spacer as a layer over each portion of the tunnel oxide liner, the method further including forming a spacer over each CT spacer. Additional aspects include: removing the gate stack, forming a cavity between each of the tunnel oxide liners; forming a high-k dielectric layer in the cavity; and forming a replacement metal gate (RMG) electrode on the high-k layer, prior to forming the first and second contacts. Some aspects include forming a hardmask layer on the RMG electrode, prior to forming the first and second contacts, the hardmask layer being formed by recessing the RMG electrode and depositing the hardmask layer in the recess or by depositing a hardmask material over the RMG electrode, tunnel oxide liners, and CT spacers, and lithographically defining and etching the hardmask layer. Further aspects include: forming the high-k layer on side surfaces of the cavity; forming a work-function tuning layer of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La2O3), or a combination thereof on the high-k layer. Additional aspects include forming the first and second contacts by forming first and second contact holes, forming block oxide liners on side surfaces of the contact holes, and filling the contact holes with a contact material. Some aspects include configuring the CT spacer on the drain side of the gate stack to: store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact; remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and determine a current or gate threshold voltage when a read voltage is applied on the second contact and a low voltage is applied to the first contact. Additional aspects include: forming the tunnel oxide liners of oxide using an in-situ steam generation (ISSG) process, a high temperature oxide (HTO), silicon oxynitride (SiON), multiple layers of oxide nitride oxide (ONO), or a combination thereof; and forming the CT spacers of nitride, silicon nitride (SiN), SiON, hafnium oxide (HfO2), TaN, or a combination thereof.
- Another aspect of the present disclosure is a device including: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a CT spacer on each tunnel oxide liner.
- Aspects include a device including a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack. Some aspects include: an ILD on the substrate surrounding the gate stack and CT spacers; a first contact, through the ILD over the drain, at least partially abutting to the CT spacer or separated from the CT spacer by a block oxide liner; and a second contact, through the ILD over the source. Further aspects include: a first block oxide liner on each side of the first contact; and a second block oxide liner on each side of the second contact. Additional aspects include a device wherein each CT spacer is formed as a layer over each portion of the tunnel oxide liner, the device further including a spacer over each CT spacer. Further aspects include a device wherein the gate stack includes: a high-k dielectric layer; a work-function tuning layer on the high-k dielectric layer; and a metal gate electrode on the work-function tuning layer. Some aspects include: the high-k dielectric layer on side surfaces of the metal gate electrode; and the work-function tuning layer being titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La2O3), or a combination thereof. Additional aspects include the tunnel oxide liners being formed of an oxide using an ISSG process, a HTO, a SiON, multiple layers of ONO, or a combination thereof. Further aspects include the CT spacers being formed of nitride, SiN, SiON, HfO2, TaN, or a combination thereof.
- Another aspect of the present disclosure is a method including: providing a dummy gate stack including an oxide layer and a dummy gate on a substrate; forming a source extension region in the substrate on one side of the dummy gate stack, wherein a drain extension region is not formed on the other side of the dummy gate stack; forming a tunnel oxide liner of oxide using an in-situ steam generation (ISSG) process, a high temperature oxide (HTO), silicon oxynitride (SiON), multiple layers of oxide nitride oxide (ONO), or a combination thereof on each side surface of the dummy gate stack and on the substrate at each side of the dummy gate stack; forming a charge-trapping (CT) spacer of nitride, silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), tantalum nitride (TaN), or a combination thereof on each tunnel oxide liner; forming a source in the substrate on the one side of the dummy gate stack adjacent the source extension region, and a drain in the substrate on the other side of the dummy gate stack; depositing an interlayer dielectric (ILD) on the substrate surrounding the dummy gate stack and CT spacers; removing the dummy gate, forming a cavity between the tunnel oxide liners; forming a high-k dielectric layer in the cavity; forming a replacement metal gate (RMG) electrode in the cavity; forming a hardmask layer on the RMG electrode, the hardmask layer being formed by recessing the RMG electrode and depositing the hardmask layer in the recess, or forming the hardmask layer over the RMG electrode and tunnel oxide liners; forming, through the ILD over the drain, a first contact trench at least partially abutting the CT spacer or separated from the CT spacer by a block oxide liner; forming, through the ILD over the source, a second contact trench; and forming a first and second contact of Al, W, Ta, Ti, TaN, TiN, or a combination thereof on the first and second block oxide liners, respectively.
- Aspects include: forming each CT spacer as a layer over the tunnel oxide liner; forming a spacer on each CT spacer, prior to forming the source and drain in the substrate; forming the high-k dielectric layer on bottom and side surfaces of the cavity; and forming a work function tuning layer on the high-k dielectric layer. Additional aspects include configuring the CT spacer on the drain side of the gate stack to: store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact; remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and determine a current or gate threshold voltage when a read voltage is applied on the second contact and a low voltage is applied to the first contact.
- Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
- The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
-
FIGS. 1 , 2, 3A, 4A, and 5A schematically illustrate sequential steps of a method, in accordance with an exemplary embodiment; -
FIGS. 1 , 2, 3B, 4B, and 5B schematically illustrate sequential steps of another method, in accordance with another exemplary embodiment; -
FIGS. 1 , 2, 3C, 4C, and 5C schematically illustrate sequential steps of an additional method, in accordance with a third exemplary embodiment; -
FIGS. 1 , 2, 3D, 4D, and 5D schematically illustrate sequential steps of an additional method, in accordance with a fourth exemplary embodiment; and -
FIGS. 6A through 6D schematically illustrate steps of a method of operation of the devices ofFIGS. 5A through 5D , in accordance with an exemplary embodiment. - In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
- The present disclosure addresses and solves the current problems of high cost, large footprint, single-time programming, and a necessity of an additional mask attendant upon fabrication of non-volatile memory devices. In accordance with embodiments of the present disclosure, a tunnel oxide liner is formed and a CT spacer is formed on each tunnel oxide liner. The CT spacer is configured, inter alia, on the drain side of the gate stack to: store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact; remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and determine a current or gate threshold voltage when a read voltage is applied on the second contact and a low voltage is applied to the first contact.
- Methodology in accordance with embodiments of the present disclosure includes: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a CT spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.
- Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
- Adverting to
FIG. 1 in accordance with exemplary embodiments, asubstrate 101, for example a bulk silicon substrate, is provided with agate stack 103 having a gate electrode or a dummy gate electrode for an RMG. As illustrated inFIG. 1 ,gate stack 103 contains agate dielectric layer 105, agate electrode 107, and ahardmask 109 formed over thegate electrode 107. Thedielectric layer 105 may be formed on the side surfaces of the gate electrode 107 (not shown for illustrative convenience). Thegate dielectric layer 105 may be a formed of a high-k material, for example HfO2, HfSiON or AlHfO, and thegate electrode 107 may be a metal gate electrode, e.g. of Al, W, Ta, Ti, TaN, TiN. A work-function layer (not shown for illustrative convenience) of TiN, TiAlN, or TaN, for example, may be formed on the high-k dielectric layer 105. Thegate electrode 107 may also be formed of polysilicon or amorphous silicon, over an oxide or SiONgate dielectric layer 105. Alternatively, thegate electrode 107 may be a dummy gate electrode for an RMG process, formed of polysilicon or amorphous silicon, overgate dielectric layer 105, formed of oxide or SiON. Thesubstrate 101 andgate stack 103 may be formed using conventional front-end-of-line (FEOL) steps for forming a gate first gate electrode or for forming a dummy gate electrode for an RMG. Adverting toFIG. 2 , asource extension region 201 is formed in thesubstrate 101 at one side ofgate stack 103, but no corresponding drain extension region is formed at the other side ofgate stack 103. - In accordance with a first embodiment, a gate first process is illustrated in
FIGS. 3A , 4A and 5A. Adverting toFIG. 3A ,tunnel oxide liners gate stack 103 and on thesubstrate 101 on each side of thegate stack 103. Thetunnel oxide liners tunnel oxide liners source region 309 is formed in thesubstrate 101 on the side of thegate stack 103 havingsource extension region 201, and adrain region 311 is formed in thesubstrate 101 on the other side of thegate stack 103. Silicidation of thesource region 309 and the drain region 311 (not shown for illustrative convenience) may be performed. - As illustrated in
FIG. 4A , anILD 401 a is formed of SiO2, nitrides, and/or doped SiO2 (e.g., BPSG, porous low-k materials, etc.) to a thickness of between 50 nm and 1,000 nm over an upper surface of thesubstrate 101. Afirst contact 501 may then be formed through theILD 401 a over thedrain region 311, at least partially abutting theCT spacer 307 a, and asecond contact 503 may be formed, through theILD 401 a over thesource region 309, separated from theCT spacer 305 a, as shown inFIG. 5A . Alternatively, thesecond contact 503 may be abutting (not shown for illustrative convenience)CT spacer 305 a.Contacts - Adverting to
FIGS. 3B , 4B, and 5B a second gate first embodiment is illustrated.Tunnel oxide liners CT spacers regions FIG. 3A . However, as shown inFIG. 3B , ablock oxide 313 is formed overCT spacers hardmask 109. Alternatively,block oxide 313 may be formed as a second set of spacers adjacent toCT spacers - As illustrated in
FIG. 4B , anILD 401 a is formed of SiO2, nitrides, and/or doped SiO2 (e.g., BPSG, porous low-k materials, etc.) to a thickness of between 50 nm and 1,000 nm over an upper surface of thesubstrate 101. Afirst contact 501 may then be formed through theILD 401 a over thedrain region 311, at least partially abuttingblock oxide 313, and asecond contact 503 may be formed, through theILD 401 a over thesource region 309, separated from theblock oxide 313, as shown inFIG. 5B Alternatively, thesecond contact 503 may be abutting (not shown for illustrative convenience)CT spacer 305 a.Contacts FIG. 5A . -
FIGS. 3C , 4C, and 5C illustrate a third embodiment in which an RMG is formed. Adverting toFIG. 3C , agate dielectric layer 105, e.g. an oxide layer, adummy gate electrode 107, e.g. of polysilicon or amorphous silicon, having a thickness of between 20 nm and 200 nm, and ahardmask 109 of oxide, SiON, or TiN having a thickness of between 5 nm and 100 nm, is to be replaced by an RMG process with a RMG electrode and high-k layer. In the third embodiment,substrate 101,gate stack 103,source extension region 201 andtunnel oxide liners FIGS. 1 , 2, 3A, and 3B. CT spacers 305 b and 307 b are formed ontunnel oxide liners regions FIGS. 3A and 3B . CT spacers 305 b and 307 b may be formed as inFIG. 3A (not shown for illustrative convenience), or may be formed as a thin layer on the horizontal surfaces (over substrate 101) and vertical surfaces (opposite sidewalls of gate 103) oftunnel oxide liners FIG. 3C . In the latter case,spacers CT spacer regions - Adverting to
FIG. 4C , anILD layer 401 b is formed of SiO2, nitrides, and/or doped SiO2 (e.g., BPSG, porous low-k materials, etc.) to a thickness of between 50 nm and 1,000 nm over an upper surface of thesubstrate 101. Chemical mechanical polishing (CMP) is performed to exposehardmask 109. Then, hardmask 109,dummy gate electrode 107, andgate dielectric layer 105 are removed by conventional processes, forming a cavity betweentunnel oxide liners k dielectric layer 403, such as HfO2 , HfSiON or AlHfO, is deposited on the bottom and side surfaces of the cavity, and ametal gate 405, e.g. of Al, W, Ta, Ti, TaN, TiN, is formed to fill the remainder of the cavity. Themetal gate 405 may then be recessed, and ahardmask 407 may be formed over themetal gate electrode 405 by filling the recess and performing CMP, completingRMG electrode stack 409. Additionally, a work-function tuning layer of TiN, TaN, TiAlN, La, La2O3, or a combination thereof may be formed (not shown for illustrative convenience) on the high-k layer 403.Contacts FIG. 5C , similar to the contacts formed inFIGS. 5A and 5B . -
FIGS. 3D , 4D and 5D illustrate a fourth embodiment in which another RMG is formed. As illustrated inFIG. 3D ,tunnel oxide liners CT spacers regions FIG. 3C (withoutspacers 315 and 317). Then,ILD layer 319 is deposited over an upper surface of thesubstrate 101 and a traditional CMP process is performed. Adverting toFIG. 4D , the high-k layer 403 andmetal gate 405 are formed similar to those described with respect toFIG. 4C (withoutspacers 315 and 317). Additionally, as shown inFIG. 4D ,hardmask 407 is deposited on themetal gate 405,tunnel oxide liners CT spacers ILD 401 b is deposited and CMP is again performed. Adverting toFIG. 5D , an etching is performed of contact holes over source and drainregions block oxide liners second contacts block oxide liners block oxide liners contacts -
FIGS. 6A through 6D schematically illustrate steps of a method of operation of the devices ofFIGS. 5A through 5D , in accordance with an exemplary embodiment.FIGS. 6A through 6D contain adrain side 601 having atunnel oxide liner 603,CT spacer 605 andfirst contact 607, agate stack 609, and asource side 611 having asecond contact 613. -
FIG. 6A illustrates a programming of a memory cell. Specifically,CT spacer 605 on thedrain side 601 of agate stack 609 is configured to store charges when a program voltage of between 3 volts and 10 volts is applied to thefirst contact 607, a low or neutral voltage is applied to thesecond contact 613, and an on voltage of between 0.5 volts and 5 volts is applied to thegate stack 609. -
FIG. 6B illustrates a first method of erasing of a memory cell by removing charges through thetunnel oxide 603 to the channel. Specifically,CT spacer 605 on thedrain side 601 of agate stack 609 is configured to remove charges when an erase voltage of between 5 volts and 10 volts is applied to thesecond contact 613, a floating or neutral voltage is applied to thefirst contact 607 and an on voltage of between 0.5 volts and 5 volts is applied to thegate stack 609. -
FIG. 6C illustrates a second method of erasing of a memory cell by removing charges through thefirst contact 607. Specifically,CT spacer 605 on thedrain side 601 of agate stack 609 is configured to remove charges when an erase voltage of between 5 volts and 10 volts is applied to thefirst contact 607, a floating or neutral voltage is applied to thesecond contact 613 and a floating or neutral voltage is applied to thegate stack 609. -
FIG. 6D illustrates a reading of a memory cell. Specifically,CT spacer 605 on thedrain side 601 of agate stack 609 is configured to provide a potential barrier or read voltage on thesecond contact 613 of between a low or neutral voltage, e.g. 0 volts, and 5 volts when a voltage of between a low or neutral voltage and 5 volts is applied to thegate stack 609 and a low or neutral voltage is applied to thefirst contact 607. Additionally, the memory cell illustrated inFIG. 6D is read by determining a state of the memory cell based on a threshold voltage or current flowing in the channel. - The embodiments of the present disclosure can achieve several technical effects, including formation of memory devices requiring no additional mask for fabrication, having a low cost, a small footprint, and multiple-time programming capability. The present disclosure enjoys industrial applicability in any of various types of highly integrated semiconductor devices, particularly in devices configured to store information, such as televisions, mobile devices, and personal computers.
- In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
Claims (20)
1. A device, comprising:
a substrate;
a gate stack on the substrate;
a source and drain in the substrate at opposite sides, respectively, of the gate stack;
a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack;
a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and
a charge-trapping (CT) spacer on each tunnel oxide liner.
2. The device according to claim 1 , further comprising:
an interlayer dielectric (ILD) on the substrate surrounding the gate stack and CT spacers;
a first contact, through the ILD over the drain, at least partially abutting to the CT spacer or separated from the CT spacer by a block oxide liner; and
a second contact, through the ILD over the source.
3. The device according to claim 2 , further comprising:
a first block oxide liner on each side of the first contact; and
a second block oxide liner on each side of the second contact.
4. The device according to claim 1 , wherein the gate stack comprises:
a high-k dielectric layer;
a work-function tuning layer on the high-k dielectric layer; and
a metal gate electrode on the work-function tuning layer.
5. The device according to claim 4 , wherein each CT spacer is formed as a layer over each portion of the tunnel oxide liner, the device further comprising:
a spacer over each CT spacer.
6. The device according to claim 4 , further comprising:
the high-k dielectric layer being on side surfaces of the metal gate electrode; and
the work-function tuning layer being titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La2O3), or a combination thereof.
7. The device according to claim 1 , further comprising:
the tunnel oxide liners being formed of an oxide using an in-situ steam generation (ISSG) process, a high temperature oxide (HTO), a silicon oxynitride (SiON), multiple layers of oxide nitride oxide (ONO), or a combination thereof.
8. The device according to claim 1 , further comprising:
the CT spacers being formed of nitride, silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), tantalum nitride (TaN), or a combination thereof.
9. A device comprising:
a substrate;
a gate stack formed on the substrate, the gate stack including a replacement metal gate (RMG) electrode;
a source extension region formed in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack;
a tunnel oxide liner formed on side surfaces of the gate stack and on the substrate on each side of the gate stack;
a charge-trapping (CT) spacer formed on each tunnel oxide liner;
a block oxide liner formed on each CT spacer; and
a source formed in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack,
wherein the source extension region and source are formed on the one side of the gate stack and the drain is formed on the other side of the gate stack with no drain extension region being formed.
10. The device according to claim 9 , further comprising:
an interlayer dielectric (ILD) over an upper surface of the substrate surrounding the gate stack and the CT spacers.
11. The device according to claim 10 , further comprising:
a first contact formed through the ILD over the drain, the first contact separated from the CT spacer by the block oxide liner; and
a second contact formed through the ILD over the source.
12. The device according to claim 9 , wherein the gate stack comprises:
a high-k dielectric layer formed between each of the tunnel oxide liners; and
the replacement metal gate (RMG) electrode on the high-k dielectric layer.
13. The device according to claim 12 , further comprising:
a hardmask layer formed on the RMG electrode.
14. The device according to claim 13 , further comprising:
a work-function tuning layer of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La2O3), or a combination thereof formed on the high-k dielectric layer.
15. The device according to claim 9 , wherein the CT spacer on the drain side of the gate stack is configured to:
store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact;
remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and
determine a current or gate threshold voltage when a read voltage is detected on the second contact and a low voltage is applied to the first contact.
16. A device comprising:
a substrate;
a gate stack formed on the substrate, the gate stack comprising:
a high-k dielectric layer,
a replacement metal gate (RMG) electrode formed over the high-k dielectric layer, and
a hardmask layer formed on the RMG electrode;
a source extension region formed in the substrate on one side of the gate stack, wherein a drain extension region is not formed on the other side of the dummy gate stack;
a tunnel liner of oxide formed on each side surface of the gate stack and on the substrate at each side of the gate stack;
a charge-trapping (CT) spacer of nitride, silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), tantalum nitride (TaN), or a combination thereof on each tunnel liner;
a source formed in the substrate on the one side of the gate stack adjacent the source extension region, and a drain in the substrate on the other side of the gate stack;
an interlayer dielectric (ILD) formed on the substrate surrounding the gate stack and CT spacers;
a first contact formed over the drain at least partially abutting the CT spacer or separated from the CT spacer by a block oxide liner; and
a second contact formed over the source.
17. The device of claim 16 , wherein the first and second contacts comprise Al, W, Ta, Ti, TaN, TiN, or a combination thereof.
18. The device according to claim 16 , further comprising:
a work-function tuning layer of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), lanthanum (La), lanthanum oxide (La2O3), or a combination thereof formed on the high-k dielectric layer.
19. The device according to claim 16 , wherein the source extension region and source are formed on the one side of the gate stack and the drain is formed on the other side of the gate stack with no drain extension region being formed.
20. The device according to claim 16 , wherein the CT spacer on the drain side of the dummy gate stack is configured to:
store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact;
remove the charges when an erase voltage is applied to one of the first and second contacts and a low voltage is applied to the other of the first and second contacts; and
determine a current or gate threshold voltage when a read voltage is detected on the second contact and a low voltage is applied to the first contact.
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US13/587,072 US9054209B2 (en) | 2012-08-16 | 2012-08-16 | Compact charge trap multi-time programmable memory |
US14/704,004 US20150236034A1 (en) | 2012-08-16 | 2015-05-05 | Novel compact charge trap multi-time programmable memory |
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CN108110006A (en) * | 2016-11-25 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof, electronic device |
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US11152264B2 (en) * | 2020-01-08 | 2021-10-19 | International Business Machines Corporation | Multi-Vt scheme with same dipole thickness for gate-all-around transistors |
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US20140048865A1 (en) | 2014-02-20 |
US9054209B2 (en) | 2015-06-09 |
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