US20150187788A1 - 3d memory structure and manufacturing method of the same - Google Patents
3d memory structure and manufacturing method of the same Download PDFInfo
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- US20150187788A1 US20150187788A1 US14/144,640 US201314144640A US2015187788A1 US 20150187788 A1 US20150187788 A1 US 20150187788A1 US 201314144640 A US201314144640 A US 201314144640A US 2015187788 A1 US2015187788 A1 US 2015187788A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H01L27/11575—
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- H01L27/11582—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Definitions
- the disclosure relates in general to a memory structure and a manufacturing method thereof, and particularly to a 3D memory structure having a 3D memory array and a manufacturing method thereof.
- stairstep structures are electrically connected to different gates, and different planes of gates are selected by the stairstep structures, such that the area occupied by the whole memory array on the substrate (2D plane) can be reduced, and areas required for disposing contacts are reduced as well.
- a 3D memory structure includes a substrate, a plurality of stacked structure, a plurality of charge trapping layers, a plurality of bit lines, and a plurality of stairstep structures.
- the stacked structures are formed on the substrate, each of the stacked structures comprises a plurality of gates and a plurality of gate insulators alternately stacked on the substrate.
- the charge trapping layers are formed on sidewalls of the stacked structures.
- the bit lines are arranged orthogonally over the stacked structures, and surfaces of the bit lines crossing the stacked structures form a plurality of memory elements.
- the stairstep structures are stacked on the substrate, and each of the stairstep structures is electrically connected to different ones of the gates.
- a manufacturing method of a 3D memory structure includes the following steps: providing a substrate; forming a plurality of stacked structures on the substrate, each of the stacked structures comprising a plurality of gates and a plurality of gate insulators alternately stacked on the substrate; forming a plurality of charge trapping layers on sidewalls of the stacked structures; forming a plurality of bit lines arranged orthogonally over the stacked structures, surfaces of the bit lines crossing the stacked structures for forming a plurality of memory elements; and forming a plurality of stairstep structures stacked on the substrate, each of the stairstep structures electrically connected to different ones of the gates.
- FIG. 1 shows a top view of a 3D memory structure according to an embodiment of the present disclosure
- FIG. 2A is a cross-sectional view along the cross-sectional line 2 A- 2 A′;
- FIG. 2B is a cross-sectional view along the cross-sectional line 2 B- 2 B′;
- FIG. 2C is a cross-sectional view along the cross-sectional line 2 C- 2 C′;
- FIG. 2D is a cross-sectional view along the cross-sectional line 2 D- 2 D′;
- FIG. 3 is a cross-sectional view along the cross-sectional line 2 A- 2 A′according to another embodiment of the present disclosure
- FIG. 4A shows a top view of a 3D memory structure according to a further embodiment of the present disclosure
- FIG. 4B is a cross-sectional view along the cross-sectional line 4 B- 4 B′;
- FIGS. 5A-14 illustrate a manufacturing method of a 3D memory structure according to an embodiment of the present disclosure.
- a 3D memory structure and a method of manufacturing the same are provided.
- stairstep structures are electrically connected to different gates, and different planes of gates are selected by the stairstep structures, such that the area occupied by the whole memory array on the substrate (2D plane) can be reduced, and areas required for disposing contacts are reduced as well.
- the following embodiments are for the purpose of elaboration only, not for limiting the scope of protection of the invention. Besides, secondary elements are omitted in the following embodiments to highlight the technical features of the invention.
- FIG. 1 shows a top view of a 3D memory structure 100 according to an embodiment of the present disclosure
- FIG. 2A is a cross-sectional view along the cross-sectional line 2 A- 2 A′
- FIG. 2B is a cross-sectional view along the cross-sectional line 2 B- 2 B′
- FIG. 2C is a cross-sectional view along the cross-sectional line 2 C- 2 C′
- FIG. 2D is a cross-sectional view along the cross-sectional line 2 D- 2 D′.
- the 3D memory structure 100 includes a substrate 110 , a plurality of stacked structures 120 , a plurality of charge trapping layers 130 , a plurality of bit lines 140 , and a plurality of stairstep structure 150 .
- the stacked structures 120 are formed on the substrate 110 , and each of the stacked structures 120 comprises a plurality of gates 121 and a plurality of gate insulators 123 alternately stacked on the substrate 110 .
- the charge trapping layers 130 are formed on sidewalls 120 s of the stacked structures 120 .
- the bit lines 140 are arranged orthogonally over the stacked structures 120 , and surfaces of the bit lines 140 cross the stacked structures 120 for forming a plurality of memory elements, thereby constructing a 3D memory array.
- the stairstep structures 150 are stacked on the substrate 110 , and each of the stairstep structures 150 is electrically connected to different ones of the gates 121 .
- the gates 121 of the same plane in the stacked structures 120 are electrically coupled via a corresponding stairstep structure 150 , and the gates 121 are such as the word lines of the 3D memory structure 100 .
- each stairstep structure 150 is connected to different gates 121 (word lines), and the word lines are for connecting to a decoding circuit for selecting a plane in the 3D memory array.
- the gates 121 (word lines) of different planes are selected via the stairstep structure 150 , such that the area occupied by the whole memory array on the substrate 110 (2D plane) can be reduced, and areas required for disposing contacts are reduced as well.
- bit lines 140 are formed from semiconductor materials, such as polysilicon, Ge, SiGe, and so on.
- the 3D memory structure 100 may further include a bottom source layer 160 , source contact structures 160 c , and an oxide layer 190 .
- the bottom source layer 160 is formed on the substrate 110 and located between the stacked structures 120 and the substrate 110 .
- the oxide layer 190 separates the bottom source layer 160 from the substrate 110 .
- the bottom source layer 160 is formed from conductive materials, such as polysilicon, heavily-doped polysilicon, Ti, TiN, or W.
- the source contact structures 160 c are electrically connected to the bottom source layer 160 .
- the source contact structures 160 c are electrically connected via the bottom source layer 160 .
- the 3D memory structure 100 may further include a plurality of gate contact structures 121 c .
- Each of the gate contact structures 120 c is electrically connected to the corresponding gate 121 via each of the stairstep structures 150 .
- the gate contact structures 121 c are arranged along a direction D 1 in which the bit lines 140 are extended.
- the stairstep structures 150 are electrically connected to different gates 121 (word lines), respectively, for selecting planes in the 3D memory array.
- the gate contact structures 121 c are arranged along the direction D 1 in which the bit lines 140 are extended, and the gate contact structures 121 c are not arranged along a direction D 2 in which the stacked structures 120 are extended. Accordingly, the ratio of the area occupied by the stairstep structures 150 in combination with the gate contact structures 121 c to the area occupied by the stacked structures 120 on the 2D plane of the 3D memory array can be minimized.
- the areas occupied by the stacked structures 120 , the stairstep structures 150 , and the gate contact structures 121 c as a whole (3D memory array) on the substrate (2D plane) can be reduced, and areas required for disposing contacts are reduced as well.
- the 3D memory structure 100 may further include a plurality of bit line contact structures 140 c , and each of the bit line contact structures 140 c is electrically connected to each of the bit lines 140 .
- the 3D memory structure 100 may further include a plurality of selection lines 170 above the gates 121 and spaced apart from one another.
- the selection lines 170 are independently controlled.
- the selection lines 170 are insulated from one another, and the selection lines 170 are insulated from the gates 121 by the gate insulators 123 .
- the gates 121 and the selection lines 170 are formed from conductive materials, and the layer of the selection lines 170 is thicker than the layer of each gate 121 , but the disclosure is not limited thereto.
- the thickness of the selection lines 170 is such as 0.05-0.5 ⁇ m, and the thickness of the gates 121 is such as 10-100 nm.
- the gates 121 include polysilicon, such as heavily-doped polysilicon.
- the gate insulators 123 include silicon oxide.
- each of the stacked structures 120 is directly connected to and terminated at the stairstep structures 150 , and the gate contact structures 121 c are arranged along the direction D 1 in which the bit lines 140 are extended, resulting in a very short distance between the gate contact structures 121 c and the gates 121 .
- the gates 121 and the selection lines 170 can electrically connect to contacts without having very long extensions along the direction D 2 in which the stacked structures 120 are extended. Therefore, the stacked structures 120 , particularly the selection lines 170 and the ground selection lines 180 which will be discussed later, can have a relatively short length.
- the area occupied by the whole memory array can be minimized, and the word lines (gates 121 ) and the selection lines 170 (as well as the ground selection lines 180 ) can have smaller resistance; as such, the dispositions of extra conductive materials or elements for lowering the resistance of the word lines and the selection lines are needless and thus avoided.
- the 3D memory structure 100 may further include a plurality of selection line contact structures 170 c , and each of the selection line contact structures 170 c is electrically connected to each of the selection lines 170 .
- the selection lines 170 are such as the string selection lines (SSL) of the 3D memory structure 100
- the selection line contact structures 170 c are such as the SSL contacts.
- two sides of the selection line contacts 170 c are disposed with 64 bit lines 140 , respectively, and each group of the 64 bit lines 140 is located between the selection line contacts 170 c and the stairstep structures 150 .
- Each of the bit lines 140 is disposed with the bit line contact structures 140 c corresponding to each of the stacked structures 120 .
- the arrangement of the combination of stairstep structure 150 /bit lines 140 /selection line contact structures 170 c can be a repeating unit, and such repeating unit can be repeatedly arranged along the direction D 2 in which the stacked structures 120 are extended.
- the selections of the number of the bit lines 140 and the number of the repeating units may vary depending on the conditions applied and are not limited thereto.
- the above-mentioned gate contact structures 121 c , the bit line contact structures 140 c , the source contact structures 160 c , and the selection line contact structures 170 c are formed from conductive materials or semiconductor materials, such as polysilicon, Si, Ge, SiGe, and so on.
- conductive materials or semiconductor materials such as polysilicon, Si, Ge, SiGe, and so on.
- the selections of the materials of the above-mentioned elements may vary depending on the conditions applied and are not limited thereto.
- the 3D memory structure 100 may further include ground selection lines (GSL) 180 on the substrate 110 .
- the ground selection lines 180 are insulated form the bottom source layer 160 by the oxide layer 181 .
- the ground selection lines 180 are formed from conductive materials, such as heavily-doped polysilicon.
- the layer of the ground selection lines 180 is thicker than the layer of each gate 121 , but the disclosure is not limited thereto. For example, the thickness of the layer of the ground selection lines 180 is about 0.05-0.5 ⁇ m.
- the 3D memory structure 100 may further include an interlayer dielectric (ILD) 195 filled outside the bit lines 140 and between the stacked structures 120 .
- the ILD 195 is formed from dielectric materials, such as BPSG, HEP OX, PEOX, TEOS, and so on.
- the dielectric material of the ILD 195 has a low dielectric constant, such as 2-15.
- the charge trapping layers 130 may be ONO composite layers or ONONO composite layers and are not limited thereto.
- the charge trapping layer 130 includes a blocking layer, a charge storage layer, and a tunneling layer (not shown).
- the blocking layer is formed on the sidewalls 120 s of the stacked structures 120 , the charge storage layer is formed on the blocking layer, and the tunneling layer is formed on the charge storage layer.
- the blocking layer is such as a silicon oxide layer with a thickness of 50-200 ⁇
- the charge storage layer is such as a silicon nitride layer with a thickness of 40-200 ⁇ .
- the tunneling layer is such as an ONO layer, wherein the two silicon oxide layers have thicknesses of 5-40 ⁇ and 5-15 ⁇ , respectively, and the silicon nitride layer has a thickness of 5-30 ⁇ .
- the charge trapping layers 130 cover the surfaces of the sidewalls of the gates 121 and the surfaces of the sidewalls of the gate insulators 123 . Also, the charge trapping layers 130 cover the surfaces of the sidewalls of the selection lines 170 and the surfaces of the sidewalls of the ground selection lines 180 .
- FIG. 3 is a cross-sectional view along the cross-sectional line 2 A- 2 A′according to another embodiment of the present disclosure.
- the charge trapping layers 330 cover the sidewalls of the gates 121 and the sidewalls of the gate insulators 123 , while the sidewalls 170 s of the selection lines 170 are exposed from the charge trapping layers 330 .
- the sidewalls 171 s of the oxide layers 171 disposed above the selection lines 170 are also exposed from the charge trapping layers 330 .
- the selection lines 170 are used for controlling the gates 121 , that is, the selection lines 170 are not regarded as storage elements.
- the sidewalls 170 s of the selection lines 170 exposed from the charge trapping layers 330 can prevent the occurrence of an undesired charge storage before the memory elements are operated, resulting in an unwanted increase of the initial threshold voltage.
- the surfaces of the sidewalls 170 s of the selection lines 170 are not covered by the charge trapping layers 330 , such that the corresponding gate insulators 123 can have a relatively smaller thickness, such as 50-70 ⁇ ; accordingly, the operation voltage of the 3D memory structure is decreased, and the controlling ability of the selection lines 170 over the gates 121 is further improved.
- the gate contact structures 121 c allow a word line signal to select a particular horizontal plane of the word lines (gates 121 ) via the stairstep structures 150 .
- a particular bit line 140 is selected via the bit line contact structures 140 c
- a particular stacked structure 120 is selected via the selection line contact structures 170 c from the selection lines 170 .
- the 3D memory structure is vertical channel type.
- the distance between the selection lines 170 and the top of the device is short; therefore, it is convenient to perform an implantation process on the selection lines 170 for lowering the resistance thereof, with a better implantation precision achieved.
- the distance between the word lines (gates 121 ) is relatively short, thereby the issues of high resistance is avoided, and the regions between the word lines can be turned on easily in operation.
- FIG. 4A shows a top view of a 3D memory structure 200 according to a further embodiment of the present disclosure
- FIG. 4B is a cross-sectional view along the cross-sectional line 4 B- 4 B′.
- the difference between the present embodiment and the embodiment illustrated in FIGS. 1 and 2 A- 2 D is that the source contact structure 460 c of the present embodiment can be disposed corresponding to where the stairstep structures 150 are located.
- the source contact structures 460 c can be electrically connected via back-end metal lines (not shown).
- back-end metal lines not shown.
- FIGS. 5A-14 illustrate a manufacturing method of a 3D memory structure 100 according to an embodiment of the present disclosure.
- the substrate 110 is provided, and the stacked structures 120 are formed on the substrate 110 .
- the manufacturing process of the stacked structures 120 includes such as the following steps.
- FIGS. 5A-5B FIG. 5B is a cross-sectional view along the cross-sectional line 5 B- 5 B′
- a plurality of conductive layers 520 and a plurality of insulating layers 523 are alternatively stacked on the substrate 110 .
- the bottom source layer 160 and the oxide layer 190 may be further formed on the substrate 110 , the bottom source layer 160 is formed between the conductive layers 521 the substrate 110 , and the oxide layer 190 is formed between the bottom source layer 160 and the substrate 110 .
- an oxide layer 581 and a conductive material layer 58 may be further formed on the substrate 110 , and the conductive material layer 580 is isolated from the bottom source layer 160 by the oxide layer 581 .
- an oxide layer 571 and a conductive material layer 570 may be further formed on the conductive layers 521 and the insulating layers 523 .
- the oxide layer 571 , the conductive material layer 570 , the conductive layers 521 , the insulating layers 523 , the oxide layer 581 , and the conductive material layer 580 are patterned.
- the patterning may be performed by an etching process, and the bottom source layer 160 having a relative large thickness may be used as an etching stop layer.
- the stacked structures 120 are formed on the substrate 110 , each stacked structure 120 including the gates 121 and the gate insulators 123 alternatively stacked on the substrate 110 .
- the gates 121 are formed of polysilicon, and the gate insulators 123 are formed of silicon oxide. Meanwhile, the bottom source layer 160 is formed between the stacked structure 120 and the substrate 110 , the selection lines 170 and the oxide layer 171 are formed separately on the gates 121 , and the selection lines 180 and the oxide layer 181 are formed on the substrate 110 . As shown in FIG. 6A , the region 650 is where the stairstep structures 150 are predetermined to be formed, and at the current step, the stairstep structures 150 are formed all together, with some needless overlying layers remained to be removed in the following steps. In other words, in the present embodiment, the gates 121 and the stairstep structures 150 may be formed in the same manufacturing process, and both of which are formed from the conductive layers 521 .
- the charge trapping layers 130 are formed on the sidewalls of the stacked structures 120 .
- the manufacturing process of the charge trapping layer 130 includes such as the following steps.
- the blocking layer is formed on the sidewalls of the stacked structures 120
- the charge storage layer is formed on the blocking layer
- the tunneling layer is formed on the charge storage layer.
- the charge trapping layers 130 are also formed on the sidewalls of the selection lines 170 and the oxide layer 171 .
- the charge trapping layer 130 may be formed by such as forming an overall charge trapping material layer on the stacked structures 120 , followed by removal of a portion of the charge trapping material layer on the top surface of the oxide layer 171 and on the surface of the substrate 110 by an etching process.
- a portion of the charge trapping layers on the sidewalls of the selection lines 170 may be optionally removed for forming the charge trapping layers 330 , as shown in FIG. 3 , for exposing the surfaces of the sidewalls 170 s of the selection lines 170 .
- bit lines 140 are formed and arranged orthogonally over the stacked structures 120 .
- the manufacturing process of the bit lines 140 includes such as the following steps.
- FIGS. 8A-8B ( FIG. 8B is a cross-sectional view along the cross-sectional line 8 B- 8 B′), a semiconductor material layer 840 is formed and covering the whole surface of the substrate 110 , the oxide layer 171 , and the charge trapping layers 130 .
- a mask layer 940 is formed on the semiconductor material layer 840 .
- the mask layer 940 may be a hard mask or an organic material mask layer.
- the organic material mask layer is such as Topaz or a composite layer of organic dielectric layer (ODL)/silicon-containing hard mask bottom antireflection coating (SHB).
- the stacked structures 120 have a relatively high height, and the focusing ability of a conventional yellow light manufacturing process is limited; accordingly, it is difficult to completely pattern the semiconductor material layer 840 , and thus a complete patterning of the semiconductor material layer 840 is more likely to be performed by using a patterned hard mask layer or a patterned organic material mask layer.
- the organic material mask layer can be easily removed after the patterning process, and the structure of the underlying layer (e.g. semiconductor material layer 840 ) is not damaged.
- the composite layer of ODL/SHB is applied by forming the ODL on the semiconductor material layer 840 , followed by forming the SHB on the ODL. And then, the semiconductor material layer 840 is patterned according to the composite layer of ODL/SHB. As such, the effect of a complete patterning from the SHB is achieved; in addition, the ODL and the SHB formed thereon can be easily removed from the semiconductor material layer 840 , such that the structure of the semiconductor material layer 840 is not damaged.
- FIGS. 10-11B FIG. 11A is a cross-sectional view along the cross-sectional line 11 A- 11 A′, and FIG. 11B is a cross-sectional view along the cross-sectional line 11 B- 11 B′
- the mask layer 940 is patterned, and the semiconductor material layer 840 is patterned according to the patterned mask layer 940 for forming the bit lines 140 . And then, the patterned mask layer is removed. It is noted that only four bit lines are shown in the present drawing. However, the amount is merely for clearly showing the manufacturing process and is not intended to limit the amount of the bit lines 140 thereto.
- the stairstep structures 150 are stacked on the substrate 110 , and each of the stairstep structures 150 is electrically connected to different gates 121 .
- the manufacturing process of the stairstep structures 150 includes such as the following steps.
- a patterned photoresist PR is disposed on the oxide layer 171 , which exposes a partial surface of the oxide layer 171 that is predetermined as the region for the stairstep structures 150 to be formed therein. And then, as shown in FIGS. 13-14 , the portions of the oxide layer 171 and the selection lines 170 exposed from the patterned photoresist PR are removed. In the embodiment, the removal is performed by such as an etching process.
- the interlayer dielectric 195 is formed.
- the interlayer dielectric 195 is filled outside the bit lines 140 and between the stacked structures 120 .
- the interlayer dielectric 195 is formed by such as depositing a dielectric material layer covering the bit lines 140 and between the stacked structures 120 , followed by a planarization of the dielectric material layer.
- the planarization of the interlayer dielectric 195 is performed by such as a CMP process.
- the gate contact structures 121 c the bit line contact structures 140 c , the source contact structures 160 c , and the selection line contact structures 170 c are formed.
- the contact structures are formed by such as a MiLC process.
- the 3D memory structure 100 as shown in FIGS. 1 and 2 A- 2 D is formed.
Abstract
Description
- 1. Technical Field
- The disclosure relates in general to a memory structure and a manufacturing method thereof, and particularly to a 3D memory structure having a 3D memory array and a manufacturing method thereof.
- 2. Description of the Related Art
- In recent years, the structures of semiconductor devices have been changed constantly, and the storage capacity of the devices has been increased continuously. Memory devices are used in storage elements for many products such as MP3 players, digital cameras, computer files, etc. As the application increases, the demand for the memory device focuses on small size and large memory capacity. For satisfying the requirement, a memory device having a high element density and a small size and the manufacturing method thereof is in need.
- As such, it is desirable to develop a three-dimensional (3D) memory device with larger number of multiple stacked planes to achieve greater storage capacity, a small size, and yet having excellent property and stability.
- The disclosure is directed to a 3D memory structure and a manufacturing method thereof. In the embodiments, stairstep structures are electrically connected to different gates, and different planes of gates are selected by the stairstep structures, such that the area occupied by the whole memory array on the substrate (2D plane) can be reduced, and areas required for disposing contacts are reduced as well.
- According to an embodiment of the present disclosure, a 3D memory structure is provided. The 3D memory structure includes a substrate, a plurality of stacked structure, a plurality of charge trapping layers, a plurality of bit lines, and a plurality of stairstep structures. The stacked structures are formed on the substrate, each of the stacked structures comprises a plurality of gates and a plurality of gate insulators alternately stacked on the substrate. The charge trapping layers are formed on sidewalls of the stacked structures. The bit lines are arranged orthogonally over the stacked structures, and surfaces of the bit lines crossing the stacked structures form a plurality of memory elements. The stairstep structures are stacked on the substrate, and each of the stairstep structures is electrically connected to different ones of the gates.
- According to another embodiment of the present disclosure, a manufacturing method of a 3D memory structure is provided. The manufacturing method includes the following steps: providing a substrate; forming a plurality of stacked structures on the substrate, each of the stacked structures comprising a plurality of gates and a plurality of gate insulators alternately stacked on the substrate; forming a plurality of charge trapping layers on sidewalls of the stacked structures; forming a plurality of bit lines arranged orthogonally over the stacked structures, surfaces of the bit lines crossing the stacked structures for forming a plurality of memory elements; and forming a plurality of stairstep structures stacked on the substrate, each of the stairstep structures electrically connected to different ones of the gates.
- The above and other embodiments of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
-
FIG. 1 shows a top view of a 3D memory structure according to an embodiment of the present disclosure; -
FIG. 2A is a cross-sectional view along thecross-sectional line 2A-2A′; -
FIG. 2B is a cross-sectional view along thecross-sectional line 2B-2B′; -
FIG. 2C is a cross-sectional view along thecross-sectional line 2C-2C′; -
FIG. 2D is a cross-sectional view along thecross-sectional line 2D-2D′; -
FIG. 3 is a cross-sectional view along thecross-sectional line 2A-2A′according to another embodiment of the present disclosure; -
FIG. 4A shows a top view of a 3D memory structure according to a further embodiment of the present disclosure; -
FIG. 4B is a cross-sectional view along thecross-sectional line 4B-4B′; and -
FIGS. 5A-14 illustrate a manufacturing method of a 3D memory structure according to an embodiment of the present disclosure. - In the embodiments of the present disclosure, a 3D memory structure and a method of manufacturing the same are provided. In the embodiments, stairstep structures are electrically connected to different gates, and different planes of gates are selected by the stairstep structures, such that the area occupied by the whole memory array on the substrate (2D plane) can be reduced, and areas required for disposing contacts are reduced as well. The following embodiments are for the purpose of elaboration only, not for limiting the scope of protection of the invention. Besides, secondary elements are omitted in the following embodiments to highlight the technical features of the invention.
-
FIG. 1 shows a top view of a3D memory structure 100 according to an embodiment of the present disclosure,FIG. 2A is a cross-sectional view along thecross-sectional line 2A-2A′,FIG. 2B is a cross-sectional view along thecross-sectional line 2B-2B′,FIG. 2C is a cross-sectional view along thecross-sectional line 2C-2C′, andFIG. 2D is a cross-sectional view along thecross-sectional line 2D-2D′. - As shown in FIGS. 1 and 2A-2C, the
3D memory structure 100 includes asubstrate 110, a plurality ofstacked structures 120, a plurality ofcharge trapping layers 130, a plurality ofbit lines 140, and a plurality ofstairstep structure 150. Thestacked structures 120 are formed on thesubstrate 110, and each of thestacked structures 120 comprises a plurality ofgates 121 and a plurality ofgate insulators 123 alternately stacked on thesubstrate 110. Thecharge trapping layers 130 are formed onsidewalls 120 s of thestacked structures 120. Thebit lines 140 are arranged orthogonally over thestacked structures 120, and surfaces of thebit lines 140 cross thestacked structures 120 for forming a plurality of memory elements, thereby constructing a 3D memory array. Thestairstep structures 150 are stacked on thesubstrate 110, and each of thestairstep structures 150 is electrically connected to different ones of thegates 121. - In one embodiment, the
gates 121 of the same plane in thestacked structures 120 are electrically coupled via acorresponding stairstep structure 150, and thegates 121 are such as the word lines of the3D memory structure 100. In other words, eachstairstep structure 150 is connected to different gates 121 (word lines), and the word lines are for connecting to a decoding circuit for selecting a plane in the 3D memory array. As such, the gates 121 (word lines) of different planes are selected via thestairstep structure 150, such that the area occupied by the whole memory array on the substrate 110 (2D plane) can be reduced, and areas required for disposing contacts are reduced as well. - In the embodiments, the
bit lines 140 are formed from semiconductor materials, such as polysilicon, Ge, SiGe, and so on. - As shown in
FIGS. 2A-2D , the3D memory structure 100 may further include abottom source layer 160,source contact structures 160 c, and anoxide layer 190. Thebottom source layer 160 is formed on thesubstrate 110 and located between thestacked structures 120 and thesubstrate 110. Theoxide layer 190 separates thebottom source layer 160 from thesubstrate 110. In the embodiment, thebottom source layer 160 is formed from conductive materials, such as polysilicon, heavily-doped polysilicon, Ti, TiN, or W. In one embodiment, thesource contact structures 160 c are electrically connected to thebottom source layer 160. Thesource contact structures 160 c are electrically connected via thebottom source layer 160. - As shown in
FIGS. 1 and 2C , the3D memory structure 100 may further include a plurality ofgate contact structures 121 c. Each of the gate contact structures 120 c is electrically connected to thecorresponding gate 121 via each of thestairstep structures 150. In the embodiment, thegate contact structures 121 c are arranged along a direction D1 in which thebit lines 140 are extended. - According to the embodiments of the present disclosure, the
stairstep structures 150 are electrically connected to different gates 121 (word lines), respectively, for selecting planes in the 3D memory array. In addition, thegate contact structures 121 c are arranged along the direction D1 in which thebit lines 140 are extended, and thegate contact structures 121 c are not arranged along a direction D2 in which thestacked structures 120 are extended. Accordingly, the ratio of the area occupied by thestairstep structures 150 in combination with thegate contact structures 121 c to the area occupied by thestacked structures 120 on the 2D plane of the 3D memory array can be minimized. As such, the areas occupied by thestacked structures 120, thestairstep structures 150, and thegate contact structures 121 c as a whole (3D memory array) on the substrate (2D plane) can be reduced, and areas required for disposing contacts are reduced as well. - As shown in
FIGS. 1 and 2B , the3D memory structure 100 may further include a plurality of bitline contact structures 140 c, and each of the bitline contact structures 140 c is electrically connected to each of the bit lines 140. - As shown in FIGS. 1 and 2A-2B, the
3D memory structure 100 may further include a plurality ofselection lines 170 above thegates 121 and spaced apart from one another. The selection lines 170 are independently controlled. The selection lines 170 are insulated from one another, and theselection lines 170 are insulated from thegates 121 by thegate insulators 123. In the embodiment, thegates 121 and theselection lines 170 are formed from conductive materials, and the layer of the selection lines 170 is thicker than the layer of eachgate 121, but the disclosure is not limited thereto. For example, the thickness of the selection lines 170 is such as 0.05-0.5 μm, and the thickness of thegates 121 is such as 10-100 nm. In the embodiment, thegates 121 include polysilicon, such as heavily-doped polysilicon. Thegate insulators 123 include silicon oxide. - According to the embodiments of the present disclosure, each of the
stacked structures 120 is directly connected to and terminated at thestairstep structures 150, and thegate contact structures 121 c are arranged along the direction D1 in which thebit lines 140 are extended, resulting in a very short distance between thegate contact structures 121 c and thegates 121. As such, thegates 121 and theselection lines 170 can electrically connect to contacts without having very long extensions along the direction D2 in which thestacked structures 120 are extended. Therefore, thestacked structures 120, particularly theselection lines 170 and theground selection lines 180 which will be discussed later, can have a relatively short length. Accordingly, the area occupied by the whole memory array can be minimized, and the word lines (gates 121) and the selection lines 170 (as well as the ground selection lines 180) can have smaller resistance; as such, the dispositions of extra conductive materials or elements for lowering the resistance of the word lines and the selection lines are needless and thus avoided. - In the embodiments, the
3D memory structure 100 may further include a plurality of selectionline contact structures 170 c, and each of the selectionline contact structures 170 c is electrically connected to each of the selection lines 170. In the embodiments, theselection lines 170 are such as the string selection lines (SSL) of the3D memory structure 100, and the selectionline contact structures 170 c are such as the SSL contacts. In the embodiment, as shown inFIG. 1 , two sides of theselection line contacts 170 c are disposed with 64bit lines 140, respectively, and each group of the 64bit lines 140 is located between theselection line contacts 170 c and thestairstep structures 150. Each of the bit lines 140 is disposed with the bitline contact structures 140 c corresponding to each of thestacked structures 120. Moreover, the arrangement of the combination ofstairstep structure 150/bit lines 140/selectionline contact structures 170 c can be a repeating unit, and such repeating unit can be repeatedly arranged along the direction D2 in which thestacked structures 120 are extended. However, the selections of the number of thebit lines 140 and the number of the repeating units may vary depending on the conditions applied and are not limited thereto. - In the embodiment, the above-mentioned
gate contact structures 121 c, the bitline contact structures 140 c, thesource contact structures 160 c, and the selectionline contact structures 170 c are formed from conductive materials or semiconductor materials, such as polysilicon, Si, Ge, SiGe, and so on. However, the selections of the materials of the above-mentioned elements may vary depending on the conditions applied and are not limited thereto. - As shown in
FIGS. 2A-2C , the3D memory structure 100 may further include ground selection lines (GSL) 180 on thesubstrate 110. In the embodiment, theground selection lines 180 are insulated form thebottom source layer 160 by theoxide layer 181. In the embodiment, theground selection lines 180 are formed from conductive materials, such as heavily-doped polysilicon. The layer of theground selection lines 180 is thicker than the layer of eachgate 121, but the disclosure is not limited thereto. For example, the thickness of the layer of theground selection lines 180 is about 0.05-0.5 μm. - As shown in
FIGS. 2A-2D , the3D memory structure 100 may further include an interlayer dielectric (ILD) 195 filled outside thebit lines 140 and between thestacked structures 120. In the embodiment, theILD 195 is formed from dielectric materials, such as BPSG, HEP OX, PEOX, TEOS, and so on. In the embodiment, the dielectric material of theILD 195 has a low dielectric constant, such as 2-15. - In the embodiments, the charge trapping layers 130 may be ONO composite layers or ONONO composite layers and are not limited thereto. In one embodiment, the
charge trapping layer 130 includes a blocking layer, a charge storage layer, and a tunneling layer (not shown). The blocking layer is formed on thesidewalls 120 s of thestacked structures 120, the charge storage layer is formed on the blocking layer, and the tunneling layer is formed on the charge storage layer. In the embodiment, the blocking layer is such as a silicon oxide layer with a thickness of 50-200 Å, and the charge storage layer is such as a silicon nitride layer with a thickness of 40-200 Å. The tunneling layer is such as an ONO layer, wherein the two silicon oxide layers have thicknesses of 5-40 Å and 5-15 Å, respectively, and the silicon nitride layer has a thickness of 5-30 Å. - In one embodiment, as shown in
FIGS. 2A-2B , the charge trapping layers 130 cover the surfaces of the sidewalls of thegates 121 and the surfaces of the sidewalls of thegate insulators 123. Also, the charge trapping layers 130 cover the surfaces of the sidewalls of theselection lines 170 and the surfaces of the sidewalls of the ground selection lines 180. -
FIG. 3 is a cross-sectional view along thecross-sectional line 2A-2A′according to another embodiment of the present disclosure. In the present embodiment, the charge trapping layers 330 cover the sidewalls of thegates 121 and the sidewalls of thegate insulators 123, while thesidewalls 170 s of theselection lines 170 are exposed from the charge trapping layers 330. In addition, thesidewalls 171 s of the oxide layers 171 disposed above theselection lines 170 are also exposed from the charge trapping layers 330. The selection lines 170 are used for controlling thegates 121, that is, theselection lines 170 are not regarded as storage elements. Therefore, thesidewalls 170 s of theselection lines 170 exposed from the charge trapping layers 330 can prevent the occurrence of an undesired charge storage before the memory elements are operated, resulting in an unwanted increase of the initial threshold voltage. Moreover, the surfaces of thesidewalls 170 s of theselection lines 170 are not covered by the charge trapping layers 330, such that thecorresponding gate insulators 123 can have a relatively smaller thickness, such as 50-70 Å; accordingly, the operation voltage of the 3D memory structure is decreased, and the controlling ability of theselection lines 170 over thegates 121 is further improved. - According to the embodiments of the present disclosure, in the
3D memory structure 100, different word lines (gates 121) are electrically connected to differentstairstep structures 150, therefore, thegate contact structures 121 c allow a word line signal to select a particular horizontal plane of the word lines (gates 121) via thestairstep structures 150. Meanwhile, aparticular bit line 140 is selected via the bitline contact structures 140 c, and a particularstacked structure 120 is selected via the selectionline contact structures 170 c from the selection lines 170. As such, it is sufficient to select a particular memory cell (memory element) from the 3D array of memory cells. - Compared to a known 3D vertical gate type memory structure, in the embodiments of the present disclosure, the 3D memory structure is vertical channel type. The distance between the
selection lines 170 and the top of the device is short; therefore, it is convenient to perform an implantation process on theselection lines 170 for lowering the resistance thereof, with a better implantation precision achieved. Moreover, the distance between the word lines (gates 121) is relatively short, thereby the issues of high resistance is avoided, and the regions between the word lines can be turned on easily in operation. -
FIG. 4A shows a top view of a3D memory structure 200 according to a further embodiment of the present disclosure, andFIG. 4B is a cross-sectional view along thecross-sectional line 4B-4B′. The difference between the present embodiment and the embodiment illustrated in FIGS. 1 and 2A-2D is that thesource contact structure 460 c of the present embodiment can be disposed corresponding to where thestairstep structures 150 are located. Thesource contact structures 460 c can be electrically connected via back-end metal lines (not shown). The similarities between the present embodiment and the previous ones are not repeated. -
FIGS. 5A-14 illustrate a manufacturing method of a3D memory structure 100 according to an embodiment of the present disclosure. - Referring to
FIGS. 5A-6B , thesubstrate 110 is provided, and thestacked structures 120 are formed on thesubstrate 110. In the embodiment, the manufacturing process of thestacked structures 120 includes such as the following steps. - As shown in
FIGS. 5A-5B (FIG. 5B is a cross-sectional view along thecross-sectional line 5B-5B′), a plurality of conductive layers 520 and a plurality of insulatinglayers 523 are alternatively stacked on thesubstrate 110. In the embodiment, thebottom source layer 160 and theoxide layer 190 may be further formed on thesubstrate 110, thebottom source layer 160 is formed between theconductive layers 521 thesubstrate 110, and theoxide layer 190 is formed between thebottom source layer 160 and thesubstrate 110. In the embodiment, anoxide layer 581 and a conductive material layer 58 may be further formed on thesubstrate 110, and theconductive material layer 580 is isolated from thebottom source layer 160 by theoxide layer 581. In the embodiment, anoxide layer 571 and aconductive material layer 570 may be further formed on theconductive layers 521 and the insulating layers 523. - As shown in
FIGS. 6A-6B (FIG. 6B is a cross-sectional view along thecross-sectional line 6B-6B′), theoxide layer 571, theconductive material layer 570, theconductive layers 521, the insulatinglayers 523, theoxide layer 581, and theconductive material layer 580 are patterned. In the embodiment, the patterning may be performed by an etching process, and thebottom source layer 160 having a relative large thickness may be used as an etching stop layer. As such, thestacked structures 120 are formed on thesubstrate 110, eachstacked structure 120 including thegates 121 and thegate insulators 123 alternatively stacked on thesubstrate 110. Thegates 121 are formed of polysilicon, and thegate insulators 123 are formed of silicon oxide. Meanwhile, thebottom source layer 160 is formed between thestacked structure 120 and thesubstrate 110, theselection lines 170 and theoxide layer 171 are formed separately on thegates 121, and theselection lines 180 and theoxide layer 181 are formed on thesubstrate 110. As shown inFIG. 6A , theregion 650 is where thestairstep structures 150 are predetermined to be formed, and at the current step, thestairstep structures 150 are formed all together, with some needless overlying layers remained to be removed in the following steps. In other words, in the present embodiment, thegates 121 and thestairstep structures 150 may be formed in the same manufacturing process, and both of which are formed from theconductive layers 521. - Next, referring to
FIGS. 7A-7B (FIG. 7B is a cross-sectional view along thecross-sectional line 7B-7B′), the charge trapping layers 130 are formed on the sidewalls of thestacked structures 120. In the embodiment, the manufacturing process of thecharge trapping layer 130 includes such as the following steps. The blocking layer is formed on the sidewalls of thestacked structures 120, the charge storage layer is formed on the blocking layer, and the tunneling layer is formed on the charge storage layer. In the embodiment, as shown inFIG. 7B , the charge trapping layers 130 are also formed on the sidewalls of theselection lines 170 and theoxide layer 171. In the embodiment, thecharge trapping layer 130 may be formed by such as forming an overall charge trapping material layer on thestacked structures 120, followed by removal of a portion of the charge trapping material layer on the top surface of theoxide layer 171 and on the surface of thesubstrate 110 by an etching process. - In another embodiment, a portion of the charge trapping layers on the sidewalls of the
selection lines 170 may be optionally removed for forming the charge trapping layers 330, as shown inFIG. 3 , for exposing the surfaces of thesidewalls 170 s of the selection lines 170. - Next, referring to
FIGS. 8A-11B , thebit lines 140 are formed and arranged orthogonally over thestacked structures 120. In the embodiment, the manufacturing process of the bit lines 140 includes such as the following steps. - As shown in
FIGS. 8A-8B (FIG. 8B is a cross-sectional view along thecross-sectional line 8B-8B′), asemiconductor material layer 840 is formed and covering the whole surface of thesubstrate 110, theoxide layer 171, and the charge trapping layers 130. - As shown in
FIGS. 9A-9B (FIG. 9B is a cross-sectional view along thecross-sectional line 9B-9B′), amask layer 940 is formed on thesemiconductor material layer 840. Themask layer 940 may be a hard mask or an organic material mask layer. The organic material mask layer is such as Topaz or a composite layer of organic dielectric layer (ODL)/silicon-containing hard mask bottom antireflection coating (SHB). Since thestacked structures 120 have a relatively high height, and the focusing ability of a conventional yellow light manufacturing process is limited; accordingly, it is difficult to completely pattern thesemiconductor material layer 840, and thus a complete patterning of thesemiconductor material layer 840 is more likely to be performed by using a patterned hard mask layer or a patterned organic material mask layer. Particularly, as thesemiconductor material layer 840 is patterned by using a patterned organic material mask layer, the organic material mask layer can be easily removed after the patterning process, and the structure of the underlying layer (e.g. semiconductor material layer 840) is not damaged. - In the embodiment, the composite layer of ODL/SHB is applied by forming the ODL on the
semiconductor material layer 840, followed by forming the SHB on the ODL. And then, thesemiconductor material layer 840 is patterned according to the composite layer of ODL/SHB. As such, the effect of a complete patterning from the SHB is achieved; in addition, the ODL and the SHB formed thereon can be easily removed from thesemiconductor material layer 840, such that the structure of thesemiconductor material layer 840 is not damaged. - As shown in
FIGS. 10-11B (FIG. 11A is a cross-sectional view along thecross-sectional line 11A-11A′, andFIG. 11B is a cross-sectional view along thecross-sectional line 11B-11B′), themask layer 940 is patterned, and thesemiconductor material layer 840 is patterned according to the patternedmask layer 940 for forming the bit lines 140. And then, the patterned mask layer is removed. It is noted that only four bit lines are shown in the present drawing. However, the amount is merely for clearly showing the manufacturing process and is not intended to limit the amount of thebit lines 140 thereto. - Next, referring to
FIGS. 12-14 (FIGS. 13 and 14 are cross-sectional views along the cross-sectional line 13-13′ in different manufacturing steps), thestairstep structures 150 are stacked on thesubstrate 110, and each of thestairstep structures 150 is electrically connected todifferent gates 121. In the embodiment, the manufacturing process of thestairstep structures 150 includes such as the following steps. - As shown in
FIG. 12 , a patterned photoresist PR is disposed on theoxide layer 171, which exposes a partial surface of theoxide layer 171 that is predetermined as the region for thestairstep structures 150 to be formed therein. And then, as shown inFIGS. 13-14 , the portions of theoxide layer 171 and theselection lines 170 exposed from the patterned photoresist PR are removed. In the embodiment, the removal is performed by such as an etching process. - Next, the
interlayer dielectric 195 is formed. Theinterlayer dielectric 195 is filled outside thebit lines 140 and between thestacked structures 120. In the embodiment, theinterlayer dielectric 195 is formed by such as depositing a dielectric material layer covering thebit lines 140 and between thestacked structures 120, followed by a planarization of the dielectric material layer. The planarization of theinterlayer dielectric 195 is performed by such as a CMP process. - Next, referring to FIGS. 1 and 2A-2D, the
gate contact structures 121 c, the bitline contact structures 140 c, thesource contact structures 160 c, and the selectionline contact structures 170 c are formed. In the embodiment, the contact structures are formed by such as a MiLC process. As such, the3D memory structure 100 as shown in FIGS. 1 and 2A-2D is formed. - While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (20)
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US20130341701A1 (en) * | 2010-10-18 | 2013-12-26 | Imec | Vertical Semiconductor Memory Device and Manufacturing Method Thereof |
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