US20150171086A1 - Selective Growth of a Work-Function Metal in a Replacement Metal Gate of a Semiconductor Device - Google Patents

Selective Growth of a Work-Function Metal in a Replacement Metal Gate of a Semiconductor Device Download PDF

Info

Publication number
US20150171086A1
US20150171086A1 US14/630,504 US201514630504A US2015171086A1 US 20150171086 A1 US20150171086 A1 US 20150171086A1 US 201514630504 A US201514630504 A US 201514630504A US 2015171086 A1 US2015171086 A1 US 2015171086A1
Authority
US
United States
Prior art keywords
recess
fet
layer
metal
wfm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/630,504
Inventor
Xiuyu Cai
Hoon Kim
Xunyuan Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Priority to US14/630,504 priority Critical patent/US20150171086A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHANG, XUNYUAN, CAI, XIUYU, KIM, HOON
Publication of US20150171086A1 publication Critical patent/US20150171086A1/en
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • This invention relates generally to the field of semiconductors and, more particularly, to forming a replacement metal gate (RMG) of a semiconductor device.
  • RMG replacement metal gate
  • MOS transistors using polysilicon gate electrodes are known.
  • Polysilicon material is able to tolerate high temperature processing better than most metals, so that polysilicon can be annealed at high temperatures along with source and drain regions.
  • polysilicon blocks ion implantation of doped atoms into a channel region, facilitating the formation of self-aligned source and drain structures after gate patterning is completed.
  • polysilicon materials as compared to most metal materials, result in polysilicon gate electrodes that operate at much slower speeds than gates made of metallic materials.
  • One way of compensating for the higher resistance of polysilicon materials is to perform extensive silicide processing on the polysilicon materials so that the speed of operation of the polysilicon materials is increased to acceptable levels.
  • Another way of compensating for the higher resistance polysilicon materials is to replace a polysilicon gate device with a metal gate device.
  • This replacement can be done with a replacement metal gate (RMG) process, wherein the higher temperature processing is performed while the polysilicon is present in the substrate, and, after such processing, the polysilicon is removed and replaced with metal to form the replacement metal gate.
  • RMG replacement metal gate
  • a device with a disposable polysilicon gate is processed, and the disposable gate and dielectrics are etched away, exposing an original gate oxide.
  • the disposable polysilicon gate is then replaced by a metal gate having lower resistivity than the polysilicon material.
  • RMG is desirable for achieving a device target at 20 nm and beyond.
  • gate resistance increases and more low-resistance metal such as tungsten (W) is needed relative to higher resistance work-function metal (WFM) such as TiN. Therefore, it is necessary for gate WFM chamfering to be performed.
  • device 100 comprises a stack of layers (i.e., a substrate 102 , a source/drain (S/D) layer 104 formed over the substrate, and an interlayer dielectric (IDL) layer 106 formed over the S/D layer 104 ), and a recess 110 formed therein.
  • S/D source/drain
  • IDL interlayer dielectric
  • Device 100 further comprises a set of spacers 112 positioned adjacent recess 110 , and a plurality of layers formed over device 100 and within recess 110 , i.e., a hafnium oxide (HfO2) layer 114 , a barrier layer 116 (e.g., titanium nitride (TiN)), a work-function (WF) layer 118 , a capping layer 120 (e.g., TiN), and an organic dielectric layer (ODL) 122 or any other patterning mask material, which is recessed.
  • HfO2 hafnium oxide
  • barrier layer 116 e.g., titanium nitride (TiN)
  • WF work-function
  • WF work-function
  • capping layer 120 e.g., TiN
  • ODL organic dielectric layer
  • a pinch-off of TiN 220 causes a seam/void 230 to form in recess 210 , which results in a non-uniform or catastrophic metal recess. Therefore, this approach is also undesirable.
  • a replacement metal gate (RMG) of a semiconductor device In general, approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically, provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer, a barrier layer, and an optional metal layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, and a metal material (e.g., Tungsten) formed within each recess.
  • WFM work-function metal
  • the risk of mask materials filling into each gate recess is reduced.
  • the selective WFM growth e.g., of a single-element metal as opposed to a metal compound improves fill-in of the metal material, which lowers gate resistance in the device.
  • One aspect of the present invention includes method for forming a replacement metal gate (RMG) of a semiconductor device, the method comprising: providing a set of field effect transistors (FET) formed over a substrate, each of the set of FETs having a recess formed therein; forming a high-k layer over the semiconductor device and within each recess; forming a barrier layer over the high-k layer; forming an organic dielectric layer (ODL) within each recess; recessing the ODL to a desired height within each recess; removing the high-k layer and the barrier layer from atop the semiconductor device selective to the ODL within each recess; removing the ODL from within each recess; selectively growing a work-function metal (WFM) within one of the recesses; and forming a metal material within each recess.
  • FET field effect transistors
  • WFM work-function metal
  • Another aspect of the present invention includes a method for selectively growing a work-function metal (WFM) within a replacement metal gate (RMG) of a semiconductor device, the method comprising: providing a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein; forming a high-k layer over the semiconductor device and within each recess; forming a barrier layer over the high-k layer; forming an organic dielectric layer (ODL) within each recess; recessing the ODL to a desired height within each recess; removing the high-k layer and the barrier layer from atop the semiconductor device selective to the ODL within each recess; removing the ODL from within each recess; and selectively growing a work-function metal (WFM) within one of the recesses.
  • WFM work-function metal
  • Yet another aspect of the present invention includes a semiconductor device, comprising: a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein; a high-k layer formed within each recess; a barrier layer formed over the high-k layer within each recess; a work-function metal (WFM) selectively grown within the recess of the n-FET; and a metal material formed within each recess.
  • p-FET p-channel field effect transistor
  • n-FET n-channel field effect transistor
  • FIG. 1 shows a cross-sectional view of a WFM recess process in a prior art semiconductor device
  • FIG. 2 shows a cross-sectional view of another WFM recess process in a prior art semiconductor device
  • FIG. 3 shows a cross-sectional view of a semiconductor device following a dummy polysilicon pull according to illustrative embodiments
  • FIG. 4 shows a cross-sectional view of the semiconductor device following deposition of a first barrier layer according to illustrative embodiments
  • FIG. 5 shows a cross-sectional view of the semiconductor device following deposition of a metal layer according to illustrative embodiments
  • FIG. 6 shows a cross-sectional view of the semiconductor device following deposition and patterning of the ODL according to illustrative embodiments
  • FIG. 7 shows a cross-sectional view of the semiconductor device following metal chamfering to remove the first barrier layer selective to the ODL according to illustrative embodiments
  • FIG. 8 shows a cross-sectional view of the semiconductor device following removal of the ODL according to illustrative embodiments
  • FIG. 9 shows a cross-sectional view of the semiconductor device following removal of the cobalt from the p-FET according to illustrative embodiments
  • FIG. 10 shows a cross-sectional view of the semiconductor device following selective growth of the n-FET WFM according to illustrative embodiments
  • FIG. 11 shows a cross-sectional view of the semiconductor device following formation of a second barrier layer and a metal material according to illustrative embodiments.
  • FIG. 12 shows a cross-sectional view of a semiconductor device, in which no metal layer is present, following formation of a second barrier layer and a metal material according to illustrative embodiments.
  • first element such as a first structure, e.g., a first layer
  • second element such as a second structure, e.g. a second layer
  • intervening elements such as an interface structure, e.g. interface layer
  • depositing may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
  • CVD chemical vapor deposition
  • LPCVD low-pressure CVD
  • PECVD plasma-enhanced CVD
  • SACVD semi-
  • a replacement metal gate (RMG) of a semiconductor device is disclosed.
  • p-FET p-channel field effect transistor
  • n-FET n-channel field effect transistor
  • WFM work-function metal
  • a metal material e.g., Tungsten
  • FIG. 3 shows a cross sectional view of a semiconductor device 300 according to an embodiment of the invention.
  • Device 300 comprises a substrate 302 having an n-FET 304 and a p-FET 306 formed thereon, n-FET 304 and p-FET 306 each having a recess 310 formed therein. Each recess 310 is formed following a dummy polysilicon pull, as is known in the art.
  • Device 300 further comprises source/drains (S/D) 312 , a liner layer 314 (e.g., SiN), an oxide interlayer dielectric (ILD) 318 , and a set of spacers 320 .
  • S/D source/drains
  • liner layer 314 e.g., SiN
  • ILD oxide interlayer dielectric
  • ILD 318 may be formed by a deposition technique known in the art, for example CVD, high-density plasma chemical vapor deposition (HDPCVD), ALD, spin-on, sputtering, or other suitable methods. ILD 318 may also contain a material that has a high etching selectivity with the polysilicon of substrate 302 . As shown, each recess 310 is formed between each set of spacers 320 .
  • substrate 302 includes a silicon substrate, e.g., a wafer, either planar or finned.
  • substrate as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention.
  • the semiconductor substrate may comprise a semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith.
  • a portion or entire semiconductor substrate may be amorphous, polycrystalline, or single-crystalline.
  • the semiconductor substrate employed in the present invention may also comprise a hybrid oriented (HOT) semiconductor substrate in which the HOT substrate has surface regions of different crystallographic orientation.
  • the semiconductor substrate may be doped, undoped or contain doped regions and undoped regions therein.
  • the semiconductor substrate may contain regions with strain and regions without strain therein, or contain regions of tensile strain and compressive strain.
  • substrate 302 may be planar or finned.
  • fins usually include silicon and form the body of the transistor device.
  • the channel of the transistor is formed in this vertical fin.
  • a gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel.
  • Other advantages of FinFET devices include reduced short channel effect and higher current flow. FinFET devices offer several advantages over traditional, planar devices. These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip.
  • IC integrated circuit
  • N-FET 304 and p-FET 306 may be fabricated using any suitable process including one or more photolithography and etch processes.
  • the photolithography process may include forming a photoresist layer (not shown) overlying substrate 302 (e.g., on a silicon layer), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist.
  • the masking element may then be used to form n-FET 304 and p-FET 306 into the silicon layer, e.g., using reactive ion etch (RIE) and/or other suitable processes.
  • RIE reactive ion etch
  • n-FET 304 and p-FET 306 are formed by a double-patterning lithography (DPL) process.
  • DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density.
  • high-k layer 424 and a barrier layer 426 are formed over device 400 , including within each recess 410 .
  • high-k layer 424 comprises a hafnium oxide (HfO2) layer deposited to thickness of approximately 2 nm
  • barrier layer 426 comprises a titanium nitride (TiN) layer deposited to a thickness of approximately 1 nm.
  • High-k layer 424 and barrier layer 426 may be formed using ALD, which involves the deposition of successive monolayers over a substrate within a deposition chamber typically maintained at sub-atmospheric pressure.
  • An exemplary ALD method includes feeding a single vaporized precursor to a deposition chamber effective to form a first monolayer over a substrate received therein. Thereafter, the flow of the first deposition precursor is ceased and an inert purge gas is flowed through the chamber effective to remove any remaining first precursor, which is not adhering to the substrate from the chamber. Subsequently, a second vapor precursor different from the first is flowed to the chamber effective to form a second monolayer on/with the first monolayer. The second monolayer might react with the first monolayer. Additional precursors can form successive monolayers, or the above process can be repeated until a desired thickness and composition layer has been formed over the substrate.
  • high-k generally refers to a dielectric material having a dielectric constant (k) value greater than that of silicon oxide.
  • the high-k material has a dielectric constant greater than 5, more preferably greater than about 10 .
  • Exemplary high-k materials include, without limitation, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , lanthanide oxides and mixtures thereof, silicates and materials such as YSZ (yttria-stabilized zirconia), BST, BT, ST, and SBT.
  • Barrier layer 426 may comprise metals, metal nitrides, and other conductive metal compounds from vapor phase reactants.
  • Metals, metal nitrides, metal carbides, metal borides, conductive oxides and other conductive metal compounds that can serve as substrate materials over which noble metals can be selectively deposited may include, for example and without limitation, selections from the group consisting of Ta, TaN, TaC x , TaB x , Ti, TiN, TiC x , TiB x , Nb, NbN, NbC x , NbB x Mo, MoN, MoC x , MoB x , W, WN, WC x , WB x , V, Cr, Fe, Cu, Co, Ni, Cd, Zn, Al, Ag, Au, Ru, RuO x , Rh, Pt, Pd, Ir, IrO x and Os.
  • a single-element metal layer 530 (e.g., cobalt) is formed over barrier layer 526 .
  • Metal layer 530 may be formed (e.g., using ALD) to a thickness of approximately 1 nm, which is adequate to act as a seeding layer for a subsequent selective growth of a WMF, which is preferably a single-element, “true” metal (e.g., Co, Ti, Al, etc.), as opposed to a metal compound (e.g., TiN, TiO2, etc.).
  • Metal layer 530 conforms to device 500 , including within each recess 510 , as shown.
  • ODL 632 is formed within each recess 610 to a desired height ‘H’.
  • ODL 632 or other similar masking materials (e.g., an organic planarization layer (OPL)), could be used as a metal chamfer mask.
  • ODL 632 may include a photo-sensitive organic polymer or an etch type organic compound.
  • the photo-sensitive organic polymer may be polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). These materials may be formed within each recess 610 using spin-on techniques or vapor deposition techniques.
  • a metal chamfer is then performed, as shown in FIG. 7 .
  • a wet/dry etch is performed to remove of high-k layer 724 , barrier layer 726 , and metal layer 730 from device 700 selective to ODL 732 within each recess 710 .
  • ODL 832 is then removed from within each recess 810 , followed by removal of metal layer 930 from p-FET 906 , as shown in FIG. 9 .
  • a WFM 1034 (e.g., a single-element metal, which can serve to tune threshold voltage for NFET) is formed over metal layer 1030 within recess 1010 of n-FET 1004 .
  • WFM 1034 is selectively grown over metal layer 1030 and may comprise aluminum (Al) or an Al/Ti multilayer stack, where the Al/Ti thickness can be tuned for target composition ratio to achieve the desired work function. Both Al and Ti could be selectively grown on the seeding metal layer 1030 . Since Co can be oxidized in previous patterning steps, an optional in-situ H2 plasma treatment subsequently performed reduces CoOx back to Co to achieve the selective growth.
  • an additional drive-in anneal may be needed for Co/AI or Co/Al/Ti to be mixed. It will be appreciated that the selective growth of NFET WFM 1034 eliminates the need for an additional chamfer because there is no growth on the dielectric top (i.e., horizontal) surfaces of HfO2 layer 1024 , barrier layer 1026 , and metal layer 1030 , or on the sidewalls of spacers 1020 .
  • a second barrier layer 1136 (e.g., TiN) is formed over device 1100 and within each recess 1110 , followed by deposition and planarization of a metal material 1140 (e.g., Tungsten) within each recess 1110 .
  • second barrier layer 1136 is formed over WFM 1134 and the sidewalls of spacers 1120 in recess 1110 of n-FET 1104 , and over the sidewall of spacers 1120 in recess 1110 of p-FET 1106 .
  • Metal material 1140 is deposited over all of device 1100 , and removed, e.g., via CMP, selective to ILD 118 and set of spacers 1120 . As such, the RMG stacks are formed for both n-FET 1104 and p-FET 1106 .
  • FIG. 12 another embodiment for selectively growing WFM within the n-FET is shown.
  • processing is similar to that shown in FIGS. 3-11 .
  • no metal layer e.g., cobalt
  • WFM 1234 is selectively grown directly on barrier layer 1226 , and subsequently removed from p-FET 1206 , resulting in device 1200 shown in FIG. 12 .
  • second barrier layer 1236 is formed over device 1200 and within each recess 1210 , followed by deposition and planarization of metal material 1240 (e.g., Tungsten) within each recess 1210 .
  • metal material 1240 e.g., Tungsten
  • second barrier layer 1236 is formed over WFM 1234 and the sidewalls of spacers 1220 in recess 1210 of n-FET 1204 , and over the sidewall of spacers 1220 in recess 1210 of p-FET 1206 .
  • embodiments of the invention have at least the following advantages.
  • design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein.
  • data sets can be created to perform the processing steps described herein, including: providing a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein; forming a high-k layer over the semiconductor device and within each recess; forming a barrier layer over the high-k layer; forming an organic dielectric layer (ODL) within each recess; recessing the ODL to a desired height within each recess; removing the high-k layer and the barrier layer from atop the semiconductor device selective to the ODL within each recess; removing the ODL from within each recess; selectively growing a work-function metal (WFM) within one of the recesses; forming a second barrier layer within each recess after the WFM is selective
  • WFM work
  • Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof.
  • a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof.
  • a tool can be a computing device or other appliance on which software runs or in which hardware is implemented.
  • a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module.
  • the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules.
  • the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Description

    BACKGROUND
  • 1. Technical Field
  • This invention relates generally to the field of semiconductors and, more particularly, to forming a replacement metal gate (RMG) of a semiconductor device.
  • 2. Related Art
  • Metal-oxide-semiconductor (MOS) transistors using polysilicon gate electrodes are known. Polysilicon material is able to tolerate high temperature processing better than most metals, so that polysilicon can be annealed at high temperatures along with source and drain regions. In addition, polysilicon blocks ion implantation of doped atoms into a channel region, facilitating the formation of self-aligned source and drain structures after gate patterning is completed.
  • The high resistivities of polysilicon materials, as compared to most metal materials, result in polysilicon gate electrodes that operate at much slower speeds than gates made of metallic materials. One way of compensating for the higher resistance of polysilicon materials is to perform extensive silicide processing on the polysilicon materials so that the speed of operation of the polysilicon materials is increased to acceptable levels.
  • Another way of compensating for the higher resistance polysilicon materials is to replace a polysilicon gate device with a metal gate device. This replacement can be done with a replacement metal gate (RMG) process, wherein the higher temperature processing is performed while the polysilicon is present in the substrate, and, after such processing, the polysilicon is removed and replaced with metal to form the replacement metal gate. More specifically, a device with a disposable polysilicon gate is processed, and the disposable gate and dielectrics are etched away, exposing an original gate oxide. The disposable polysilicon gate is then replaced by a metal gate having lower resistivity than the polysilicon material.
  • RMG is desirable for achieving a device target at 20 nm and beyond. However, as gate dimensions shrink, gate resistance increases and more low-resistance metal such as tungsten (W) is needed relative to higher resistance work-function metal (WFM) such as TiN. Therefore, it is necessary for gate WFM chamfering to be performed. This is demonstrated in prior art device 100 of FIG. 1. Here, device 100 comprises a stack of layers (i.e., a substrate 102, a source/drain (S/D) layer 104 formed over the substrate, and an interlayer dielectric (IDL) layer 106 formed over the S/D layer 104), and a recess 110 formed therein. Device 100 further comprises a set of spacers 112 positioned adjacent recess 110, and a plurality of layers formed over device 100 and within recess 110, i.e., a hafnium oxide (HfO2) layer 114, a barrier layer 116 (e.g., titanium nitride (TiN)), a work-function (WF) layer 118, a capping layer 120 (e.g., TiN), and an organic dielectric layer (ODL) 122 or any other patterning mask material, which is recessed. However, tight PC dimensions make metal chamfering challenging. In this embodiment, a narrow gap (e.g., less than 2 nm) is difficult to fill in with the ODL or any other patterning mask material.
  • In another approach, shown in FIG. 2, a pinch-off of TiN 220 causes a seam/void 230 to form in recess 210, which results in a non-uniform or catastrophic metal recess. Therefore, this approach is also undesirable.
    • SUMMARY
  • In general, approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically, provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer, a barrier layer, and an optional metal layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, and a metal material (e.g., Tungsten) formed within each recess. By performing a chamfer of the high-k layer, barrier layer, and the metal layer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth (e.g., of a single-element metal as opposed to a metal compound) improves fill-in of the metal material, which lowers gate resistance in the device.
  • One aspect of the present invention includes method for forming a replacement metal gate (RMG) of a semiconductor device, the method comprising: providing a set of field effect transistors (FET) formed over a substrate, each of the set of FETs having a recess formed therein; forming a high-k layer over the semiconductor device and within each recess; forming a barrier layer over the high-k layer; forming an organic dielectric layer (ODL) within each recess; recessing the ODL to a desired height within each recess; removing the high-k layer and the barrier layer from atop the semiconductor device selective to the ODL within each recess; removing the ODL from within each recess; selectively growing a work-function metal (WFM) within one of the recesses; and forming a metal material within each recess.
  • Another aspect of the present invention includes a method for selectively growing a work-function metal (WFM) within a replacement metal gate (RMG) of a semiconductor device, the method comprising: providing a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein; forming a high-k layer over the semiconductor device and within each recess; forming a barrier layer over the high-k layer; forming an organic dielectric layer (ODL) within each recess; recessing the ODL to a desired height within each recess; removing the high-k layer and the barrier layer from atop the semiconductor device selective to the ODL within each recess; removing the ODL from within each recess; and selectively growing a work-function metal (WFM) within one of the recesses.
  • Yet another aspect of the present invention includes a semiconductor device, comprising: a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein; a high-k layer formed within each recess; a barrier layer formed over the high-k layer within each recess; a work-function metal (WFM) selectively grown within the recess of the n-FET; and a metal material formed within each recess.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
  • FIG. 1 shows a cross-sectional view of a WFM recess process in a prior art semiconductor device;
  • FIG. 2 shows a cross-sectional view of another WFM recess process in a prior art semiconductor device;
  • FIG. 3 shows a cross-sectional view of a semiconductor device following a dummy polysilicon pull according to illustrative embodiments;
  • FIG. 4 shows a cross-sectional view of the semiconductor device following deposition of a first barrier layer according to illustrative embodiments;
  • FIG. 5 shows a cross-sectional view of the semiconductor device following deposition of a metal layer according to illustrative embodiments;
  • FIG. 6 shows a cross-sectional view of the semiconductor device following deposition and patterning of the ODL according to illustrative embodiments;
  • FIG. 7 shows a cross-sectional view of the semiconductor device following metal chamfering to remove the first barrier layer selective to the ODL according to illustrative embodiments;
  • FIG. 8 shows a cross-sectional view of the semiconductor device following removal of the ODL according to illustrative embodiments;
  • FIG. 9 shows a cross-sectional view of the semiconductor device following removal of the cobalt from the p-FET according to illustrative embodiments;
  • FIG. 10 shows a cross-sectional view of the semiconductor device following selective growth of the n-FET WFM according to illustrative embodiments;
  • FIG. 11 shows a cross-sectional view of the semiconductor device following formation of a second barrier layer and a metal material according to illustrative embodiments; and
  • FIG. 12 shows a cross-sectional view of a semiconductor device, in which no metal layer is present, following formation of a second barrier layer and a metal material according to illustrative embodiments.
    •
  • The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements.
  • Furthermore, certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines, which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. Also, for clarity, some reference numbers may be omitted in certain drawings.
    • DETAILED DESCRIPTION
  • Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
  • Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
  • The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
  • As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
  • As mentioned above, approaches for forming a replacement metal gate (RMG) of a semiconductor device are disclosed. Specifically, provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, and a metal material (e.g., Tungsten) formed within each recess. By performing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth methodology makes it easier to fill-in of the patterning mask material such as ODL, because of the reduced required WFM thickness before metal chamfering.
  • With reference again to the figures, FIG. 3 shows a cross sectional view of a semiconductor device 300 according to an embodiment of the invention. Device 300 comprises a substrate 302 having an n-FET 304 and a p-FET 306 formed thereon, n-FET 304 and p-FET 306 each having a recess 310 formed therein. Each recess 310 is formed following a dummy polysilicon pull, as is known in the art. Device 300 further comprises source/drains (S/D) 312, a liner layer 314 (e.g., SiN), an oxide interlayer dielectric (ILD) 318, and a set of spacers 320. ILD 318 may be formed by a deposition technique known in the art, for example CVD, high-density plasma chemical vapor deposition (HDPCVD), ALD, spin-on, sputtering, or other suitable methods. ILD 318 may also contain a material that has a high etching selectivity with the polysilicon of substrate 302. As shown, each recess 310 is formed between each set of spacers 320.
  • In one embodiment, substrate 302 includes a silicon substrate, e.g., a wafer, either planar or finned. The term “substrate” as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention. For example, the semiconductor substrate may comprise a semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith. A portion or entire semiconductor substrate may be amorphous, polycrystalline, or single-crystalline. In addition to the aforementioned types of semiconductor substrates, the semiconductor substrate employed in the present invention may also comprise a hybrid oriented (HOT) semiconductor substrate in which the HOT substrate has surface regions of different crystallographic orientation. The semiconductor substrate may be doped, undoped or contain doped regions and undoped regions therein. The semiconductor substrate may contain regions with strain and regions without strain therein, or contain regions of tensile strain and compressive strain.
  • Furthermore, substrate 302 may be planar or finned. In a typical finned substrate, he fins usually include silicon and form the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow. FinFET devices offer several advantages over traditional, planar devices. These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip.
  • N-FET 304 and p-FET 306 may be fabricated using any suitable process including one or more photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) overlying substrate 302 (e.g., on a silicon layer), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. The masking element may then be used to form n-FET 304 and p-FET 306 into the silicon layer, e.g., using reactive ion etch (RIE) and/or other suitable processes. In one embodiment, n-FET 304 and p-FET 306 are formed by a double-patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density.
  • Next, as shown in FIG. 4, a high-k layer 424 and a barrier layer 426 are formed over device 400, including within each recess 410. In this embodiment, high-k layer 424 comprises a hafnium oxide (HfO2) layer deposited to thickness of approximately 2 nm, while barrier layer 426 comprises a titanium nitride (TiN) layer deposited to a thickness of approximately 1 nm. High-k layer 424 and barrier layer 426 may be formed using ALD, which involves the deposition of successive monolayers over a substrate within a deposition chamber typically maintained at sub-atmospheric pressure. With typical ALD, successive mono-atomic layers are adsorbed to a substrate and/or reacted with the outer layer on the substrate, typically by successive feeding of different deposition precursors to the substrate surface. An exemplary ALD method includes feeding a single vaporized precursor to a deposition chamber effective to form a first monolayer over a substrate received therein. Thereafter, the flow of the first deposition precursor is ceased and an inert purge gas is flowed through the chamber effective to remove any remaining first precursor, which is not adhering to the substrate from the chamber. Subsequently, a second vapor precursor different from the first is flowed to the chamber effective to form a second monolayer on/with the first monolayer. The second monolayer might react with the first monolayer. Additional precursors can form successive monolayers, or the above process can be repeated until a desired thickness and composition layer has been formed over the substrate.
  • Furthermore, it will be appreciated that “high-k” generally refers to a dielectric material having a dielectric constant (k) value greater than that of silicon oxide. Preferably, the high-k material has a dielectric constant greater than 5, more preferably greater than about 10. Exemplary high-k materials include, without limitation, HfO2, ZrO2, Al2O3, TiO2, Ta2O5, lanthanide oxides and mixtures thereof, silicates and materials such as YSZ (yttria-stabilized zirconia), BST, BT, ST, and SBT. Barrier layer 426 may comprise metals, metal nitrides, and other conductive metal compounds from vapor phase reactants. Metals, metal nitrides, metal carbides, metal borides, conductive oxides and other conductive metal compounds that can serve as substrate materials over which noble metals can be selectively deposited may include, for example and without limitation, selections from the group consisting of Ta, TaN, TaCx, TaBx, Ti, TiN, TiCx, TiBx, Nb, NbN, NbCx, NbBxMo, MoN, MoCx, MoBx, W, WN, WCx, WBx, V, Cr, Fe, Cu, Co, Ni, Cd, Zn, Al, Ag, Au, Ru, RuOx, Rh, Pt, Pd, Ir, IrOx and Os.
  • In an exemplary embodiment, as shown in FIG. 5, a single-element metal layer 530 (e.g., cobalt) is formed over barrier layer 526. Metal layer 530 may be formed (e.g., using ALD) to a thickness of approximately 1 nm, which is adequate to act as a seeding layer for a subsequent selective growth of a WMF, which is preferably a single-element, “true” metal (e.g., Co, Ti, Al, etc.), as opposed to a metal compound (e.g., TiN, TiO2, etc.). Metal layer 530 conforms to device 500, including within each recess 510, as shown.
  • Next, device 600 is patterned for metal chamfering, as shown in FIG. 6. Here, an organic dielectric layer (ODL) 632 is formed within each recess 610 to a desired height ‘H’. ODL 632, or other similar masking materials (e.g., an organic planarization layer (OPL)), could be used as a metal chamfer mask. ODL 632 (or OPL) may include a photo-sensitive organic polymer or an etch type organic compound. For instance, the photo-sensitive organic polymer may be polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). These materials may be formed within each recess 610 using spin-on techniques or vapor deposition techniques.
  • A metal chamfer is then performed, as shown in FIG. 7. In this embodiment, a wet/dry etch is performed to remove of high-k layer 724, barrier layer 726, and metal layer 730 from device 700 selective to ODL 732 within each recess 710. As shown in FIG. 8, ODL 832 is then removed from within each recess 810, followed by removal of metal layer 930 from p-FET 906, as shown in FIG. 9.
  • Next, as shown in FIG. 10, a WFM 1034 (e.g., a single-element metal, which can serve to tune threshold voltage for NFET) is formed over metal layer 1030 within recess 1010 of n-FET 1004. In an exemplary embodiment, WFM 1034 is selectively grown over metal layer 1030 and may comprise aluminum (Al) or an Al/Ti multilayer stack, where the Al/Ti thickness can be tuned for target composition ratio to achieve the desired work function. Both Al and Ti could be selectively grown on the seeding metal layer 1030. Since Co can be oxidized in previous patterning steps, an optional in-situ H2 plasma treatment subsequently performed reduces CoOx back to Co to achieve the selective growth. In one embodiment, an additional drive-in anneal may be needed for Co/AI or Co/Al/Ti to be mixed. It will be appreciated that the selective growth of NFET WFM 1034 eliminates the need for an additional chamfer because there is no growth on the dielectric top (i.e., horizontal) surfaces of HfO2 layer 1024, barrier layer 1026, and metal layer 1030, or on the sidewalls of spacers 1020.
  • Processing continues as shown in FIG. 11, wherein a second barrier layer 1136 (e.g., TiN) is formed over device 1100 and within each recess 1110, followed by deposition and planarization of a metal material 1140 (e.g., Tungsten) within each recess 1110. As shown, second barrier layer 1136 is formed over WFM 1134 and the sidewalls of spacers 1120 in recess 1110 of n-FET 1104, and over the sidewall of spacers 1120 in recess 1110 of p-FET 1106. Metal material 1140 is deposited over all of device 1100, and removed, e.g., via CMP, selective to ILD 118 and set of spacers 1120. As such, the RMG stacks are formed for both n-FET 1104 and p-FET 1106.
  • Turning now to FIG. 12, another embodiment for selectively growing WFM within the n-FET is shown. In this embodiment, processing is similar to that shown in FIGS. 3-11. However, no metal layer (e.g., cobalt) is formed over high-k layer 1224 and barrier layer 1226. Instead, WFM 1234 is selectively grown directly on barrier layer 1226, and subsequently removed from p-FET 1206, resulting in device 1200 shown in FIG. 12. Processing then continues, and second barrier layer 1236 is formed over device 1200 and within each recess 1210, followed by deposition and planarization of metal material 1240 (e.g., Tungsten) within each recess 1210. As shown, second barrier layer 1236 is formed over WFM 1234 and the sidewalls of spacers 1220 in recess 1210 of n-FET 1204, and over the sidewall of spacers 1220 in recess 1210 of p-FET 1206.
  • As shown and described herein, embodiments of the invention have at least the following advantages. First, early WFM chamfering eliminates the issue of mask materials filling into gate trench. Second, the selective metal growth makes it easier to increase the amount of tungsten present in the device, which lowers gate resistance.
  • In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example, data sets can be created to perform the processing steps described herein, including: providing a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein; forming a high-k layer over the semiconductor device and within each recess; forming a barrier layer over the high-k layer; forming an organic dielectric layer (ODL) within each recess; recessing the ODL to a desired height within each recess; removing the high-k layer and the barrier layer from atop the semiconductor device selective to the ODL within each recess; removing the ODL from within each recess; selectively growing a work-function metal (WFM) within one of the recesses; forming a second barrier layer within each recess after the WFM is selectively grown within the recess of the n-FET; and forming a metal material within each recess.
  • Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.
  • It is apparent that there has been provided approaches for selectively growing a WFM within RMGs of a semiconductor device. While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.

Claims (6)

1-15. (canceled)
16. A semiconductor device, comprising:
a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein;
a high-k layer formed within each recess;
a barrier layer formed over the high-k layer within each recess;
a work-function metal (WFM) selectively grown within the recess of the n-FET; and
a metal material formed within each recess.
17. The device according to claim 16, further comprising a metal layer formed over the barrier layer within the recess of the n-FET.
18. The device according to claim 16, further comprising a second barrier layer formed over the WFM within the recess of the n-FET and over the barrier layer within the recess of the p-FET.
19. The device according to claim 16, wherein the high-k layer comprises hafnium oxide, and wherein the barrier layer comprises titanium nitride.
20. The device according to claim 16, the n-FET and p-FET each comprising a fin-shaped FET.
US14/630,504 2013-10-17 2015-02-24 Selective Growth of a Work-Function Metal in a Replacement Metal Gate of a Semiconductor Device Abandoned US20150171086A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/630,504 US20150171086A1 (en) 2013-10-17 2015-02-24 Selective Growth of a Work-Function Metal in a Replacement Metal Gate of a Semiconductor Device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/056,144 US9018711B1 (en) 2013-10-17 2013-10-17 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
US14/630,504 US20150171086A1 (en) 2013-10-17 2015-02-24 Selective Growth of a Work-Function Metal in a Replacement Metal Gate of a Semiconductor Device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/056,144 Division US9018711B1 (en) 2013-10-17 2013-10-17 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device

Publications (1)

Publication Number Publication Date
US20150171086A1 true US20150171086A1 (en) 2015-06-18

Family

ID=52825453

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/056,144 Expired - Fee Related US9018711B1 (en) 2013-10-17 2013-10-17 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
US14/630,504 Abandoned US20150171086A1 (en) 2013-10-17 2015-02-24 Selective Growth of a Work-Function Metal in a Replacement Metal Gate of a Semiconductor Device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/056,144 Expired - Fee Related US9018711B1 (en) 2013-10-17 2013-10-17 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device

Country Status (1)

Country Link
US (2) US9018711B1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496361B1 (en) 2015-08-27 2016-11-15 United Microelectronics Corp. Selectively deposited metal gates and method of manufacturing thereof
US9960284B2 (en) * 2015-10-30 2018-05-01 Globalfoundries Inc. Semiconductor structure including a varactor
US10032890B2 (en) 2015-12-08 2018-07-24 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor devices
US10177042B2 (en) 2015-10-21 2019-01-08 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US10367078B2 (en) * 2017-11-09 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and FinFET devices having shielding layers
US10636890B2 (en) 2018-05-08 2020-04-28 Globalfoundries Inc. Chamfered replacement gate structures

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150118836A1 (en) * 2013-10-28 2015-04-30 United Microelectronics Corp. Method of fabricating semiconductor device
US9570319B2 (en) * 2014-05-30 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device
US9190488B1 (en) * 2014-08-13 2015-11-17 Globalfoundries Inc. Methods of forming gate structure of semiconductor devices and the resulting devices
US9379221B1 (en) * 2015-01-08 2016-06-28 International Business Machines Corporation Bottom-up metal gate formation on replacement metal gate finFET devices
US9613959B2 (en) 2015-07-28 2017-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming metal gate to mitigate antenna defect
US9722038B2 (en) * 2015-09-11 2017-08-01 International Business Machines Corporation Metal cap protection layer for gate and contact metallization
KR102480219B1 (en) 2015-09-16 2022-12-26 삼성전자주식회사 Semiconductor devices and methods of manufacturing semiconductor devices
US9673101B2 (en) 2015-09-30 2017-06-06 International Business Machines Corporation Minimize middle-of-line contact line shorts
US9865703B2 (en) * 2015-12-31 2018-01-09 International Business Machines Corporation High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process
US10283605B2 (en) 2016-01-29 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd Self-aligned metal gate etch back process and device
US10038076B2 (en) 2016-08-08 2018-07-31 International Business Machines Corporation Parasitic capacitance reducing contact structure in a finFET
US20180138123A1 (en) * 2016-11-15 2018-05-17 Globalfoundries Inc. Interconnect structure and method of forming the same
US9780197B1 (en) 2016-12-14 2017-10-03 Globalfoundries Inc. Method of controlling VFET channel length
DE102017117794A1 (en) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. RETENTION AND SELECTIVE DEPOSITION OF A METAL GATE
US10879370B2 (en) * 2016-12-15 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Etching back and selective deposition of metal gate
US10056303B1 (en) 2017-04-21 2018-08-21 Globalfoundries Inc. Integration scheme for gate height control and void free RMG fill
KR20220129116A (en) * 2017-06-23 2022-09-22 메르크 파텐트 게엠베하 Methods of atomic layer deposition for selective film growth
TWI729181B (en) * 2017-08-03 2021-06-01 聯華電子股份有限公司 Semiconductor device and method for fabricating the same
US10014180B1 (en) 2017-08-21 2018-07-03 Globalfoundries Inc. Tungsten gate and method for forming
CN110690199B (en) 2018-07-06 2023-07-25 三星电子株式会社 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
US10727317B2 (en) 2018-10-04 2020-07-28 International Business Machines Corporation Bottom contact formation for vertical transistor devices
US10804163B2 (en) * 2018-10-31 2020-10-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of metal gate formation and structures formed by the same
CN110752180B (en) * 2019-10-25 2022-03-08 中国科学院微电子研究所 Substrate and preparation method thereof
CN113314530A (en) * 2020-02-27 2021-08-27 台湾积体电路制造股份有限公司 Method of manufacturing semiconductor device and semiconductor device

Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020177263A1 (en) * 2001-05-24 2002-11-28 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US20030067017A1 (en) * 2001-10-05 2003-04-10 Meikei Ieong Variable threshold voltage double gated transistors and method of fabrication
US20040142524A1 (en) * 2002-08-12 2004-07-22 Grupp Daniel E. Insulated gate field effect transistor having passivated Schottky barriers to the channel
US20050020020A1 (en) * 2002-07-16 2005-01-27 Nadine Collaert Integrated semiconductor fin device and a method for manufacturing such device
US20050148137A1 (en) * 2003-12-30 2005-07-07 Brask Justin K. Nonplanar transistors with metal gate electrodes
US20050153530A1 (en) * 2004-01-09 2005-07-14 International Business Machines Corporation Fet gate structure with metal gate electrode and silicide contact
US20060071285A1 (en) * 2004-09-29 2006-04-06 Suman Datta Inducing strain in the channels of metal gate transistors
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20070111419A1 (en) * 2005-09-28 2007-05-17 Doyle Brian S CMOS Devices with a single work function gate electrode and method of fabrication
US20070262389A1 (en) * 2004-01-16 2007-11-15 Robert Chau Tri-gate transistors and methods to fabricate same
US20090042405A1 (en) * 2004-09-08 2009-02-12 Doczy Mark L Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US20110062526A1 (en) * 2009-09-14 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
US20110193181A1 (en) * 2003-11-12 2011-08-11 Samsung Electronics Co., Ltd. Semiconductor device having different metal gate structures
US20110215409A1 (en) * 2010-03-04 2011-09-08 International Business Machines Corporation Structure and method to make replacement metal gate and contact metal
US20120248509A1 (en) * 2011-03-30 2012-10-04 International Business Machines Corporation Structure and process for metal fill in replacement metal gate integration
US20120313178A1 (en) * 2011-06-13 2012-12-13 Po-Jui Liao Semiconductor device having metal gate and manufacturing method thereof
US20130026578A1 (en) * 2011-07-28 2013-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US20130280900A1 (en) * 2012-04-24 2013-10-24 United Microelectronics Corp. Manufacturing method for semiconductor device having metal gate
US20130295758A1 (en) * 2012-05-02 2013-11-07 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
US20130299914A1 (en) * 2012-05-14 2013-11-14 Ju-youn Kim Semiconductor device and method for manufacturing the device
US20140084383A1 (en) * 2012-09-27 2014-03-27 Globalfoundries Inc. Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
US20140256094A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and Methods for Forming the Same
US20140312423A1 (en) * 2013-04-18 2014-10-23 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted soi mosfets
US20140349476A1 (en) * 2013-05-27 2014-11-27 United Microelectronics Corp. Manufacturing method for forming a semiconductor structure
US20140349452A1 (en) * 2013-05-22 2014-11-27 United Microelectronics Corp. Method for manufacturing semiconductor devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3634320B2 (en) * 2002-03-29 2005-03-30 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
KR100502407B1 (en) * 2002-04-11 2005-07-19 삼성전자주식회사 Gate Structure Having High-k Dielectric And Highly Conductive Electrode And Method Of Forming The Same
US7745270B2 (en) * 2007-12-28 2010-06-29 Intel Corporation Tri-gate patterning using dual layer gate stack
US8436404B2 (en) * 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
KR101777662B1 (en) * 2010-10-06 2017-09-14 삼성전자 주식회사 Method for forming gate of semiconductor device
US8232204B1 (en) * 2011-06-29 2012-07-31 International Business Machines Corporation Method of forming borderless contact for transistor
US9041076B2 (en) 2013-02-03 2015-05-26 International Business Machines Corporation Partial sacrificial dummy gate with CMOS device with high-k metal gate
US8785283B2 (en) 2012-12-05 2014-07-22 United Microelectronics Corp. Method for forming semiconductor structure having metal connection
US9054172B2 (en) 2012-12-05 2015-06-09 United Microelectrnics Corp. Semiconductor structure having contact plug and method of making the same
US8921226B2 (en) 2013-01-14 2014-12-30 United Microelectronics Corp. Method of forming semiconductor structure having contact plug
US9349812B2 (en) * 2013-05-27 2016-05-24 United Microelectronics Corp. Semiconductor device with self-aligned contact and method of manufacturing the same

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020177263A1 (en) * 2001-05-24 2002-11-28 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US20030067017A1 (en) * 2001-10-05 2003-04-10 Meikei Ieong Variable threshold voltage double gated transistors and method of fabrication
US20050020020A1 (en) * 2002-07-16 2005-01-27 Nadine Collaert Integrated semiconductor fin device and a method for manufacturing such device
US20040142524A1 (en) * 2002-08-12 2004-07-22 Grupp Daniel E. Insulated gate field effect transistor having passivated Schottky barriers to the channel
US20110193181A1 (en) * 2003-11-12 2011-08-11 Samsung Electronics Co., Ltd. Semiconductor device having different metal gate structures
US20050148137A1 (en) * 2003-12-30 2005-07-07 Brask Justin K. Nonplanar transistors with metal gate electrodes
US20050153530A1 (en) * 2004-01-09 2005-07-14 International Business Machines Corporation Fet gate structure with metal gate electrode and silicide contact
US20070262389A1 (en) * 2004-01-16 2007-11-15 Robert Chau Tri-gate transistors and methods to fabricate same
US20090042405A1 (en) * 2004-09-08 2009-02-12 Doczy Mark L Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US20060071285A1 (en) * 2004-09-29 2006-04-06 Suman Datta Inducing strain in the channels of metal gate transistors
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20070111419A1 (en) * 2005-09-28 2007-05-17 Doyle Brian S CMOS Devices with a single work function gate electrode and method of fabrication
US20110062526A1 (en) * 2009-09-14 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
US20110215409A1 (en) * 2010-03-04 2011-09-08 International Business Machines Corporation Structure and method to make replacement metal gate and contact metal
US20120248509A1 (en) * 2011-03-30 2012-10-04 International Business Machines Corporation Structure and process for metal fill in replacement metal gate integration
US20120313178A1 (en) * 2011-06-13 2012-12-13 Po-Jui Liao Semiconductor device having metal gate and manufacturing method thereof
US20130026578A1 (en) * 2011-07-28 2013-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US20130280900A1 (en) * 2012-04-24 2013-10-24 United Microelectronics Corp. Manufacturing method for semiconductor device having metal gate
US20130295758A1 (en) * 2012-05-02 2013-11-07 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
US20130299914A1 (en) * 2012-05-14 2013-11-14 Ju-youn Kim Semiconductor device and method for manufacturing the device
US20140084383A1 (en) * 2012-09-27 2014-03-27 Globalfoundries Inc. Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
US20140256094A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and Methods for Forming the Same
US20140312423A1 (en) * 2013-04-18 2014-10-23 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted soi mosfets
US20140349452A1 (en) * 2013-05-22 2014-11-27 United Microelectronics Corp. Method for manufacturing semiconductor devices
US20140349476A1 (en) * 2013-05-27 2014-11-27 United Microelectronics Corp. Manufacturing method for forming a semiconductor structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496361B1 (en) 2015-08-27 2016-11-15 United Microelectronics Corp. Selectively deposited metal gates and method of manufacturing thereof
US10177042B2 (en) 2015-10-21 2019-01-08 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9960284B2 (en) * 2015-10-30 2018-05-01 Globalfoundries Inc. Semiconductor structure including a varactor
US10886419B2 (en) 2015-10-30 2021-01-05 Globalfoundries Inc. Semiconductor structure including a varactor and method for the formation thereof
US10032890B2 (en) 2015-12-08 2018-07-24 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor devices
US10367078B2 (en) * 2017-11-09 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and FinFET devices having shielding layers
US10636890B2 (en) 2018-05-08 2020-04-28 Globalfoundries Inc. Chamfered replacement gate structures

Also Published As

Publication number Publication date
US20150108577A1 (en) 2015-04-23
US9018711B1 (en) 2015-04-28

Similar Documents

Publication Publication Date Title
US9018711B1 (en) Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
US10553493B2 (en) Fabrication of a vertical transistor with self-aligned bottom source/drain
US10236355B2 (en) Fabrication of a vertical fin field effect transistor with a reduced contact resistance
KR101799636B1 (en) Structure and method for finfet device
US8008145B2 (en) High-K metal gate structure fabrication method including hard mask
US20200075737A1 (en) Wrap-around-contact structure for top source/drain in vertical fets
US10497796B1 (en) Vertical transistor with reduced gate length variation
US11088139B2 (en) Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy
DE112018005623T5 (en) PRODUCTION OF LOGIC UNITS AND POWER UNITS ON THE SAME SUBSTRATE
US9679817B2 (en) Semiconductor structures and methods of forming the same
CN108122742A (en) The manufacturing method of semiconductor device structure
US11810948B2 (en) Semiconductor device and method
US11855141B2 (en) Local epitaxy nanofilms for nanowire stack GAA device
US10134633B1 (en) Self-aligned contact with CMP stop layer
US10886395B2 (en) Method for fabricating tunneling field effect transistor having interfacial layer containing nitrogen
US11315835B2 (en) Methods of forming an IC product comprising transistor devices with different threshold voltage levels
US20230238240A1 (en) Semiconductor device and method for fabricating the same
US11670697B2 (en) Semiconductor device and manufacturing method thereof
US11824100B2 (en) Gate structure of semiconductor device and method of forming same
US11264481B2 (en) Self-aligned source and drain contacts
CN106158749B (en) Selective growth of work function metal in replacement metal gate of semiconductor device
TWI575581B (en) Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
US12107006B2 (en) Method for manufacturing semiconductor structure with dielectric feature
US12087838B2 (en) Self-aligned contact hard mask structure of semiconductor device and method of forming same
US20230147329A1 (en) Single Process Double Gate and Variable Threshold Voltage MOSFET

Legal Events

Date Code Title Description
AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CAI, XIUYU;KIM, HOON;ZHANG, XUNYUAN;SIGNING DATES FROM 20131015 TO 20131016;REEL/FRAME:035030/0049

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001

Effective date: 20201117