US20150155301A1 - SEMICONDUCTOR SUBSTRATE WITH MULTIPLE SiGe REGIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS BY A SINGLE EPITAXY PROCESS - Google Patents
SEMICONDUCTOR SUBSTRATE WITH MULTIPLE SiGe REGIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS BY A SINGLE EPITAXY PROCESS Download PDFInfo
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- US20150155301A1 US20150155301A1 US14/595,311 US201514595311A US2015155301A1 US 20150155301 A1 US20150155301 A1 US 20150155301A1 US 201514595311 A US201514595311 A US 201514595311A US 2015155301 A1 US2015155301 A1 US 2015155301A1
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 114
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 title claims abstract description 61
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title abstract description 32
- 239000004065 semiconductor Substances 0.000 title description 83
- 238000000407 epitaxy Methods 0.000 title description 2
- 239000012212 insulator Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 description 63
- 229910052710 silicon Inorganic materials 0.000 description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- 238000002955 isolation Methods 0.000 description 16
- 238000000151 deposition Methods 0.000 description 14
- 230000008021 deposition Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 238000002156 mixing Methods 0.000 description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- -1 nFETs and pFETS) Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
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- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- OXTURSYJKMYFLT-UHFFFAOYSA-N dichlorogermane Chemical compound Cl[GeH2]Cl OXTURSYJKMYFLT-UHFFFAOYSA-N 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- VXGHASBVNMHGDI-UHFFFAOYSA-N digermane Chemical compound [Ge][Ge] VXGHASBVNMHGDI-UHFFFAOYSA-N 0.000 description 1
- UCMVNBCLTOOHMN-UHFFFAOYSA-N dimethyl(silyl)silane Chemical compound C[SiH](C)[SiH3] UCMVNBCLTOOHMN-UHFFFAOYSA-N 0.000 description 1
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- KCWYOFZQRFCIIE-UHFFFAOYSA-N ethylsilane Chemical compound CC[SiH3] KCWYOFZQRFCIIE-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- NEXSMEBSBIABKL-UHFFFAOYSA-N hexamethyldisilane Chemical compound C[Si](C)(C)[Si](C)(C)C NEXSMEBSBIABKL-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- IQCYANORSDPPDT-UHFFFAOYSA-N methyl(silyl)silane Chemical compound C[SiH2][SiH3] IQCYANORSDPPDT-UHFFFAOYSA-N 0.000 description 1
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- IEXRMSFAVATTJX-UHFFFAOYSA-N tetrachlorogermane Chemical compound Cl[Ge](Cl)(Cl)Cl IEXRMSFAVATTJX-UHFFFAOYSA-N 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- MUDDKLJPADVVKF-UHFFFAOYSA-N trichlorogermane Chemical compound Cl[GeH](Cl)Cl MUDDKLJPADVVKF-UHFFFAOYSA-N 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Definitions
- the present invention relates to semiconductor structure and semiconductor devices containing germanium, and more particularly, to semiconductor structures and semiconductor devices containing silicon germanium layers.
- MOSFETs metal oxide semiconductor field effect transistors
- CMOS complementary metal oxide semiconductor
- One aspect of the Invention is directed to improve device performance and to have different threshold voltages. For example, it may be desirable to use different SiGe channel materials for the different pFETs in a circuit (or nFETs and other devices); and while it may be desirable to fabricate pFETs with a SiGe channel having, for example, 25% Germanium, it may be desirable to fabricate another set of pFETs with a SiGe channel having, for example, 40% Germanium. Further, different sets of pFETs are often fabricated on the same substrate. Therefore, it may be desirable to form regions of two different pFET, (or another kind of device, i.e. nFET, and/or different sets of devices on the same substrate, i.e. nFETs and pFETS), semiconductor materials on the same substrate.
- One aspect of the invention includes an ETSGOI substrate with at least two active regions, where each of the at least two active regions has a SiGe layer with uniform Germanium concentration, and the Germanium concentration of the SiGe layer of one of the at least two active regions is different than the Germanium concentration of the SiGe layer of the other of at least two active regions.
- FIG. 1 illustrates a semiconductor structure that can be employed in at least one embodiment of the present application.
- FIG. 2 illustrates the semiconductor structure after it has undergone a shallow trench isolation process, and as a result, contains shallow-trench regions therein, and can also be employed in at least one embodiment of the present application.
- FIG. 3 illustrates the semiconductor structure having a silicon layer in-between a first SiGe layer and a second SiGe layer in a first active region and a second active region, in accordance with an embodiment of the present invention.
- FIG. 4 illustrates a mask covering the first active region of the semiconductor structure in accordance with an embodiment of the present invention.
- FIG. 5 illustrates the removal of the second SiGe layer from the second active region of the semiconductor structure in accordance with an embodiment of the present invention.
- FIG. 6 illustrates the removal of the mask from the first active region of the semiconductor structure in accordance with an embodiment of the present invention.
- FIG. 7 illustrates thermal mixing of the first SiGe layer and the silicon layer in the first active region and the thermal mixing of the second SiGe layer, the silicon layer, and the first SiGe layer in the first active region of the semiconductor structure in accordance with an embodiment of the present invention.
- FIG. 8 illustrates the formation of a device in the first active region and a device in the second active region of the semiconductor structure in accordance with an embodiment of the present invention.
- FIG. 1 there is illustrated a first exemplary semiconductor structure including, from bottom to top, a handle substrate 40 , a insulator layer 30 and an semiconductor material layer 20 that can be employed in accordance with an embodiment of the present application.
- the handle substrate 40 , the insulator layer 30 and the semiconductor material layer 20 may be referred to as an extremely-thin-semiconductor-on-insulator (ETSOI) substrate 10 .
- the semiconductor material layer 20 may be referred to as the ETSOI portion of the ETSOI substrate 10 .
- ETSOI substrate 10 Although the present application is described and illustrated utilizing an ETSOI substrate 10 , other semiconductor substrates can also be used including, for example, a semiconductor substrate in which handle substrate 40 is omitted.
- the semiconductor material layer 20 is present on an uppermost surface of the insulator layer 30 .
- the insulator layer 30 is present on an uppermost surface of the handle substrate 40 .
- the handle substrate 40 provides mechanical support to the insulator layer 30 and the semiconductor material layer 20 .
- the handle substrate 40 and the semiconductor material layer 20 of the ETSOI substrate 10 may comprise a same semiconductor material. In other embodiments of the present application, the handle substrate 40 and the semiconductor material layer 20 of the ETSOI substrate 10 may comprise a different semiconductor material.
- the term “semiconductor” as used herein in connection with the semiconductor material of the handle substrate 40 and the semiconductor material layer 20 denotes any semiconducting material including, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other like III/V compound semiconductors. Multilayers of these semiconductor materials can also be used as the semiconductor material of the handle substrate 40 and the semiconductor material layer 20 .
- the handle substrate 40 and the semiconductor material layer 20 are both comprised of silicon.
- the handle substrate 40 is a non-semiconductor material including, for example, a dielectric material and/or a conductive material.
- the handle substrate 40 and the semiconductor material layer 20 may have the same or different crystal orientation.
- the crystal orientation of the handle substrate 40 and/or the semiconductor material layer 20 may be ⁇ 100 ⁇ , ⁇ 110 ⁇ , or ⁇ 111 ⁇ . Other crystallographic orientations besides those specifically mentioned can also be used in the present application.
- the handle substrate 40 and/or the semiconductor material layer 20 of the ETSOI substrate 10 may be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material.
- at least the semiconductor material layer 20 is a single crystalline semiconductor material.
- the semiconductor material layer 20 that is located atop the insulator layer 30 can be processed to include semiconductor regions having different crystal orientations.
- the insulator layer 30 of the ETSOI substrate 10 may be a crystalline or non-crystalline oxide or nitride.
- the insulator layer 30 is an oxide such as, for example, silicon dioxide.
- the insulator layer 30 may be continuous or it may be discontinuous. When a discontinuous insulator region is present, the insulator region exists as an isolated island that is surrounded by semiconductor material.
- the thickness of semiconductor material layer 20 of the ETSOI substrate 10 is typically from 1 nm to 10 nm, with a thickness from 3 nm to 8 nm being more typical. If the thickness of the semiconductor material layer 20 is not within one of the above mentioned ranges, a thinning step such as, for example, planarization, etching, such as for example, thermal dry or wet oxidation, such as, for example, dry etch or oxidation followed by oxide etch, or any combination thereof, can be used to reduce the thickness of semiconductor material layer 20 to a value within one of the ranges mentioned above.
- a thinning step such as, for example, planarization, etching, such as for example, thermal dry or wet oxidation, such as, for example, dry etch or oxidation followed by oxide etch, or any combination thereof, can be used to reduce the thickness of semiconductor material layer 20 to a value within one of the ranges mentioned above.
- the semiconductor material layer 20 should be thin, i.e. less than 8 nm, and even more preferably between 4 nm and 6 nm (or thinned out as required using the processes described above—) and made of pure Silicon or a material comprising primarily Silicon, although it should be reiterated that other variations are possible, including greater dimensions and different material compositions (as may have been mentioned above).
- the insulator layer 30 of the ETSOI substrate 10 typically has a thickness from 1 nm to 200 nm, with a thickness from 100 nm to 150 nm being more typical.
- the thickness of the handle substrate 40 of the SOI substrate can vary greatly and remain in accordance with the teaching of the present application.
- the insulator layer 30 can be a buried dielectric layer 30 and may be composed of any dielectric material.
- the buried dielectric layer 30 may be composed of an oxide, e.g., silicon oxide, a nitride, e.g., silicon nitride, oxynitrides of silicon, e.g. silicon oxynitride, or a combination thereof.
- the buried dielectric layer 30 may include crystalline or non-crystalline insulator material.
- the buried dielectric layer 30 may be formed using any of several known methods. Non-limiting examples include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods.
- the buried dielectric layer 30 may have a thickness of 300 nm or less. In another embodiment, the buried dielectric layer 30 may have a thickness ranging from 2 nm to 150 nm. In yet another embodiment, the buried dielectric layer 30 may have a thickness ranging from 5 nm to 30 nm. Preferably, the buried dielectric layer 30 is a buried oxide layer (“BOX”).
- BOX buried oxide layer
- the semiconductor material layer 20 may be doped, undoped or contain doped and undoped regions therein. For clarity, the doped regions are not specifically shown in the drawings of the present application. Each doped region within the semiconductor material layer 20 may have the same, or they may have different conductivities and/or doping concentrations.
- the doped regions that are present in the semiconductor material layer 20 can be formed by ion implantation process or gas phase doping.
- the semiconductor device of FIG. 1 can be processed to include at least one isolation region therein.
- isolation regions 50 may be formed in the ETSOI substrate 10 to isolate structures formed on the ETSOI substrate 10 from adjacent structures.
- the ETSOI substrate 10 can further include a buried insulator layer 30 , which as stated, can be made of, for example, oxides, nitrides, oxynitrides of silicon, and combinations thereof, and is preferably a buried dielectric layer such as a buried oxide layer (BOX) layer.
- the buried dielectric layer 30 may improve device isolation and prevent dopant diffusion.
- Isolation regions 50 may be formed by any known method in the art, including, for example, lithography or etching into the ETSOI substrate 10 to form trenches, and then filling the trenches with an insulating material, such as silicon dioxide. After forming isolation regions 50 , an active region 60 in the ETSOI substrate 10 is defined as the region between a pair of isolation regions 50 . Active region 60 may include doped and undoped regions that have been omitted from FIG. 2 for illustrative clarity.
- Other embodiments may include other means of isolating structures formed on the ETSOI substrate 10 , or may have isolation around none or only some structures.
- the at least one isolation region is a shallow trench isolation region (“STI”), but it can be a trench isolation region, a field oxide isolation region (not shown), or any other equivalent known in the art.
- a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well.
- the field oxide isolation region may be formed utilizing a so-called local oxidation of silicon process.
- the at least one isolation region provides isolation between neighboring gate structure regions, typically required when the neighboring gates have opposite conductivities, i.e., nFETs and pFETs. As such, the at least one isolation region can separate an nFET device region from a pFET device region.
- a first germanium containing silicon layer (‘a first SiGe layer”) 70 is epitaxially grown on each of the active regions 60 .
- the active regions will not be explicitly identified numerically, and are to be understood as the region between the STI layers, as mentioned above).
- a layer of epitaxial silicon (“Si layer”) 80 is deposited over each of the first SiGe layers 70 of the semiconductor substrate.
- the thin Si layer 80 can operate as an etch stop layer.
- epitaxial growth and/or deposition and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface.
- the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed.
- an epitaxial semiconductor material deposited on a ⁇ 100 ⁇ crystal surface will take on a ⁇ 100 ⁇ orientation.
- epitaxial growth and/or deposition processes are selective to forming on semiconductor surface, and do not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.
- Examples of various epitaxial growth process apparatuses that are suitable for use in forming the first germanium containing silicon layer 70 and the second silicon germanium containing silicon layer 80 include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE).
- RTCVD rapid thermal chemical vapor deposition
- LEPD low-energy plasma deposition
- UHVCVD ultra-high vacuum chemical vapor deposition
- APCVD atmospheric pressure chemical vapor deposition
- MBE molecular beam epitaxy
- the temperature for epitaxial deposition process for forming germanium containing silicon layer 70 and the second silicon germanium containing silicon layer 80 typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.
- the gas source for the deposition of epitaxial semiconductor material include a silicon containing gas source, a germanium containing gas source, or a combination thereof.
- an epitaxial Si layer may be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof.
- a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof.
- An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used.
- a second germanium containing silicon layer 90 (“a second SiGe layer”) is epitaxially deposited over each of the Si layers 80 that are over the first SiGe layers 70 .
- the thickness of each of the first SiGe layers 70 , the Si layer 80 , and the second SiGe layers 90 and the concentration of Germanium in both the first SiGe layers 70 and the second SiGe layers 90 are chosen with a final product in mind, where higher germanium concentration leads to increased electron mobility, and as a general matter, different germanium concentrations allow one to tune the threshold voltage of a given device. As such, and as may be mentioned elsewhere below, the parameters mentioned in the preceding sentence are determined based on the physical properties desired in a final product.
- the first SiGe layer 70 will have a different thickness and/or concentration of Germanium than the second SiGe layer 90 , and in other embodiments, the first SiGe layer 70 will have the same concentration of Germanium and/or the same thickness. This will be discussed in greater detail below.
- Epitaxial growth of the first SiGe layer 70 and the second SiGe layer 90 is preferably uniform.
- the above process steps can all be performed in the same epitaxial reactor, in the same recipe during the same process run by starting with growth of the first SiGe layer 70 , followed by growing the thin Si layer 80 and then continuing with the growth of the second SiGe layer 90 .
- This feature increases efficiency and promotes economic advantage, i.e. cost reduction, by eliminating the need for an additional process run.
- the presence of the Si layer 80 operates as an etch stop layer as will later be shown, and obviates masking of one of the active regions while epitaxially growing the second SiGe layer 90 , i.e. the second epitaxial layer, on the other active region.
- Processing all process steps in one process run eliminates a second independent epitaxy process run, including an epitaxial prebake to preclean the semiconductor surfaces for epitaxial processing.
- the prebake and preclean process are more challenging for SiGe than for Silicon due to the strain in the SiGe layers on Silicon and the tendency of strained SiGe to relax and to form defects during high temperature processing.
- the presence of the Si layer 80 enables the ability to form the first SiGe layer 70 , the Si layer 80 , and the second SiGe layer 90 in a single process run; where epitaxial single process run means a continuous epitaxial growth process in a single epitaxial reactor, without requiring removing the ETSOI substrate 10 and reinstalling it in the same or another epitaxial reactor for further epitaxial processing.
- FIG. 4 another aspect of and embodiment of the invention is shown.
- a hard mask 100 is deposited over one of the active regions.
- FIGS. 3-7 show some lateral overgrowth with respect to the active region 30 from one or both of the SiGe layers; however, in application, the overgrowth can be negligible or non-existent.
- the hard mask material can be, for example, silicon nitride and/or silicon dioxide.
- the second SiGe layer 90 of one of the unmasked active regions is removed.
- the removal of the SiGe layer can be by gaseous HCl etch or by wet etch processing, i.e. with TMAH. Gaseous HCl etch removal is the preferred method.
- the SiGe layers of the other active region are protected by the hardmask 100 .
- the hardmask 100 covering one of the active regions is removed.
- FIG. 7 another aspect of an embodiment of the invention is shown. Specifically, after the hardmask 100 is removed, the Si layer 80 and the first SiGe layer 70 remain for one of the active regions, the second SiGe layer 90 having been removed, and the Si layer 80 and both the first SiGe layer 70 and the second SiGe layer 90 of the other one of the active regions remains in place.
- the remaining layers on each active region can be thermally mixed by thermally annealing them. Specifically, in the active region that has the second SiGe layer 90 removed, the semiconductor material layer 20 of the ETSOI substrate 10 in that region, the first SiGe layer 70 , and the Si layer 80 will thermally mix to form one final, merged, SiGe layer 110 .
- the anneal process can be furnace anneal, rapid thermal anneal, flash anneal, or any suitable combination of those processes.
- the anneal temperature ranges from 600 degrees to 1300 degrees Centigrade.
- the anneal time ranges from 1 millisecond to 2 hours, depending on the anneal temperature. Higher anneal temperatures require shorter anneal times.
- a typical anneal condition is about 30 minutes at 1000° C.
- such annealing causes the mixing of the first SiGe layer 70 and the Si 80 layer of one active region and the semiconductor material layer 20 of the ETSOI substrate 10 in that region, forming one merged SiGe layer 110 on one of the active regions. Furthermore, such annealing causes the mixing of the first SiGe layer 70 , the Si 80 layer, the semiconductor material layer 20 of the ETSOI substrate 10 in that region and the second SiGe layer 90 of the other active region and the semiconductor material layer 20 of the ETSOI substrate 10 in that region, forming another merged SiGe layer 120 on one of the active regions.
- two active regions with extremely-thin-silicon-germanium-on-insulator (ETSGOI) layers 110 and 120 with different Germanium concentrations are formed. Accordingly, one aspect of an embodiment of the present invention produces a substrate that has active regions with two distinct SiGe layers with different Germanium concentrations.
- the resulting merged SiGe layer 110 which had its second SiGe layer removed, will usually have a lower Germanium content than the first SiGe layer 70 before the mixing.
- the reason for this is that the thin Si layer 80 and the semiconductor material layer 20 of the ETSOI substrate 10 reduce the overall Germanium content when mixed with the first SiGe layer 70 . (This is the case when the semiconductor material layer 20 is pure silicon or primarily silicon).
- the thermal annealing of the layers of the other active region since the first SiGe layer 70 , the Si layer 80 , the second SiGe layer 90 and the ETSOI 20 will be thermally mixed, it is possible, depending on the selection of the thickness of each of the layers and the concentration of Germanium in each of the SiGe layers, for the second merged SiGe layer 120 to have a higher or lower concentration of Germanium than each of the first SiGe layer 70 and the second SiGe layer 90 , which were originally present in the active regions.
- the final Germanium content of the final merged layers 110 and 120 by selecting the thickness of the ETSOI layer 20 and the thin Si layer 80 , and by selecting the thickness and/or the Germanium concentration of the First SiGe layer 70 and the second SiGe layer 80 ; however, the final two thermally mixed SiGe layers, SiGe layer 110 and SiGe layer 120 , will usually have different Germanium contents because one of the active regions at the thermal mixing stage has the extra SiGe layer 90 .
- Germanium content of the final thermally mixed silicon germanium layers can be engineered as desired for particular applications by ensuring that the initial deposited germanium containing layers have an appropriate germanium content and/or thickness for the particular application desired.
- the thin Si layer 80 will be very thin, ranging from 1-2 nm.
- the thin Si layer 80 is between 1-2 nm, substantial benefit is obtained in that it reduces the dilution effect on the overall SiGe concentration while still affording some of the benefits of the described herein, including the reduced process steps, which is possible at least due to the thin Si layer's 80 function as an etch stop layer.
- the thickness of the semiconductor material layer 20 of the ETSOI substrate 10 is 6 nm
- the thickness of the first SiGe layer 70 of both active regions is 4 nm, with a Germanium concentration of 35%
- the thickness of the thin Si layer 80 is 2 nm
- the thickness of the second SiGe layer 90 is 5 nm, with a Germanium concentration of 60%.
- one active region After undergoing the process steps described above, including the removal of the second SiGe layer 90 for one of the active regions and the thermal mixing of the various layers as described above, one active region will have a final merged SiGe layer 110 with a thickness of 12 nm and a Germanium concentration of about 12%, and the other active region will have a final merged SiGe layer 120 with a thickness of 17 nm and a Germanium concentration of about 25%.
- the thickness of the semiconductor material layer 20 of the ETSOI substrate 10 is 4 nm
- the thickness of the first SiGe layer 70 of both active regions is 6 nm, with a Germanium concentration of 40%
- the thickness of the thin Si layer 80 is 2 nm
- the thickness of the second SiGe layer 90 is 6 nm, with a Germanium concentration of 40%.
- one active region After undergoing the process steps described above, including the removal of the second SiGe layer 90 for one of the active regions and the thermal mixing of the various layers as described above, one active region will have a final merged SiGe layer 110 with a thickness of 12 nm and a Germanium concentration of about 20%, and the other active region will have a final merged SiGe layer 120 with a thickness of 18 nm and a Germanium concentration of about 33%.
- the particular embodiments have both the first SiGe layer 70 and the second SiGe layer 90 as being of the same thickness, it is possible to arrive at configurations where the thicknesses differ from one another. It is also possible to vary the thickness of the thin Si layer 80 and the semiconductor material layer 20 of the ETSOI substrate 10 in relation to one another and in relation to the SiGe layers. The same applies with respect with the initial concentration of the germanium content of the first SiGe layer 70 and the second SiGe layer 90 , i.e. they do not have to be the same.
- one of the SiGe layers has the same thickness as the semiconductor material layer 20 of the ETSOI substrate 10 . In one embodiment, one of the SiGe layers has a thickness that is less than the semiconductor material layer 20 of the ETSOI substrate 10 . In yet another embodiment, one of the SiGe layers has a thickness that is greater than the semiconductor material layer 20 of the ETSOI substrate 10 .
- the semiconductor material layer 20 of the ETSOI substrate 10 which as stated is preferably made of pure silicon or a material primarily made of silicon, and whether it is of the same as one of the SiGe layers or otherwise, is made as thin as possible, i.e. 3-4 nm, to reduce the amount of dilution from the pure silicon in forming higher percentage SiGe layers.
- FIG. 8 another aspect of the invention is shown.
- devices may be placed over layer 110 and 120 .
- two pFET devices are shown 130 and 140 devices are provided as the examples in FIG. 8 .
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Abstract
Description
- The present application is a divisional of, and claims priority under 35 U.S.C. §120, U.S. patent application Ser. No. 14/096,120, filed on Dec. 4, 2013, which is incorporated by reference in its entirety.
- The present invention relates to semiconductor structure and semiconductor devices containing germanium, and more particularly, to semiconductor structures and semiconductor devices containing silicon germanium layers.
- For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicted for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
- One aspect of the Invention is directed to improve device performance and to have different threshold voltages. For example, it may be desirable to use different SiGe channel materials for the different pFETs in a circuit (or nFETs and other devices); and while it may be desirable to fabricate pFETs with a SiGe channel having, for example, 25% Germanium, it may be desirable to fabricate another set of pFETs with a SiGe channel having, for example, 40% Germanium. Further, different sets of pFETs are often fabricated on the same substrate. Therefore, it may be desirable to form regions of two different pFET, (or another kind of device, i.e. nFET, and/or different sets of devices on the same substrate, i.e. nFETs and pFETS), semiconductor materials on the same substrate.
- One aspect of the invention includes an ETSGOI substrate with at least two active regions, where each of the at least two active regions has a SiGe layer with uniform Germanium concentration, and the Germanium concentration of the SiGe layer of one of the at least two active regions is different than the Germanium concentration of the SiGe layer of the other of at least two active regions.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 illustrates a semiconductor structure that can be employed in at least one embodiment of the present application. -
FIG. 2 illustrates the semiconductor structure after it has undergone a shallow trench isolation process, and as a result, contains shallow-trench regions therein, and can also be employed in at least one embodiment of the present application. -
FIG. 3 illustrates the semiconductor structure having a silicon layer in-between a first SiGe layer and a second SiGe layer in a first active region and a second active region, in accordance with an embodiment of the present invention. -
FIG. 4 illustrates a mask covering the first active region of the semiconductor structure in accordance with an embodiment of the present invention. -
FIG. 5 illustrates the removal of the second SiGe layer from the second active region of the semiconductor structure in accordance with an embodiment of the present invention. -
FIG. 6 illustrates the removal of the mask from the first active region of the semiconductor structure in accordance with an embodiment of the present invention. -
FIG. 7 illustrates thermal mixing of the first SiGe layer and the silicon layer in the first active region and the thermal mixing of the second SiGe layer, the silicon layer, and the first SiGe layer in the first active region of the semiconductor structure in accordance with an embodiment of the present invention. -
FIG. 8 illustrates the formation of a device in the first active region and a device in the second active region of the semiconductor structure in accordance with an embodiment of the present invention. - It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for purpose of clarity.
- Referring first
FIG. 1 , there is illustrated a first exemplary semiconductor structure including, from bottom to top, ahandle substrate 40, ainsulator layer 30 and ansemiconductor material layer 20 that can be employed in accordance with an embodiment of the present application. Collectively, thehandle substrate 40, theinsulator layer 30 and thesemiconductor material layer 20 may be referred to as an extremely-thin-semiconductor-on-insulator (ETSOI)substrate 10. Thesemiconductor material layer 20 may be referred to as the ETSOI portion of theETSOI substrate 10. Although the present application is described and illustrated utilizing anETSOI substrate 10, other semiconductor substrates can also be used including, for example, a semiconductor substrate in which handlesubstrate 40 is omitted. - In the embodiment illustrated in
FIG. 1 , thesemiconductor material layer 20 is present on an uppermost surface of theinsulator layer 30. Theinsulator layer 30 is present on an uppermost surface of thehandle substrate 40. Thehandle substrate 40 provides mechanical support to theinsulator layer 30 and thesemiconductor material layer 20. - In some embodiments of the present application, the
handle substrate 40 and thesemiconductor material layer 20 of theETSOI substrate 10 may comprise a same semiconductor material. In other embodiments of the present application, thehandle substrate 40 and thesemiconductor material layer 20 of theETSOI substrate 10 may comprise a different semiconductor material. The term “semiconductor” as used herein in connection with the semiconductor material of thehandle substrate 40 and thesemiconductor material layer 20 denotes any semiconducting material including, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other like III/V compound semiconductors. Multilayers of these semiconductor materials can also be used as the semiconductor material of thehandle substrate 40 and thesemiconductor material layer 20. In one embodiment, thehandle substrate 40 and thesemiconductor material layer 20 are both comprised of silicon. In some embodiments, thehandle substrate 40 is a non-semiconductor material including, for example, a dielectric material and/or a conductive material. - The
handle substrate 40 and thesemiconductor material layer 20 may have the same or different crystal orientation. For example, the crystal orientation of thehandle substrate 40 and/or thesemiconductor material layer 20 may be {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used in the present application. Thehandle substrate 40 and/or thesemiconductor material layer 20 of theETSOI substrate 10 may be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. Typically, at least thesemiconductor material layer 20 is a single crystalline semiconductor material. In some embodiments, thesemiconductor material layer 20 that is located atop theinsulator layer 30 can be processed to include semiconductor regions having different crystal orientations. - The
insulator layer 30 of theETSOI substrate 10 may be a crystalline or non-crystalline oxide or nitride. In one embodiment, theinsulator layer 30 is an oxide such as, for example, silicon dioxide. Theinsulator layer 30 may be continuous or it may be discontinuous. When a discontinuous insulator region is present, the insulator region exists as an isolated island that is surrounded by semiconductor material. - The thickness of
semiconductor material layer 20 of theETSOI substrate 10 is typically from 1 nm to 10 nm, with a thickness from 3 nm to 8 nm being more typical. If the thickness of thesemiconductor material layer 20 is not within one of the above mentioned ranges, a thinning step such as, for example, planarization, etching, such as for example, thermal dry or wet oxidation, such as, for example, dry etch or oxidation followed by oxide etch, or any combination thereof, can be used to reduce the thickness ofsemiconductor material layer 20 to a value within one of the ranges mentioned above. - Preferably, the
semiconductor material layer 20 should be thin, i.e. less than 8 nm, and even more preferably between 4 nm and 6 nm (or thinned out as required using the processes described above—) and made of pure Silicon or a material comprising primarily Silicon, although it should be reiterated that other variations are possible, including greater dimensions and different material compositions (as may have been mentioned above). - The
insulator layer 30 of theETSOI substrate 10 typically has a thickness from 1 nm to 200 nm, with a thickness from 100 nm to 150 nm being more typical. The thickness of thehandle substrate 40 of the SOI substrate can vary greatly and remain in accordance with the teaching of the present application. - The
insulator layer 30 can be a burieddielectric layer 30 and may be composed of any dielectric material. For example, the burieddielectric layer 30 may be composed of an oxide, e.g., silicon oxide, a nitride, e.g., silicon nitride, oxynitrides of silicon, e.g. silicon oxynitride, or a combination thereof. In addition, as already stated, the burieddielectric layer 30 may include crystalline or non-crystalline insulator material. Moreover, the burieddielectric layer 30 may be formed using any of several known methods. Non-limiting examples include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. - The buried
dielectric layer 30 may have a thickness of 300 nm or less. In another embodiment, the burieddielectric layer 30 may have a thickness ranging from 2 nm to 150 nm. In yet another embodiment, the burieddielectric layer 30 may have a thickness ranging from 5 nm to 30 nm. Preferably, the burieddielectric layer 30 is a buried oxide layer (“BOX”). - The
semiconductor material layer 20 may be doped, undoped or contain doped and undoped regions therein. For clarity, the doped regions are not specifically shown in the drawings of the present application. Each doped region within thesemiconductor material layer 20 may have the same, or they may have different conductivities and/or doping concentrations. The doped regions that are present in thesemiconductor material layer 20 can be formed by ion implantation process or gas phase doping. - The semiconductor device of
FIG. 1 can be processed to include at least one isolation region therein. Referring toFIG. 2 ,isolation regions 50 may be formed in theETSOI substrate 10 to isolate structures formed on theETSOI substrate 10 from adjacent structures. As stated shown inFIG. 1 andFIG. 2 , in some embodiments, theETSOI substrate 10 can further include a buriedinsulator layer 30, which as stated, can be made of, for example, oxides, nitrides, oxynitrides of silicon, and combinations thereof, and is preferably a buried dielectric layer such as a buried oxide layer (BOX) layer. The burieddielectric layer 30 may improve device isolation and prevent dopant diffusion.Isolation regions 50 may be formed by any known method in the art, including, for example, lithography or etching into theETSOI substrate 10 to form trenches, and then filling the trenches with an insulating material, such as silicon dioxide. After formingisolation regions 50, anactive region 60 in theETSOI substrate 10 is defined as the region between a pair ofisolation regions 50.Active region 60 may include doped and undoped regions that have been omitted fromFIG. 2 for illustrative clarity. - Other embodiments may include other means of isolating structures formed on the
ETSOI substrate 10, or may have isolation around none or only some structures. - The example shown above is where the at least one isolation region is a shallow trench isolation region (“STI”), but it can be a trench isolation region, a field oxide isolation region (not shown), or any other equivalent known in the art. Optionally, a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well. The field oxide isolation region may be formed utilizing a so-called local oxidation of silicon process. Note that the at least one isolation region provides isolation between neighboring gate structure regions, typically required when the neighboring gates have opposite conductivities, i.e., nFETs and pFETs. As such, the at least one isolation region can separate an nFET device region from a pFET device region.
- Referring now to
FIG. 3 , one aspect of an embodiment of the invention is shown. A first germanium containing silicon layer (‘a first SiGe layer”) 70 is epitaxially grown on each of theactive regions 60. (Note that in subsequent Figures, the active regions will not be explicitly identified numerically, and are to be understood as the region between the STI layers, as mentioned above). After epitaxial deposition of thefirst SiGe layer 70, a layer of epitaxial silicon (“Si layer”) 80 is deposited over each of the first SiGe layers 70 of the semiconductor substrate. As will be discussed, thethin Si layer 80 can operate as an etch stop layer. - The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes are selective to forming on semiconductor surface, and do not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.
- Examples of various epitaxial growth process apparatuses that are suitable for use in forming the first germanium containing
silicon layer 70 and the second silicon germanium containing silicon layer 80 (discussed further below include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition process for forming germanium containingsilicon layer 70 and the second silicon germanium containing silicon layer 80 (discussed further below) typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. - A number of different sources may be used for the deposition of the first silicon germanium containing
silicon layer 70 and the second silicon germanium containing silicon layer 80 (discussed further below). In some embodiments, the gas source for the deposition of epitaxial semiconductor material include a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial Si layer may be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used. - After epitaxial deposition of the first SiGe layers 70, a second germanium containing silicon layer 90 (“a second SiGe layer”) is epitaxially deposited over each of the Si layers 80 that are over the first SiGe layers 70. The thickness of each of the first SiGe layers 70, the
Si layer 80, and the second SiGe layers 90 and the concentration of Germanium in both the first SiGe layers 70 and the second SiGe layers 90 are chosen with a final product in mind, where higher germanium concentration leads to increased electron mobility, and as a general matter, different germanium concentrations allow one to tune the threshold voltage of a given device. As such, and as may be mentioned elsewhere below, the parameters mentioned in the preceding sentence are determined based on the physical properties desired in a final product. In some embodiments, thefirst SiGe layer 70 will have a different thickness and/or concentration of Germanium than thesecond SiGe layer 90, and in other embodiments, thefirst SiGe layer 70 will have the same concentration of Germanium and/or the same thickness. This will be discussed in greater detail below. - Epitaxial growth of the
first SiGe layer 70 and thesecond SiGe layer 90 is preferably uniform. - The above process steps can all be performed in the same epitaxial reactor, in the same recipe during the same process run by starting with growth of the
first SiGe layer 70, followed by growing thethin Si layer 80 and then continuing with the growth of thesecond SiGe layer 90. This feature increases efficiency and promotes economic advantage, i.e. cost reduction, by eliminating the need for an additional process run. The presence of theSi layer 80 operates as an etch stop layer as will later be shown, and obviates masking of one of the active regions while epitaxially growing thesecond SiGe layer 90, i.e. the second epitaxial layer, on the other active region. Processing all process steps in one process run eliminates a second independent epitaxy process run, including an epitaxial prebake to preclean the semiconductor surfaces for epitaxial processing. The prebake and preclean process are more challenging for SiGe than for Silicon due to the strain in the SiGe layers on Silicon and the tendency of strained SiGe to relax and to form defects during high temperature processing. - In other words, the presence of the
Si layer 80 enables the ability to form thefirst SiGe layer 70, theSi layer 80, and thesecond SiGe layer 90 in a single process run; where epitaxial single process run means a continuous epitaxial growth process in a single epitaxial reactor, without requiring removing theETSOI substrate 10 and reinstalling it in the same or another epitaxial reactor for further epitaxial processing. - Referring to
FIG. 4 , another aspect of and embodiment of the invention is shown. Ahard mask 100 is deposited over one of the active regions. (Note thatFIGS. 3-7 show some lateral overgrowth with respect to theactive region 30 from one or both of the SiGe layers; however, in application, the overgrowth can be negligible or non-existent.) The hard mask material can be, for example, silicon nitride and/or silicon dioxide. - Referring to
FIG. 5 , another aspect of and embodiment of the invention is shown. Thesecond SiGe layer 90 of one of the unmasked active regions is removed. The removal of the SiGe layer can be by gaseous HCl etch or by wet etch processing, i.e. with TMAH. Gaseous HCl etch removal is the preferred method. Moreover, as the etch process removes thesecond SiGe layer 90 of one of the active regions, the SiGe layers of the other active region are protected by thehardmask 100. - With reference to
FIG. 6 , another aspect of an embodiment of the invention is shown, thehardmask 100 covering one of the active regions is removed. With reference toFIG. 7 , another aspect of an embodiment of the invention is shown. Specifically, after thehardmask 100 is removed, theSi layer 80 and thefirst SiGe layer 70 remain for one of the active regions, thesecond SiGe layer 90 having been removed, and theSi layer 80 and both thefirst SiGe layer 70 and thesecond SiGe layer 90 of the other one of the active regions remains in place. - The remaining layers on each active region can be thermally mixed by thermally annealing them. Specifically, in the active region that has the
second SiGe layer 90 removed, thesemiconductor material layer 20 of theETSOI substrate 10 in that region, thefirst SiGe layer 70, and theSi layer 80 will thermally mix to form one final, merged,SiGe layer 110. The anneal process can be furnace anneal, rapid thermal anneal, flash anneal, or any suitable combination of those processes. The anneal temperature ranges from 600 degrees to 1300 degrees Centigrade. The anneal time ranges from 1 millisecond to 2 hours, depending on the anneal temperature. Higher anneal temperatures require shorter anneal times. A typical anneal condition is about 30 minutes at 1000° C. - As shown in
FIG. 8 , which demonstrates another aspect of an embodiment of the invention, such annealing causes the mixing of thefirst SiGe layer 70 and theSi 80 layer of one active region and thesemiconductor material layer 20 of theETSOI substrate 10 in that region, forming onemerged SiGe layer 110 on one of the active regions. Furthermore, such annealing causes the mixing of thefirst SiGe layer 70, theSi 80 layer, thesemiconductor material layer 20 of theETSOI substrate 10 in that region and thesecond SiGe layer 90 of the other active region and thesemiconductor material layer 20 of theETSOI substrate 10 in that region, forming anothermerged SiGe layer 120 on one of the active regions. - Essentially, two active regions with extremely-thin-silicon-germanium-on-insulator (ETSGOI) layers 110 and 120 with different Germanium concentrations are formed. Accordingly, one aspect of an embodiment of the present invention produces a substrate that has active regions with two distinct SiGe layers with different Germanium concentrations.
- The resulting
merged SiGe layer 110, which had its second SiGe layer removed, will usually have a lower Germanium content than thefirst SiGe layer 70 before the mixing. The reason for this is that thethin Si layer 80 and thesemiconductor material layer 20 of theETSOI substrate 10 reduce the overall Germanium content when mixed with thefirst SiGe layer 70. (This is the case when thesemiconductor material layer 20 is pure silicon or primarily silicon). However, with respect to the thermal annealing of the layers of the other active region, since thefirst SiGe layer 70, theSi layer 80, thesecond SiGe layer 90 and theETSOI 20 will be thermally mixed, it is possible, depending on the selection of the thickness of each of the layers and the concentration of Germanium in each of the SiGe layers, for the secondmerged SiGe layer 120 to have a higher or lower concentration of Germanium than each of thefirst SiGe layer 70 and thesecond SiGe layer 90, which were originally present in the active regions. In other words, it is possible to create any number of variations for the final Germanium content of the finalmerged layers ETSOI layer 20 and thethin Si layer 80, and by selecting the thickness and/or the Germanium concentration of theFirst SiGe layer 70 and thesecond SiGe layer 80; however, the final two thermally mixed SiGe layers,SiGe layer 110 andSiGe layer 120, will usually have different Germanium contents because one of the active regions at the thermal mixing stage has theextra SiGe layer 90. - As stated and implied above during the discussion of
FIG. 4 , the Germanium content of the final thermally mixed silicon germanium layers can be engineered as desired for particular applications by ensuring that the initial deposited germanium containing layers have an appropriate germanium content and/or thickness for the particular application desired. - In an instance where a higher Germanium content is desired, the
thin Si layer 80 will be very thin, ranging from 1-2 nm. For the particular embodiment where thethin Si layer 80 is between 1-2 nm, substantial benefit is obtained in that it reduces the dilution effect on the overall SiGe concentration while still affording some of the benefits of the described herein, including the reduced process steps, which is possible at least due to the thin Si layer's 80 function as an etch stop layer. - In one particular embodiment, the thickness of the
semiconductor material layer 20 of theETSOI substrate 10 is 6 nm, the thickness of thefirst SiGe layer 70 of both active regions is 4 nm, with a Germanium concentration of 35%, the thickness of thethin Si layer 80 is 2 nm, and the thickness of thesecond SiGe layer 90 is 5 nm, with a Germanium concentration of 60%. After undergoing the process steps described above, including the removal of thesecond SiGe layer 90 for one of the active regions and the thermal mixing of the various layers as described above, one active region will have a finalmerged SiGe layer 110 with a thickness of 12 nm and a Germanium concentration of about 12%, and the other active region will have a finalmerged SiGe layer 120 with a thickness of 17 nm and a Germanium concentration of about 25%. - In another particular embodiment, the thickness of the
semiconductor material layer 20 of theETSOI substrate 10 is 4 nm, the thickness of thefirst SiGe layer 70 of both active regions is 6 nm, with a Germanium concentration of 40%, the thickness of thethin Si layer 80 is 2 nm, and the thickness of thesecond SiGe layer 90 is 6 nm, with a Germanium concentration of 40%. After undergoing the process steps described above, including the removal of thesecond SiGe layer 90 for one of the active regions and the thermal mixing of the various layers as described above, one active region will have a finalmerged SiGe layer 110 with a thickness of 12 nm and a Germanium concentration of about 20%, and the other active region will have a finalmerged SiGe layer 120 with a thickness of 18 nm and a Germanium concentration of about 33%. - Although the particular embodiments have both the
first SiGe layer 70 and thesecond SiGe layer 90 as being of the same thickness, it is possible to arrive at configurations where the thicknesses differ from one another. It is also possible to vary the thickness of thethin Si layer 80 and thesemiconductor material layer 20 of theETSOI substrate 10 in relation to one another and in relation to the SiGe layers. The same applies with respect with the initial concentration of the germanium content of thefirst SiGe layer 70 and thesecond SiGe layer 90, i.e. they do not have to be the same. - In one embodiment, one of the SiGe layers has the same thickness as the
semiconductor material layer 20 of theETSOI substrate 10. In one embodiment, one of the SiGe layers has a thickness that is less than thesemiconductor material layer 20 of theETSOI substrate 10. In yet another embodiment, one of the SiGe layers has a thickness that is greater than thesemiconductor material layer 20 of theETSOI substrate 10. - In yet another embodiment, the
semiconductor material layer 20 of theETSOI substrate 10, which as stated is preferably made of pure silicon or a material primarily made of silicon, and whether it is of the same as one of the SiGe layers or otherwise, is made as thin as possible, i.e. 3-4 nm, to reduce the amount of dilution from the pure silicon in forming higher percentage SiGe layers. - With reference to
FIG. 8 , another aspect of the invention is shown. Once the final merged SiGe layers,layer layer FIG. 8 , two pFET devices are shown 130 and 140 devices are provided as the examples inFIG. 8 . - It should be understood that although the particular examples and figures provided above refer to two active regions on a particular substrate, the principles of this invention can be applied to two or more, including some or all, of the active regions of a given substrate. Moreover, the various embodiments referring to dimensional or concentration (such as Germanium concentration) limitations can be combined and are non-limiting, unless their combination is logically/physically impossible or expressly disproved. For instance, a hybrid embodiment with one of the deposited SiGe layers having a thickness less than the
semiconductor material layer 20 of theETSOI substrate 10 and another one of the deposited SiGe layer having a thickness greater than thesemiconductor material layer 20 of theETSOI substrate 10, with Germanium concentrations being the same or different. Again, this is a non-limiting example, and any combination can be formed based on the embodiments described above. - While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (4)
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