US20150140781A1 - Semiconductor isolation structure and method of manufacture - Google Patents
Semiconductor isolation structure and method of manufacture Download PDFInfo
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- US20150140781A1 US20150140781A1 US14/605,100 US201514605100A US2015140781A1 US 20150140781 A1 US20150140781 A1 US 20150140781A1 US 201514605100 A US201514605100 A US 201514605100A US 2015140781 A1 US2015140781 A1 US 2015140781A1
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- 238000002955 isolation Methods 0.000 title claims abstract description 61
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- 239000000377 silicon dioxide Substances 0.000 description 9
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H01L27/10844—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Definitions
- Embodiments of the invention relate to isolation structures for semiconductor devices, and more particularly, to isolation structures for vertically constructed semiconductor devices.
- DRAM dynamic random access memory
- DRAM includes a memory array having a plurality of memory cells that can be arranged in rows and columns. Conductive word lines may be positioned along the rows of the array to couple cells in respective rows, while conductive bit lines may be positioned along columns of the array and coupled to cells in the respective columns.
- the memory cells in the array may include an access device, such as a transistor device, and a storage device, such as a capacitor. The access device and the storage device may be coupled so that information is stored within a memory cell by imposing a predetermined charge state (corresponding to a selected logic level) on the storage device, and retrieved by accessing the charge state through the access device.
- the storage device within each memory cell may be periodically refreshed.
- Current leakage from the cells in the DRAM may occur along several different paths, and if the current leakage is excessive, then the cell refresh interval may be relatively short, which can adversely affect access time for the memory device, and increase the amount of power consumed.
- semiconductor devices such as access devices, that are vertically disposed in a supporting substrate are increasingly favored.
- a vertical semiconductor device has a reduced footprint when compared to a laterally-disposed device, electrical device isolation presents a concern with ever increasing packing densities.
- FIG. 1 is a circuit schematic of a partial memory device and processing system according to a disclosed embodiment.
- FIG. 2 is a top view of a vertical access device according to a disclosed embodiment.
- FIG. 3 is a step in the fabrication of memory elements according to a disclosed embodiment.
- FIG. 4 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 3 .
- FIG. 5 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 4 .
- FIG. 6 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 5 .
- FIG. 7 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 6 .
- FIG. 8 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 4 .
- FIG. 9 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 8 .
- FIG. 10 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 9 .
- FIG. 11 is a close-up partial view of an access device according to a disclosed embodiment.
- FIG. 12 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 7 .
- FIG. 13 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 6 .
- FIG. 14 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 12 .
- FIG. 15 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 12 .
- FIG. 16 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 14 .
- FIG. 17 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 14 .
- FIG. 18 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 12 .
- FIG. 19 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 16 .
- FIG. 20 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 17 .
- FIG. 21 is a step in the fabrication of memory elements according to a disclosed embodiment after FIG. 18 .
- FIG. 22 is a completed vertical access device and associated storage device according to a disclosed embodiment.
- substrate includes silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “substrate” in the following description, previous process steps may have been utilized to form regions, junctions or material layers in or on the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, gallium arsenide, or other known semiconductor materials.
- Embodiments described herein provide an isolation structure suitable for isolating vertical semiconductor devices.
- One example is a vertical access device that may be used in a memory product.
- the described embodiments are not limited to memory products, even though a memory product is described herein a providing a context for the invention.
- FIG. 1 is a partial schematic illustration of a memory device 10 , incorporating an array of memory elements 12 .
- the memory device 10 may be a DRAM device, for example, although the embodiments described herein are not limited to DRAM or even memory devices.
- Memory device 10 includes a number of memory elements 12 arranged in a grid pattern comprising a number of rows and columns. As can be appreciated, the number of memory elements 12 (and corresponding rows and columns) may vary depending on system requirements and fabrication technology.
- Each memory element 12 includes an access device 14 and a storage device 16 .
- the access device 14 comprises a transistor and the storage device 16 comprises a capacitor.
- the access device 14 provides controlled access to the storage device 16 .
- the access device 14 includes a source terminal 18 , a drain terminal 20 , and a gate terminal 22 for controlling conduction between the source and drain terminals 18 , 20 .
- the storage device 16 is coupled between one of the source/drain terminals 18 , 20 and a reference voltage (illustrated as a ground potential).
- an electrical charge is placed on the source 18 of the access device 14 via a corresponding bit line (BL).
- BL bit line
- WL word line
- the bit lines BL are used to read from and write data to the memory elements 12 .
- the word lines WL are used to activate the access device 14 to access a particular row of memory elements 12 .
- the memory device 10 includes an address buffer 24 , a row decoder 26 , and column decoder 28 to control the word lines WL and bit lines BL.
- the address buffer 24 controls the row decoder 26 and the column decoder 28 such that the row decoder 26 and column decoder 28 selectively access memory elements 12 in response to address signals 30 provided during read and write operations.
- the address signals 30 are typically provided by an external controller 35 such as a microprocessor or other memory controller.
- the column decoder 28 may also include sense amplifiers and input/output circuitry to further enable data to be read from and written to the memory elements 12 via the bit lines BL.
- FIG. 2 illustrates the FIG. 1 memory device 10 showing vertical access devices 110 from a top view.
- the memory device 10 may be implemented with an array of vertical access devices 110 that are coupled by access lines, for example word lines (WL), connected to the gates of the access devices 110 , in rows and coupled by data/sense lines, for example bit lines (BL), connected to the source/drain regions, in columns. Between each row and column of access devices 110 , an isolation region 105 is provided to isolate access devices 110 and reduce leakage among the access devices 110 and from the access devices 110 to the substrate.
- the word lines (WL) and bit lines (BL) are provided at different vertical elevations of the access devices 110 .
- Embodiments described herein provide an isolation structure which reduces leakage from vertical access devices to the substrate without affecting leakage from one vertical access device to adjacent vertical access devices. Fabrication of such an isolation structure is now described with reference to FIGS. 3-22 .
- a semiconductor substrate 115 is provided with a P-type doped first semiconductor region 116 , an overlying second semiconductor region 117 doped to an opposite conductivity type, a third semiconductor region 118 doped with a P-type conductivity, and fourth semiconductor region 119 doped with an N-type conductivity.
- the semiconductor region 117 is an N-type doped semiconductor substrate, although, the second semiconductor region 117 may be doped to a higher concentration of dopant (e.g. N+ or N++type).
- semiconductor regions 116 , 117 , 118 , 119 are described as being formed of either N-type or P-type conductivities, in other embodiments the semiconductor regions 116 , 117 , 118 , 119 may be formed of materials of an opposite conductivity type as that described.
- bit lines 132 are provided in the trenches 131 along each side of the access device regions 130 .
- the bit lines 132 may be provided only along one side of the access device regions 130 .
- the bit lines 132 are formed so that the bottoms of the bit lines 132 do not contact the first semiconductor region 116 .
- the bit lines 132 may be formed of any suitable bit line material known in the art including titanium nitride (TiN).
- the first semiconductor region 116 is etched to create trenches 126 between adjacent access device regions 130 and to provide P-type semiconductor isolation regions 125 below the access device regions 130 .
- the trenches 126 are etched to the maximum depth permitted by the aspect ratio of the device.
- the semiconductor isolation regions 125 may be subjected to further P-type implantation to more heavily dope the P-type semiconductor isolation regions 125 .
- the dopant may be implanted through the semiconductor access device regions 130 , 135 , 140 , implanted into the first semiconductor region 116 at the bottom of the trenches 126 from where it diffuses up into the semiconductor isolation regions 125 , or implanted through other techniques known in the art. With the additional doping, the semiconductor isolation regions 125 will become P+ doped regions while the first semiconductor region 116 remains doped P-type.
- a dielectric liner material 127 is provided along the sidewalls and bottom of the trenches 126 and on the bit lines 132 .
- the dielectric liner material 127 may be silicon nitride (Si3N4), silicon dioxide (SiO2), silicon oxynitride (SiOxNy) or another suitable dielectric material that provides a fixed positive interface charge at the interface of the dielectric liner material and semiconductor material.
- the dielectric liner material may be formed with a thickness of from between 20 and 50 ⁇ . In the embodiment shown in FIG.
- the dielectric liner material 127 is provided along both the side of the semiconductor isolation regions 125 , the bit lines 132 , the semiconductor access device regions 135 , 140 , and the exposed portions 133 of the semiconductor access device regions 130 and first semiconductor region 116 . Since the bit lines 132 are spaced away from the first semiconductor region 116 , the dielectric liner material 127 covers the junction 128 between the semiconductor isolation regions 125 and the access device regions 130 .
- bit lines 132 a are formed as shown in FIG. 8 such that each bit line 132 a contacts the first semiconductor region 116 .
- the first semiconductor region 116 is then etched, as shown in FIG. 9 , to form semiconductor isolation regions 125 such that no portions of the semiconductor access device regions 130 are exposed.
- the dielectric liner material 127 a is provided in the sidewalls and bottom of the trenches 126 , as shown in FIG. 10 . By lining the trenches 126 as shown in FIG. 10 , no portion of the access device regions 130 are coated with the dielectric liner material 127 a.
- an intermediary material 129 may be formed adjacent to the bit line 132 , semiconductor isolation region 125 , and semiconductor access device regions 130 , 135 , 140 to facilitate deposition of the dielectric liner material 127 b to the bit line 132 , semiconductor isolation region 125 , and semiconductor access device regions 130 , 135 , 140 and provide a higher quality interface between the dielectric liner material 127 b and the bit line 132 , semiconductor isolation region 125 , and semiconductor access device regions 130 , 135 , 140 .
- the intermediary material may only be provided on the semiconductor isolation region 125 and the exposed portion 133 of the semiconductor access device region 130 .
- the intermediary material 129 may be formed of silicon dioxide (SiO2), hafnium oxide (HfO2) or other suitable materials to facilitate the adhesion of the dielectric liner material 127 b. In one embodiment, the intermediary material 129 is less than about 10 ⁇ thick.
- the dielectric liner material 127 is etched from the bottom of the trenches 126 to expose the first semiconductor region 116 , as shown in FIG. 12 .
- an anisotropic etch is utilized to ensure that the dielectric liner material 127 extends the entire height of the semiconductor isolation region 125 from the upper extent of the semiconductor region 140 to the surface of the first semiconductor region 116 .
- the dielectric liner material 127 c may be deposited such that it does not cover the bit lines 132 or the semiconductor regions 135 , 140 , by, for example, omitting the intermediary material 129 .
- the dielectric liner material 127 c may also be etched from the bit lines 132 using the same anisotropic etch discussed above, which removes the dielectric liner material 127 from the bottom of trenches 126 , or with the use of a second etching.
- the first semiconductor region 116 is further etched to deepen the trenches 126 , now 126 a.
- the etching is an anisotropic etching as is shown in FIG. 14 .
- an isotropic etching may be utilized to extend the trench 126 b beneath the semiconductor isolation regions 125 as shown in FIG. 15 .
- the bottom of the trench 126 a is oxidized to create a silicon dioxide isolation region 120 a, as shown in FIG. 16 .
- the silicon dioxide isolation region 120 a may be created through thermal oxidization or other suitable oxidization techniques. In the embodiment shown in FIG. 16 , the silicon dioxide isolation region 120 a does not extend completely beneath the semiconductor isolation regions 125 . However, in another embodiment, shown in FIG. 17 , the silicon dioxide isolation region 120 b may be formed such that adjacent silicon dioxide isolation region 120 b connect to further reduce band-band leakage from the partially-completed vertical access devices 110 a to the substrate 115 .
- the first semiconductor region 116 is not etched further, as was shown in FIGS. 14 and 15 .
- the exposed surface 118 of the first semiconductor region 116 at the bottom of the trenches 126 in FIG. 13 may be oxidized to create oxidation regions 120 c as is shown in FIG. 18 .
- the trenches 126 a of FIG. 16 are filled with a dielectric material, to the extent the grown oxide does not fill the trenches, creating an isolation region 120 .
- the trenches 126 a of FIG. 17 or trenches 126 of FIG. 18 could also be filled with dielectric material creating isolation regions 120 d, 120 e as was shown in FIG. 16 .
- the dielectric material may be applied by any suitable technique including spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD, atomic layer deposition (ALD), plasma enhanced ALD, or physical vapor deposition (PVD).
- the dielectric material may be formed from any suitable material including oxides, nitrides, or combinations thereof.
- FIG. 22 shows a perspective view of the completed vertical access device 110 , here a vertical MOSFET, completed using techniques known in the art once the isolation regions 120 are formed and the top surface of the FIG. 19 structure is planarized. Trenches are formed perpendicular to the bit lines 132 to the depth even with the top of the semiconductor regions 130 to allow for formation of the gate oxide elements 136 and word lines 137 .
- Gate oxide elements 136 are provided adjacent each second access device region 135 . In the embodiment shown in FIG. 22 , a gate oxide element 136 is provided on each side of the second access device region 135 . In a second embodiment, only one gate oxide element 136 is provided adjacent each second access device region 135 .
- a word line 137 is provided over the associated gate oxide element 136 to form a transistor gate.
- the first and third access device regions 130 , 140 act as source/drain regions for the associated access device 110 .
- the third access device region 140 is then coupled to a storage device 145 .
- the storage device 145 can be a capacitor or other suitable storage device known in the art.
- the second and third access device regions 135 , 140 could be formed after formation of dielectric liner material 127 and the isolation region 120 . In this embodiment, the dielectric liner material would not be formed on the second and third semiconductor regions 135 , 140 , as was shown in FIG. 13 .
- the isolation structure described above serves to reduce leakage from one vertical access device to another as well as from the vertical access device to the substrate.
- the isolation structure serves to have a fixed positive interface charge between the dielectric liner material and the isolation regions. In one embodiment, this fixed charge is between 1e12 and 5e12 cm ⁇ 2 , more preferably, approximately 3e12 cm 2 .
- This interface charge serves to reduce the Band-Band tunneling, which reduces bit line leakage.
- the isolation structure also increases the effective base length for the parasitic path between adjacent devices and reduces bit line-to-bit line leakage. If desired to further reduce Band-Band tunneling, the intermediary material 129 , shown in FIG.
- the isolation structure may be selected to move the fixed positive interface charge from the surface of the semiconductor material and locate the fixed charge at the interface of the intermediary material 129 and the dielectric liner material 127 , 127 a, 127 b, 127 c.
Abstract
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.
Description
- This application is a continuation of application Ser. No. 14/104,575, filed Dec. 12, 2013, which is a divisional of application Ser. No. 13/310,145, filed Dec. 2, 2011, now U.S. Pat. No. 8,633,564, which are incorporated by reference in their entirety.
- Embodiments of the invention relate to isolation structures for semiconductor devices, and more particularly, to isolation structures for vertically constructed semiconductor devices.
- Many electronic devices, such as personal computers, workstations, computer servers, mainframes and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. One type of memory device that is well-suited for use in such devices is dynamic random access memory (DRAM).
- Generally, DRAM includes a memory array having a plurality of memory cells that can be arranged in rows and columns. Conductive word lines may be positioned along the rows of the array to couple cells in respective rows, while conductive bit lines may be positioned along columns of the array and coupled to cells in the respective columns. The memory cells in the array may include an access device, such as a transistor device, and a storage device, such as a capacitor. The access device and the storage device may be coupled so that information is stored within a memory cell by imposing a predetermined charge state (corresponding to a selected logic level) on the storage device, and retrieved by accessing the charge state through the access device. Since the charge state in the storage device typically dissipates due to leakage from the cell, the storage device within each memory cell may be periodically refreshed. Current leakage from the cells in the DRAM may occur along several different paths, and if the current leakage is excessive, then the cell refresh interval may be relatively short, which can adversely affect access time for the memory device, and increase the amount of power consumed.
- As the cell density of memory devices increases, semiconductor devices, such as access devices, that are vertically disposed in a supporting substrate are increasingly favored. Although a vertical semiconductor device has a reduced footprint when compared to a laterally-disposed device, electrical device isolation presents a concern with ever increasing packing densities.
-
FIG. 1 is a circuit schematic of a partial memory device and processing system according to a disclosed embodiment. -
FIG. 2 is a top view of a vertical access device according to a disclosed embodiment. -
FIG. 3 is a step in the fabrication of memory elements according to a disclosed embodiment. -
FIG. 4 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 3 . -
FIG. 5 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 4 . -
FIG. 6 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 5 . -
FIG. 7 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 6 . -
FIG. 8 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 4 . -
FIG. 9 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 8 . -
FIG. 10 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 9 . -
FIG. 11 is a close-up partial view of an access device according to a disclosed embodiment. -
FIG. 12 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 7 . -
FIG. 13 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 6 . -
FIG. 14 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 12 . -
FIG. 15 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 12 . -
FIG. 16 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 14 . -
FIG. 17 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 14 . -
FIG. 18 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 12 . -
FIG. 19 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 16 . -
FIG. 20 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 17 . -
FIG. 21 is a step in the fabrication of memory elements according to a disclosed embodiment afterFIG. 18 . -
FIG. 22 is a completed vertical access device and associated storage device according to a disclosed embodiment. - In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate specific embodiments of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to make and use them. It is to be understood that structural, logical, or procedural changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the invention.
- The term “substrate” includes silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “substrate” in the following description, previous process steps may have been utilized to form regions, junctions or material layers in or on the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, gallium arsenide, or other known semiconductor materials.
- Embodiments described herein provide an isolation structure suitable for isolating vertical semiconductor devices. One example is a vertical access device that may be used in a memory product. However, the described embodiments are not limited to memory products, even though a memory product is described herein a providing a context for the invention.
-
FIG. 1 is a partial schematic illustration of amemory device 10, incorporating an array ofmemory elements 12. Thememory device 10 may be a DRAM device, for example, although the embodiments described herein are not limited to DRAM or even memory devices.Memory device 10 includes a number ofmemory elements 12 arranged in a grid pattern comprising a number of rows and columns. As can be appreciated, the number of memory elements 12 (and corresponding rows and columns) may vary depending on system requirements and fabrication technology. Eachmemory element 12 includes anaccess device 14 and astorage device 16. In this exemplary embodiment, theaccess device 14 comprises a transistor and thestorage device 16 comprises a capacitor. Theaccess device 14 provides controlled access to thestorage device 16. Theaccess device 14 includes asource terminal 18, adrain terminal 20, and agate terminal 22 for controlling conduction between the source anddrain terminals storage device 16 is coupled between one of the source/drain terminals - As is known in the art, an electrical charge is placed on the
source 18 of theaccess device 14 via a corresponding bit line (BL). By controlling the voltage at thegate 22 via the word line (WL), a voltage potential may be created across theaccess device 14 such that the electrical charge at thesource 18 can flow to or from thestorage device 16. - The bit lines BL are used to read from and write data to the
memory elements 12. The word lines WL are used to activate theaccess device 14 to access a particular row ofmemory elements 12. Thememory device 10 includes anaddress buffer 24, arow decoder 26, andcolumn decoder 28 to control the word lines WL and bit lines BL. Theaddress buffer 24 controls therow decoder 26 and thecolumn decoder 28 such that therow decoder 26 andcolumn decoder 28 selectively accessmemory elements 12 in response to addresssignals 30 provided during read and write operations. The address signals 30 are typically provided by anexternal controller 35 such as a microprocessor or other memory controller. Thecolumn decoder 28 may also include sense amplifiers and input/output circuitry to further enable data to be read from and written to thememory elements 12 via the bit lines BL. -
FIG. 2 illustrates theFIG. 1 memory device 10 showingvertical access devices 110 from a top view. As can be seen, thememory device 10 may be implemented with an array ofvertical access devices 110 that are coupled by access lines, for example word lines (WL), connected to the gates of theaccess devices 110, in rows and coupled by data/sense lines, for example bit lines (BL), connected to the source/drain regions, in columns. Between each row and column ofaccess devices 110, anisolation region 105 is provided to isolateaccess devices 110 and reduce leakage among theaccess devices 110 and from theaccess devices 110 to the substrate. As is understood, the word lines (WL) and bit lines (BL) are provided at different vertical elevations of theaccess devices 110. - In high density arrays it becomes increasingly difficult to prevent source/drain leakage from a vertical access device to the semiconductor substrate and device to device leakage due to band-band and trap assisted band-band tunneling. Embodiments described herein provide an isolation structure which reduces leakage from vertical access devices to the substrate without affecting leakage from one vertical access device to adjacent vertical access devices. Fabrication of such an isolation structure is now described with reference to
FIGS. 3-22 . - As is shown in the cross section of
FIG. 3 , asemiconductor substrate 115 is provided with a P-type dopedfirst semiconductor region 116, an overlyingsecond semiconductor region 117 doped to an opposite conductivity type, athird semiconductor region 118 doped with a P-type conductivity, andfourth semiconductor region 119 doped with an N-type conductivity. In one embodiment, thesemiconductor region 117 is an N-type doped semiconductor substrate, although, thesecond semiconductor region 117 may be doped to a higher concentration of dopant (e.g. N+ or N++type). As should be appreciated, whilesemiconductor regions semiconductor regions - The
second semiconductor region 117,third semiconductor region 118, andfourth semiconductor region 119 are then etched to formtrenches 131 between N-type semiconductoraccess device regions access device regions 135, as is shown inFIG. 4 . Next, as is shown inFIG. 5 ,bit lines 132 are provided in thetrenches 131 along each side of theaccess device regions 130. In another embodiment, thebit lines 132 may be provided only along one side of theaccess device regions 130. As is also shown inFIG. 5 , thebit lines 132 are formed so that the bottoms of thebit lines 132 do not contact thefirst semiconductor region 116. The bit lines 132 may be formed of any suitable bit line material known in the art including titanium nitride (TiN). - As is shown next in
FIG. 6 , thefirst semiconductor region 116 is etched to createtrenches 126 between adjacentaccess device regions 130 and to provide P-typesemiconductor isolation regions 125 below theaccess device regions 130. In one embodiment, thetrenches 126 are etched to the maximum depth permitted by the aspect ratio of the device. After thefirst semiconductor region 116 is etched to form thesemiconductor isolation regions 125, thesemiconductor isolation regions 125 may be subjected to further P-type implantation to more heavily dope the P-typesemiconductor isolation regions 125. The dopant may be implanted through the semiconductoraccess device regions first semiconductor region 116 at the bottom of thetrenches 126 from where it diffuses up into thesemiconductor isolation regions 125, or implanted through other techniques known in the art. With the additional doping, thesemiconductor isolation regions 125 will become P+ doped regions while thefirst semiconductor region 116 remains doped P-type. - Next, as is shown in
FIG. 7 , adielectric liner material 127 is provided along the sidewalls and bottom of thetrenches 126 and on the bit lines 132. Thedielectric liner material 127 may be silicon nitride (Si3N4), silicon dioxide (SiO2), silicon oxynitride (SiOxNy) or another suitable dielectric material that provides a fixed positive interface charge at the interface of the dielectric liner material and semiconductor material. In one embodiment, the dielectric liner material may be formed with a thickness of from between 20 and 50 Å. In the embodiment shown inFIG. 7 , thedielectric liner material 127 is provided along both the side of thesemiconductor isolation regions 125, thebit lines 132, the semiconductoraccess device regions portions 133 of the semiconductoraccess device regions 130 andfirst semiconductor region 116. Since thebit lines 132 are spaced away from thefirst semiconductor region 116, thedielectric liner material 127 covers thejunction 128 between thesemiconductor isolation regions 125 and theaccess device regions 130. - In another embodiment, the
bit lines 132 a are formed as shown inFIG. 8 such that eachbit line 132 a contacts thefirst semiconductor region 116. Thefirst semiconductor region 116 is then etched, as shown inFIG. 9 , to formsemiconductor isolation regions 125 such that no portions of the semiconductoraccess device regions 130 are exposed. Thedielectric liner material 127 a is provided in the sidewalls and bottom of thetrenches 126, as shown inFIG. 10 . By lining thetrenches 126 as shown inFIG. 10 , no portion of theaccess device regions 130 are coated with thedielectric liner material 127 a. - In another embodiment, shown in
FIG. 11 in an up-close, cross-sectional view of thebit line 132,semiconductor isolation region 125, and semiconductoraccess device regions FIG. 7 , anintermediary material 129 may be formed adjacent to thebit line 132,semiconductor isolation region 125, and semiconductoraccess device regions dielectric liner material 127 b to thebit line 132,semiconductor isolation region 125, and semiconductoraccess device regions dielectric liner material 127 b and thebit line 132,semiconductor isolation region 125, and semiconductoraccess device regions semiconductor isolation region 125 and the exposedportion 133 of the semiconductoraccess device region 130. Theintermediary material 129 may be formed of silicon dioxide (SiO2), hafnium oxide (HfO2) or other suitable materials to facilitate the adhesion of thedielectric liner material 127 b. In one embodiment, theintermediary material 129 is less than about 10 Å thick. - After the
dielectric liner material 127 has been deposited, thedielectric liner material 127 is etched from the bottom of thetrenches 126 to expose thefirst semiconductor region 116, as shown inFIG. 12 . In one embodiment, an anisotropic etch is utilized to ensure that thedielectric liner material 127 extends the entire height of thesemiconductor isolation region 125 from the upper extent of thesemiconductor region 140 to the surface of thefirst semiconductor region 116. As is shown inFIG. 13 in alternative embodiments, thedielectric liner material 127 c may be deposited such that it does not cover thebit lines 132 or thesemiconductor regions intermediary material 129. In the alternative, thedielectric liner material 127 c may also be etched from thebit lines 132 using the same anisotropic etch discussed above, which removes thedielectric liner material 127 from the bottom oftrenches 126, or with the use of a second etching. - Next, as is shown in
FIG. 14 , thefirst semiconductor region 116 is further etched to deepen thetrenches 126, now 126 a. In one embodiment, the etching is an anisotropic etching as is shown inFIG. 14 . In another embodiment, an isotropic etching may be utilized to extend thetrench 126 b beneath thesemiconductor isolation regions 125 as shown inFIG. 15 . - Next, the bottom of the
trench 126 a is oxidized to create a silicondioxide isolation region 120 a, as shown inFIG. 16 . The silicondioxide isolation region 120 a may be created through thermal oxidization or other suitable oxidization techniques. In the embodiment shown inFIG. 16 , the silicondioxide isolation region 120 a does not extend completely beneath thesemiconductor isolation regions 125. However, in another embodiment, shown inFIG. 17 , the silicon dioxide isolation region 120 b may be formed such that adjacent silicon dioxide isolation region 120 b connect to further reduce band-band leakage from the partially-completedvertical access devices 110 a to thesubstrate 115. - In an alternative embodiment, the
first semiconductor region 116 is not etched further, as was shown inFIGS. 14 and 15 . Instead, the exposedsurface 118 of thefirst semiconductor region 116 at the bottom of thetrenches 126 inFIG. 13 may be oxidized to createoxidation regions 120 c as is shown inFIG. 18 . - Next, as illustrated in
FIG. 19 , thetrenches 126 a ofFIG. 16 are filled with a dielectric material, to the extent the grown oxide does not fill the trenches, creating anisolation region 120. In other embodiments shown inFIGS. 20 and 21 , thetrenches 126 a ofFIG. 17 ortrenches 126 ofFIG. 18 could also be filled with dielectric material creatingisolation regions FIG. 16 . The dielectric material may be applied by any suitable technique including spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD, atomic layer deposition (ALD), plasma enhanced ALD, or physical vapor deposition (PVD). The dielectric material may be formed from any suitable material including oxides, nitrides, or combinations thereof. -
FIG. 22 shows a perspective view of the completedvertical access device 110, here a vertical MOSFET, completed using techniques known in the art once theisolation regions 120 are formed and the top surface of theFIG. 19 structure is planarized. Trenches are formed perpendicular to thebit lines 132 to the depth even with the top of thesemiconductor regions 130 to allow for formation of thegate oxide elements 136 and word lines 137.Gate oxide elements 136 are provided adjacent each secondaccess device region 135. In the embodiment shown inFIG. 22 , agate oxide element 136 is provided on each side of the secondaccess device region 135. In a second embodiment, only onegate oxide element 136 is provided adjacent each secondaccess device region 135. Aword line 137 is provided over the associatedgate oxide element 136 to form a transistor gate. As was shown and described above with respect toFIG. 1 , the first and thirdaccess device regions access device 110. As is shown inFIG. 22 , the thirdaccess device region 140 is then coupled to astorage device 145. Thestorage device 145 can be a capacitor or other suitable storage device known in the art. In another embodiment, the second and thirdaccess device regions dielectric liner material 127 and theisolation region 120. In this embodiment, the dielectric liner material would not be formed on the second andthird semiconductor regions FIG. 13 . - The isolation structure described above serves to reduce leakage from one vertical access device to another as well as from the vertical access device to the substrate. The isolation structure serves to have a fixed positive interface charge between the dielectric liner material and the isolation regions. In one embodiment, this fixed charge is between 1e12 and 5e12 cm−2, more preferably, approximately 3e12 cm 2. This interface charge serves to reduce the Band-Band tunneling, which reduces bit line leakage. The isolation structure also increases the effective base length for the parasitic path between adjacent devices and reduces bit line-to-bit line leakage. If desired to further reduce Band-Band tunneling, the
intermediary material 129, shown inFIG. 11 , may be selected to move the fixed positive interface charge from the surface of the semiconductor material and locate the fixed charge at the interface of theintermediary material 129 and thedielectric liner material - While various embodiments have been described herein, various modifications and changes can be made. As is understood by one of ordinary skill in the art, the disclosed process is not limited to construction of MOSFET devices. In other embodiments, the disclosed process may be utilized in the formation of other devices using semiconductor regions of the type described above including bipolar transistors. Accordingly, the disclosed embodiments are not to be considered as limiting as the invention is defined solely by the scope of the appended claims.
Claims (20)
1. (canceled)
2. An isolation structure comprising:
a trench in a first portion of a semiconductor substrate, the trench defining an area between adjacent first semiconductor regions, the first semiconductor regions having a first type of conductivity, each first semiconductor region being adjacent to a second semiconductor region of a vertical access device, the second semiconductor region having a second type of conductivity;
a dielectric liner material formed in the trench of the adjacent first semiconductor regions; and
a dielectric liner material that fills the trench to form at least a portion of an isolation region such that only the dielectric material is provided between the dielectric liner material formed in the trench between the adjacent first semiconductor regions,
wherein the trench extends into a second portion of the semiconductor substrate residing below the first portion, and wherein the isolation region is formed in the second portion of the semiconductor substrate.
3. The trench isolation structure of claim 2 , wherein the trench extends beneath adjacent first semiconductor regions.
4. The trench isolation structure of claim 2 , wherein the isolation region is formed in the second portion of the semiconductor substrate to extend beneath an adjacent first semiconductor regions.
5. The isolation structure of claim 4 , wherein the dielectric liner material is formed in contact with at least a portion of at least one adjacent first semiconductor regions.
6. The isolation structure of claim 2 , further comprising a bit line adjacent to and in electrical communication with the second semiconductor region.
7. The isolation structure of claim 6 , wherein the bit line is formed such that the bit line is spaced from a junction where the first semiconductor region and the second semiconductor region contact.
8. The isolation structure of claim 6 , wherein the dielectric liner material is formed over the bit line.
9. The isolation structure of claim 6 , further comprising an intermediary material formed adjacent to the bit line.
10. The isolation structure of claim 2 , further comprising:
a third semiconductor region formed adjacent to the second semiconductor region, the third semiconductor region having a first dopant type;
a gate oxide formed adjacent to the third semiconductor region; and
a word line formed adjacent to the gate oxide.
11. A memory device comprising:
a plurality of storage devices; and
an array of vertical access devices, wherein each storage device is coupled to a corresponding vertical access device, the array comprising:
at least one trench in a first portion of a semiconductor substrate, the trench defining an area between adjacent first semiconductor regions of adjacent vertical access devices, the first semiconductor regions being doped to a first type of conductivity;
a dielectric liner material formed in the trench between the adjacent first semiconductor regions; and
an isolation region comprising a dielectric material that fills the trench such that only the dielectric material is provided between the dielectric liner material formed in the trench region between the adjacent first semiconductor regions,
wherein the trench extends into a second portion of the semiconductor substrate residing below the first portion, and wherein the isolation region is formed in the second portion of the semiconductor substrate.
12. The memory device of claim 11 , wherein the trench extends beneath adjacent first semiconductor regions.
13. The memory device of claim 11 , wherein the isolation region is formed in the second portion of the semiconductor substrate to extend beneath an adjacent first semiconductor regions.
14. The memory device of claim 11 , wherein the isolation region is formed in the second portion of the semiconductor substrate to extend beneath an adjacent first semiconductor regions.
15. The memory device of claim 13 , wherein the dielectric liner material is formed in contact with at least a portion of at least one adjacent first semiconductor regions.
16. The memory device of claim 11 , further comprising a bit line adjacent to and in electrical communication with the second semiconductor region.
17. The memory device of claim 16 , wherein the bit line is formed such that the bit line is spaced from a junction where the first semiconductor region and the second semiconductor region contact.
18. The memory device of claim 17 , further comprising an intermediary material formed adjacent to the bit line.
19. The memory device of claim 11 , further comprising:
a third semiconductor region formed adjacent to the second semiconductor region, the third semiconductor region having a first dopant type;
a gate oxide formed adjacent to the third semiconductor region; and
a word line formed adjacent to the gate oxide.
20. A memory device comprising:
a plurality of storage devices; and
an array of vertical access devices, wherein each storage device is coupled to a corresponding vertical access device, the array comprising:
at least one trench in a first portion of a semiconductor substrate, the trench defining an area between adjacent first semiconductor regions of adjacent vertical access devices, the first semiconductor regions being doped to a first type of conductivity;
a dielectric liner material formed in the trench between the adjacent first semiconductor regions; and
an isolation region comprising a dielectric material that fills the trench such that only the dielectric material is provided between the dielectric liner material formed in the trench region between the adjacent first semiconductor regions,
wherein the trench extends into a second portion of the semiconductor substrate residing below the first portion, wherein the isolation region is formed in the second portion of the semiconductor substrate, and wherein the isolation region extends beneath an adjacent first semiconductor regions such that it contacts an adjacent isolation region.
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US14/605,100 US20150140781A1 (en) | 2011-12-02 | 2015-01-26 | Semiconductor isolation structure and method of manufacture |
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US13/310,145 US8633564B2 (en) | 2011-12-02 | 2011-12-02 | Semicondutor isolation structure |
US14/104,575 US8962445B2 (en) | 2011-12-02 | 2013-12-12 | Method of manufacture of semiconductor isolation structure |
US14/605,100 US20150140781A1 (en) | 2011-12-02 | 2015-01-26 | Semiconductor isolation structure and method of manufacture |
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US9761580B1 (en) | 2016-11-01 | 2017-09-12 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
US9837420B1 (en) | 2017-01-10 | 2017-12-05 | Micron Technology, Inc. | Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor |
US9842839B1 (en) | 2017-01-12 | 2017-12-12 | Micron Technology, Inc. | Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above |
US9935114B1 (en) | 2017-01-10 | 2018-04-03 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
US10014305B2 (en) | 2016-11-01 | 2018-07-03 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
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US9761580B1 (en) | 2016-11-01 | 2017-09-12 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
US10014305B2 (en) | 2016-11-01 | 2018-07-03 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
US10157913B2 (en) | 2016-11-01 | 2018-12-18 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
US10062745B2 (en) | 2017-01-09 | 2018-08-28 | Micron Technology, Inc. | Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor |
US9837420B1 (en) | 2017-01-10 | 2017-12-05 | Micron Technology, Inc. | Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor |
US9935114B1 (en) | 2017-01-10 | 2018-04-03 | Micron Technology, Inc. | Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors |
US10202583B2 (en) | 2017-01-10 | 2019-02-12 | Micron Technology, Inc. | Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor |
US9842839B1 (en) | 2017-01-12 | 2017-12-12 | Micron Technology, Inc. | Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above |
US10192873B2 (en) | 2017-01-12 | 2019-01-29 | Micron Technology, Inc. | Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above |
US10388658B1 (en) | 2018-04-27 | 2019-08-20 | Micron Technology, Inc. | Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors |
Also Published As
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US20130140631A1 (en) | 2013-06-06 |
US8633564B2 (en) | 2014-01-21 |
US20140106539A1 (en) | 2014-04-17 |
US8962445B2 (en) | 2015-02-24 |
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