US20150118844A1 - Methods of Forming Patterns, and Methods of Forming Integrated Circuitry - Google Patents

Methods of Forming Patterns, and Methods of Forming Integrated Circuitry Download PDF

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US20150118844A1
US20150118844A1 US14/584,611 US201414584611A US2015118844A1 US 20150118844 A1 US20150118844 A1 US 20150118844A1 US 201414584611 A US201414584611 A US 201414584611A US 2015118844 A1 US2015118844 A1 US 2015118844A1
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lines
openings
forming
patterned
pattern
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Vishal Sipani
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices

Definitions

  • a continuing goal in semiconductor processing is to reduce the size of individual electronic components, and to thereby enable smaller and denser integrated circuitry. For instance, it can be desired to form memory circuitry (such as DRAM, NAND memory, etc.) to increasingly higher levels of integration.
  • memory circuitry such as DRAM, NAND memory, etc.
  • Pitch can be used to quantify the density of an integrated circuit pattern.
  • Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern.
  • Feature size limitations of a lithographic technique can set a minimum pitch that can be obtained from the lithographic technique.
  • Lithographic processes such as photolithography, are commonly utilized during semiconductor processing for fabricating integrated structures.
  • Lithographic processes have minimum capable feature sizes, F, which are the smallest feature sizes that can be reasonably formed with the processes.
  • F minimum capable feature sizes
  • photolithography may be limited by factors such as optics and radiation wavelength.
  • Pitch multiplication such as pitch-doubling
  • Pitch multiplication is a method for extending the capabilities of lithographic techniques beyond their minimum pitches.
  • Pitch multiplication may involve forming sub-lithographic features (i.e., features narrower than minimum lithographic resolution) by depositing a material to have a thickness which is less than that of the minimum capable lithographic feature size, F.
  • the material may be anisotropically etched to form the sub-lithographic features.
  • the sub-lithographic features may then be used for integrated circuit fabrication to create higher density circuit patterns than can be achieved with conventional lithographic processing.
  • FIGS. 1-60 illustrate a semiconductor construction at various stages of an example embodiment method of forming a pattern.
  • FIG. 1 shows a top view of the construction
  • FIGS. 2-4 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 1 , respectively.
  • FIG. 5 shows a top view of the construction at a processing stage subsequent to that of FIG. 1
  • FIGS. 6-8 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 5 , respectively.
  • FIG. 9 shows a top view of the construction at a processing stage subsequent to that of FIG. 5
  • FIGS. 10-12 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 9 , respectively.
  • FIG. 13 shows a top view of the construction at a processing stage subsequent to that of FIG. 9
  • FIGS. 14-16 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 13 , respectively.
  • FIG. 17 shows a top view of the construction at a processing stage subsequent to that of FIG. 13
  • FIGS. 18-20 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 17 , respectively.
  • FIG. 21 shows a top view of the construction at a processing stage subsequent to that of FIG. 17
  • FIGS. 22-24 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 21 , respectively.
  • FIG. 25 shows a top view of the construction at a processing stage subsequent to that of FIG. 21
  • FIGS. 26-28 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 25 , respectively.
  • FIG. 29 shows a top view of the construction at a processing stage subsequent to that of FIG. 25
  • FIGS. 30-32 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 29 , respectively.
  • FIG. 33 shows a top view of the construction at a processing stage subsequent to that of FIG. 29
  • FIGS. 34-36 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 33 , respectively.
  • FIG. 37 shows a top view of the construction at a processing stage subsequent to that of FIG. 33
  • FIGS. 38-40 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 37 , respectively.
  • FIG. 41 shows a top view of the construction at a processing stage subsequent to that of FIG. 37
  • FIGS. 42-44 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 41 , respectively.
  • FIG. 45 shows a top view of the construction at a processing stage subsequent to that of FIG. 41
  • FIGS. 46-48 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 45 , respectively.
  • FIG. 49 shows a top view of the construction at a processing stage subsequent to that of FIG. 45
  • FIGS. 50-52 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 49 , respectively.
  • FIG. 53 shows a top view of the construction at a processing stage subsequent to that of FIG. 49
  • FIGS. 54-56 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 53 , respectively.
  • FIG. 57 shows a top view of the construction at a processing stage subsequent to that of FIG. 53
  • FIGS. 58-60 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 57 , respectively.
  • FIG. 61 shows an expanded view of a region labeled “D” in FIG. 57 .
  • FIG. 62 shows the construction of FIG. 59 at a processing stage subsequent to that of FIG. 59 in accordance with an example embodiment method.
  • FIG. 63 shows the construction of FIG. 59 at a processing stage subsequent to that of FIG. 59 in accordance with another example embodiment method.
  • Some embodiments comprise methods of forming patterns in which a second series of lines is overlaid across a first series of lines to form a grid.
  • Such grid may be utilized to define a repeating pattern, and such a pattern may be utilized to fabricate an array of highly-integrated integrated circuitry, such as a DRAM array, a NAND memory array, etc.
  • Example embodiments are described with reference to FIGS. 1-63 .
  • a semiconductor construction 10 is shown in top view ( FIG. 1 ) and cross-sectional side views ( FIGS. 2-4 ).
  • the construction comprises a base 12 and a stack 14 of materials 16 , 18 and 20 over the base.
  • the base may comprise, consist essentially of, or consist of monocrystalline silicon, and may be referred to as a semiconductor substrate, or as a portion of a semiconductor substrate.
  • semiconductor substrate semiconductor substrate
  • semiconductor construction semiconductor substrate
  • semiconductor substrate semiconductor substrate
  • semiconductor substrate semiconductor substrate
  • semiconductor substrate semiconductor substrate
  • semiconductor material layers semiconductive material layers
  • substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. In such embodiments, such materials may correspond to one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.
  • the materials 16 , 18 and 20 may be selectively etchible relative to one another, and may comprise any suitable materials.
  • a first material is considered to be “selectively etchible” relative to a second material if etching conditions may be chosen which remove the first material at a faster rate than the second material; which can include, but is not limited to, embodiments in which the first material is removed under conditions which are 100 percent selective for the first material relative to the second material.
  • material 16 may be electrically insulative material which is ultimately patterned into a hard mask suitable for forming an integrated circuit pattern which extends into base 12 (as discussed below with reference to FIG. 63 ).
  • material 16 may comprise, consist essentially of, or consist of, for example, silicon nitride.
  • material 16 may be an electrically conductive material which ultimately supports electrically conductive contacts formed thereover (as discussed below with reference to FIG. 62 ).
  • material 16 may comprise, consist essentially of, or consist of, for example, one or more of various metals (e.g., copper, aluminum, tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitrides, metal carbides, metal silicides, etc.), and conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).
  • the material 16 may be considered to be an expanse which extends across at least a portion of base 12 .
  • material 18 may comprise, consist essentially of, or consist of silicon.
  • material 18 may consist essentially of one or both of polycrystalline silicon and amorphous silicon.
  • material 20 may comprise silicon oxynitride (e.g., a deposited antireflective composition (DARC)).
  • silicon oxynitride e.g., a deposited antireflective composition (DARC)
  • the silicon oxynitride maybe oxygen enriched.
  • the materials 16 , 18 and 20 may be formed to any suitable thicknesses, and in some embodiments the individual materials may be formed to thicknesses of from about 50 ⁇ to about 1000 ⁇ .
  • materials 18 and 20 are utilized to form a pattern which is ultimately transferred into one or more structures underlying the materials (for instance, the structures underlying materials 18 and 20 include the material 16 and the base 12 in the shown embodiment).
  • materials 18 and 20 may be referred to as stacked first and second materials, respectively, which are of different compositions relative to one another.
  • Patterned photoresist 22 is formed over the stack 14 .
  • the patterned photoresist may be formed utilizing photolithography, and in some embodiments may be referred to as a photolithographically-patterned photoresist mask.
  • the patterned photoresist is configured as a plurality of spaced apart lines 24 (which may be referred to as features in some embodiments) extending across an upper surface of material 20 .
  • the lines 24 extend primarily along a direction of an axis 5 .
  • the lines 24 are illustrated to be straight, in other embodiments the lines may be curved or wavy.
  • the photoresist lines 24 are subjected to trimming to reduce widths of the lines.
  • the trimming conditions may decrease the heights of the lines and/or may induce other changes to the lines (e.g., may impose a dome-shape to the lines).
  • trimming conditions may be chosen which isotropically etch the lines.
  • the trimming of the lines may be omitted in some embodiments. If the trimming is utilized, such trimming may be accomplished with any suitable processing; including, for example, plasma etching with an inductively coupled reactor.
  • the trimmed lines 24 at the processing stage of FIGS. 5-8 may have sub-lithographic widths.
  • the initial photoresist lines 24 formed at the processing stage of FIGS. 1-4 have widths of at least about 40 nanometers (nm), and the trimmed lines 24 at the processing stage of FIGS. 5-8 have widths of less than 40 nm, less than 20 nm, etc.
  • the pattern of trimmed photoresist lines 24 ( FIGS. 5-8 ) is transferred into material 20 , and subsequently the photoresist lines are removed.
  • the patterning of material 20 forms material 20 into a series of lines 26 over an upper surface of material 18 , with the individual lines extending along the direction of axis 5 .
  • the lines 26 are spaced-apart from one another by spaces 28 .
  • the lines 26 and spaces 28 together define an undulating topography of construction 10 .
  • a material 30 is formed across the undulating topography of lines 26 and spaces 28 .
  • the material 30 may be a spin-on material, and may be deposited to a suitable thickness and under appropriate conditions to form the shown planarized surface 31 above lines 26 .
  • material 30 may comprise one or more organic polymers, and accordingly may be a carbon-containing spin-on material.
  • material 30 may comprise other compositions besides spin-on compositions, and the planarized surface 31 may be formed by chemical-mechanical polishing (CMP) or other suitable planarization.
  • CMP chemical-mechanical polishing
  • material 30 may be referred to as a third material to distinguish it from the above-discussed first and second materials 18 and 20 . In some embodiments, material 30 may be about twice as thick as material 20 .
  • a hard mask material 32 is formed over surface 31 , and patterned photoresist 34 is formed over the hard mask material.
  • the patterned photoresist may be formed utilizing photolithography, and in some embodiments may be referred to as a photolithographically-patterned photoresist mask.
  • the patterned photoresist is configured as a plurality of spaced-apart lines 36 (which may be referred to as features in some embodiments) extending across an upper surface of hard mask material 32 . In the shown embodiment, the lines 36 extend primarily along a direction of an axis 7 .
  • the axis 7 intersects the axis 5 (described above in FIGS. 1-4 ).
  • axis 7 is substantially orthogonal to axis 5 ; with the term “substantially orthogonal” meaning that the axes are orthogonal to within reasonable tolerances of fabrication and measurement. In other embodiments, axis 7 may not be substantially orthogonal to axis 5 , and accordingly may intersect axis 5 at an angle other than about 90°.
  • lines 36 are illustrated to be straight, in other embodiments the lines may be curved or wavy.
  • the hard mask material 32 may comprise any suitable composition or combination of compositions, and in some embodiments may comprise, consist essentially of, or consist of silicon nitride, silicon oxynitride, etc.
  • the pattern of photoresist lines 36 ( FIGS. 13-16 ) is transferred through hard mask material 32 ( FIGS. 13-16 ) and into material 30 , and subsequently the hard mask material and photoresist lines are removed.
  • the patterning of material 30 forms material 30 into a series of lines 38 extending over lines 26 and across an upper surface of the material 18 , with the individual lines 38 extending along the direction of axis 7 .
  • the lines 38 may be about twice as tall as the lines 26 .
  • the photoresist lines 36 may be trimmed with processing analogous to that of FIGS. 5-8 prior to transferring the pattern of the photoresist lines into material 30 . Accordingly, the lines 38 may have sub-lithographic widths at the processing stage of FIGS. 17-20 .
  • the lines 38 are subjected to trimming to reduce widths of the lines.
  • the trimming conditions may decrease the heights of the lines and/or may induce other changes to the lines (e.g., may impose a dome-shape to the lines).
  • trimming conditions may be chosen which isotropically etch the lines.
  • the trimming of the lines may be omitted in some embodiments. If the trimming is utilized, and the lines 38 comprise organic material, such trimming may be accomplished utilizing, for example, plasma etching with an inductively coupled reactor.
  • the lines 38 at the processing stage of FIGS. 21-24 have widths of less than 40 nm, less than 20 nm, etc. In some embodiments, the trimmed lines 38 at the processing stage of FIGS. 21-24 may have sub-lithographic widths. In some embodiments, the trimming shown in FIGS. 21-24 may be omitted. In some embodiments, the photoresist lines 36 of FIGS. 13-16 may be trimmed additionally, or alternatively, to trimming the lines 38 of material 30 .
  • the lines 26 of material 20 may be referred to as first lines, and the lines 38 of material 30 may be referred to as second lines.
  • Such first and second lines form a crosshatch pattern (or lattice) over material 18 .
  • Openings 40 extend through the crosshatch pattern, with such openings exposing regions of material 18 .
  • the first and second lines 26 and 38 are both on about the same pitch, P 1 , and are orthogonal to one another. Accordingly, the openings 40 are substantially square. In other embodiments, the lines 38 may be at an angle which is other than orthogonal relative to the lines 26 , and/or the lines 38 may be on a different pitch than the lines 26 . Accordingly, the openings may be rectangular in some embodiments, and may be of other polygonal shapes besides square or rectangular in yet other embodiments. In some embodiments, the lines 26 and/or 38 may be curved or wavy, and thus at least some of the openings may have curved shapes.
  • the lines 38 have about the same widths as the lines 26 , but in other embodiments the lines 38 may have different widths than the lines 26 . In the shown embodiment, all of the openings 40 are about the same size and shape as one another. However, in some embodiments the lines 26 may be arranged in a pattern other than the shown uniform pitch, and/or the lines 38 may be arranged in a pattern other than the shown uniform pitch, which can enable openings 40 to be formed in a repeating pattern with some of the openings being larger and/or differently shaped than others.
  • spacer material 42 (only some of which is labeled) is provided along and over the first and second lines 26 and 38 , and then anisotropically etched to form spacers 44 (only some which are labeled).
  • the spacers narrow the openings 40 .
  • the spacer material 42 may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide or silicon nitride.
  • the narrowed openings 40 are extended through material 18 to expose an upper surface of material 16 .
  • material 18 comprises silicon (e.g., polycrystalline and/or amorphous silicon), and material 16 comprise silicon nitride.
  • the narrowed openings 40 are extended through a silicon-containing material to expose an upper surface of a silicon nitride-containing material.
  • material 16 may be referred to as an expanse under material 18 , and in such embodiments the narrowed openings may be considered to be extended through material 18 to expose an upper surface of the expanse.
  • the openings 40 may be extended through material 18 with any suitable processing, including, for example, utilization of a plasma etch.
  • the spacers 44 are removed with an etch selective for the spacer material 42 ( FIGS. 29-32 ) relative to materials 16 , 18 , 20 and 30 .
  • a first material is considered to be “selectively removed” relative to a second material if the first material is removed at a faster rate than the second material; which can include, but is not limited to, embodiments in which the first material is removed under conditions which are 100 percent selective for the first material relative to the second material.
  • the spacer material consists of silicon dioxide
  • material 16 consists of silicon nitride
  • material 18 consists of silicon
  • material 20 consists of silicon oxynitride
  • material 30 consists of an organic polymer.
  • exposed portions of material 20 are removed selectively relative to material 16 , 18 and 30 . Such removes portions of lines 26 ( FIGS. 33-36 ) while leaving segments 48 of the lines 26 underneath the lines 38 of material 30 .
  • the cross-section of FIG. 40 shows some segments 48 of lines 26 under one of the lines 38 of material 30 .
  • the lines 38 of material 30 are removed to uncover the segments 48 of material 20 .
  • the segments 48 are pedestals having about the same dimensions as openings 40 . In other embodiments, the pedestals may have other dimensions and/or shapes than openings 40 .
  • FIG. 41 shows that the segments 48 (i.e., the segments of material 20 ) and the openings 40 together form a repeating pattern across the construction 10 .
  • the processing of FIGS. 45-60 aligns openings in material 18 to the locations of the segments 48 .
  • a masking material 50 is formed between the segments 48 .
  • the masking material fills the openings 40 , and leaves upper surfaces of the segments 48 exposed.
  • the material 50 comprises a composition to which material 20 may be selectively removed, and may comprise any suitable substance.
  • the masking material 50 may comprise a spin-on carbon-containing material, and may be identical to the material 30 described above with reference to FIGS. 13-16 .
  • the material 50 may be formed in the shown configuration by initially forming material 50 to cover the segments 48 , and then utilizing CMP or other suitable planarization to remove excess material 50 from over the segments 48 ; and/or utilizing a plasma etch to remove the excess material 50 .
  • the segments 48 are removed selectively relative to material 50 to leave openings 52 extending through material 50 to an upper surface of material 18 .
  • the openings 52 are extended through material 18 to an upper surface of material 16 .
  • the openings 52 may be extended through material 18 with any suitable processing, including, for example, utilization of a plasma etch.
  • the masking material 50 ( FIGS. 53-56 ) is removed.
  • the remaining material 18 is a patterned mask 60 having openings 40 and 52 extending therethrough.
  • the openings 40 and 52 may be referred to as first and second openings, respectively.
  • such first and second openings are about the same size and shape as one another, but in other embodiments the second openings may be different sizes and/or shapes than the first openings.
  • the first and second openings are approximately square-shaped.
  • the openings may have other shapes, including rectangular shapes, other polygonal shapes, circular shapes, elliptical shapes, other curved shapes, etc.
  • the first openings 40 are all approximately the same size and shape as one another. As discussed above with reference to FIGS. 21-24 , in other embodiments some of the openings 40 may be of different size and/or shapes relative to others of such openings.
  • the patterned mask 60 may comprise the dense repeating pattern illustrated in FIGS. 57-60 , or may comprise other patterns in other embodiments.
  • the pattern of openings 40 and 52 of FIGS. 57-60 may be considered to be suitable for fabrication of a cross-point array of integrated structures. Such pattern may be tailored for particular applications by adjusting various aspects of the pattern including, for example, sizes of the openings, shapes of the openings, spacings between the openings, pitch regularity, etc.
  • FIG. 61 shows an expanded region “D” of FIG. 57 and shows that the illustrated dense pattern of mask 60 may have a pitch P 2 which is reduced relative to the pitch P 1 of the lines 26 and 38 of FIGS. 21-24 .
  • the pitch P 2 is reduced relative to P 1 by a factor of about ⁇ square root over (2) ⁇ .
  • the patterned mask 60 may be utilized for patterning integrated circuitry.
  • FIG. 62 shows a construction 10 a at a processing stage subsequent to that of FIG. 59 .
  • the construction 10 a comprises electrically conductive material 16
  • the mask 60 is utilized for patterning a material 70 into electrically conductive interconnects that extend to the conductive material 16 .
  • FIG. 63 shows a construction 10 b at a processing stage subsequent to that of FIG. 59 in which the openings 40 are extended through material 16 to upper surface of base 12 .
  • one or more materials may be formed within openings 40 during fabrication of integrated circuitry supported by base 12 , and/or openings 40 may be extended into one or more materials of base 12 , and/or one or more dopants may be implanted through openings 40 and into base 12 .
  • the patterned mask 60 may be utilized for fabricating one or more components of highly-integrated memory circuitry; such as, for example, DRAM, NAND memory, etc.
  • Some embodiments include a method of forming a pattern.
  • a series of first lines are formed over a first material.
  • a series of second lines are formed over the first lines.
  • the first and second lines form a crosshatch pattern over the first material. Regions of the first material are exposed within first openings in the crosshatch pattern.
  • the first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments.
  • the second lines are removed to uncover the segments.
  • Masking material is formed between the segments.
  • the masking material fills the first openings.
  • the segments are removed to form second openings extending through the masking material to the first material.
  • the second openings are extended through the first material.
  • the masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein.
  • Some embodiments include a method of forming a pattern. Stacked first and second materials are formed over a base. The first and second materials are of different compositions relative to one another. The second material is over the first material. The second material is patterned into spaced-apart first lines extending primarily along a first direction. The first lines and spaces between the first lines define an undulating topography. A third material is formed over the undulating topography. The third material has a substantially planar upper surface. The third material is patterned into spaced-apart second lines extending primarily along a second direction that intersects the first direction. The first and second lines form a crosshatch pattern over the first material. Regions of the first material are exposed within first openings in the crosshatch pattern.
  • Spacers are formed along sidewalls of the first and second lines to narrow the first openings in the crosshatch pattern.
  • the narrowed first openings are extended through the first material.
  • the spacers are removed. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments.
  • the second lines are removed to uncover the segments.
  • Masking material is formed between the segments. The masking material fills the narrowed first openings.
  • the segments are removed to form second openings that extend through the masking material to the first material.
  • the second openings are extended through the first material.
  • the masking material is removed to leave a pattern of the second openings and the narrowed first openings within the first material.
  • Some embodiments include a method of forming a pattern.
  • a first material is formed over an expanse.
  • a second material is formed over the first material.
  • the second material comprises a different composition from the first material.
  • the second material is patterned into spaced-apart first lines extending primarily along a first direction.
  • the first lines and spaces between the first lines define an undulating topography.
  • Third material is deposited over the undulating topography with a spin-on process.
  • the third material has a substantially planar upper surface.
  • the third material is patterned into spaced-apart second lines extending primarily along a second direction that intersects the first direction.
  • the first and second lines form a crosshatch pattern over the first material. Regions of the first material are exposed within first openings in the crosshatch pattern.
  • Spacers are formed along sidewalls of the first and second lines to narrow the first openings in the crosshatch pattern.
  • the spacers comprise a different material from the first and second materials.
  • the narrowed first openings are extended through the first material.
  • the spacers are removed. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments.
  • the second lines are removed to uncover the segments.
  • Masking material is formed between the segments.
  • the masking material fills the narrowed first openings.
  • the segments are removed to form second openings that extend through the masking material to the first material.
  • the second openings are extended through the first material.
  • the masking material is removed to leave a repeating pattern comprising the second openings and the narrowed first openings.
  • the repeating pattern exposes an upper surface of the expanse.

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Abstract

Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.

Description

    RELATED PATENT DATA
  • This patent resulted from a continuation application of U.S. patent application Ser. No. 14/160,659 filed on Jan. 22, 2014, which is a continuation of U.S. patent application Ser. No. 13/600,714, which was filed on Aug. 31, 2012, now U.S. Pat. No. 8,647,981, both of which are incorporated by reference herein.
  • TECHNICAL FIELD
  • Methods of forming patterns, and methods of forming integrated circuitry.
  • BACKGROUND
  • A continuing goal in semiconductor processing is to reduce the size of individual electronic components, and to thereby enable smaller and denser integrated circuitry. For instance, it can be desired to form memory circuitry (such as DRAM, NAND memory, etc.) to increasingly higher levels of integration.
  • A concept commonly referred to as “pitch” can be used to quantify the density of an integrated circuit pattern. Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern. Feature size limitations of a lithographic technique can set a minimum pitch that can be obtained from the lithographic technique.
  • Lithographic processes, such as photolithography, are commonly utilized during semiconductor processing for fabricating integrated structures. Lithographic processes have minimum capable feature sizes, F, which are the smallest feature sizes that can be reasonably formed with the processes. For instance, photolithography may be limited by factors such as optics and radiation wavelength.
  • Pitch multiplication, such as pitch-doubling, is a method for extending the capabilities of lithographic techniques beyond their minimum pitches. Pitch multiplication may involve forming sub-lithographic features (i.e., features narrower than minimum lithographic resolution) by depositing a material to have a thickness which is less than that of the minimum capable lithographic feature size, F. The material may be anisotropically etched to form the sub-lithographic features. The sub-lithographic features may then be used for integrated circuit fabrication to create higher density circuit patterns than can be achieved with conventional lithographic processing.
  • It is desired to develop new methods of patterning which are suitable for fabrication of highly-integrated structures.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-60 illustrate a semiconductor construction at various stages of an example embodiment method of forming a pattern.
  • FIG. 1 shows a top view of the construction, and FIGS. 2-4 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 1, respectively.
  • FIG. 5 shows a top view of the construction at a processing stage subsequent to that of FIG. 1, and FIGS. 6-8 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 5, respectively.
  • FIG. 9 shows a top view of the construction at a processing stage subsequent to that of FIG. 5, and FIGS. 10-12 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 9, respectively.
  • FIG. 13 shows a top view of the construction at a processing stage subsequent to that of FIG. 9, and FIGS. 14-16 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 13, respectively.
  • FIG. 17 shows a top view of the construction at a processing stage subsequent to that of FIG. 13, and FIGS. 18-20 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 17, respectively.
  • FIG. 21 shows a top view of the construction at a processing stage subsequent to that of FIG. 17, and FIGS. 22-24 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 21, respectively.
  • FIG. 25 shows a top view of the construction at a processing stage subsequent to that of FIG. 21, and FIGS. 26-28 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 25, respectively.
  • FIG. 29 shows a top view of the construction at a processing stage subsequent to that of FIG. 25, and FIGS. 30-32 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 29, respectively.
  • FIG. 33 shows a top view of the construction at a processing stage subsequent to that of FIG. 29, and FIGS. 34-36 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 33, respectively.
  • FIG. 37 shows a top view of the construction at a processing stage subsequent to that of FIG. 33, and FIGS. 38-40 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 37, respectively.
  • FIG. 41 shows a top view of the construction at a processing stage subsequent to that of FIG. 37, and FIGS. 42-44 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 41, respectively.
  • FIG. 45 shows a top view of the construction at a processing stage subsequent to that of FIG. 41, and FIGS. 46-48 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 45, respectively.
  • FIG. 49 shows a top view of the construction at a processing stage subsequent to that of FIG. 45, and FIGS. 50-52 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 49, respectively.
  • FIG. 53 shows a top view of the construction at a processing stage subsequent to that of FIG. 49, and FIGS. 54-56 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 53, respectively.
  • FIG. 57 shows a top view of the construction at a processing stage subsequent to that of FIG. 53, and FIGS. 58-60 show cross-sectional side views along the lines A-A, B-B and C-C of FIG. 57, respectively.
  • FIG. 61 shows an expanded view of a region labeled “D” in FIG. 57.
  • FIG. 62 shows the construction of FIG. 59 at a processing stage subsequent to that of FIG. 59 in accordance with an example embodiment method.
  • FIG. 63 shows the construction of FIG. 59 at a processing stage subsequent to that of FIG. 59 in accordance with another example embodiment method.
  • DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
  • Some embodiments comprise methods of forming patterns in which a second series of lines is overlaid across a first series of lines to form a grid. Such grid may be utilized to define a repeating pattern, and such a pattern may be utilized to fabricate an array of highly-integrated integrated circuitry, such as a DRAM array, a NAND memory array, etc.
  • Example embodiments are described with reference to FIGS. 1-63.
  • Referring to FIGS. 1-4, a semiconductor construction 10 is shown in top view (FIG. 1) and cross-sectional side views (FIGS. 2-4). The construction comprises a base 12 and a stack 14 of materials 16, 18 and 20 over the base.
  • The base may comprise, consist essentially of, or consist of monocrystalline silicon, and may be referred to as a semiconductor substrate, or as a portion of a semiconductor substrate. The terms “semiconductive substrate,” “semiconductor construction” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. In some embodiments, the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. In such embodiments, such materials may correspond to one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.
  • The materials 16, 18 and 20 may be selectively etchible relative to one another, and may comprise any suitable materials. For purposes of interpreting this disclosure and the claims that follow, a first material is considered to be “selectively etchible” relative to a second material if etching conditions may be chosen which remove the first material at a faster rate than the second material; which can include, but is not limited to, embodiments in which the first material is removed under conditions which are 100 percent selective for the first material relative to the second material.
  • In some embodiments, material 16 may be electrically insulative material which is ultimately patterned into a hard mask suitable for forming an integrated circuit pattern which extends into base 12 (as discussed below with reference to FIG. 63). In such embodiments, material 16 may comprise, consist essentially of, or consist of, for example, silicon nitride. In some embodiments, material 16 may be an electrically conductive material which ultimately supports electrically conductive contacts formed thereover (as discussed below with reference to FIG. 62). In such embodiments, material 16 may comprise, consist essentially of, or consist of, for example, one or more of various metals (e.g., copper, aluminum, tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitrides, metal carbides, metal silicides, etc.), and conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the material 16 may be considered to be an expanse which extends across at least a portion of base 12.
  • In some embodiments, material 18 may comprise, consist essentially of, or consist of silicon. For instance, material 18 may consist essentially of one or both of polycrystalline silicon and amorphous silicon.
  • In some embodiments, material 20 may comprise silicon oxynitride (e.g., a deposited antireflective composition (DARC)). In some embodiments, the silicon oxynitride maybe oxygen enriched.
  • The materials 16, 18 and 20 may be formed to any suitable thicknesses, and in some embodiments the individual materials may be formed to thicknesses of from about 50 Å to about 1000 Å.
  • In some embodiments, materials 18 and 20 are utilized to form a pattern which is ultimately transferred into one or more structures underlying the materials (for instance, the structures underlying materials 18 and 20 include the material 16 and the base 12 in the shown embodiment). In some embodiments, materials 18 and 20 may be referred to as stacked first and second materials, respectively, which are of different compositions relative to one another.
  • Patterned photoresist 22 is formed over the stack 14. The patterned photoresist may be formed utilizing photolithography, and in some embodiments may be referred to as a photolithographically-patterned photoresist mask. The patterned photoresist is configured as a plurality of spaced apart lines 24 (which may be referred to as features in some embodiments) extending across an upper surface of material 20. In the shown embodiment, the lines 24 extend primarily along a direction of an axis 5. Although the lines 24 are illustrated to be straight, in other embodiments the lines may be curved or wavy.
  • Referring next to FIGS. 5-8, the photoresist lines 24 are subjected to trimming to reduce widths of the lines. Although the tops of the lines 24 are shown to be unaffected by the trimming, in some embodiments the trimming conditions may decrease the heights of the lines and/or may induce other changes to the lines (e.g., may impose a dome-shape to the lines). For instance, trimming conditions may be chosen which isotropically etch the lines. The trimming of the lines may be omitted in some embodiments. If the trimming is utilized, such trimming may be accomplished with any suitable processing; including, for example, plasma etching with an inductively coupled reactor.
  • In some embodiments, the trimmed lines 24 at the processing stage of FIGS. 5-8 may have sub-lithographic widths. In some embodiments, the initial photoresist lines 24 formed at the processing stage of FIGS. 1-4 have widths of at least about 40 nanometers (nm), and the trimmed lines 24 at the processing stage of FIGS. 5-8 have widths of less than 40 nm, less than 20 nm, etc.
  • Referring next to FIGS. 9-12, the pattern of trimmed photoresist lines 24 (FIGS. 5-8) is transferred into material 20, and subsequently the photoresist lines are removed. The patterning of material 20 forms material 20 into a series of lines 26 over an upper surface of material 18, with the individual lines extending along the direction of axis 5. The lines 26 are spaced-apart from one another by spaces 28. The lines 26 and spaces 28 together define an undulating topography of construction 10.
  • Referring next to FIGS. 13-16, a material 30 is formed across the undulating topography of lines 26 and spaces 28. The material 30 may be a spin-on material, and may be deposited to a suitable thickness and under appropriate conditions to form the shown planarized surface 31 above lines 26. In some embodiments, material 30 may comprise one or more organic polymers, and accordingly may be a carbon-containing spin-on material. In some embodiments, material 30 may comprise other compositions besides spin-on compositions, and the planarized surface 31 may be formed by chemical-mechanical polishing (CMP) or other suitable planarization.
  • In some embodiments, material 30 may be referred to as a third material to distinguish it from the above-discussed first and second materials 18 and 20. In some embodiments, material 30 may be about twice as thick as material 20.
  • A hard mask material 32 is formed over surface 31, and patterned photoresist 34 is formed over the hard mask material. The patterned photoresist may be formed utilizing photolithography, and in some embodiments may be referred to as a photolithographically-patterned photoresist mask. The patterned photoresist is configured as a plurality of spaced-apart lines 36 (which may be referred to as features in some embodiments) extending across an upper surface of hard mask material 32. In the shown embodiment, the lines 36 extend primarily along a direction of an axis 7. The axis 7 intersects the axis 5 (described above in FIGS. 1-4). In the shown embodiment, axis 7 is substantially orthogonal to axis 5; with the term “substantially orthogonal” meaning that the axes are orthogonal to within reasonable tolerances of fabrication and measurement. In other embodiments, axis 7 may not be substantially orthogonal to axis 5, and accordingly may intersect axis 5 at an angle other than about 90°.
  • Although the lines 36 are illustrated to be straight, in other embodiments the lines may be curved or wavy.
  • The hard mask material 32 may comprise any suitable composition or combination of compositions, and in some embodiments may comprise, consist essentially of, or consist of silicon nitride, silicon oxynitride, etc.
  • Referring next to FIGS. 17-20, the pattern of photoresist lines 36 (FIGS. 13-16) is transferred through hard mask material 32 (FIGS. 13-16) and into material 30, and subsequently the hard mask material and photoresist lines are removed. The patterning of material 30 forms material 30 into a series of lines 38 extending over lines 26 and across an upper surface of the material 18, with the individual lines 38 extending along the direction of axis 7. In some embodiments, the lines 38 may be about twice as tall as the lines 26.
  • In some embodiments, the photoresist lines 36 (FIGS. 13-16) may be trimmed with processing analogous to that of FIGS. 5-8 prior to transferring the pattern of the photoresist lines into material 30. Accordingly, the lines 38 may have sub-lithographic widths at the processing stage of FIGS. 17-20.
  • Referring next to FIGS. 21-24, the lines 38 are subjected to trimming to reduce widths of the lines. Although the tops of the lines 38 are shown to be unaffected by the trimming, in some embodiments the trimming conditions may decrease the heights of the lines and/or may induce other changes to the lines (e.g., may impose a dome-shape to the lines). For instance, trimming conditions may be chosen which isotropically etch the lines. The trimming of the lines may be omitted in some embodiments. If the trimming is utilized, and the lines 38 comprise organic material, such trimming may be accomplished utilizing, for example, plasma etching with an inductively coupled reactor.
  • In some embodiments, the lines 38 at the processing stage of FIGS. 21-24 have widths of less than 40 nm, less than 20 nm, etc. In some embodiments, the trimmed lines 38 at the processing stage of FIGS. 21-24 may have sub-lithographic widths. In some embodiments, the trimming shown in FIGS. 21-24 may be omitted. In some embodiments, the photoresist lines 36 of FIGS. 13-16 may be trimmed additionally, or alternatively, to trimming the lines 38 of material 30.
  • In some embodiments, the lines 26 of material 20 may be referred to as first lines, and the lines 38 of material 30 may be referred to as second lines. Such first and second lines form a crosshatch pattern (or lattice) over material 18. Openings 40 (only some of which are labeled) extend through the crosshatch pattern, with such openings exposing regions of material 18.
  • In the shown embodiment, the first and second lines 26 and 38 are both on about the same pitch, P1, and are orthogonal to one another. Accordingly, the openings 40 are substantially square. In other embodiments, the lines 38 may be at an angle which is other than orthogonal relative to the lines 26, and/or the lines 38 may be on a different pitch than the lines 26. Accordingly, the openings may be rectangular in some embodiments, and may be of other polygonal shapes besides square or rectangular in yet other embodiments. In some embodiments, the lines 26 and/or 38 may be curved or wavy, and thus at least some of the openings may have curved shapes.
  • In the shown embodiment the lines 38 have about the same widths as the lines 26, but in other embodiments the lines 38 may have different widths than the lines 26. In the shown embodiment, all of the openings 40 are about the same size and shape as one another. However, in some embodiments the lines 26 may be arranged in a pattern other than the shown uniform pitch, and/or the lines 38 may be arranged in a pattern other than the shown uniform pitch, which can enable openings 40 to be formed in a repeating pattern with some of the openings being larger and/or differently shaped than others.
  • Referring next to FIGS. 25-28, spacer material 42 (only some of which is labeled) is provided along and over the first and second lines 26 and 38, and then anisotropically etched to form spacers 44 (only some which are labeled). The spacers narrow the openings 40.
  • The spacer material 42 may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide or silicon nitride.
  • Referring to FIGS. 29-32, the narrowed openings 40 are extended through material 18 to expose an upper surface of material 16. As discussed above, in some embodiments material 18 comprises silicon (e.g., polycrystalline and/or amorphous silicon), and material 16 comprise silicon nitride. Accordingly, in some embodiments the narrowed openings 40 are extended through a silicon-containing material to expose an upper surface of a silicon nitride-containing material. In some embodiments material 16 may be referred to as an expanse under material 18, and in such embodiments the narrowed openings may be considered to be extended through material 18 to expose an upper surface of the expanse. The openings 40 may be extended through material 18 with any suitable processing, including, for example, utilization of a plasma etch.
  • Referring next to FIGS. 33-36, the spacers 44 (FIGS. 29-32) are removed with an etch selective for the spacer material 42 (FIGS. 29-32) relative to materials 16, 18, 20 and 30. For purposes of interpreting this disclosure and the claims that follow, a first material is considered to be “selectively removed” relative to a second material if the first material is removed at a faster rate than the second material; which can include, but is not limited to, embodiments in which the first material is removed under conditions which are 100 percent selective for the first material relative to the second material. In some embodiments, the spacer material consists of silicon dioxide, material 16 consists of silicon nitride, material 18 consists of silicon, material 20 consists of silicon oxynitride, and material 30 consists of an organic polymer.
  • Referring next to FIGS. 37-40, exposed portions of material 20 are removed selectively relative to material 16, 18 and 30. Such removes portions of lines 26 (FIGS. 33-36) while leaving segments 48 of the lines 26 underneath the lines 38 of material 30. The cross-section of FIG. 40 shows some segments 48 of lines 26 under one of the lines 38 of material 30.
  • Referring next to FIGS. 41-44, the lines 38 of material 30 (FIGS. 37-40) are removed to uncover the segments 48 of material 20. In the shown embodiment, the segments 48 are pedestals having about the same dimensions as openings 40. In other embodiments, the pedestals may have other dimensions and/or shapes than openings 40.
  • The top view of FIG. 41 shows that the segments 48 (i.e., the segments of material 20) and the openings 40 together form a repeating pattern across the construction 10. The processing of FIGS. 45-60 aligns openings in material 18 to the locations of the segments 48.
  • Referring to FIGS. 45-48, a masking material 50 is formed between the segments 48. The masking material fills the openings 40, and leaves upper surfaces of the segments 48 exposed. The material 50 comprises a composition to which material 20 may be selectively removed, and may comprise any suitable substance. In some embodiments, the masking material 50 may comprise a spin-on carbon-containing material, and may be identical to the material 30 described above with reference to FIGS. 13-16. The material 50 may be formed in the shown configuration by initially forming material 50 to cover the segments 48, and then utilizing CMP or other suitable planarization to remove excess material 50 from over the segments 48; and/or utilizing a plasma etch to remove the excess material 50.
  • Referring next to FIGS. 49-52, the segments 48 (FIGS. 45-48) are removed selectively relative to material 50 to leave openings 52 extending through material 50 to an upper surface of material 18.
  • Referring to FIGS. 53-56, the openings 52 are extended through material 18 to an upper surface of material 16. The openings 52 may be extended through material 18 with any suitable processing, including, for example, utilization of a plasma etch.
  • Referring to FIGS. 57-60, the masking material 50 (FIGS. 53-56) is removed. The remaining material 18 is a patterned mask 60 having openings 40 and 52 extending therethrough. The openings 40 and 52 may be referred to as first and second openings, respectively. In the shown embodiment, such first and second openings are about the same size and shape as one another, but in other embodiments the second openings may be different sizes and/or shapes than the first openings. In the shown embodiment, the first and second openings are approximately square-shaped. In other embodiments, the openings may have other shapes, including rectangular shapes, other polygonal shapes, circular shapes, elliptical shapes, other curved shapes, etc. In the shown embodiment, the first openings 40 are all approximately the same size and shape as one another. As discussed above with reference to FIGS. 21-24, in other embodiments some of the openings 40 may be of different size and/or shapes relative to others of such openings. Thus, the patterned mask 60 may comprise the dense repeating pattern illustrated in FIGS. 57-60, or may comprise other patterns in other embodiments.
  • In some embodiments, the pattern of openings 40 and 52 of FIGS. 57-60 may be considered to be suitable for fabrication of a cross-point array of integrated structures. Such pattern may be tailored for particular applications by adjusting various aspects of the pattern including, for example, sizes of the openings, shapes of the openings, spacings between the openings, pitch regularity, etc.
  • FIG. 61 shows an expanded region “D” of FIG. 57 and shows that the illustrated dense pattern of mask 60 may have a pitch P2 which is reduced relative to the pitch P1 of the lines 26 and 38 of FIGS. 21-24. In the shown embodiment, the pitch P2 is reduced relative to P1 by a factor of about √{square root over (2)}.
  • In subsequent processing, the patterned mask 60 may be utilized for patterning integrated circuitry. For instance, FIG. 62 shows a construction 10 a at a processing stage subsequent to that of FIG. 59. The construction 10 a comprises electrically conductive material 16, and the mask 60 is utilized for patterning a material 70 into electrically conductive interconnects that extend to the conductive material 16. As another example, FIG. 63 shows a construction 10 b at a processing stage subsequent to that of FIG. 59 in which the openings 40 are extended through material 16 to upper surface of base 12. In subsequent processing, one or more materials may be formed within openings 40 during fabrication of integrated circuitry supported by base 12, and/or openings 40 may be extended into one or more materials of base 12, and/or one or more dopants may be implanted through openings 40 and into base 12. In some embodiments, the patterned mask 60 may be utilized for fabricating one or more components of highly-integrated memory circuitry; such as, for example, DRAM, NAND memory, etc.
  • The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.
  • The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.
  • When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present. When a structure is referred to as being “connected” or “coupled” to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being “directly connected” or “directly coupled” to another structure, there are no intervening structures present.
  • Some embodiments include a method of forming a pattern. A series of first lines are formed over a first material. A series of second lines are formed over the first lines. The first and second lines form a crosshatch pattern over the first material. Regions of the first material are exposed within first openings in the crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The masking material fills the first openings. The segments are removed to form second openings extending through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein.
  • Some embodiments include a method of forming a pattern. Stacked first and second materials are formed over a base. The first and second materials are of different compositions relative to one another. The second material is over the first material. The second material is patterned into spaced-apart first lines extending primarily along a first direction. The first lines and spaces between the first lines define an undulating topography. A third material is formed over the undulating topography. The third material has a substantially planar upper surface. The third material is patterned into spaced-apart second lines extending primarily along a second direction that intersects the first direction. The first and second lines form a crosshatch pattern over the first material. Regions of the first material are exposed within first openings in the crosshatch pattern. Spacers are formed along sidewalls of the first and second lines to narrow the first openings in the crosshatch pattern. The narrowed first openings are extended through the first material. The spacers are removed. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The masking material fills the narrowed first openings. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a pattern of the second openings and the narrowed first openings within the first material.
  • Some embodiments include a method of forming a pattern. A first material is formed over an expanse. A second material is formed over the first material. The second material comprises a different composition from the first material. The second material is patterned into spaced-apart first lines extending primarily along a first direction. The first lines and spaces between the first lines define an undulating topography. Third material is deposited over the undulating topography with a spin-on process. The third material has a substantially planar upper surface. The third material is patterned into spaced-apart second lines extending primarily along a second direction that intersects the first direction. The first and second lines form a crosshatch pattern over the first material. Regions of the first material are exposed within first openings in the crosshatch pattern. Spacers are formed along sidewalls of the first and second lines to narrow the first openings in the crosshatch pattern. The spacers comprise a different material from the first and second materials. The narrowed first openings are extended through the first material. The spacers are removed. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The masking material fills the narrowed first openings. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a repeating pattern comprising the second openings and the narrowed first openings. The repeating pattern exposes an upper surface of the expanse.
  • In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.

Claims (15)

I/we claim:
1. A method of forming a pattern, comprising:
forming a first material over and in direct physical contact with an underlying material;
forming a crosshatch pattern over the first material, the crosshatch patterns having first openings;
narrowing the first openings in the crosshatch pattern;
extending the first openings through the first material;
after the extending, further patterning the cross hatch pattern;
forming a masking material over the first material and within the first openings;
forming second openings extending through the masking material to the first material;
extending the second openings through the first material; and
removing the masking material.
2. The method of claim 1 wherein the first material is over a base, and further comprising transferring a pattern from the patterned mask into the base.
3. The method of claim 1 further comprising forming electrically conductive material within the first and second openings of the patterned mask.
4. The method of claim 1 wherein the first material comprises amorphous silicon and/or polycrystalline silicon.
5. A method of forming a pattern, comprising:
forming stacked first and second materials over a base, the first material being over and in direct contact with an underlying material selected from the group consisting of silicon nitride, metals, metal comprising compositions and conductively doped semiconductor materials, the second material being over the first material;
patterning the second material into spaced-apart first lines;
forming a third material over the first lines;
patterning the third material into spaced-apart second lines, the first and second lines forming a crosshatch pattern over the first material;
forming spacers along sidewalls of the first and second lines to narrow the first openings in the crosshatch pattern;
extending the narrowed first openings through the first material;
patterning the first lines into segments;
forming masking material between the segments, the masking material filling the narrowed first openings;
removing the segments to form second openings through the masking material;
extending the second openings through the first material; and
removing the masking material.
6. The method of claim 5 wherein the patterning of the second material comprises forming a photolithographically-patterned photoresist mask over the second material, and transferring a pattern from the photoresist mask into the second material.
7. The method of claim 6 wherein the photolithographically-patterned photoresist mask comprises spaced-apart features, and further comprising trimming the features prior to transferring the pattern from the photoresist mask into the second material.
8. The method of claim 5 wherein the third material is a carbon-containing material.
9. The method of claim 5 wherein the patterning of the third material into the second lines comprises forming a hard mask over the third material, forming a photolithographically-patterned photoresist mask over the hard mask, transferring a pattern from the photoresist mask into the hard mask, and transferring a pattern from the hard mask into the third material.
10. The method of claim 9 wherein the photolithographically-patterned photoresist mask comprises spaced-apart features, and further comprising trimming the features prior to transferring the pattern from the photoresist mask into the hard mask.
11. A method of forming a semiconductor construction comprising:
providing a base and a stack of materials over the base;
forming a patterned photoresist over the stack of materials, the patterned photoresist comprising a plurality of spaced apart lines;
trimming the patterned photoresist to form narrowed lines;
transferring the pattern of the trimmed photoresist into an uppermost material comprised by the stack to form patterned first material lines;
forming a spin-on material over the patterned first material lines;
forming a hardmask material over the spin-on material;
patterning the hardmask material and the spin-on material into a series of patterned lines;
removing the hardmask material;
trimming the series of patterned lines; the series of patterned lines and patterned first material lines forming a lattice having openings therethrough; the patterned lines and the patterned first material lines having maximum linewidths of 40 nm;
narrowing the openings; and
extending the openings into a second material comprised by the stack.
12. The method of claim 11 wherein the spin-on material comprises one or more type of organic polymer.
13. The method of claim 11 wherein the narrowing the openings comprises formation of spacers within the openings.
14. The method of claim 13 further comprising removing the spacers after extending the openings into the second material.
15. The method of claim 11 wherein the patterned first material lines are orthogonal relative to the series of patterned lines.
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