US20150108558A1 - Scalable integrated mim capacitor using gate metal - Google Patents
Scalable integrated mim capacitor using gate metal Download PDFInfo
- Publication number
- US20150108558A1 US20150108558A1 US14/578,924 US201414578924A US2015108558A1 US 20150108558 A1 US20150108558 A1 US 20150108558A1 US 201414578924 A US201414578924 A US 201414578924A US 2015108558 A1 US2015108558 A1 US 2015108558A1
- Authority
- US
- United States
- Prior art keywords
- metal
- gate metal
- filler
- coplanar
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 134
- 239000002184 metal Substances 0.000 title claims abstract description 134
- 239000003990 capacitor Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000000945 filler Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 34
- 125000006850 spacer group Chemical group 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 abstract description 16
- 238000012545 processing Methods 0.000 description 24
- 239000003989 dielectric material Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- -1 tantalum carbide nitride Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
- H01L27/0811—MIS diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention is generally in the field of semiconductors. More particularly, the present invention is in the field of capacitor fabrication in semiconductor dies.
- Integrated capacitors comprise a fundamental building block of integrated analog and mixed signal circuits fabricated on semiconductor dies.
- Metal-insulator-metal (MIM) type capacitors are particularly desired in the field because, for example, they exhibit a substantially linear response to an applied voltage and because they are relatively insensitive to temperature fluctuations.
- Conventional integrated MIM capacitors are typically fabricated during back end of the line (BEOL) processing because, historically, metal has not been a conventional constituent of other semiconductor device processing steps.
- a conventional MIM capacitor can be fabricated, for example, by forming a dielectric layer for a MIM capacitor dielectric between metal layers for lower and upper MIM capacitor electrodes in the otherwise unused “vertical” space available over a semiconductor die during BEOL processing.
- forming the dielectric and metal layers during BEOL processing can require multiple process steps and masks, which can undesirably increase manufacturing cost.
- BEOL processing significantly lags state-of-the-art size reduction techniques, and so as other design processes scale down, BEOL processing increasingly fails to produce detailed device structures as small as desired or as precisely as desired.
- BEOL fabricated MIM capacitors have relatively poor reliability, accuracy and density statistics.
- a scalable integrated MIM capacitor using gate metal substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
- FIG. 1A illustrates a top-down view of a portion of a wafer processed according to an embodiment of the invention.
- FIG. 1B illustrates a cross-sectional view of the portion of the wafer shown in FIG. 1A , processed according to an embodiment of the invention.
- FIG. 2 shows a flowchart illustrating steps taken to implement an embodiment of the present invention.
- FIG. 3A illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an initial step in the flowchart in FIG. 2 .
- FIG. 3B illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 2 .
- FIG. 3C illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 2 .
- FIG. 3D illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to a final step in the flowchart in FIG. 2 .
- FIG. 4A illustrates a top-down view of a portion of a wafer processed according to an embodiment of the invention.
- FIG. 4B illustrates a cross-sectional view of the portion of the wafer shown in FIG. 4A , processed according to an embodiment of the invention.
- the present invention is directed to a scalable integrated MIM capacitor using gate metal.
- the following description contains specific information pertaining to the implementation of the present invention.
- One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.
- MIM capacitors inherently require metal in their construction.
- Conventional fabrication techniques typically have not included a metal processing step during a high precision front end of the line (FEOL) series of processing steps, so fabrication of integrated MIM capacitors has typically been relegated to the relatively low precision back end of the line (BEOL) series of processing steps.
- Such conventionally fabricated MIM capacitors may be relatively large and may have relatively thick segments of capacitor dielectric situated between their metal terminals.
- conventional integrated MIM capacitors typically use a large amount of die area for the amount of capacitance they exhibit, add time and cost to device fabrication, are relatively unreliable and inaccurate, and do not scale with advances in FEOL resolution enhancements.
- FIG. 1A and FIG. 1B illustrate respective top-down and cross-sectional views of an embodiment of the present invention that addresses the above problems.
- FIGS. 1A and 1B show MIM capacitor structure 100 formed by leveraging FEOL processing techniques originally developed to fabricate high dielectric constant (high-k) metal gate transistors (e.g., P type or N type field effect transistors—PFETs or NFETs) and other CMOS devices.
- high-k metal gate transistors
- MIM capacitor structure 100 can comprise a series of gate metal terminals laterally separated from each other by a filler, wherein each element of MIM capacitor structure 100 can be formed during a high-k metal gate device fabrication process.
- MIM capacitor structure 100 comprises substrate 110 , isolation region 120 , multiple capacitor terminal stacks 101 a , and etch-stop filler 160 .
- Individual capacitor terminal stacks 101 a can comprise high-k dielectric segment 130 , gate metal terminal 170 , and spacers 150 . Composition and formation details of the above elements are more fully described with respect to FIGS. 2 and 3A through 3 D below.
- Substrate 110 can be configured to support isolation region 120 as well as other semiconductor devices as is shown in FIGS. 3A through 3D .
- Isolation region 120 can be configured to electrically isolate capacitor terminal stacks 101 a from substrate 110 .
- high-k dielectric segment 130 can be configured to serve, among other things, to further electrically isolate gate metal terminal 170 .
- gate metal terminal 170 can be configured to serve, among other things, as a capacitor terminal within each capacitor terminal stack 100 a .
- Spacers 150 and etch-stop filler 160 can be configured to form a capacitor dielectric, thereby, for example, completing MIM capacitor structure 100 .
- Individual capacitor terminal stacks 101 a can be configured to act as positive or negative capacitor terminals by, for example, using conventional techniques to form contacts 180 .
- Contacts 180 may comprise, for example, tungsten, formed over an end of each capacitor terminal stack 101 a corresponding to either a positive or negative lead, thereby facilitating later integration into analog and mixed signal semiconductor circuits.
- One example of such a configuration can result in a comb-like capacitive structure as is shown in the top-down view of FIG. 1A .
- the capacitance of a completed integrated capacitor such as MIM capacitor structure 100 can roughly depend on the height, width, length, spacing and profile of gate metal terminals 170 , spacers 150 and etch-stop filler 160 , as well as which of gate metal terminals 170 in a particular MIM capacitor structure, such as MIM capacitor structure 100 , are configured as positive or negative.
- MIM capacitor structure 100 can scale with available FEOL processing technology. As a result, MIM capacitor structure 100 can be configured to exhibit a smaller overall size as well as a thinner dielectric segment than conventional MIM capacitors fabricated during BEOL processing.
- MIM capacitor structure 100 can exhibit a relatively large capacitance for the amount of die area it uses because its terminals can be formed relatively closely to one another, can exhibit better reliability and accuracy statistics due to the relatively greater precision and consistency of FEOL processing techniques, and can reduce overall time and cost of device fabrication by utilizing a process that can form high-k metal gate PFETs and other CMOS devices substantially concurrently with MIM capacitor structure 100 .
- FIG. 2 shows a flow chart illustrating a method for fabricating an integrated capacitor in a semiconductor die, according to an embodiment of the present invention.
- Certain details and features have been left out of flowchart 200 that are apparent to a person of ordinary skill in the art.
- a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art.
- Steps 201 through 204 indicated in flowchart 200 are sufficient to describe one embodiment of the present invention; however, other embodiments of the invention may make use of steps different from those shown in flowchart 200 .
- FIGS. 3A through 3D illustrate the result of performing steps 201 through 204 of flowchart 200 , respectively.
- FIG. 3A shows a semiconductor structure after processing step 201
- FIG. 3B shows the structure in FIG. 3A after processing step 202
- FIG. 3C shows the structure in FIG. 3B after processing step 203 , and so forth.
- processing steps shown in flowchart 200 are performed on a portion of a processed wafer, which, prior to step 201 , may include, among other things, a substrate, such as a silicon substrate, isolation regions, such as STI regions, and partially formed high-k metal gate transistor gate stacks, such as pre-form PFET gate stacks, all formed in the substrate using conventional techniques.
- the wafer is also referred to simply as a wafer or a semiconductor die or simply a die in the present application.
- each corresponding feature can comprise the same material as its counterpart, and each can be formed utilizing the same methods used to form its counterpart.
- step 201 of flowchart 200 comprises forming a filler layer over, for example, a series of partially formed high-k metal gate transistor stacks.
- FIG. 3A shows a structure including substrate 310 , isolation region 320 , pre-form capacitor terminal stacks 301 a and pre-form PFET gate stack 301 b after completion of step 201 of flowchart 200 in FIG. 2 , where etch-stop filler 360 can be formed over pre-form capacitor terminal stacks 301 a and pre-form PFET gate stack 301 b.
- substrate 310 can comprise, for example, silicon, and can be configured to support formation of isolation region 320 , pre-form PFET gate stack 301 b , and gate/source regions 311 , or other semiconductor structures or multiple embodiments of any of the above.
- Isolation region 320 can be a shallow trench isolation (STI) region comprised of silicon oxide or other dielectric material, for example, and can be configured to electrically isolate semiconductor structures (e.g., pre-form capacitor terminal stacks 301 a ) from substrate 310 .
- STI shallow trench isolation
- Pre-form capacitor terminal stacks 301 a and pre-form PFET gate stack 301 b can each comprise, for example, high-k dielectric segment 330 , spacers 350 , and dummy-material segment 340 .
- pre-form capacitor terminal stacks 301 a can be formed, for example, over isolation region 320 in substrate 310 .
- pre-form PFET gate stack 301 b can be formed over source/drain areas 311 in substrate 300 , where source/drain areas 311 comprise, for example, portions of substrate 310 doped appropriately to match design requirements for PFET gate stack 301 b , as known in the art.
- pre-form capacitor terminal stacks 301 a and pre-form PFET gate stack 301 b can comprise the same high-k dielectric segment 330 , dummy-material segment 340 and spacers 350 in cross-section, as shown in FIG. 3A , it should be noted that a patterned length (the unseen 3rd dimension) of each individual stack is not necessarily consistent across all stacks.
- pre-form PFET gate stack 301 b can be configured to exhibit a length substantially the same as its width, resulting in a square-like profile as seen from the top of the wafer, while each pre-form capacitor terminal stack 301 a can, for example, be configured, as with each capacitor terminal stack 101 a in FIG.
- a length of a pre-form capacitor terminal stack can be configured to produce, for example, a correspondingly larger or smaller metal-dielectric interface area (once a gate metal terminal is formed within each stack), and therein a larger or smaller capacitance for a completed integrated MIM capacitor, without significantly changing the FEOL processing steps used to produce, for example, a PFET gate stack. This distinction applies for each device stack described with respect to FIGS. 3B through 3D .
- high-k dielectric segment 330 can be, for example, an approximately 1.5 to 3.0 nm thick segment of a layer of high-k gate dielectric (e.g. a high-k dielectric suitable for forming a PFET gate dielectric) comprising, for example, a metal oxide such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), or the like, and can be formed in layer form by, for example, employing a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or other deposition process as known in the art.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- High-k dielectric segment 330 can be configured to serve, concurrently, both as an insulator for a capacitor terminal and as a gate dielectric for a high-k metal gate PFET, or it can be configured to serve similarly for multiple embodiments of each.
- Dummy-material segment 340 can be, for example, a segment of a layer of polysilicon, or some other material suitable for later removal without significantly altering a then-existing height, width, length, spacing or profile of high-k dielectric segment 330 , spacers 350 , or etch-stop filler 360 .
- Such layer can be configured to exhibit a vertical thickness equal to or greater than the desired height of, for example, either a capacitor terminal or a PFET metal gate, and can be formed over a layer of high-k dielectric (e.g., a high-k dielectric used to form high-k dielectric segment 330 ) by, for example, employing a low pressure chemical vapor deposition (LPCVD) process or other suitable deposition process as known in the art.
- LPCVD low pressure chemical vapor deposition
- Such layer can then be patterned, along with any layers formed under or over it, into, for example, dummy-material segment 340 using, for example, a conventional mask and etch process as known in the art.
- Dummy-material segment 340 can be configured to serve as a removable placeholder for gate metal terminal 370 as described further below with respect to FIGS. 3B through 3D .
- Spacers 350 can comprise silicon oxide or other dielectric material as known in the art, and can be formed, for example, by conformally depositing a layer of dielectric material, such as silicon oxide, over high-k dielectric segment 330 and dummy-material segment 340 , or multiple embodiments thereof, by employing a CVD process or other deposition process and then appropriately etching the layer of dielectric material in an etch-back process as known in the art. As shown in FIG. 3A , spacers 350 can be formed around high-k dielectric segment 330 and dummy-material segment 340 to form, for example, semiconductor device stacks such as pre-form capacitor terminal stacks 301 a and pre-form PFET gate stack 301 b , or multiple embodiments of each.
- Etch-stop filler 360 can comprise a nitride material or other dielectric material suitable for discouraging removal of material other than dummy-material segment 340 during a dummy-material replacement process as is described more fully below, and can be formed, for example, by conformally depositing a layer of material, such as a nitride material, over pre-form capacitor terminal stacks 301 a and pre-form PFET gate stack 301 b by employing a CVD process or other deposition process as known in the art.
- Spacers 350 and etch-stop filler 360 can be configured to form a capacitor dielectric for a MIM capacitor structure, as explained above with spacers 150 and etch-stop filler 160 with respect to MIM capacitor structure 100 in FIG. 1 .
- Spacers 350 and etch-stop filler 360 can also be configured, concurrently, to protect substrate 310 (including source/drain regions 311 ) and isolation region 320 during, for example, a dummy-material replacement process used to remove dummy-material segment 340 from each pre-form capacitor terminal stack 301 a and pre-form PFET gate stack 301 b , as described below.
- step 202 of flowchart 200 comprises performing a chemical-mechanical planarization (CMP) step to accurately and concurrently shape dummy-material segment 340 in each pre-form capacitor terminal stack 302 a and pre-form PFET gate stack 302 b in preparation of replacing dummy-material segment 340 with gate metal.
- FIG. 3B shows the structure in FIG. 3A after completion of step 202 of flowchart 200 in FIG. 2 , where each dummy-material segment 340 , each spacer 350 , and etch-stop filler 360 can be concurrently planarized using a CMP process as known in the art.
- Such CMP step can be used, for example, to remove portions of etch-stop filler 360 , dummy-material segment 340 , and spacers 350 to expose a surface of dummy-material segment 340 sufficient to enable, for example, removing dummy-material segment 340 without significantly altering the height, width, length, spacing or profile of high-k dielectric segment 330 , spacers 350 , or etch-stop filler 360 .
- FIG. 3C shows the structure in FIG. 3B after completion of step 203 of flowchart 200 in FIG. 2 , which comprises removing each dummy-material segment 340 from pre-form capacitor terminal stacks 302 a and pre-form PFET gate stack 302 b , which can result in empty spaces 341 in pre-form capacitor terminal stacks 303 a and pre-form PFET gate stack 303 b . Removal of dummy-material segment 340 of FIG.
- 3B can be accomplished by a removal process tailored to dummy-material segment 340 and etch-stop filler 360 , as well as to spacers 350 and high-k dielectric segment 330 , comprising, for example, a conventional etch process as known in the art, and can result in removal of dummy-material segment 340 without significantly altering the height, width, length, spacing or profile of high-k dielectric segment 330 , spacers 350 , or etch-stop filler 360 , leaving empty spaces 341 as shown in FIG. 3C .
- step 204 of flowchart 200 comprises forming gate metal terminals 370 in empty spaces 341 of FIG. 3C by depositing gate metal over the structure of FIG. 3C (thereby completing a dummy-material replacement process) and then cleaning and shaping the resulting surface with a final CMP step.
- FIG. 3D shows the structure in FIG. 3C after completion of step 204 of flowchart 200 in FIG. 2 , where empty spaces 341 of FIG. 3C can be filled with, for example, gate metal, and the overall structure surface planarized to form, for example, gate metal terminals 370 , which can result in capacitor terminal stacks 304 a and PFET gate stack 304 b .
- Capacitor terminal stacks 304 a can be configured to form a MIM capacitor structure similar to MIM capacitor structure 100 in FIGS. 1A and 1B (using, for example, tungsten metal contacts such as contacts 180 shown in FIG. 1A ), and PFET gate stack 304 b can be configured to form a gate for a PFET transistor.
- gate metal terminal 370 can be, for example, an approximately 5 to 10 nm thick segment of gate metal comprising, for example, molybdenum (Mo), ruthenium (Ru), tantalum carbide nitride (TaCN), or other gate metal suitable for utilization in a PFET gate, and can be formed over high-k dielectric segment 330 by, for example, employing a PVD process, a CVD process, or other deposition process as known in the art, which can then be followed by, for example, a CMP step to clean any residual gate metal from the surface of etch-stop filler 360 or spacers 150 and to shape gate metal terminal 370 , etch-stop layer 360 , and spacers 350 according to a common desired height for capacitor terminal stacks 304 a and PFET gate stack 304 b .
- Gate metal terminal 370 can be configured to serve as a capacitor terminal within capacitor terminal stacks 304 a , and
- FIG. 3D can use three capacitor terminal stacks 304 a to form a comb-like MIM capacitor structure similar to that depicted in FIG. 1A
- other embodiments of the present invention can comprise only two capacitor terminal stacks (comprising, for example, one positive terminal and one negative terminal), or can comprise many multiple capacitor terminal stacks, or many multiple MIM capacitor structures connected in series or parallel, where each design is limited only by available wafer size and available fabrication techniques.
- capacitor terminal stack 304 a may be characterized as a PFET gate stack 304 b such that gate metal terminal 370 of capacitor terminal stack 304 a (i.e. the capacitor terminal of capacitor terminal stack 304 a ) can comprise the same gate metal as the metal gate in PFET gate stack 304 b .
- the process for forming capacitor terminal stack 304 a can be suitably modified to correspond to an NFET gate stack process (not explicitly shown by the present figures).
- the capacitor terminal of capacitor terminal stack 304 a can comprise the same gate metal as a metal gate in an NFET gate stack (also not explicitly shown by the present figures).
- FIGS. 4A and 4B illustrate a high density MIM capacitor structure 400 similar to MIM capacitor structure 100 in FIGS. 1A and 1B , but where metal contact bars 490 , formed in etch-stop filler 460 , are configured to significantly increase a metal-dielectric interface area of high density MIM capacitor structure 400 with respect to MIM capacitor structure 100 , thereby significantly increasing the capacitance of high density MIM capacitor structure 400 without significantly increasing die area usage.
- MIM capacitor structure 400 includes substrate 410 , isolation region 420 , etch-stop filler 460 and multiple capacitor terminal stacks 401 a comprising high-k dielectric segment 430 , gate metal terminals 470 and spacers 450 , corresponding respectively to substrate 310 , isolation region 320 , etch-stop filler 360 and multiple capacitor terminal stacks comprising high-k dielectric 330 , gate metal terminal 370 and spacers 350 , in FIG. 3D .
- Each feature can comprise the same material as its counterpart, and each can be formed utilizing the same methods used to form its counterpart, for example.
- Metal contact bars 490 can comprise, for example, tungsten or some other metal used, for example, to form contacts 480 , and can be formed by, for example, first employing a conventional mask and etch process as known in the art to form trenches in, for example, etch-stop filler 460 , and then using a conventional contact formation process as known in the art to form contact bars 490 substantially concurrently with contacts 480 .
- metal contact bars 490 can be configured to significantly increase the available metal-dielectric interface area, and can also be configured to serve as a contact surface to facilitate later integration into analog and mixed signal semiconductor circuits such as integrated circuits (ICs) containing multiple NFETs, PFETs, integrated resistors, integrated inductors and integrated MIM capacitors formed according to the present inventive concepts.
- ICs integrated circuits
- the process for forming an embodiment of the disclosed integrated MIM capacitor structure is compatible with multiple high-k metal gate processes for advanced process technologies, such as 45 nm and smaller process technologies. Consequently, by forming at least one integrated MIM capacitor in at least one region of a substrate while concurrently forming at least one PFET or NFET gate stack in another region of a substrate, an embodiment of the present invention can advantageously form an integrated MIM capacitor without requiring additional masks or process steps beyond those required to form the PFET or NFET gate stacks.
- an embodiment of the present invention's integrated MIM capacitor can be fabricated more precisely than a conventional MIM capacitor, and can therefore exhibit a smaller overall size for a given desired capacitance because its metal terminals can be formed closer together than when using conventional BEOL techniques. Accordingly, the present invention can produce a more reliable and more accurate integrated MIM capacitor than a conventional integrated MIM capacitor fabricated using BEOL processing techniques.
- embodiments of the present invention provide an integrated MIM capacitor that uses a gate dielectric material, such as a high-k gate dielectric material, as an insulating material and a gate metal for a metal terminal.
- a gate dielectric material such as a high-k gate dielectric material
- an integrated MIM capacitor according to the present inventive concepts can be advantageously formed substantially concurrently with formation of PFET or NFET gate stacks without requiring additional masks or process steps beyond those required to form PFET or NFET gate stacks.
- embodiments of the present invention provide an integrated MIM capacitor that can be fabricated at a significantly lower cost compared to a conventional MIM capacitor, as is described above.
- embodiments of the present invention provide a reliable, accurate, scalable integrated MIM capacitor that can increase flexibility in the design of semiconductor circuits which can lead, for example, to overall advantageous reductions in device size and complexity.
Abstract
Description
- This application is a continuation of U.S. application Ser. No. 12/660,619 filed Mar. 1, 2010, the entire content of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention is generally in the field of semiconductors. More particularly, the present invention is in the field of capacitor fabrication in semiconductor dies.
- 2. Background Art
- Integrated capacitors comprise a fundamental building block of integrated analog and mixed signal circuits fabricated on semiconductor dies. Metal-insulator-metal (MIM) type capacitors are particularly desired in the field because, for example, they exhibit a substantially linear response to an applied voltage and because they are relatively insensitive to temperature fluctuations. Conventional integrated MIM capacitors are typically fabricated during back end of the line (BEOL) processing because, historically, metal has not been a conventional constituent of other semiconductor device processing steps.
- A conventional MIM capacitor can be fabricated, for example, by forming a dielectric layer for a MIM capacitor dielectric between metal layers for lower and upper MIM capacitor electrodes in the otherwise unused “vertical” space available over a semiconductor die during BEOL processing. However, forming the dielectric and metal layers during BEOL processing can require multiple process steps and masks, which can undesirably increase manufacturing cost.
- In addition, BEOL processing significantly lags state-of-the-art size reduction techniques, and so as other design processes scale down, BEOL processing increasingly fails to produce detailed device structures as small as desired or as precisely as desired. As a result, BEOL fabricated MIM capacitors have relatively poor reliability, accuracy and density statistics.
- Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing an integrated capacitor that leverages high resolution processing techniques while minimizing the number of additional required processing steps.
- A scalable integrated MIM capacitor using gate metal, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
-
FIG. 1A illustrates a top-down view of a portion of a wafer processed according to an embodiment of the invention. -
FIG. 1B illustrates a cross-sectional view of the portion of the wafer shown inFIG. 1A , processed according to an embodiment of the invention. -
FIG. 2 shows a flowchart illustrating steps taken to implement an embodiment of the present invention. -
FIG. 3A illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an initial step in the flowchart inFIG. 2 . -
FIG. 3B illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart inFIG. 2 . -
FIG. 3C illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart inFIG. 2 . -
FIG. 3D illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to a final step in the flowchart inFIG. 2 . -
FIG. 4A illustrates a top-down view of a portion of a wafer processed according to an embodiment of the invention. -
FIG. 4B illustrates a cross-sectional view of the portion of the wafer shown inFIG. 4A , processed according to an embodiment of the invention. - The present invention is directed to a scalable integrated MIM capacitor using gate metal. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.
- The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be understood that unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
- MIM capacitors inherently require metal in their construction. Conventional fabrication techniques typically have not included a metal processing step during a high precision front end of the line (FEOL) series of processing steps, so fabrication of integrated MIM capacitors has typically been relegated to the relatively low precision back end of the line (BEOL) series of processing steps. Such conventionally fabricated MIM capacitors may be relatively large and may have relatively thick segments of capacitor dielectric situated between their metal terminals. Thus, conventional integrated MIM capacitors typically use a large amount of die area for the amount of capacitance they exhibit, add time and cost to device fabrication, are relatively unreliable and inaccurate, and do not scale with advances in FEOL resolution enhancements.
-
FIG. 1A andFIG. 1B illustrate respective top-down and cross-sectional views of an embodiment of the present invention that addresses the above problems.FIGS. 1A and 1B showMIM capacitor structure 100 formed by leveraging FEOL processing techniques originally developed to fabricate high dielectric constant (high-k) metal gate transistors (e.g., P type or N type field effect transistors—PFETs or NFETs) and other CMOS devices. -
MIM capacitor structure 100 can comprise a series of gate metal terminals laterally separated from each other by a filler, wherein each element ofMIM capacitor structure 100 can be formed during a high-k metal gate device fabrication process. As shown inFIG. 1B ,MIM capacitor structure 100 comprisessubstrate 110,isolation region 120, multiple capacitor terminal stacks 101 a, and etch-stop filler 160. Individualcapacitor terminal stacks 101 a can comprise high-kdielectric segment 130,gate metal terminal 170, andspacers 150. Composition and formation details of the above elements are more fully described with respect toFIGS. 2 and 3A through 3D below. -
Substrate 110 can be configured to supportisolation region 120 as well as other semiconductor devices as is shown inFIGS. 3A through 3D .Isolation region 120 can be configured to electrically isolate capacitor terminal stacks 101 a fromsubstrate 110. - Within each individual
capacitor terminal stack 101 a, high-k dielectric segment 130 can be configured to serve, among other things, to further electrically isolategate metal terminal 170. Also within each individualcapacitor terminal stack 101 a,gate metal terminal 170 can be configured to serve, among other things, as a capacitor terminal within each capacitor terminal stack 100 a.Spacers 150 and etch-stop filler 160 can be configured to form a capacitor dielectric, thereby, for example, completingMIM capacitor structure 100. - Individual capacitor terminal stacks 101 a can be configured to act as positive or negative capacitor terminals by, for example, using conventional techniques to form
contacts 180.Contacts 180 may comprise, for example, tungsten, formed over an end of eachcapacitor terminal stack 101 a corresponding to either a positive or negative lead, thereby facilitating later integration into analog and mixed signal semiconductor circuits. One example of such a configuration can result in a comb-like capacitive structure as is shown in the top-down view ofFIG. 1A . The capacitance of a completed integrated capacitor such asMIM capacitor structure 100 can roughly depend on the height, width, length, spacing and profile ofgate metal terminals 170,spacers 150 and etch-stop filler 160, as well as which ofgate metal terminals 170 in a particular MIM capacitor structure, such asMIM capacitor structure 100, are configured as positive or negative. - The height, width, length, spacing and profile of
gate metal terminals 170,spacers 150 and etch-stop filler 160 can all be controlled by high precision FEOL processing techniques, which means thatMIM capacitor structure 100 can scale with available FEOL processing technology. As a result,MIM capacitor structure 100 can be configured to exhibit a smaller overall size as well as a thinner dielectric segment than conventional MIM capacitors fabricated during BEOL processing. Accordingly,MIM capacitor structure 100 can exhibit a relatively large capacitance for the amount of die area it uses because its terminals can be formed relatively closely to one another, can exhibit better reliability and accuracy statistics due to the relatively greater precision and consistency of FEOL processing techniques, and can reduce overall time and cost of device fabrication by utilizing a process that can form high-k metal gate PFETs and other CMOS devices substantially concurrently withMIM capacitor structure 100. -
FIG. 2 shows a flow chart illustrating a method for fabricating an integrated capacitor in a semiconductor die, according to an embodiment of the present invention. Certain details and features have been left out offlowchart 200 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art.Steps 201 through 204 indicated inflowchart 200 are sufficient to describe one embodiment of the present invention; however, other embodiments of the invention may make use of steps different from those shown inflowchart 200. - Moreover,
FIGS. 3A through 3D illustrate the result of performingsteps 201 through 204 offlowchart 200, respectively. For example,FIG. 3A shows a semiconductor structure after processingstep 201,FIG. 3B shows the structure inFIG. 3A after processingstep 202,FIG. 3C shows the structure inFIG. 3B after processingstep 203, and so forth. - It is noted that the processing steps shown in
flowchart 200 are performed on a portion of a processed wafer, which, prior to step 201, may include, among other things, a substrate, such as a silicon substrate, isolation regions, such as STI regions, and partially formed high-k metal gate transistor gate stacks, such as pre-form PFET gate stacks, all formed in the substrate using conventional techniques. The wafer is also referred to simply as a wafer or a semiconductor die or simply a die in the present application. It is also noted thatsubstrate 310,isolation region 320, high-k dielectric 330,gate metal terminal 370,spacers 350 and etch-stop filler 360 inFIGS. 3A through 3D correspond respectively tosubstrate 110,isolation region 120, high-k dielectric 130,gate metal terminal 170,spacers 150 and etch-stop filler 160 discussed with respect toFIGS. 1A and 1B above, e.g., each corresponding feature can comprise the same material as its counterpart, and each can be formed utilizing the same methods used to form its counterpart. - Referring now to step 201 of the method embodied in
FIG. 2 , step 201 offlowchart 200 comprises forming a filler layer over, for example, a series of partially formed high-k metal gate transistor stacks.FIG. 3A shows astructure including substrate 310,isolation region 320, pre-form capacitor terminal stacks 301 a and pre-formPFET gate stack 301 b after completion ofstep 201 offlowchart 200 inFIG. 2 , where etch-stop filler 360 can be formed over pre-form capacitor terminal stacks 301 a and pre-formPFET gate stack 301 b. - As depicted in
FIG. 3A ,substrate 310 can comprise, for example, silicon, and can be configured to support formation ofisolation region 320, pre-formPFET gate stack 301 b, and gate/source regions 311, or other semiconductor structures or multiple embodiments of any of the above.Isolation region 320 can be a shallow trench isolation (STI) region comprised of silicon oxide or other dielectric material, for example, and can be configured to electrically isolate semiconductor structures (e.g., pre-form capacitor terminal stacks 301 a) fromsubstrate 310. - Pre-form capacitor terminal stacks 301 a and pre-form
PFET gate stack 301 b can each comprise, for example, high-k dielectric segment 330,spacers 350, and dummy-material segment 340. As shown inFIG. 3A , pre-form capacitor terminal stacks 301 a can be formed, for example, overisolation region 320 insubstrate 310. Also as shown inFIG. 3A , pre-formPFET gate stack 301 b can be formed over source/drain areas 311 in substrate 300, where source/drain areas 311 comprise, for example, portions ofsubstrate 310 doped appropriately to match design requirements forPFET gate stack 301 b, as known in the art. - While both pre-form capacitor terminal stacks 301 a and pre-form
PFET gate stack 301 b can comprise the same high-k dielectric segment 330, dummy-material segment 340 andspacers 350 in cross-section, as shown inFIG. 3A , it should be noted that a patterned length (the unseen 3rd dimension) of each individual stack is not necessarily consistent across all stacks. For example, pre-formPFET gate stack 301 b can be configured to exhibit a length substantially the same as its width, resulting in a square-like profile as seen from the top of the wafer, while each pre-formcapacitor terminal stack 301 a can, for example, be configured, as with eachcapacitor terminal stack 101 a inFIG. 1 , to have a length that is longer than its width, resulting in, for example, a comb-like shape similar to the top-down view ofMIM capacitor structure 100 inFIG. 1A . A length of a pre-form capacitor terminal stack can be configured to produce, for example, a correspondingly larger or smaller metal-dielectric interface area (once a gate metal terminal is formed within each stack), and therein a larger or smaller capacitance for a completed integrated MIM capacitor, without significantly changing the FEOL processing steps used to produce, for example, a PFET gate stack. This distinction applies for each device stack described with respect toFIGS. 3B through 3D . - Within each device stack, high-
k dielectric segment 330 can be, for example, an approximately 1.5 to 3.0 nm thick segment of a layer of high-k gate dielectric (e.g. a high-k dielectric suitable for forming a PFET gate dielectric) comprising, for example, a metal oxide such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or the like, and can be formed in layer form by, for example, employing a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or other deposition process as known in the art. Such layer can then be patterned, along with any layers formed over or under it, into, for example, high-k dielectric segment 330 using, for example, a conventional mask and etch process as known in the art. High-k dielectric segment 330 can be configured to serve, concurrently, both as an insulator for a capacitor terminal and as a gate dielectric for a high-k metal gate PFET, or it can be configured to serve similarly for multiple embodiments of each. - Dummy-
material segment 340 can be, for example, a segment of a layer of polysilicon, or some other material suitable for later removal without significantly altering a then-existing height, width, length, spacing or profile of high-k dielectric segment 330,spacers 350, or etch-stop filler 360. Such layer can be configured to exhibit a vertical thickness equal to or greater than the desired height of, for example, either a capacitor terminal or a PFET metal gate, and can be formed over a layer of high-k dielectric (e.g., a high-k dielectric used to form high-k dielectric segment 330) by, for example, employing a low pressure chemical vapor deposition (LPCVD) process or other suitable deposition process as known in the art. Such layer can then be patterned, along with any layers formed under or over it, into, for example, dummy-material segment 340 using, for example, a conventional mask and etch process as known in the art. Dummy-material segment 340 can be configured to serve as a removable placeholder forgate metal terminal 370 as described further below with respect toFIGS. 3B through 3D . -
Spacers 350 can comprise silicon oxide or other dielectric material as known in the art, and can be formed, for example, by conformally depositing a layer of dielectric material, such as silicon oxide, over high-k dielectric segment 330 and dummy-material segment 340, or multiple embodiments thereof, by employing a CVD process or other deposition process and then appropriately etching the layer of dielectric material in an etch-back process as known in the art. As shown inFIG. 3A , spacers 350 can be formed around high-k dielectric segment 330 and dummy-material segment 340 to form, for example, semiconductor device stacks such as pre-form capacitor terminal stacks 301 a and pre-formPFET gate stack 301 b, or multiple embodiments of each. - Etch-
stop filler 360 can comprise a nitride material or other dielectric material suitable for discouraging removal of material other than dummy-material segment 340 during a dummy-material replacement process as is described more fully below, and can be formed, for example, by conformally depositing a layer of material, such as a nitride material, over pre-form capacitor terminal stacks 301 a and pre-formPFET gate stack 301 b by employing a CVD process or other deposition process as known in the art. -
Spacers 350 and etch-stop filler 360 can be configured to form a capacitor dielectric for a MIM capacitor structure, as explained above withspacers 150 and etch-stop filler 160 with respect toMIM capacitor structure 100 inFIG. 1 .Spacers 350 and etch-stop filler 360 can also be configured, concurrently, to protect substrate 310 (including source/drain regions 311) andisolation region 320 during, for example, a dummy-material replacement process used to remove dummy-material segment 340 from each pre-formcapacitor terminal stack 301 a and pre-formPFET gate stack 301 b, as described below. - Continuing with
step 202 inFIG. 2 and referring toFIG. 3B , step 202 offlowchart 200 comprises performing a chemical-mechanical planarization (CMP) step to accurately and concurrently shape dummy-material segment 340 in each pre-formcapacitor terminal stack 302 a and pre-formPFET gate stack 302 b in preparation of replacing dummy-material segment 340 with gate metal.FIG. 3B shows the structure inFIG. 3A after completion ofstep 202 offlowchart 200 inFIG. 2 , where each dummy-material segment 340, eachspacer 350, and etch-stop filler 360 can be concurrently planarized using a CMP process as known in the art. Such CMP step can be used, for example, to remove portions of etch-stop filler 360, dummy-material segment 340, andspacers 350 to expose a surface of dummy-material segment 340 sufficient to enable, for example, removing dummy-material segment 340 without significantly altering the height, width, length, spacing or profile of high-k dielectric segment 330,spacers 350, or etch-stop filler 360. -
FIG. 3C shows the structure inFIG. 3B after completion ofstep 203 offlowchart 200 inFIG. 2 , which comprises removing each dummy-material segment 340 from pre-form capacitor terminal stacks 302 a and pre-formPFET gate stack 302 b, which can result inempty spaces 341 in pre-form capacitor terminal stacks 303 a and pre-formPFET gate stack 303 b. Removal of dummy-material segment 340 ofFIG. 3B can be accomplished by a removal process tailored to dummy-material segment 340 and etch-stop filler 360, as well as to spacers 350 and high-k dielectric segment 330, comprising, for example, a conventional etch process as known in the art, and can result in removal of dummy-material segment 340 without significantly altering the height, width, length, spacing or profile of high-k dielectric segment 330,spacers 350, or etch-stop filler 360, leavingempty spaces 341 as shown inFIG. 3C . - Moving now to step 204 of
FIG. 2 and referring toFIG. 3D , step 204 offlowchart 200 comprises forminggate metal terminals 370 inempty spaces 341 ofFIG. 3C by depositing gate metal over the structure ofFIG. 3C (thereby completing a dummy-material replacement process) and then cleaning and shaping the resulting surface with a final CMP step.FIG. 3D shows the structure inFIG. 3C after completion ofstep 204 offlowchart 200 inFIG. 2 , whereempty spaces 341 ofFIG. 3C can be filled with, for example, gate metal, and the overall structure surface planarized to form, for example,gate metal terminals 370, which can result in capacitor terminal stacks 304 a andPFET gate stack 304 b. Capacitor terminal stacks 304 a can be configured to form a MIM capacitor structure similar toMIM capacitor structure 100 inFIGS. 1A and 1B (using, for example, tungsten metal contacts such ascontacts 180 shown inFIG. 1A ), andPFET gate stack 304 b can be configured to form a gate for a PFET transistor. - Within each
capacitor terminal stack 304 a andPFET gate stack 304 b,gate metal terminal 370 can be, for example, an approximately 5 to 10 nm thick segment of gate metal comprising, for example, molybdenum (Mo), ruthenium (Ru), tantalum carbide nitride (TaCN), or other gate metal suitable for utilization in a PFET gate, and can be formed over high-k dielectric segment 330 by, for example, employing a PVD process, a CVD process, or other deposition process as known in the art, which can then be followed by, for example, a CMP step to clean any residual gate metal from the surface of etch-stop filler 360 orspacers 150 and to shapegate metal terminal 370, etch-stop layer 360, andspacers 350 according to a common desired height for capacitor terminal stacks 304 a andPFET gate stack 304 b.Gate metal terminal 370 can be configured to serve as a capacitor terminal within capacitor terminal stacks 304 a, and, concurrently, a metal gate withinPFET gate stack 304 b, or configured to serve similarly within multiple embodiments for each. - While the embodiment in
FIG. 3D can use three capacitor terminal stacks 304 a to form a comb-like MIM capacitor structure similar to that depicted inFIG. 1A , other embodiments of the present invention can comprise only two capacitor terminal stacks (comprising, for example, one positive terminal and one negative terminal), or can comprise many multiple capacitor terminal stacks, or many multiple MIM capacitor structures connected in series or parallel, where each design is limited only by available wafer size and available fabrication techniques. - It is noted that in the embodiment shown in
FIGS. 3A through 3D ,capacitor terminal stack 304 a may be characterized as aPFET gate stack 304 b such thatgate metal terminal 370 ofcapacitor terminal stack 304 a (i.e. the capacitor terminal ofcapacitor terminal stack 304 a) can comprise the same gate metal as the metal gate inPFET gate stack 304 b. However, in another embodiment, the process for formingcapacitor terminal stack 304 a can be suitably modified to correspond to an NFET gate stack process (not explicitly shown by the present figures). Thus, in that latter embodiment, the capacitor terminal ofcapacitor terminal stack 304 a can comprise the same gate metal as a metal gate in an NFET gate stack (also not explicitly shown by the present figures). - Another embodiment of the present invention is shown in
FIGS. 4A and 4B .FIGS. 4A and 4B illustrate a high densityMIM capacitor structure 400 similar toMIM capacitor structure 100 inFIGS. 1A and 1B , but where metal contact bars 490, formed in etch-stop filler 460, are configured to significantly increase a metal-dielectric interface area of high densityMIM capacitor structure 400 with respect toMIM capacitor structure 100, thereby significantly increasing the capacitance of high densityMIM capacitor structure 400 without significantly increasing die area usage. - In addition to metal contact bars 490,
MIM capacitor structure 400 includessubstrate 410,isolation region 420, etch-stop filler 460 and multiple capacitor terminal stacks 401 a comprising high-k dielectric segment 430,gate metal terminals 470 andspacers 450, corresponding respectively tosubstrate 310,isolation region 320, etch-stop filler 360 and multiple capacitor terminal stacks comprising high-k dielectric 330,gate metal terminal 370 andspacers 350, inFIG. 3D . Each feature can comprise the same material as its counterpart, and each can be formed utilizing the same methods used to form its counterpart, for example. - Metal contact bars 490 can comprise, for example, tungsten or some other metal used, for example, to form
contacts 480, and can be formed by, for example, first employing a conventional mask and etch process as known in the art to form trenches in, for example, etch-stop filler 460, and then using a conventional contact formation process as known in the art to form contact bars 490 substantially concurrently withcontacts 480. As explained above, metal contact bars 490 can be configured to significantly increase the available metal-dielectric interface area, and can also be configured to serve as a contact surface to facilitate later integration into analog and mixed signal semiconductor circuits such as integrated circuits (ICs) containing multiple NFETs, PFETs, integrated resistors, integrated inductors and integrated MIM capacitors formed according to the present inventive concepts. - Thus, by using a high-k gate dielectric material as an insulating material and a gate metal as a capacitor terminal, the process for forming an embodiment of the disclosed integrated MIM capacitor structure is compatible with multiple high-k metal gate processes for advanced process technologies, such as 45 nm and smaller process technologies. Consequently, by forming at least one integrated MIM capacitor in at least one region of a substrate while concurrently forming at least one PFET or NFET gate stack in another region of a substrate, an embodiment of the present invention can advantageously form an integrated MIM capacitor without requiring additional masks or process steps beyond those required to form the PFET or NFET gate stacks.
- In addition, by utilizing FEOL process technology, such as the multiple high-k metal gate processes above, an embodiment of the present invention's integrated MIM capacitor can be fabricated more precisely than a conventional MIM capacitor, and can therefore exhibit a smaller overall size for a given desired capacitance because its metal terminals can be formed closer together than when using conventional BEOL techniques. Accordingly, the present invention can produce a more reliable and more accurate integrated MIM capacitor than a conventional integrated MIM capacitor fabricated using BEOL processing techniques.
- As described above, embodiments of the present invention provide an integrated MIM capacitor that uses a gate dielectric material, such as a high-k gate dielectric material, as an insulating material and a gate metal for a metal terminal. As such, an integrated MIM capacitor according to the present inventive concepts can be advantageously formed substantially concurrently with formation of PFET or NFET gate stacks without requiring additional masks or process steps beyond those required to form PFET or NFET gate stacks. By requiring no additional processing steps, or, in the case of a high density version of the present invention, potentially requiring only a single additional mask and etch step, embodiments of the present invention provide an integrated MIM capacitor that can be fabricated at a significantly lower cost compared to a conventional MIM capacitor, as is described above. Additionally, because the present inventive concepts disclose an integrated MIM capacitor fabricated using FEOL processing technology, embodiments of the present invention provide a reliable, accurate, scalable integrated MIM capacitor that can increase flexibility in the design of semiconductor circuits which can lead, for example, to overall advantageous reductions in device size and complexity.
- From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would appreciate that changes can be made in form and detail without departing from the spirit and the scope of the invention. Thus, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
Claims (22)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/578,924 US20150108558A1 (en) | 2010-03-01 | 2014-12-22 | Scalable integrated mim capacitor using gate metal |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/660,619 US8963223B2 (en) | 2010-03-01 | 2010-03-01 | Scalable integrated MIM capacitor using gate metal |
US14/578,924 US20150108558A1 (en) | 2010-03-01 | 2014-12-22 | Scalable integrated mim capacitor using gate metal |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/660,619 Continuation US8963223B2 (en) | 2010-03-01 | 2010-03-01 | Scalable integrated MIM capacitor using gate metal |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150108558A1 true US20150108558A1 (en) | 2015-04-23 |
Family
ID=44504840
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/660,619 Active 2032-04-15 US8963223B2 (en) | 2010-03-01 | 2010-03-01 | Scalable integrated MIM capacitor using gate metal |
US14/578,924 Abandoned US20150108558A1 (en) | 2010-03-01 | 2014-12-22 | Scalable integrated mim capacitor using gate metal |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/660,619 Active 2032-04-15 US8963223B2 (en) | 2010-03-01 | 2010-03-01 | Scalable integrated MIM capacitor using gate metal |
Country Status (1)
Country | Link |
---|---|
US (2) | US8963223B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11115438B2 (en) | 2013-09-20 | 2021-09-07 | Open Text Sa Ulc | System and method for geofencing |
US11388037B2 (en) | 2016-02-25 | 2022-07-12 | Open Text Sa Ulc | Systems and methods for providing managed services |
US11593075B2 (en) | 2015-11-03 | 2023-02-28 | Open Text Sa Ulc | Streamlined fast and efficient application building and customization systems and methods |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9184214B2 (en) * | 2011-04-11 | 2015-11-10 | Globalfoundries Inc. | Semiconductor device exhibiting reduced parasitics and method for making same |
US9029983B2 (en) | 2013-03-12 | 2015-05-12 | Qualcomm Incorporated | Metal-insulator-metal (MIM) capacitor |
US9969613B2 (en) | 2013-04-12 | 2018-05-15 | International Business Machines Corporation | Method for forming micro-electro-mechanical system (MEMS) beam structure |
US9337188B2 (en) * | 2013-10-22 | 2016-05-10 | Broadcom Corporation | Metal-insulator-metal capacitor structure |
US20160027772A1 (en) * | 2014-07-22 | 2016-01-28 | Mediatek Inc. | Integrated capacitor in an integrated circuit |
US9478490B2 (en) | 2014-09-10 | 2016-10-25 | Qualcomm Incorporated | Capacitor from second level middle-of-line layer in combination with decoupling capacitors |
US20160197071A1 (en) * | 2015-01-06 | 2016-07-07 | Mediatek Inc. | Integrated circuit device and method for forming the same |
US10312318B2 (en) | 2015-09-22 | 2019-06-04 | International Business Machines Corporation | Metal-insulator-metal capacitor structure |
US9893145B1 (en) | 2016-08-09 | 2018-02-13 | International Business Machines Corporation | On chip MIM capacitor |
US10770454B2 (en) | 2018-04-09 | 2020-09-08 | Globalfoundries Inc. | On-chip metal-insulator-metal (MIM) capacitor and methods and systems for forming same |
US10868108B2 (en) * | 2018-06-27 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having high voltage lateral capacitor and manufacturing method thereof |
EP3850665B1 (en) | 2019-01-30 | 2023-11-15 | Yangtze Memory Technologies Co., Ltd. | Capacitor structure having vertical diffusion plates |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040175909A1 (en) * | 2003-03-05 | 2004-09-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20080173978A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | MIM capacitor and metal gate transistor |
US20090090951A1 (en) * | 2007-10-08 | 2009-04-09 | Chung-Long Chang | Capacitors Integrated with Metal Gate Formation |
US20100001332A1 (en) * | 2008-07-03 | 2010-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a capacitor in a metal gate last process |
US20100078695A1 (en) * | 2008-09-30 | 2010-04-01 | Law Oscar M K | Low Leakage Capacitors Including Portions in Inter-Layer Dielectrics |
US20100163949A1 (en) * | 2008-12-29 | 2010-07-01 | International Business Machines Corporation | Vertical metal-insulator-metal (mim) capacitor using gate stack, gate spacer and contact via |
US20110031585A1 (en) * | 2009-08-07 | 2011-02-10 | Broadcom Corporation | Method for fabricating a MIM capacitor using gate metal for electrode and related structure |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3638778B2 (en) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device and manufacturing method thereof |
KR100272166B1 (en) * | 1998-06-30 | 2000-11-15 | 윤종용 | Semiconductor device having dummy conductive layer formed on isolation regio and manufacturing method thereof |
EP1071130A3 (en) * | 1999-07-14 | 2005-09-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device interconnection structure comprising additional capacitors |
JP2005026586A (en) * | 2003-07-04 | 2005-01-27 | Semiconductor Leading Edge Technologies Inc | Semiconductor device and its manufacturing method |
KR100705937B1 (en) * | 2003-12-19 | 2007-04-11 | 에스티마이크로일렉트로닉스 엔.브이. | Semiconductor device having the structure of a pad for preventing and buffering the stress of a barrier nitride |
JP4671614B2 (en) * | 2004-03-03 | 2011-04-20 | パナソニック株式会社 | Semiconductor device |
US7271083B2 (en) * | 2004-07-22 | 2007-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | One-transistor random access memory technology compatible with metal gate process |
JP5114844B2 (en) * | 2005-02-14 | 2013-01-09 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US7189613B2 (en) * | 2005-02-23 | 2007-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for metal-insulator-metal capacitor based memory device |
KR100660720B1 (en) * | 2005-12-29 | 2006-12-21 | 동부일렉트로닉스 주식회사 | Horizontal gate capacitor, and manufacturing method thereof |
-
2010
- 2010-03-01 US US12/660,619 patent/US8963223B2/en active Active
-
2014
- 2014-12-22 US US14/578,924 patent/US20150108558A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040175909A1 (en) * | 2003-03-05 | 2004-09-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20080173978A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | MIM capacitor and metal gate transistor |
US20090090951A1 (en) * | 2007-10-08 | 2009-04-09 | Chung-Long Chang | Capacitors Integrated with Metal Gate Formation |
US20100001332A1 (en) * | 2008-07-03 | 2010-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a capacitor in a metal gate last process |
US20100078695A1 (en) * | 2008-09-30 | 2010-04-01 | Law Oscar M K | Low Leakage Capacitors Including Portions in Inter-Layer Dielectrics |
US20100163949A1 (en) * | 2008-12-29 | 2010-07-01 | International Business Machines Corporation | Vertical metal-insulator-metal (mim) capacitor using gate stack, gate spacer and contact via |
US20110031585A1 (en) * | 2009-08-07 | 2011-02-10 | Broadcom Corporation | Method for fabricating a MIM capacitor using gate metal for electrode and related structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11115438B2 (en) | 2013-09-20 | 2021-09-07 | Open Text Sa Ulc | System and method for geofencing |
US11593075B2 (en) | 2015-11-03 | 2023-02-28 | Open Text Sa Ulc | Streamlined fast and efficient application building and customization systems and methods |
US11388037B2 (en) | 2016-02-25 | 2022-07-12 | Open Text Sa Ulc | Systems and methods for providing managed services |
Also Published As
Publication number | Publication date |
---|---|
US20110210384A1 (en) | 2011-09-01 |
US8963223B2 (en) | 2015-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8963223B2 (en) | Scalable integrated MIM capacitor using gate metal | |
US8614497B2 (en) | Method for fabricating a MIM capacitor using gate metal for electrode and related structure | |
US10460788B2 (en) | Memory cell and methods thereof | |
CN103383933B (en) | Semiconductor device and manufacture method thereof | |
US10985163B2 (en) | Semiconductor capacitor structure | |
US10879133B2 (en) | Replacement metal gate process for CMOS integrated circuits | |
TWI645571B (en) | Memory device and capacitor | |
CN102456750A (en) | Method and apparatus for improving capacitor capacitance and compatibility | |
US20160254345A1 (en) | Metal-insulator-metal capacitor architecture | |
US10256321B2 (en) | Semiconductor device including enhanced low-k spacer | |
US9337188B2 (en) | Metal-insulator-metal capacitor structure | |
US20160268253A1 (en) | Resistor and Metal-Insulator-Metal Capacitor Structure and Method | |
US10886363B2 (en) | Metal-insulator-metal capacitor structure | |
US20220384311A1 (en) | Semiconductor device and method for fabricating the same | |
TWI597818B (en) | Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors | |
US20090059466A1 (en) | Metal-insulator-metal capacitor and method for manufacturing the same | |
US9269761B2 (en) | Metal-insulator-metal capacitor | |
US20110198705A1 (en) | Integrated resistor using gate metal for a resistive element | |
US20180158821A1 (en) | Gate structures with low resistance | |
CN113690237A (en) | Semiconductor device and method of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: BROADCOM CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:XIA, WEI;CHEN, XIANGDONG;REEL/FRAME:034567/0578 Effective date: 20100222 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001 Effective date: 20160201 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001 Effective date: 20170120 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001 Effective date: 20170120 |
|
AS | Assignment |
Owner name: BROADCOM CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041712/0001 Effective date: 20170119 |