US20150103489A1 - Integrated circuit chip comprising electronic device and electronic system - Google Patents
Integrated circuit chip comprising electronic device and electronic system Download PDFInfo
- Publication number
- US20150103489A1 US20150103489A1 US14/512,214 US201414512214A US2015103489A1 US 20150103489 A1 US20150103489 A1 US 20150103489A1 US 201414512214 A US201414512214 A US 201414512214A US 2015103489 A1 US2015103489 A1 US 2015103489A1
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- electrical connection
- substrate wafer
- layer
- connection network
- integrated circuit
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- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000011810 insulating material Substances 0.000 claims abstract description 9
- 239000012530 fluid Substances 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 17
- 230000000295 complement effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 description 4
- 239000013529 heat transfer fluid Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000012809 cooling fluid Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/20—Modifications to facilitate cooling, ventilating, or heating
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Definitions
- the present invention relates to the field of microelectronics.
- Stacking electronic devices in particular has the advantage of improving the performance of electrical connections and of reducing footprint. Nevertheless, in certain cases integrated circuit chips may produce heat and the heat produced may heat other integrated circuit chips and thus degrade the performance of the latter. This is especially the case when a first electronic device comprises a processor chip that produces heat, and a second electronic device stacked on the first comprises a memory chip, the operation of which in particular degrades when its temperature increases.
- an electronic device which comprises a substrate wafer made of an insulating material, which is equipped with an electrical connection network and which bears, on at least one side, at least one integrated circuit chip, and in which the substrate wafer contains at least one internal duct.
- Said internal duct may contain a thermally conductive material.
- Said internal duct may be arranged a distance away from the electrical connection network.
- Said duct may be arranged in the substrate wafer and take the form of a groove, and the substrate wafer may comprise a superficial layer covering this groove.
- the substrate wafer may contain complementary internal ducts connected to said internal duct and connected to means for making a fluid flow.
- the electrical connection network may comprise, on an internal plane, a metal level including electrical connection pads
- the substrate wafer may comprise, on this internal plane, an intermediate layer covered by said superficial layer and in which said groove is arranged, the intermediate layer and said superficial layer containing apertures above electrical connection pads, and said groove lying a distance away from these apertures.
- the depth of said groove may be smaller than the depth of the frontal side of the metal level.
- Said electrical connection network may comprise, in said metal level, electrical connection pads connected to the chip by intermediate electrical connection elements and electrical connection pads located around the chip, and, on the other side of the substrate wafer, electrical connection pads.
- An electronic system which comprises the above electronic device, and which comprises another electronic device placed on said electronic device and comprising another wafer equipped with another electrical connection network connected to said electrical connection network and bearing at least one other integrated circuit chip connected to this other electrical connection network.
- Said system may comprise a printed circuit board bearing said electronic device by way of external metal elements connected to said electrical connection network.
- FIG. 1 shows a cross section of an electronic device
- FIG. 2 shows a top view of the electronic device in FIG. 1 without its superficial layer
- FIG. 3 shows an enlarged partial cross section of the electronic device in FIG. 1 ;
- FIG. 4 shows an electronic system including the electronic device in FIG. 1 .
- an electronic device 1 comprises a substrate wafer 2 made of an insulating material, which wafer 2 is equipped with an integrated metal electrical connection network 3 connecting one side to the other.
- the electrical connection network 3 comprises a metal level M 1 formed on an internal back plane 4 of the substrate wafer 2 and comprising a plurality of electrical connection pads and/or lines 5 comprising a matrix of electrical connection pads 5 a arranged on a central zone of the plane 4 and a matrix of electrical connection pads 5 b arranged on a zone encircling this central zone.
- the substrate wafer 2 comprises an intermediate layer 6 formed on the plane 4 and covering the metal level 5 .
- the substrate wafer 2 contains grooves 7 a extending depthwise from the surface 8 of this layer 6 . These grooves 7 a are formed in locations not passing above electrical connection pads 5 a and 5 b.
- the substrate wafer 2 furthermore comprises a superficial layer 10 formed on the surface 8 of the layer 6 and covering the grooves 7 a so as to provide internal ducts 7 formed in the substrate wafer 2 .
- the internal ducts 7 are filled with a thermally conductive or heat transfer fluid 9 .
- a thermally conductive or heat transfer fluid 9 By way of heat transfer fluid, those sold under the trade mark Galden HT may be used.
- the thermally conductive fluid 9 may be injected, using a syringe, through the superficial layer 10 , a conduit being provided through the superficial layer 10 in order to allow this filling operation to be carried out.
- the hole left by the syringe and this conduit may then be blocked by virtue of beads of adhesive.
- the layer 6 and the superficial layer 10 contain apertures 11 a and 11 b at least partially exposing the electrical connection pads 5 a and 5 b , respectively.
- the electronic device 1 furthermore comprises an integrated circuit chip 12 placed on the substrate wafer 2 on the same side as the superficial layer 10 , and comprises metal electrical connection elements 13 , for example taking the form of columns, engaged in the apertures 11 a and interposed between the chip 12 and the electrical connection pads 5 a so as to connect the chip 12 and the electrical connection network 3 .
- the electronic device 1 also comprises an insulating encapsulation material 14 filling the space between the chip 12 and the substrate wafer 2 .
- the electronic device 1 may comprise a layer 15 made of an insulating material on the frontal side of the substrate wafer 2 and encircling the chip 12 .
- this layer 15 is flush with the frontal back side of the chip 12 .
- apertures are arranged 16 exposing the apertures 11 b of the layers 6 and 10 .
- Electrical connection elements 17 such as bumps may be placed on the electrical connection pads 11 a and in the holes formed by the apertures 11 b and 16 .
- the ducts 7 may be arranged so as to lie between the rows of the matrices of electrical connection pads 5 a and 5 b and peripherally, thereby forming a closed circuit.
- Other arrangements are possible.
- more than one closed-circuit duct could be provided.
- the ducts 7 may be connected to complementary ducts 18 , for example supply/return ducts, arranged in the layer 6 of the substrate wafer 2 , these ducts 18 emerging laterally from the substrate wafer 2 and possibly being connected to external means suitable for making a cooling fluid 9 flow.
- complementary ducts 18 for example supply/return ducts, arranged in the layer 6 of the substrate wafer 2 , these ducts 18 emerging laterally from the substrate wafer 2 and possibly being connected to external means suitable for making a cooling fluid 9 flow.
- the electronic device 1 may be equipped with a component incorporating a micropump, which component may be fixed to one of the sides of the device, for example by bonding, this micropump being connected to the internal ducts 7 , for example at two remote locations, through the superficial layer 10 , in order to make the heat transfer fluid 9 flow through these internal ducts 7 .
- the depth P 1 of the grooves 7 a is smaller than the depth P 2 of the frontal side of the metal level M 1 , such that the grooves 7 a may be arranged so as to pass above electrical connection lines of the metal level M 1 without exposing them.
- the integrated circuit chip 12 may generate heat. At least some of this generated heat may be preferentially captured by the material 9 filling the internal ducts 7 and dispersed to substantially the entire volume of the substrate wafer 2 , i.e. both to the zone of the chip 12 and to the peripheral zone of the latter.
- the thermally conductive material 9 forms a means of capturing and dispersing to the bulk of the substrate wafer 2 , at least some of the heat produced by the chip 12 .
- the electronic device 1 may be included in an electronic system 100 furthermore comprising another electronic device 101 stacked a distance above the electronic device 1 , on the same side as the chip 12 .
- the electronic device 101 may comprise, borne by a wafer 102 made of an insulating material and equipped with an electrical connection network 103 , an integrated circuit chip 104 electrically connected to the electrical connection network 103 by electrical connection wires 105 embedded in the wafer 102 .
- the electronic device 101 is mounted on the electronic device 1 by way of electrical connection elements 106 such as metal bumps, which elements 106 are interposed between said devices, and electrically and selectively connect the electrical connection network 103 of the electronic device 101 to the electrical connection network 3 of the electronic device 1 by being soldered to electrical connection elements 17 placed on the pads 5 b.
- electrical connection elements 106 such as metal bumps, which elements 106 are interposed between said devices, and electrically and selectively connect the electrical connection network 103 of the electronic device 101 to the electrical connection network 3 of the electronic device 1 by being soldered to electrical connection elements 17 placed on the pads 5 b.
- the electronic device 1 and therefore the electronic system 100 are mounted on a printed circuit board 107 by way of electrical connection elements 108 , such as metal bumps, interposed between electrical connection pads 19 of the electrical connection network 3 and electrical connection pads 109 of the printed circuit board 107 .
- electrical connection elements 108 such as metal bumps
- the heat produced by the chip 4 and, as described above, transferred and dispersed to the substrate wafer 2 by virtue of the existence of the ducts 7 and the material 9 that they contain, may be transferred, at least partially, to the printed circuit board 107 by way of the electrical connection elements 108 .
- the electrical connection network 3 of the substrate wafer 2 participates in the transfer of the heat produced by the chip 12 to the printed circuit board 107 .
- the heat produced by the chip 4 also diffuses into the space separating the electronic device 1 and the electronic device 101 , in order to be evacuated toward the exterior.
- the heat produced by the chip 4 may thus be at least partially evacuated by this means.
- the chip 12 is cooled and diffusion of the heat produced by the chip 12 of the electronic device 1 in the direction of the chip 104 of the electronic device 101 is limited in such a way that the chip 104 is protected from any excessive increase in its temperature.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thermal Sciences (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
- This application claims priority from French Application for Patent No. 1360008 filed Oct. 15, 2013, the disclosure of which is incorporated by reference.
- The present invention relates to the field of microelectronics.
- It is known to make electronic systems that comprise electronic devices stacked one on top of the other and electrically connected together, including at least one integrated circuit chip respectively.
- Stacking electronic devices in particular has the advantage of improving the performance of electrical connections and of reducing footprint. Nevertheless, in certain cases integrated circuit chips may produce heat and the heat produced may heat other integrated circuit chips and thus degrade the performance of the latter. This is especially the case when a first electronic device comprises a processor chip that produces heat, and a second electronic device stacked on the first comprises a memory chip, the operation of which in particular degrades when its temperature increases.
- The above circumstances are an obstacle to increasing the performance of said electronic systems, such as in particular the speed at which they run programs. However, the situation that at the present time consists in making a compromise between the performance desired from said electronic systems and their footprint, is unsatisfactory, especially in the field of portable devices such as mobile phones.
- According to one embodiment, an electronic device is provided which comprises a substrate wafer made of an insulating material, which is equipped with an electrical connection network and which bears, on at least one side, at least one integrated circuit chip, and in which the substrate wafer contains at least one internal duct.
- Said internal duct may contain a thermally conductive material.
- Said internal duct may be arranged a distance away from the electrical connection network.
- Said duct may be arranged in the substrate wafer and take the form of a groove, and the substrate wafer may comprise a superficial layer covering this groove.
- The substrate wafer may contain complementary internal ducts connected to said internal duct and connected to means for making a fluid flow.
- The electrical connection network may comprise, on an internal plane, a metal level including electrical connection pads, and the substrate wafer may comprise, on this internal plane, an intermediate layer covered by said superficial layer and in which said groove is arranged, the intermediate layer and said superficial layer containing apertures above electrical connection pads, and said groove lying a distance away from these apertures.
- The depth of said groove may be smaller than the depth of the frontal side of the metal level.
- Said electrical connection network may comprise, in said metal level, electrical connection pads connected to the chip by intermediate electrical connection elements and electrical connection pads located around the chip, and, on the other side of the substrate wafer, electrical connection pads.
- An electronic system is also provided, which comprises the above electronic device, and which comprises another electronic device placed on said electronic device and comprising another wafer equipped with another electrical connection network connected to said electrical connection network and bearing at least one other integrated circuit chip connected to this other electrical connection network.
- Said system may comprise a printed circuit board bearing said electronic device by way of external metal elements connected to said electrical connection network.
- Electronic devices and electronic systems, according to particular embodiments of the present invention, will now be described by way of nonlimiting examples, these devices and systems being illustrated by the drawings, in which:
-
FIG. 1 shows a cross section of an electronic device; -
FIG. 2 shows a top view of the electronic device inFIG. 1 without its superficial layer; -
FIG. 3 shows an enlarged partial cross section of the electronic device inFIG. 1 ; and -
FIG. 4 shows an electronic system including the electronic device inFIG. 1 . - As illustrated in
FIG. 1 , anelectronic device 1 comprises asubstrate wafer 2 made of an insulating material, whichwafer 2 is equipped with an integrated metalelectrical connection network 3 connecting one side to the other. - The
electrical connection network 3 comprises a metal level M1 formed on aninternal back plane 4 of thesubstrate wafer 2 and comprising a plurality of electrical connection pads and/orlines 5 comprising a matrix ofelectrical connection pads 5 a arranged on a central zone of theplane 4 and a matrix ofelectrical connection pads 5 b arranged on a zone encircling this central zone. - The
substrate wafer 2 comprises anintermediate layer 6 formed on theplane 4 and covering themetal level 5. - In the
intermediate layer 6, thesubstrate wafer 2 containsgrooves 7 a extending depthwise from thesurface 8 of thislayer 6. Thesegrooves 7 a are formed in locations not passing aboveelectrical connection pads - The
substrate wafer 2 furthermore comprises asuperficial layer 10 formed on thesurface 8 of thelayer 6 and covering thegrooves 7 a so as to provideinternal ducts 7 formed in thesubstrate wafer 2. - The
internal ducts 7 are filled with a thermally conductive orheat transfer fluid 9. By way of heat transfer fluid, those sold under the trade mark Galden HT may be used. - According to a variant embodiment, the thermally
conductive fluid 9 may be injected, using a syringe, through thesuperficial layer 10, a conduit being provided through thesuperficial layer 10 in order to allow this filling operation to be carried out. The hole left by the syringe and this conduit may then be blocked by virtue of beads of adhesive. - The
layer 6 and thesuperficial layer 10 containapertures electrical connection pads - The
electronic device 1 furthermore comprises anintegrated circuit chip 12 placed on thesubstrate wafer 2 on the same side as thesuperficial layer 10, and comprises metalelectrical connection elements 13, for example taking the form of columns, engaged in theapertures 11 a and interposed between thechip 12 and theelectrical connection pads 5 a so as to connect thechip 12 and theelectrical connection network 3. - The
electronic device 1 also comprises aninsulating encapsulation material 14 filling the space between thechip 12 and thesubstrate wafer 2. Optionally, theelectronic device 1 may comprise alayer 15 made of an insulating material on the frontal side of thesubstrate wafer 2 and encircling thechip 12. For example, thislayer 15 is flush with the frontal back side of thechip 12. - In the
layer 15, apertures are arranged 16 exposing theapertures 11 b of thelayers Electrical connection elements 17 such as bumps may be placed on theelectrical connection pads 11 a and in the holes formed by theapertures - As illustrated in
FIG. 2 , theducts 7 may be arranged so as to lie between the rows of the matrices ofelectrical connection pads - According to one variant embodiment, illustrated in
FIG. 2 , theducts 7 may be connected tocomplementary ducts 18, for example supply/return ducts, arranged in thelayer 6 of thesubstrate wafer 2, theseducts 18 emerging laterally from thesubstrate wafer 2 and possibly being connected to external means suitable for making acooling fluid 9 flow. - According to another variant embodiment, the
electronic device 1 may be equipped with a component incorporating a micropump, which component may be fixed to one of the sides of the device, for example by bonding, this micropump being connected to theinternal ducts 7, for example at two remote locations, through thesuperficial layer 10, in order to make theheat transfer fluid 9 flow through theseinternal ducts 7. - As illustrated in
FIG. 3 , the depth P1 of thegrooves 7 a is smaller than the depth P2 of the frontal side of the metal level M1, such that thegrooves 7 a may be arranged so as to pass above electrical connection lines of the metal level M1 without exposing them. - According to one embodiment, the integrated
circuit chip 12, which may be a processor chip, may generate heat. At least some of this generated heat may be preferentially captured by thematerial 9 filling theinternal ducts 7 and dispersed to substantially the entire volume of thesubstrate wafer 2, i.e. both to the zone of thechip 12 and to the peripheral zone of the latter. Thus, the thermallyconductive material 9 forms a means of capturing and dispersing to the bulk of thesubstrate wafer 2, at least some of the heat produced by thechip 12. - As illustrated in
FIG. 4 , theelectronic device 1 may be included in anelectronic system 100 furthermore comprising anotherelectronic device 101 stacked a distance above theelectronic device 1, on the same side as thechip 12. - The
electronic device 101 may comprise, borne by awafer 102 made of an insulating material and equipped with anelectrical connection network 103, an integratedcircuit chip 104 electrically connected to theelectrical connection network 103 byelectrical connection wires 105 embedded in thewafer 102. - The
electronic device 101 is mounted on theelectronic device 1 by way of electrical connection elements 106 such as metal bumps, which elements 106 are interposed between said devices, and electrically and selectively connect theelectrical connection network 103 of theelectronic device 101 to theelectrical connection network 3 of theelectronic device 1 by being soldered toelectrical connection elements 17 placed on thepads 5 b. - Furthermore, the
electronic device 1 and therefore theelectronic system 100, are mounted on a printedcircuit board 107 by way ofelectrical connection elements 108, such as metal bumps, interposed betweenelectrical connection pads 19 of theelectrical connection network 3 andelectrical connection pads 109 of the printedcircuit board 107. - The arrangement described above by way of example has the following advantages.
- The heat produced by the
chip 4 and, as described above, transferred and dispersed to thesubstrate wafer 2 by virtue of the existence of theducts 7 and thematerial 9 that they contain, may be transferred, at least partially, to the printedcircuit board 107 by way of theelectrical connection elements 108. - The
electrical connection network 3 of thesubstrate wafer 2 participates in the transfer of the heat produced by thechip 12 to the printedcircuit board 107. - Furthermore, the heat produced by the
chip 4 also diffuses into the space separating theelectronic device 1 and theelectronic device 101, in order to be evacuated toward the exterior. - In so far as the
material 9 is made to flow through theducts 7 by external means by way of thecomplementary ducts 18, the heat produced by thechip 4 may thus be at least partially evacuated by this means. - Thus, the
chip 12 is cooled and diffusion of the heat produced by thechip 12 of theelectronic device 1 in the direction of thechip 104 of theelectronic device 101 is limited in such a way that thechip 104 is protected from any excessive increase in its temperature. - The present invention is not limited to the examples described above. Many variant embodiments of the electronic devices and the heat transfer and cooling means are possible without departing from the scope of the invention.
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1360008A FR3011977A1 (en) | 2013-10-15 | 2013-10-15 | ELECTRONIC DEVICE WITH CHIP OF INTEGRATED CIRCUITS AND ELECTRONIC SYSTEM |
FR1360008 | 2013-10-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20150103489A1 true US20150103489A1 (en) | 2015-04-16 |
US9402331B2 US9402331B2 (en) | 2016-07-26 |
Family
ID=50101945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/512,214 Active US9402331B2 (en) | 2013-10-15 | 2014-10-10 | Integrated circuit chip comprising electronic device and electronic system |
Country Status (3)
Country | Link |
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US (1) | US9402331B2 (en) |
CN (2) | CN104576572B (en) |
FR (1) | FR3011977A1 (en) |
Cited By (2)
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EP3098847A1 (en) * | 2015-05-29 | 2016-11-30 | Alcatel Lucent | Device with a microchannel for transporting a fluid and manufacturing method thereof |
FR3070573A1 (en) * | 2017-08-25 | 2019-03-01 | Stmicroelectronics (Grenoble 2) Sas | ELECTRONIC DEVICE INCLUDING AT LEAST ONE ELECTRONIC CHIP AND ELECTRONIC ASSEMBLY |
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US6670699B2 (en) * | 2001-03-13 | 2003-12-30 | Nec Corporation | Semiconductor device packaging structure |
US6903929B2 (en) * | 2003-03-31 | 2005-06-07 | Intel Corporation | Two-phase cooling utilizing microchannel heat exchangers and channeled heat sink |
US7727807B2 (en) * | 2006-08-11 | 2010-06-01 | Dongbu Hitek Co., Ltd. | Semiconductor device |
US8563365B2 (en) * | 2011-03-09 | 2013-10-22 | Georgia Tech Research Corporation | Air-gap C4 fluidic I/O interconnects and methods of fabricating same |
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US8546930B2 (en) * | 2008-05-28 | 2013-10-01 | Georgia Tech Research Corporation | 3-D ICs equipped with double sided power, coolant, and data features |
US8624360B2 (en) * | 2008-11-13 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling channels in 3DIC stacks |
US7990711B1 (en) * | 2010-02-24 | 2011-08-02 | International Business Machines Corporation | Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate |
-
2013
- 2013-10-15 FR FR1360008A patent/FR3011977A1/en not_active Withdrawn
-
2014
- 2014-09-25 CN CN201410497513.8A patent/CN104576572B/en active Active
- 2014-09-25 CN CN201420555614.1U patent/CN204230226U/en not_active Withdrawn - After Issue
- 2014-10-10 US US14/512,214 patent/US9402331B2/en active Active
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US6670699B2 (en) * | 2001-03-13 | 2003-12-30 | Nec Corporation | Semiconductor device packaging structure |
US6903929B2 (en) * | 2003-03-31 | 2005-06-07 | Intel Corporation | Two-phase cooling utilizing microchannel heat exchangers and channeled heat sink |
US7727807B2 (en) * | 2006-08-11 | 2010-06-01 | Dongbu Hitek Co., Ltd. | Semiconductor device |
US8563365B2 (en) * | 2011-03-09 | 2013-10-22 | Georgia Tech Research Corporation | Air-gap C4 fluidic I/O interconnects and methods of fabricating same |
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EP3098847A1 (en) * | 2015-05-29 | 2016-11-30 | Alcatel Lucent | Device with a microchannel for transporting a fluid and manufacturing method thereof |
FR3070573A1 (en) * | 2017-08-25 | 2019-03-01 | Stmicroelectronics (Grenoble 2) Sas | ELECTRONIC DEVICE INCLUDING AT LEAST ONE ELECTRONIC CHIP AND ELECTRONIC ASSEMBLY |
US10811349B2 (en) | 2017-08-25 | 2020-10-20 | Stmicroelectronics (Grenoble 2) Sas | Electronic device including at least one electronic chip and electronic package |
Also Published As
Publication number | Publication date |
---|---|
FR3011977A1 (en) | 2015-04-17 |
CN204230226U (en) | 2015-03-25 |
CN104576572B (en) | 2018-12-11 |
CN104576572A (en) | 2015-04-29 |
US9402331B2 (en) | 2016-07-26 |
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