US20150048477A1 - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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US20150048477A1
US20150048477A1 US13/968,726 US201313968726A US2015048477A1 US 20150048477 A1 US20150048477 A1 US 20150048477A1 US 201313968726 A US201313968726 A US 201313968726A US 2015048477 A1 US2015048477 A1 US 2015048477A1
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dielectric material
semiconductor structure
conductors
dielectric layer
phosphorous
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Jia-You Tsai
Kung-Wei Lee
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, KUNG-WEI, TSAI, JIA-YOU
Publication of US20150048477A1 publication Critical patent/US20150048477A1/en
Priority to US14/813,707 priority patent/US10014207B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H01L29/0649—
    • H01L21/76224—
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6329—Deposition from the gas or vapour phase using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6924—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Definitions

  • the disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure with a dielectric material.
  • Semiconductor devices are widely used in different fields as costs and physical dimensions reduce with advancing technologies. Structures of semiconductor devices become more and more complicated because transistor density per unit area increases. Multilevel of conductive pattern features are also adopted to improve performance of semiconductor devices.
  • Dielectric material is adopted as a structure in semiconductor devices to isolate transistors in different regions. Dielectric material is also utilized to separate conductive patterns located in different levels. As the geometry shrinks, a multi-step method is used to grow the dielectric material in a multi-layer manner. However, the interface between each layer is a weak point of the dielectric material.
  • FIG. 1 is a schematic of a semiconductor structure, in accordance with some embodiments of the present disclosure
  • FIG. 2 is a fluorine concentration distribution in a dielectric material of the structure in FIG. 1 , according to some embodiments of the present disclosure.
  • FIGS. 3A-3G are schematic diagrams illustrating a method of manufacturing the semiconductor structure in FIG. 1 at an STI stage, according to some embodiments of the present disclosure.
  • FIG. 4 is an exemplary semiconductor structure at an ILD stage, according to some embodiments of the present disclosure.
  • FIG. 5 is a fluorine and phosphorous concentration distribution of a dielectric material in the structure of FIG. 4 , according to some embodiments of the present disclosure.
  • FIGS. 6A-6H are schematic diagrams illustrating a method of manufacturing the semiconductor structure in FIG. 5 at an ILD stage, according to some embodiments of the present disclosure.
  • FIG. 7 is an exemplary semiconductor structure at an IMD stage, according to some embodiments of the present disclosure.
  • FIG. 8 is a fluorine concentration distribution of a dielectric material of the structure in FIG. 7 , according to some embodiments of the present disclosure.
  • FIGS. 9A-9E are schematic diagrams illustrating a method of manufacturing the semiconductor structure in FIG. 8 at IMD stage, according to some embodiments of the present disclosure.
  • a dielectric material is introduced in a semiconductor structure.
  • the dielectric material is arranged as a gap filling film between pattern features in some stages.
  • the dielectric material acts as an isolation filled in a trench of a substrate.
  • the dielectric material acts as an isolation between conductive lines.
  • the conductive lines are electrically conductive or semi-conductive.
  • concentration of phosphorus is substantially constant across the dielectric material.
  • fluorine concentration changes in a substantially linear manner across the dielectric material.
  • the dielectric layer is a portion of the dielectric material.
  • a shallow trench isolation (STI) stage refers to a stage in which STI structures are defined.
  • the STI structures are designed to isolate transistor gates, sources, drains, etc.
  • An inter layer dielectric (ILD) stage is in between formation of a transistor gate and formation of a first metal layer.
  • An IMD stage is after the ILD stage.
  • FIG. 1 is an exemplary semiconductor structure 100 at an STI stage, in accordance with some embodiments.
  • a semiconductor substrate 120 of the semiconductor structure 100 provides a foundation to form semiconductor circuitry.
  • the substrate 120 is a silicon substrate with a first conductivity type, which is a p-type, for example.
  • the substrate 120 has several doped regions. Some of the doped regions have a second conductivity type opposite to the first conductivity type. Some of the doped regions have the first conductivity type with a higher concentration than that of the substrate 120 .
  • the semiconductor substrate 120 has a surface 122 (not labeled in the drawing) that includes two portions 122 A, two portions 122 C, and a portion 122 B.
  • the surface 122 is a jagged surface and is illustrated by a coarse line in FIG. 1 .
  • Each portion 122 C is in between a corresponding portion 122 A and the portion 122 B.
  • the portion 122 B is connected with two portions 122 C.
  • a liner 125 is disposed on the surface 122 . As illustratively shown in FIG. 1 , the liner 125 is disposed on the portion 122 B and two portions 122 C of the surface 122 . In some embodiments not shown in FIG. 1 , the liner 125 is also disposed on two portions 122 A. The liner 125 has a thickness D between about 50 ⁇ and 700 ⁇ . In some embodiments, the liner 125 is electrically isolative.
  • a dielectric material 127 is disposed on the liner 125 .
  • the dielectric material 127 is directly disposed on the portion 122 B and two portions 122 C.
  • the dielectric material 127 has a predetermined shape, which is determined by the portion 122 B and two portions 122 C. As illustratively shown in FIG. 1 , the dielectric material 127 has a shape of a trapezoid. In some other embodiments, the dielectric material 127 has a shape of a quadrilateral. Other shapes of the dielectric material 127 are within the contemplated scope of the present disclosure.
  • the dielectric material 127 has predetermined dimensions, such as a first width W 1 , a second width W 2 and a height H.
  • the width W 1 is defined by a corner 132 and a corner 134 of the dielectric material 127 .
  • the width W 2 is defined by a corner 136 and a corner 137 of the dielectric material 127 .
  • the height H is defined by a top surface 130 of the dielectric material 127 and a bottom surface 131 of the dielectric material 127 .
  • the bottom surface 131 is an interface between the dielectric material 127 and the liner 125 .
  • the dielectric material 127 has an aspect ratio, which is defined by a ratio of the height H over the width W 1 of the dielectric material 127 .
  • the height H is greater than 72 nm and the width W is smaller than 30 nm.
  • the aspect ratio of the dielectric material 127 is 2.4.
  • the aspect ratio of the dielectric material 127 is greater than 2.4, and is, for example, 2.8, 3.5, etc.
  • the aspect ratio of the dielectric material 127 in the STI stage is greater than 2.4 in order to meet the design rule. Other values of the aspect ratio are within the contemplated scope of the present disclosure.
  • the dielectric material 127 has a silicon glass matrix and electrically isolates active regions in the substrate 120 .
  • the dielectric material 127 has a fluorine ion in the silicon glass matrix.
  • FIG. 2 is a graph representing fluorine concentration distribution in the dielectric material 127 according to some embodiments. The fluorine concentration is measured by a secondary ion mass spectrometer (SIMS), an Auger electron nanoscope (Auger) or other suitable analysis tools.
  • SIMS secondary ion mass spectrometer
  • Auger Auger electron nanoscope
  • the Y-axis represents the fluorine concentration in atomic ratio per cubic centimeters (Atoms/cm 3 ).
  • the X-axis represents a depth of the dielectric material 127 that is referenced from the top surface 130 of the dielectric material 127 , and the unit is ⁇ .
  • the dielectric material 127 has a depth of about 1000 ⁇ .
  • the depth is also the height H of the dielectric material 127 shown in FIG. 1 .
  • the fluorine concentration is thus illustrated from 0 ⁇ to about 1000 ⁇ . From 0 ⁇ to about 1000 ⁇ , the fluorine concentration changes from about 1 ⁇ E20 Atoms/cm 3 to about 2 ⁇ E20 Atoms/cm 3 . Effectively, the fluorine concentration is lowest at the surface 130 and is highest at the interface 131 .
  • FIGS. 3A-3G are cross sectional views of the semiconductor structure 100 at the STI stage illustrated in FIG. 1 , according to some embodiments of the present disclosure.
  • a substrate 120 having a surface 121 is provided.
  • a portion of the substrate 120 is removed to form a trench in the substrate 120 .
  • Two portions labeled 122 A are remaining portions of the surface 121 in FIG. 3B .
  • Two sidewalls of the trench correspond to two portions 122 C in FIG. 1 .
  • a bottom surface of the trench corresponds to the portion 122 B in FIG. 1 .
  • Two portions 122 A, two portions 122 C and portion 122 C form the surface 122 in FIG. 1 .
  • the trench has a height H′ defined as a distance from the surface portion 122 A and the surface portion 122 B.
  • a layer 125 A is formed on the surface 122 .
  • the layer 125 A has a thickness D referenced from the bottom of the trench.
  • a dielectric layer 127 - 1 is formed on the layer 125 A. Effectively, the dielectric layer 127 - 1 is also formed over the surface 122 . In some embodiments without the liner 125 , the dielectric layer 127 - 1 is formed on the surface 122 .
  • the dielectric layer 127 - 1 has a thickness h 1 .
  • a chemical vapor deposition (CVD) process is used to form the dielectric layer 127 A.
  • the CVD process is a high density plasma (HDP) or high aspect ratio process (HARP).
  • the CVD process includes a deposition step and an insitu sputter step.
  • the deposition step is to form some dielectric material in the trench and the insitu sputter step uses ions such as argon ions to remove a portion of the dielectric material.
  • the dielectric layer 127 - 1 in FIG. 3D is a final profile formed by the CVD process.
  • the dielectric layer 127 - 1 has two overhangs 127 - 1 a.
  • an insitu etch step is used to remove a portion of the dielectric layer 127 - 1 .
  • the overhangs 127 - 1 a in FIG. 3D are removed.
  • an NF 3 gas is ionized to remove the portion of the dielectric layer 127 - 1 .
  • a circle with an “F” represents a fluorine ion of the ionized NF3 gas.
  • the thickness of the dielectric layer 127 - 1 is reduced to h 1 ′. In some embodiments, the thickness h 1 ′ is about 1 ⁇ 6 of the height H.
  • the height H is defined by a surface portion 122 A and the interface between the dielectric layer 127 - 1 and the liner 125 .
  • FIG. 3F an operation to treat a top surface of the dielectric layer 127 - 1 with plasma is illustrated.
  • a gas is introduced and ionized by a first radio frequency (RF) power to form the plasma.
  • the gas is oxygen and the first RF power is between about 1000 W and 9000 W.
  • a circle with an “O” illustrates an oxygen ion.
  • a second RF power is also introduced to accelerate the plasma to treat the top surface of the dielectric layer 127 - 1 .
  • the second RF power is between about 1000 W and 9000 W.
  • fluorine concentration at the top surface of the dielectric layer 127 - 1 is adjusted. The fluorine concentration in the dielectric layer 127 - 1 changes in a linear manner.
  • several cycles are used to form the dielectric material 127 to a predetermined thickness. For example, operations with reference to FIGS. 3D to 3F are repeated to form a cycle of forming the dielectric layer 127 - 1 . In some embodiments as illustrated in FIG. 3G , an operation that repeats the cycle 6-7 times is used to form the dielectric material 127 in the trench having the thickness H. A portion of the layer 125 A in FIG. 3F is also removed to result in the liner 125 .
  • FIG. 4 is an exemplary semiconductor structure 400 at an ILD stage, in accordance with some embodiments.
  • the semiconductor structure 400 has a surface 122 - 1 (not labeled in the drawing) and two conductors 150 on the substrate 120 .
  • the surface 122 - 1 includes at least two portions 122 - 1 A, two portions 122 - 1 C, and a portion 122 - 1 B.
  • the portion 122 - 1 A, 122 - 1 B, and 122 - 1 C correspond to the portion 122 A, 122 B, and 122 C in FIG. 1 , respectively.
  • the conductors 150 are electrically conductive and, in some embodiments, are gates of the semiconductor structure 400 .
  • the two conductors 150 are identical, and the conductor 150 on the right side is used in the exemplary illustration that is also applicable to the other conductor 150 .
  • a portion 122 - 1 C is a sidewall of the conductor 150 and a portion 122 - 1 A is a top surface of the conductor 150 .
  • a first spacer 123 A is adjacent to a sidewall of the conductor 150 .
  • a second spacer 123 B is adjacent to the first spacer 123 A. Spacers 123 A and 123 B are symmetrical with reference to the conductor 150 .
  • the semiconductor structure 400 has at least one spacer at each side of the conductor 150 .
  • a liner 125 A is disposed over the substrate 120 and other locations. For example, a portion of the liner 125 A is over the conductors 150 , another portion is on the top surface 122 - 1 A of the conductor 150 , and another portion is on the spacers 123 A and 123 B. In some embodiments, the liner 125 A is an etch stop layer.
  • a dielectric material 127 A corresponds to the dielectric material 127 in FIG. 1 , and includes phosphorous ions in addition to fluorine ions as in the dielectric material 127 .
  • the dielectric material 127 A also has a silicon glass matrix and electrically isolates the conductors 150 .
  • FIG. 5 is a fluorine concentration distribution of the dielectric material 127 A in FIG. 4 according to some embodiments.
  • the fluorine concentration is measured by a secondary ion mass spectrometer (SIMS), an Auger electron nanoscope (Auger) or other suitable analysis tools.
  • SIMS secondary ion mass spectrometer
  • Auger Auger electron nanoscope
  • the Y-axis represents the fluorine concentration and the unit is atomic ratio per cubic centimeters (atoms/cm 3 ).
  • the X-axis represents a depth of the dielectric material 127 A with reference to a line AA′ in FIG. 4 , and the unit is ⁇ .
  • Line 501 represents the fluorine concentration versus the depth of the dielectric material 127 A. In the illustration of FIG.
  • the dielectric material 127 A has a depth of about 1000 ⁇ .
  • the depth is also the height H of the dielectric material 127 A.
  • the fluorine concentration is thus illustrated from 0 ⁇ to about 1000 ⁇ . From 0 ⁇ to about 1000 ⁇ , the fluorine concentration changes from about 1 ⁇ E20 Atoms/cm 3 to about 2 ⁇ E20 Atoms/cm 3 . Effectively, the fluorine concentration is lowest at the surface 130 shown in FIG. 4 and is highest at the interface 131 .
  • Line 502 represents the phosphorous concentration distribution versus the depth of the dielectric material 127 A.
  • the phosphorous concentration is substantially constant in the dielectric material 127 A.
  • FIGS. 6A-6H are cross sectional views of the semiconductor structure 400 at the ILD stage illustrated in FIG. 4 , according to some embodiments of the present disclosure.
  • each conductor 150 includes a sidewall 122 - 1 C.
  • the top surface of each conductor 150 corresponds to the portion 122 - 1 A in FIG. 4 .
  • a portion of the surface 121 between the two conductors 150 corresponds to the portion 122 - 1 B in FIG. 4 .
  • a first spacer 123 A is formed on a corresponding sidewall 122 - 1 C of the conductors 150 .
  • a second spacer 123 B is formed adjacently to the first spacer 123 A. For simplicity, only elements associated with one conductor 150 are labeled.
  • a liner 125 A is formed and covers the top surface 122 - 1 A of the conductor 150 and on the spacers 123 A and 123 B. A portion of the liner 125 A is on the bottom surface 122 - 1 B.
  • An opening 126 between the conductors 150 has a height H and a width W.
  • a doped chemical vapor deposition (CVD) process is used to form a dielectric layer 127 A- 1 on the liner 125 A.
  • the doped CVD process is a high density plasma (HDP) or HARP process.
  • the dopant is phosphorous ions.
  • the doped chemical vapor deposition includes a deposition step and an insitu sputter step.
  • the deposition step forms doped dielectric material on the liner 125 A.
  • the insitu sputter step uses ion such as argon ions and removes a portion of the doped dielectric material.
  • FIG. 6F illustrates the height of dielectric layer 127 A- 1 is reduced to h 1 ′.
  • FIG. 6G an operation to treat a top surface of the dielectric layer 127 A- 1 with plasma is illustrated.
  • a PH 3 gas is introduced and ionized by a first radio frequency (RF) power to form the plasma.
  • Phosphorous ions are generated from the ionized PH 3 gas.
  • a circle with an “P” illustrates an phosphorous ion.
  • a second RF power is also introduced to accelerate the plasma to treat the top surface of the dielectric layer 127 A- 1 .
  • the magnitude of the first and the second RF powers are as illustrated with reference to FIGS. 3A-3G .
  • phosphorous concentration at the top surface of the dielectric layer 127 A- 1 is adjusted.
  • the phosphorous concentration in the dielectric layer 127 A- 1 is substantially constant throughout the dielectric layer 127 A- 1 .
  • Fluorine concentration at the top surface of the dielectric layer 127 A- 1 is adjusted to change in a linear manner throughout the dielectric layer 127 A- 1 .
  • several cycles are used to form the dielectric material 127 A to a predetermined height. For example, operations with reference to FIGS. 6E to 6G are repeated as a cycle to form the dielectric layer 127 A- 1 . An operation that repeats the cycle 6-7 times is used and results in the dielectric material 127 A having the height H.
  • FIG. 7 is an exemplary semiconductor structure 700 at an IMD stage, in accordance with some embodiments.
  • the semiconductor structure 700 has a surface 122 - 2 not labeled in the drawing) and two conductors 160 on a substrate 120 A.
  • the surface 122 - 2 includes at least two portions 122 - 2 A two portions 122 - 2 C and a portion 122 - 2 B.
  • the portion 122 - 2 A, 122 - 2 B, and 122 - 2 C correspond to the portion 122 A, 122 B, and 122 C in FIG. 1 , respectively.
  • the conductors 160 include metal.
  • the substrate 120 A corresponds to the substrate 120 in FIG. 1 , and, in addition to silicon, also includes metal and dielectric.
  • a dielectric material 127 is on the portions 122 - 2 C and the portion 122 - 2 B. In some embodiments, a liner 125 A (not shown in the drawing) is between the dielectric material 127 and the surface 122 - 2 .
  • the dielectric material 127 has a fluorine ion in the silicon glass matrix.
  • the dielectric material 127 has a height H. In some embodiments, the height of the dielectric material 127 is dependant on a height of the conductor 160 .
  • FIG. 8 is a fluorine concentration distribution in the dielectric material 127 according to some embodiments.
  • the X-axis represents a depth of the dielectric material 127 with reference to a line AA′ in FIG. 7 , and the unit is ⁇ .
  • Line 801 represents the fluorine concentration versus the depth of the dielectric material 127 .
  • the dielectric material 127 has a depth of about 1000 ⁇ .
  • the depth is also the height H of the dielectric material 127 .
  • the fluorine concentration is thus illustrated from 0 ⁇ to about 1000 ⁇ , which is substantially equal to the height H of the dielectric material 127 .
  • Other values of the height are within the contemplated scope of the present disclosure.
  • the fluorine concentration changes from about 1 ⁇ E20 Atoms/cm 3 to about 2 ⁇ E20 Atoms/cm 3 . Effectively, the fluorine concentration is lowest at the surface 130 and is highest at the portion 122 - 2 B.
  • FIGS. 9A-9E are cross sectional views of the semiconductor structure 700 at the IMD stage illustrated in FIG. 7 , according to some embodiments of the present disclosure.
  • two conductors 160 are formed on a surface 121 of a substrate 120 A.
  • the conductor 150 has a shape of a trapezoid.
  • a CVD process is used to form a dielectric layer 127 - 1 on the portions 122 - 2 A, 122 - 2 B and 122 - 2 C.
  • the CVD process is a HDP or HARP process.
  • Two overhangs 127 - 1 a are formed on top corners 164 of the conductors 160 .
  • a same fluorine ion etch process illustrated in FIG. 3E is adopted to remove the overhangs 127 - 1 a.
  • the thickness of the dielectric layer 127 - 1 is reduced to h 1 ′ as illustrated in FIG. 9C .
  • FIG. 9D is used to illustrate an operation to treat a top surface of the dielectric layer 127 - 1 with plasma.
  • the plasma includes oxygen ions.
  • several cycles are used to form the dielectric material 127 to a predetermined height. For example, operations with reference to FIGS. 9B to 9D are repeated to form a cycle to form the dielectric layer 127 - 1 . In some embodiments as illustrated in FIG. 9E , an operation that repeats the cycle 6-7 times is used to form the dielectric material 127 having the thickness H.
  • a semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface.
  • the dielectric material includes an aspect ratio that is substantially equal to or greater than a predetermined value.
  • a semiconductor structure in some embodiments, includes conductors and a spacer disposed on a sidewall of each conductor of the conductors.
  • the semiconductor structure has a liner on the spacer and a top surface of each conductor of the conductors.
  • the semiconductor structure also has a phosphorous doped dielectric material between two conductors and the phosphorous concentration throughout the phosphorous doped dielectric material is substantially constant.
  • a method of manufacturing a semiconductor structure includes forming a surface, forming a dielectric layer over the surface, etching the dielectric layer, and treating a top surface of the dielectric layer with plasma.

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Abstract

A semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio substantially equal to or greater than a predetermined value.

Description

    FIELD
  • The disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure with a dielectric material.
    • BACKGROUND
  • Semiconductor devices are widely used in different fields as costs and physical dimensions reduce with advancing technologies. Structures of semiconductor devices become more and more complicated because transistor density per unit area increases. Multilevel of conductive pattern features are also adopted to improve performance of semiconductor devices.
  • Dielectric material is adopted as a structure in semiconductor devices to isolate transistors in different regions. Dielectric material is also utilized to separate conductive patterns located in different levels. As the geometry shrinks, a multi-step method is used to grow the dielectric material in a multi-layer manner. However, the interface between each layer is a weak point of the dielectric material.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, some features are not drawn to scale. In fact, the dimensions of the some features may be arbitrarily increased or reduced for clarity of discussion.
  • FIG. 1 is a schematic of a semiconductor structure, in accordance with some embodiments of the present disclosure
  • FIG. 2 is a fluorine concentration distribution in a dielectric material of the structure in FIG. 1, according to some embodiments of the present disclosure.
  • FIGS. 3A-3G are schematic diagrams illustrating a method of manufacturing the semiconductor structure in FIG. 1 at an STI stage, according to some embodiments of the present disclosure.
  • FIG. 4 is an exemplary semiconductor structure at an ILD stage, according to some embodiments of the present disclosure.
  • FIG. 5 is a fluorine and phosphorous concentration distribution of a dielectric material in the structure of FIG. 4, according to some embodiments of the present disclosure.
  • FIGS. 6A-6H are schematic diagrams illustrating a method of manufacturing the semiconductor structure in FIG. 5 at an ILD stage, according to some embodiments of the present disclosure.
  • FIG. 7 is an exemplary semiconductor structure at an IMD stage, according to some embodiments of the present disclosure.
  • FIG. 8 is a fluorine concentration distribution of a dielectric material of the structure in FIG. 7, according to some embodiments of the present disclosure.
  • FIGS. 9A-9E are schematic diagrams illustrating a method of manufacturing the semiconductor structure in FIG. 8 at IMD stage, according to some embodiments of the present disclosure.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • According to the present disclosure, a dielectric material is introduced in a semiconductor structure. The dielectric material is arranged as a gap filling film between pattern features in some stages. In some embodiments, the dielectric material acts as an isolation filled in a trench of a substrate. In some embodiments, the dielectric material acts as an isolation between conductive lines. The conductive lines are electrically conductive or semi-conductive.
  • In some embodiments of the present disclosure, concentration of phosphorus is substantially constant across the dielectric material. In some embodiments, fluorine concentration changes in a substantially linear manner across the dielectric material. In some embodiments, the dielectric layer is a portion of the dielectric material.
  • In the present disclosure, some exemplary stages are used to illustrate some embodiments. A shallow trench isolation (STI) stage refers to a stage in which STI structures are defined. The STI structures are designed to isolate transistor gates, sources, drains, etc. An inter layer dielectric (ILD) stage is in between formation of a transistor gate and formation of a first metal layer. An IMD stage is after the ILD stage.
    • Semiconductor Structure at STI Stage
  • FIG. 1 is an exemplary semiconductor structure 100 at an STI stage, in accordance with some embodiments. A semiconductor substrate 120 of the semiconductor structure 100 provides a foundation to form semiconductor circuitry. In some embodiments, the substrate 120 is a silicon substrate with a first conductivity type, which is a p-type, for example. In some embodiments, the substrate 120 has several doped regions. Some of the doped regions have a second conductivity type opposite to the first conductivity type. Some of the doped regions have the first conductivity type with a higher concentration than that of the substrate 120. The semiconductor substrate 120 has a surface 122 (not labeled in the drawing) that includes two portions 122A, two portions 122C, and a portion 122B. The surface 122 is a jagged surface and is illustrated by a coarse line in FIG. 1. Each portion 122C is in between a corresponding portion 122A and the portion 122B. The portion 122B is connected with two portions 122C.
  • A liner 125 is disposed on the surface 122. As illustratively shown in FIG. 1, the liner 125 is disposed on the portion 122B and two portions 122C of the surface 122. In some embodiments not shown in FIG. 1, the liner 125 is also disposed on two portions 122A. The liner 125 has a thickness D between about 50 Å and 700 Å. In some embodiments, the liner 125 is electrically isolative.
  • A dielectric material 127 is disposed on the liner 125. In some other embodiments that there is not the liner 125, the dielectric material 127 is directly disposed on the portion 122B and two portions 122C. The dielectric material 127 has a predetermined shape, which is determined by the portion 122B and two portions 122C. As illustratively shown in FIG. 1, the dielectric material 127 has a shape of a trapezoid. In some other embodiments, the dielectric material 127 has a shape of a quadrilateral. Other shapes of the dielectric material 127 are within the contemplated scope of the present disclosure.
  • The dielectric material 127 has predetermined dimensions, such as a first width W1, a second width W2 and a height H. As shown in FIG. 1, the width W1 is defined by a corner 132 and a corner 134 of the dielectric material 127. The width W2 is defined by a corner 136 and a corner 137 of the dielectric material 127. The height H is defined by a top surface 130 of the dielectric material 127 and a bottom surface 131 of the dielectric material 127. In FIG. 1, the bottom surface 131 is an interface between the dielectric material 127 and the liner 125. The dielectric material 127 has an aspect ratio, which is defined by a ratio of the height H over the width W1 of the dielectric material 127. In some embodiments, the height H is greater than 72 nm and the width W is smaller than 30 nm. As a result, the aspect ratio of the dielectric material 127 is 2.4. In some embodiments, the aspect ratio of the dielectric material 127 is greater than 2.4, and is, for example, 2.8, 3.5, etc. In some embodiments, such as a 40 nm CMOS (complimentary metal oxide semiconductor) device, the aspect ratio of the dielectric material 127 in the STI stage is greater than 2.4 in order to meet the design rule. Other values of the aspect ratio are within the contemplated scope of the present disclosure.
  • The dielectric material 127 has a silicon glass matrix and electrically isolates active regions in the substrate 120. In some embodiments with references to FIG. 1, the dielectric material 127 has a fluorine ion in the silicon glass matrix. FIG. 2 is a graph representing fluorine concentration distribution in the dielectric material 127 according to some embodiments. The fluorine concentration is measured by a secondary ion mass spectrometer (SIMS), an Auger electron nanoscope (Auger) or other suitable analysis tools. In FIG. 2, the Y-axis represents the fluorine concentration in atomic ratio per cubic centimeters (Atoms/cm3). The X-axis represents a depth of the dielectric material 127 that is referenced from the top surface 130 of the dielectric material 127, and the unit is Å.
  • In the illustration of FIG. 2, the dielectric material 127 has a depth of about 1000 Å. The depth is also the height H of the dielectric material 127 shown in FIG. 1. The fluorine concentration is thus illustrated from 0 Å to about 1000 Å. From 0 Å to about 1000 Å, the fluorine concentration changes from about 1×E20 Atoms/cm3 to about 2×E20 Atoms/cm3. Effectively, the fluorine concentration is lowest at the surface 130 and is highest at the interface 131.
  • FIGS. 3A-3G are cross sectional views of the semiconductor structure 100 at the STI stage illustrated in FIG. 1, according to some embodiments of the present disclosure.
  • In FIG. 3A, a substrate 120 having a surface 121 is provided. In FIG. 3B, a portion of the substrate 120 is removed to form a trench in the substrate 120. Two portions labeled 122A are remaining portions of the surface 121 in FIG. 3B. Two sidewalls of the trench correspond to two portions 122C in FIG. 1. A bottom surface of the trench corresponds to the portion 122B in FIG. 1. Two portions 122A, two portions 122C and portion 122C form the surface 122 in FIG. 1. The trench has a height H′ defined as a distance from the surface portion 122A and the surface portion 122B.
  • In FIG. 3C, a layer 125A is formed on the surface 122. The layer 125A has a thickness D referenced from the bottom of the trench. In FIG. 3D, a dielectric layer 127-1 is formed on the layer 125A. Effectively, the dielectric layer 127-1 is also formed over the surface 122. In some embodiments without the liner 125, the dielectric layer 127-1 is formed on the surface 122. The dielectric layer 127-1 has a thickness h1.
  • A chemical vapor deposition (CVD) process is used to form the dielectric layer 127A. In some embodiments, the CVD process is a high density plasma (HDP) or high aspect ratio process (HARP). The CVD process includes a deposition step and an insitu sputter step. The deposition step is to form some dielectric material in the trench and the insitu sputter step uses ions such as argon ions to remove a portion of the dielectric material. The dielectric layer 127-1 in FIG. 3D is a final profile formed by the CVD process. The dielectric layer 127-1 has two overhangs 127-1 a.
  • In FIG. 3E, an insitu etch step is used to remove a portion of the dielectric layer 127-1. During this operation, the overhangs 127-1 a in FIG. 3D are removed. In some embodiments as illustrated with reference to FIG. 3E, an NF3 gas is ionized to remove the portion of the dielectric layer 127-1. A circle with an “F” represents a fluorine ion of the ionized NF3 gas. The thickness of the dielectric layer 127-1 is reduced to h1′. In some embodiments, the thickness h1′ is about ⅙ of the height H. The height H is defined by a surface portion 122A and the interface between the dielectric layer 127-1 and the liner 125.
  • In FIG. 3F, an operation to treat a top surface of the dielectric layer 127-1 with plasma is illustrated. In this operation, a gas is introduced and ionized by a first radio frequency (RF) power to form the plasma. In some embodiments, the gas is oxygen and the first RF power is between about 1000 W and 9000 W. A circle with an “O” illustrates an oxygen ion. A second RF power is also introduced to accelerate the plasma to treat the top surface of the dielectric layer 127-1. In some embodiments, the second RF power is between about 1000 W and 9000 W. During this operation, fluorine concentration at the top surface of the dielectric layer 127-1 is adjusted. The fluorine concentration in the dielectric layer 127-1 changes in a linear manner.
  • In some embodiments, several cycles are used to form the dielectric material 127 to a predetermined thickness. For example, operations with reference to FIGS. 3D to 3F are repeated to form a cycle of forming the dielectric layer 127-1. In some embodiments as illustrated in FIG. 3G, an operation that repeats the cycle 6-7 times is used to form the dielectric material 127 in the trench having the thickness H. A portion of the layer 125A in FIG. 3F is also removed to result in the liner 125.
    • Semiconductor Structure at ILD Stage
  • FIG. 4 is an exemplary semiconductor structure 400 at an ILD stage, in accordance with some embodiments. The semiconductor structure 400 has a surface 122-1 (not labeled in the drawing) and two conductors 150 on the substrate 120. The surface 122-1 includes at least two portions 122-1A, two portions 122-1C, and a portion 122-1B. The portion 122-1A, 122-1B, and 122-1C correspond to the portion 122A, 122B, and 122C in FIG. 1, respectively. The conductors 150 are electrically conductive and, in some embodiments, are gates of the semiconductor structure 400. The two conductors 150 are identical, and the conductor 150 on the right side is used in the exemplary illustration that is also applicable to the other conductor 150. A portion 122-1C is a sidewall of the conductor 150 and a portion 122-1A is a top surface of the conductor 150. A first spacer 123A is adjacent to a sidewall of the conductor 150. A second spacer 123B is adjacent to the first spacer 123A. Spacers 123A and 123B are symmetrical with reference to the conductor 150. In some embodiments, the semiconductor structure 400 has at least one spacer at each side of the conductor 150.
  • A liner 125A is disposed over the substrate 120 and other locations. For example, a portion of the liner 125A is over the conductors 150, another portion is on the top surface 122-1A of the conductor 150, and another portion is on the spacers 123A and 123B. In some embodiments, the liner 125A is an etch stop layer.
  • A dielectric material 127A corresponds to the dielectric material 127 in FIG. 1, and includes phosphorous ions in addition to fluorine ions as in the dielectric material 127. The dielectric material 127A also has a silicon glass matrix and electrically isolates the conductors 150.
  • FIG. 5 is a fluorine concentration distribution of the dielectric material 127A in FIG. 4 according to some embodiments. The fluorine concentration is measured by a secondary ion mass spectrometer (SIMS), an Auger electron nanoscope (Auger) or other suitable analysis tools. In FIG. 5, the Y-axis represents the fluorine concentration and the unit is atomic ratio per cubic centimeters (atoms/cm3). The X-axis represents a depth of the dielectric material 127A with reference to a line AA′ in FIG. 4, and the unit is Å. Line 501 represents the fluorine concentration versus the depth of the dielectric material 127A. In the illustration of FIG. 5, the dielectric material 127A has a depth of about 1000 Å. The depth is also the height H of the dielectric material 127A. The fluorine concentration is thus illustrated from 0 Å to about 1000 Å. From 0 Å to about 1000 Å, the fluorine concentration changes from about 1×E20 Atoms/cm3 to about 2×E20 Atoms/cm3. Effectively, the fluorine concentration is lowest at the surface 130 shown in FIG. 4 and is highest at the interface 131.
  • Line 502 represents the phosphorous concentration distribution versus the depth of the dielectric material 127A. In FIG. 5, the phosphorous concentration is substantially constant in the dielectric material 127A.
  • FIGS. 6A-6H are cross sectional views of the semiconductor structure 400 at the ILD stage illustrated in FIG. 4, according to some embodiments of the present disclosure.
  • In FIG. 6A, two conductors 150 are formed on the surface 121 of the substrate 120. Each conductor 150 includes a sidewall 122-1C. The top surface of each conductor 150 corresponds to the portion 122-1A in FIG. 4. A portion of the surface 121 between the two conductors 150 corresponds to the portion 122-1B in FIG. 4.
  • In FIG. 6B, a first spacer 123A is formed on a corresponding sidewall 122-1C of the conductors 150. In FIG. 6C, a second spacer 123B is formed adjacently to the first spacer 123A. For simplicity, only elements associated with one conductor 150 are labeled.
  • In FIG. 6D, a liner 125A is formed and covers the top surface 122-1A of the conductor 150 and on the spacers 123A and 123B. A portion of the liner 125A is on the bottom surface 122-1B. An opening 126 between the conductors 150 has a height H and a width W.
  • In FIG. 6E, a doped chemical vapor deposition (CVD) process is used to form a dielectric layer 127A-1 on the liner 125A. In some embodiments, the doped CVD process is a high density plasma (HDP) or HARP process. The dopant is phosphorous ions. The doped chemical vapor deposition includes a deposition step and an insitu sputter step. The deposition step forms doped dielectric material on the liner 125A. The insitu sputter step uses ion such as argon ions and removes a portion of the doped dielectric material.
  • A same fluorine ion etch process as illustrated in FIG. 3E is adopted to remove the overhangs 127A-1 a after the operation in FIG. 6E. FIG. 6F illustrates the height of dielectric layer 127A-1 is reduced to h1′.
  • In FIG. 6G, an operation to treat a top surface of the dielectric layer 127A-1 with plasma is illustrated. For some embodiments, a PH3 gas is introduced and ionized by a first radio frequency (RF) power to form the plasma. Phosphorous ions are generated from the ionized PH3 gas. A circle with an “P” illustrates an phosphorous ion. A second RF power is also introduced to accelerate the plasma to treat the top surface of the dielectric layer 127A-1. The magnitude of the first and the second RF powers are as illustrated with reference to FIGS. 3A-3G. During the first and second RF operations, phosphorous concentration at the top surface of the dielectric layer 127A-1 is adjusted. The phosphorous concentration in the dielectric layer 127A-1 is substantially constant throughout the dielectric layer 127A-1. Fluorine concentration at the top surface of the dielectric layer 127A-1 is adjusted to change in a linear manner throughout the dielectric layer 127A-1.
  • In some embodiments, several cycles are used to form the dielectric material 127A to a predetermined height. For example, operations with reference to FIGS. 6E to 6G are repeated as a cycle to form the dielectric layer 127A-1. An operation that repeats the cycle 6-7 times is used and results in the dielectric material 127A having the height H.
    • Semiconductor Structure at IMD Stage
  • FIG. 7 is an exemplary semiconductor structure 700 at an IMD stage, in accordance with some embodiments. The semiconductor structure 700 has a surface 122-2 not labeled in the drawing) and two conductors 160 on a substrate 120A. The surface 122-2 includes at least two portions 122-2A two portions 122-2C and a portion 122-2B. The portion 122-2A, 122-2B, and 122-2C correspond to the portion 122A, 122B, and 122C in FIG. 1, respectively. In some embodiments, the conductors 160 include metal. The substrate 120A corresponds to the substrate 120 in FIG. 1, and, in addition to silicon, also includes metal and dielectric.
  • A dielectric material 127 is on the portions 122-2C and the portion 122-2B. In some embodiments, a liner 125A (not shown in the drawing) is between the dielectric material 127 and the surface 122-2. The dielectric material 127 has a fluorine ion in the silicon glass matrix. The dielectric material 127 has a height H. In some embodiments, the height of the dielectric material 127 is dependant on a height of the conductor 160.
  • FIG. 8 is a fluorine concentration distribution in the dielectric material 127 according to some embodiments. The X-axis represents a depth of the dielectric material 127 with reference to a line AA′ in FIG. 7, and the unit is Å. Line 801 represents the fluorine concentration versus the depth of the dielectric material 127.
  • In the illustration of FIG. 8, the dielectric material 127 has a depth of about 1000 Å. The depth is also the height H of the dielectric material 127. For the embodiments as illustrated in FIG. 8, the fluorine concentration is thus illustrated from 0 Å to about 1000 Å, which is substantially equal to the height H of the dielectric material 127. Other values of the height are within the contemplated scope of the present disclosure. From 0 Å to about 1000 Å, the fluorine concentration changes from about 1×E20 Atoms/cm3 to about 2×E20 Atoms/cm3. Effectively, the fluorine concentration is lowest at the surface 130 and is highest at the portion 122-2B.
  • FIGS. 9A-9E are cross sectional views of the semiconductor structure 700 at the IMD stage illustrated in FIG. 7, according to some embodiments of the present disclosure.
  • In FIG. 9A, two conductors 160 are formed on a surface 121 of a substrate 120A. In some embodiments with referenced to FIG. 9A, the conductor 150 has a shape of a trapezoid. In FIG. 9B, a CVD process is used to form a dielectric layer 127-1 on the portions 122-2A, 122-2B and 122-2C. In some embodiments, the CVD process is a HDP or HARP process. Two overhangs 127-1 a are formed on top corners 164 of the conductors 160.
  • A same fluorine ion etch process illustrated in FIG. 3E is adopted to remove the overhangs 127-1 a. The thickness of the dielectric layer 127-1 is reduced to h1′ as illustrated in FIG. 9C.
  • FIG. 9D is used to illustrate an operation to treat a top surface of the dielectric layer 127-1 with plasma. In some embodiments with reference to FIG. 9D, the plasma includes oxygen ions.
  • In some embodiments, several cycles are used to form the dielectric material 127 to a predetermined height. For example, operations with reference to FIGS. 9B to 9D are repeated to form a cycle to form the dielectric layer 127-1. In some embodiments as illustrated in FIG. 9E, an operation that repeats the cycle 6-7 times is used to form the dielectric material 127 having the thickness H.
  • In some embodiments, a semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio that is substantially equal to or greater than a predetermined value.
  • In some embodiments, a semiconductor structure includes conductors and a spacer disposed on a sidewall of each conductor of the conductors. The semiconductor structure has a liner on the spacer and a top surface of each conductor of the conductors. The semiconductor structure also has a phosphorous doped dielectric material between two conductors and the phosphorous concentration throughout the phosphorous doped dielectric material is substantially constant.
  • In some embodiments, a method of manufacturing a semiconductor structure includes forming a surface, forming a dielectric layer over the surface, etching the dielectric layer, and treating a top surface of the dielectric layer with plasma.
  • The above description includes exemplary operations, but these operations are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, skipped, and/or eliminated as appropriate, in accordance with the spirit and scope of the disclosure. Accordingly, the scope of the disclosure should be determined with reference to the following claims, along with the full scope of equivalences to which such claims are entitled.

Claims (20)

What is claimed is:
1. A semiconductor structure, comprising:
a surface including a plurality of portions;
a dielectric material over the surface, wherein the dielectric material includes an aspect ratio that is substantially equal to or greater than a predetermined value.
2. The semiconductor structure of claim 1, further comprising a liner between a portion of the plurality of portions and the dielectric material.
3. The semiconductor structure of claim 1, wherein the dielectric material includes an impurity having a concentration distributed in a linear manner throughout the dielectric material.
4. The semiconductor of claim 3, wherein the impurity includes fluorine.
5. The semiconductor structure of claim 1, wherein the dielectric material has an impurity with a concentration substantially constant throughout the dielectric material.
6. The semiconductor of claim 5, wherein the impurity includes phosphorous.
7. The semiconductor of claim 1, further comprising a plurality of conductors wherein each of the conductors includes a sidewall that is a portion of the surface.
8. A semiconductor structure, comprising:
a plurality of conductors;
a spacer disposed on a sidewall of each of the plurality of conductors;
a liner on the spacer and a surface of each of the plurality of conductors; and
a phosphorous doped dielectric material between two conductors of the plurality of conductors, wherein a phosphorous concentration throughout the phosphorous doped dielectric material is substantially constant.
9. The semiconductor structure of claim 8, wherein the phosphorous doped dielectric material includes a thickness substantially equal to a height of the plurality of conductors.
10. The semiconductor structure of claim 8, wherein the phosphorous doped dielectric material includes an aspect ratio equal to or greater than about 2.4.
11. The semiconductor structure of claim 8, wherein the dielectric material has a width smaller than 30 nm.
12. The semiconductor structure of claim 8, wherein the phosphorous doped dielectric material further comprises fluorine.
13. The semiconductor structure of claim 12, wherein a fluorine concentration is distributed in a linear manner throughout the phosphorous doped dielectric material.
14. The semiconductor structure of claim 12, wherein a fluorine concentration is highest at an interface between the phosphorous doped dielectric material and the liner.
15. A method of manufacturing a semiconductor structure, comprising:
forming a surface on substrate;
forming a dielectric layer over the surface;
etching the dielectric layer; and
treating a top surface of the dielectric layer with plasma.
16. The method of claim 15, wherein treating the top surface of the dielectric layer is with phosphorous plasma.
17. The method of claim 15, wherein treating the top surface of the dielectric layer is with oxygen plasma.
18. The method of claim 15, wherein etching the dielectric layer is an NF3 etch.
19. The method of claim 15, further comprising repeating forming the dielectric layer.
20. The method of claim 15 further comprising forming a liner between the surface and the dielectric layer.
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