US20150031187A1 - Methods for forming a round bottom silicon trench recess for semiconductor applications - Google Patents
Methods for forming a round bottom silicon trench recess for semiconductor applications Download PDFInfo
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- US20150031187A1 US20150031187A1 US13/948,269 US201313948269A US2015031187A1 US 20150031187 A1 US20150031187 A1 US 20150031187A1 US 201313948269 A US201313948269 A US 201313948269A US 2015031187 A1 US2015031187 A1 US 2015031187A1
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- silicon substrate
- bias power
- etching
- active region
- gas mixture
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Images
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
Definitions
- Embodiments of the present invention generally relate to a method for forming a round bottom silicon trench recess, more specifically, to a method for forming a round bottom silicon trench recess in semiconductor fabrication applications.
- VLSI very large scale integration
- ULSI ultra large scale integration
- VLSI very large scale integration
- ULSI ultra large scale integration
- the multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
- the integration densities have been increased by decreasing transistor feature sizes, including gate length and channel length. Decreased channel length may result in short channel effects, which may increase an off-current threshold of the transistors ad can deteriorate refresh characteristics of memory devices having such transistors.
- forming a recess channel for semiconductor device manufacture has been introduced to extend the channel length of the transistors. The recess channel increases a channel length and reduces an ion-implantation concentration, thereby improving a refresh property of the semiconductor device.
- recess channels may also be configured to have different shapes or features formed within a trench, instead of conventional vertical only trench shapes, so as to further increase surface area or length of the channels to further improve refresh properties.
- formation of such shapes or features often require complicated and multiple process steps to complete the manufacture process, resulting in increases of manufacturing cycle time and cost with decreased process throughput.
- poor etching selectivity and control occurring during manufacturing processes for such shapes or features in the recess channels may undesirably result in an inaccurate profile control, thereby eventually leading to device failure.
- Embodiments of the present invention provide methods for etching a recess channel in a semiconductor substrate, for example, a silicon containing material.
- a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl 2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
- a method of forming a recess structure in a semiconductor substrate includes providing a silicon substrate into a processing chamber, wherein the silicon substrate has a patterned photoresist layer disposed thereon, exposing an active region formed in the silicon substrate, wherein the active region is defined between shallow trench isolations (STI) in the silicon substrate, supplying an etching gas mixture in the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, performing an anisotropic etching process by applying a RF bias power in the etching gas mixture, and performing an isotropic etching process by turning off the RF bias power in the etching gas mixture.
- STI shallow trench isolations
- a method of forming a recess structure in a semiconductor substrate includes providing a silicon substrate into a processing chamber, wherein the silicon substrate has a patterned photoresist layer disposed thereon, exposing an active region formed in the silicon substrate, wherein the active region is defined between shallow trench isolations (STI) in the silicon substrate, etching the active region in the silicon substrate with a RF bias power on to form a trench in the active region, and continuously etching the active region in the silicon substrate with the RF bias off to form a round feature to a bottom of the trench in the active region.
- STI shallow trench isolations
- FIG. 1 depicts a schematic cross-sectional view of a processing chamber that may be utilized to fabricate a recess channel structure in a semiconductor substrate in accordance with embodiments of the present invention
- FIG. 2 depicts a flow diagram of a method for manufacturing a recess channel structure in a semiconductor substrate in accordance with embodiments of the present invention.
- FIGS. 3A-3D depict a sequence for manufacturing a recess channel structure in a semiconductor substrate of FIG. 2 ;
- FIGS. 4A-4C depicts a flow diagram of magnified views of the recess channel structure formed in the semiconductor substrate depicted in FIGS. 3A-3C .
- the present invention provides a method and apparatus for manufacturing a recess channel structure in a semiconductor substrate. More specifically, the invention relates to methods of utilizing a single etching step to manufacture a recess channel structure in a semiconductor substrate in semiconductor device applications.
- the recess channel structure with a round bottom feature, e.g., a spherical-like structure, formed at a bottom of a trench is formed by using a single etching step to etch a silicon material defining the semiconductor substrate.
- the single etching step utilizes a pulsed RF bias power mode to incrementally etch the round bottom feature at the bottom of the trench, thereby forming a channel recess with round bottom feature, e.g., a spherical-like structure, in the semiconductor substrate.
- FIG. 1 is a sectional view of one embodiment of a processing chamber 100 suitable for manufacturing a recess channel structure in a semiconductor substrate.
- Suitable processing chambers that may be adapted for use with the teachings disclosed herein include, for example, a ENABLER® processing chamber, Decoupled Plasma Source (DPS®) II reactor, or other suitable reactors, available from Applied Materials, Inc. of Santa Clara, Calif.
- DPS® Decoupled Plasma Source
- the particular embodiment of the processing chamber 100 shown herein is provided for illustrative purposes and should not be used to limit the scope of the invention. It is contemplated that the invention may be utilized in other plasma processing chambers, including those from other manufacturers.
- the processing chamber 100 includes a chamber body 102 and a lid 104 which together enclose an interior volume 106 .
- the chamber body 102 is typically fabricated from aluminum, stainless steel or other suitable material.
- the chamber body 102 generally includes sidewalls 108 and a bottom 110 .
- a substrate access port (not shown) is generally defined in a sidewall 108 and a selectively sealed by a slit valve to facilitate entry and egress of a substrate 101 from the processing chamber 100 .
- An exhaust port 126 is defined in the chamber body 102 and couples the interior volume 106 to a pump system 128 .
- the pump system 128 generally includes one or more pumps and throttle valves utilized to evacuate and regulate the pressure of the interior volume 106 of the processing chamber 100 . In one embodiment, the pump system 128 maintains the pressure inside the interior volume 106 at operating pressures typically between about 10 mTorr to about 20 Torr.
- the lid 104 is sealingly supported on the sidewall 108 of the chamber body 102 .
- the lid 104 may be opened to allow excess to the interior volume 106 of the processing chamber 100 .
- the lid 104 includes a window 142 that facilitates optical process monitoring.
- the window 142 is comprised of quartz or other suitable material that is transmissive to a signal utilized by an optical monitoring system 140 .
- the optical monitoring system 140 is positioned to view at least one of the interior volume 106 of the chamber body 102 and/or the substrate support pedestal assembly 148 positioned on a substrate support pedestal assembly 148 through the window 142 .
- the optical monitoring system 140 is coupled to the lid 104 and facilitates an integrated deposition process that uses optical metrology to provide information that enables process adjustment to compensate for incoming substrate pattern feature inconsistencies (such as thickness, and the like), provide process state monitoring (such as plasma monitoring, temperature monitoring, and the like) as needed.
- One optical monitoring system that may be adapted to benefit from the invention is the EyeD® full-spectrum, interferometric metrology module, available from Applied Materials, Inc., of Santa Clara, Calif.
- a gas panel 158 is coupled to the processing chamber 100 to provide process and/or cleaning gases to the interior volume 106 .
- inlet ports 132 ′, 132 ′′ are provided in the lid 104 to allow gases to be delivered from the gas panel 158 to the interior volume 106 of the processing chamber 100 .
- a showerhead assembly 130 is coupled to an interior surface 114 of the lid 104 .
- the showerhead assembly 130 includes a plurality of apertures that allow the gases flowing through the showerhead assembly 130 from the inlet ports 132 ′, 132 ′′ into the interior volume 106 of the processing chamber 100 in a predefined distribution across the surface of the substrate support pedestal assembly 148 being processed in the processing chamber 100 .
- a remote plasma source 177 may be coupled to the gas panel 158 to facilitate dissociating gas mixture from a remote plasma prior to entering into the interior volume 106 for processing.
- a RF source power 143 is coupled through a matching network 141 to the showerhead assembly 130 .
- the RF source power 143 typically is capable of producing up to about 3000 W at a tunable frequency in a range from about 50 kHz to about 13.56 MHz.
- the showerhead assembly 130 additionally includes a region transmissive to an optical metrology signal.
- the optically transmissive region or passage 138 is suitable for allowing the optical monitoring system 140 to view the interior volume 106 and/or substrate 101 positioned on the substrate support pedestal assembly 148 .
- the passage 138 may be a material, an aperture or plurality of apertures formed or disposed in the showerhead assembly 130 that is substantially transmissive to the wavelengths of energy generated by, and reflected back to, the optical monitoring system 140 .
- the passage 138 includes a window 142 to prevent gas leakage from the passage 138 .
- the window 142 may be a sapphire plate, quartz plate or other suitable material.
- the window 142 may alternatively be disposed in the lid 104 .
- the showerhead assembly 130 is configured with a plurality of zones that allow for separate control of gas flowing into the interior volume 106 of the processing chamber 100 .
- the showerhead assembly 130 has an inner zone 134 and an outer zone 136 that are separately coupled to the gas panel 158 through separate inlets 132 ′, 132 ′′.
- the substrate support pedestal assembly 148 is disposed in the interior volume 106 of the processing chamber 100 below the showerhead assembly 130 .
- the substrate support pedestal assembly 148 holds the substrate 101 during processing.
- the substrate support pedestal assembly 148 generally includes a plurality of lift pins (not shown) disposed therethrough that are configured to lift the 101 from the substrate support pedestal assembly 148 and facilitate exchange of the substrate 101 with a robot (not shown) in a conventional manner.
- An inner liner 118 may closely circumscribe the periphery of the substrate support pedestal assembly 148 .
- the substrate support pedestal assembly 148 includes a mounting plate 162 , a base 164 and an electrostatic chuck 166 .
- the mounting plate 162 is coupled to the bottom 110 of the chamber body 102 and includes passages for routing utilities, such as fluids, power lines and sensor leads, among others, to the base 164 and the electrostatic chuck 166 .
- the electrostatic chuck 166 comprises at least one clamping electrode 180 for retaining a substrate support pedestal assembly 148 below showerhead assembly 130 .
- the electrostatic chuck 166 is driven by a chucking power source 182 to develop an electrostatic force that holds the substrate support pedestal assembly 148 to the chuck surface, as is conventionally known.
- the substrate support pedestal assembly 148 may be retained to the substrate support pedestal assembly 148 by clamping, vacuum or gravity.
- At least one of the base 164 or electrostatic chuck 166 may include at least one optional embedded heater 176 , at least one optional embedded isolator 174 and a plurality of conduits 168 , 170 to control the lateral temperature profile of the substrate support pedestal assembly 148 .
- the conduits 168 , 170 are fluidly coupled to a fluid source 172 that circulates a temperature regulating fluid therethrough.
- the heater 176 is regulated by a power source 178 .
- the conduits 168 , 170 and heater 176 are utilized to control the temperature of the base 164 , thereby heating and/or cooling the electrostatic chuck 166 , and thereby facilitating the operative control of the substrate 101 .
- the temperature of the electrostatic chuck 166 and the base 164 may be monitored using a plurality of temperature sensors 190 , 192 .
- the electrostatic chuck 166 may further comprise a plurality of gas passages (not shown), such as grooves, that are formed in a substrate support pedestal supporting surface of the chuck 166 and fluidly coupled to a source of a heat transfer (or backside) gas, such as He.
- a heat transfer (or backside) gas such as He.
- the backside gas is provided at controlled pressure into the gas passages to enhance the heat transfer between the electrostatic chuck 166 and the substrate support pedestal assembly 148 .
- the substrate support pedestal assembly 148 is configured as a cathode and includes an electrode 180 that is coupled to a RF power bias source 184 .
- the RF bias power source 184 is coupled between the electrode 180 disposed in the pedestal assembly 148 and another electrode, such as the showerhead assembly 130 or lid 104 of the chamber body 102 .
- the RF bias power excites and sustains a plasma discharge formed from the gases disposed in the processing region of the chamber body 102 .
- the RF bias power source 184 is coupled to the electrode 180 disposed in the pedestal assembly 148 through a matching network 188 .
- the signal generated by the RF bias power source 184 is delivered through matching network 188 to the substrate support pedestal assembly 148 through a single feed to ionize the gas mixture provided in the plasma processing chamber 100 , thereby providing ion energy necessary for performing a deposition or other plasma enhanced process.
- the RF bias power source 184 is generally capable of producing an RF signal having a frequency of from about 50 kHz to about 200 MHz and a power between about 0 Watts and about 5000 Watts.
- An additional bias power source 189 may be coupled to the electrode 180 to control the characteristics of the plasma. It is noted that although the example depicted in FIG. 1 includes one RF bias power source 184 and an additional optional RF bias power source 189 , it is noted that the RF bias power included in the processing chamber 100 may be in any number as needed.
- the substrate 101 is disposed on the substrate support pedestal assembly 148 in the plasma processing chamber 100 .
- a process gas and/or gas mixture is introduced into the chamber body 102 through the showerhead assembly 130 from the gas panel 158 .
- additional gases may be supplied from the remote plasma source 177 through the showerhead assembly 130 to the processing chamber 100 .
- a vacuum pump system 128 maintains the pressure inside the chamber body 102 while removing deposition by-products.
- the vacuum pump system 128 typically maintains an operating pressure between about 10 mTorr to about 20 Torr.
- the RF source power 143 and the RF bias power sources 184 , 189 provide RF source and bias power at separate frequencies to the anode and/or cathode through the matching network 141 and 188 respectively, thereby providing energy to form the plasma and excite the gas mixture in the chamber body 102 into ions to perform a plasma process.
- a controller 150 is coupled to the processing chamber 100 to control operation of the processing chamber 100 .
- the controller 150 includes a central processing unit (CPU) 152 , a memory 154 , and a support circuit 156 utilized to control the process sequence and regulate the gas flows from the gas panel 158 .
- the CPU 152 may be any form of general purpose computer processor that may be used in an industrial setting.
- the software routines can be stored in the memory 154 , such as random access memory, read only memory, floppy, or hard disk drive, or other form of digital storage.
- the support circuit 156 is conventionally coupled to the CPU 152 and may include cache, clock circuits, input/output systems, power supplies, and the like. Bi-directional communications between the controller 150 and the various components of the processing chamber 100 are handled through numerous signal cables.
- FIG. 1 only shows one exemplary configuration of various types of plasma processing chamber that can be used to practice the invention.
- different types of microwave power, magnetic power and bias power can be coupled into the plasma chamber using different coupling mechanisms.
- different types of plasma may be generated in a different chamber from the one in which the substrate is located, e.g., remote plasma source, and the plasma subsequently guided into the chamber using techniques known in the art.
- FIG. 2 is a flow diagram of a method 200 for manufacturing a recess channel structure 313 in a semiconductor substrate, which may be performed in a processing chamber, such as the processing chamber 100 depicted in FIG. 1 .
- FIGS. 3A-3D are schematic cross-sectional views illustrating a sequence for manufacturing the recess channel structure in the semiconductor substrate, such as the substrate 101 , depicted in FIG. 1 , according to the method 200 .
- the method 200 is described below with reference to a semiconductor substrate utilized to fabricate a channel recess structure with round bottom features, the method 200 may also be used to advantage in other trench recess process, such as recess for shallow trench isolations (STI) or any other suitable structures for semiconductor device fabrications.
- STI shallow trench isolations
- the method 200 begins at block 202 when the substrate 101 is transferred to and placed on the substrate support pedestal assembly 148 disposed in the processing chamber 100 , as depicted in FIG. 1 .
- the substrate 101 may have shallow trench isolation (STI) 302 formed in the substrate 101 defining an active region 304 in between the shallow trench isolation (STI) 302 , as shown in FIG. 3A .
- the active region 304 may include different types of active dopants doped in silicon materials, such as a single crystalline silicon, from the substrate 101 .
- a patterned photoresist layer 308 along with a patterned hardmask layer 306 may be disposed on the substrate 101 with defined openings 310 in the patterned photoresist layer 308 and the patterned hardmask layer 306 , exposing a surface 312 of the active region 304 for processing.
- the patterned photoresist layer 308 may comprise any suitable photosensitive resist materials, such as an e-beam resist (for example, a chemically amplified resist (CAR)), and deposited and patterned in any suitable manner.
- the patterned photoresist layer 308 may be deposited to a thickness between about 100 nm and about 3000 nm.
- the hardmask layer 306 may be any suitable dielectric materials, such as amorphous carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and the like.
- the hardmask layer 306 may include an amorphous carbon layer, or combinations of amorphous carbon layer and silicon oxide layer.
- the substrate 101 may have a substantially planar surface, an uneven surface, or a substantially planar surface having a structure formed thereon.
- the substrate 101 may be a material such as crystalline silicon (e.g., Si ⁇ 100> or Si ⁇ 111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire.
- SOI silicon on insulator
- the substrate 101 may have various dimensions, such as 200 mm, 300 mm, 450 mm or other diameter wafers, as well as rectangular or square panels.
- the substrate 101 may include a buried dielectric layer disposed on a silicon crystalline substrate.
- the substrate 101 may be a crystalline silicon substrate.
- the photoresist layer 308 and the hardmask layer 306 may be patterned by any suitable patterning techniques.
- an etching gas mixture is supplied into the processing chamber 100 to etch portions of the surface 312 of the active region 304 defined in the substrate 101 exposed by the patterned photoresist layer 308 and the hardmask layer 306 , as shown in FIG. 3B .
- the hardmask layer 306 may be patterned/etched together with the active region 304 continuously in a single chamber with the same process step, such as a single etchant chemistry, or separately etched by multiple steps in one or different etching processes as needed.
- the patterns/openings 310 from the photoresist layer 308 and the hardmask layer 306 are then transferred into the active region 304 through the etching process.
- the etching gas mixture supplied to etch the active region 304 in the semiconductor substrate 101 includes at least one halogen containing gas and a chlorine containing gas.
- Suitable examples of the halogen containing gas include HBr, CF 4 , CHF 3 , CH 2 F 2 , C 2 F 6 , C 2 F 8 , C 4 F 6 , SF 6 , NF 3 , and the like.
- Suitable examples of the chlorine containing gas include HCl, Cl 2 , and the like.
- HBr and Cl 2 are supplied in the etching gas mixture.
- Some halogen containing gases with carbon elements formed therein may also be utilized in the etching gas mixture.
- Halogen containing gases with carbon elements e.g., a carbon and halogen containing gas
- a carbon and halogen containing gas formed therein that may be supplied in the etching gas mixture
- CF 4 , CHF 3 may be supplied with the HBr and Cl 2 gas in the etching gas mixture to etch the active region 304 to form desired features/openings, such as a trench 318 , as part of a recess channel structure 313 in the substrate 101 .
- fluorine, bromide and chlorine elements are aggressive etchants, these elements, included in the etching gas mixture, are utilized to etch away portions of the active region 304 , forming the trench 318 in the active region 304 of the semiconductor substrate 101 , as shown in FIG. 3B .
- Carbon elements from the CF 4 , CHF 3 gas may provide a polymer source to assist passivating sidewalls 330 of the trench 318 .
- an inert gas may also be supplied as part of the etching gas mixture to assist the profile control as needed.
- the inert gas supplied in the gas mixture include Ar, He, Ne, Kr, Xe or the like.
- HBr gas and Cl 2 gas supplied in the etching gas mixture may be maintained at a predetermined ratio to yield an efficient etching rate.
- Carbon and halogen containing gas are supplied to protect the sidewalls from undesired etching.
- the HBr gas and Cl 2 gas are supplied in the etching gas mixture at a HBr:Cl 2 ratio of between about 5:1 and about 1:5.
- HBr gas may be supplied at a flow rate by volume between about 5 sccm and about 70 sccm.
- Cl 2 gas may be supplied at a flow rate by volume between about 5 sccm and about 70 sccm.
- CF 4 gas and CHF 3 gas are supplied in the etching gas mixture at a CHF 3 :CF 4 ratio of between about 5:1 to about 10:1.
- CF 4 gas may be supplied at a flow rate by volume between about 10 sccm and about 100 sccm.
- CHF 3 gas may be supplied at a flow rate by volume between about 30 sccm and about 200 sccm.
- a RF source power and a pulsed RF bias power are supplied to form a plasma from the gas mixture to form the trenches 318 in the active region 304 of the substrate 101 .
- the RF power including source and bias power, may be applied to the processing chamber to ignite a plasma in the etching gas mixture.
- the RF bias power may be set to a pulsed mode, intermittently applying RF bias power over different time periods during the etching process. The RF bias power may maintain in the pulsed mode and intermittently applied into the processing chamber until the predetermined process time period is expired.
- Pulsed RF bias power mode may maintain the RF bias power in an “on-off” pulsed mode.
- ions, radicals, or active species generated in the plasma become directional and may be accelerated toward the substrate, performing an anisotropic etching process, e.g., with directional ions, radicals, or active species generated in the plasma, to etch the trench 318 with substantially vertical sidewalls 330 (i.e., with a specific controlled direction) at a predetermined length 316 , as shown in FIG. 3B .
- ions, radicals, or active species may be uniformly distributed in the plasma, gradually falling onto the substrate without specific directionality, performing an isotropic etching process, e.g., with non-directional ions, to etch the substrate 101 .
- the isotropic etching process further etches the recess channel structure 313 outward of the sidewalls 330 , forming a round bottom feature 320 connecting to the vertical sidewall 330 of the recess channel structure 313 , as shown in FIG. 3C .
- the reactive ions may scatter radially and symmetrically to chemically react with the silicon materials in the active region 304 .
- the resultant round bottom feature 320 formed at the end of the recess channel structure 313 may have a lateral width 322 from a feature corner 325 of the round bottom feature 320 substantially similar to the vertical width 323 from a bottom 326 of the round bottom feature 320 , due the isotropic nature of the non-directional etching process.
- the etching process with pulsed RF bias mode is performed to form a recess channel structure 313 in the substrate 101 .
- an anisotropic etching process with RF bias power on is performed for a first period of time to form a trench 416 with substantially vertical sidewalls 410 and a planar bottom 411 in the substrate 101 with a first width 418 and a first length 402 , as shown in FIG. 4A .
- the RF bias power is then switched to be maintained in an off state to perform an isotropic etching process.
- the isotropic etching process etches the substrate 101 radially and symmetrically from the bottom 411 of the trench 416 , forming a bulb type, e.g., a sphere-like, round bottom feature 412 from the bottom 411 of the trench 416 with a first lateral width 406 that extends outward of the sidewalls 410 , as shown in FIG. 4B .
- a bulb type e.g., a sphere-like, round bottom feature 412 from the bottom 411 of the trench 416 with a first lateral width 406 that extends outward of the sidewalls 410 , as shown in FIG. 4B .
- the silicon materials from the sidewall 410 of the recess channel structure 313 along with the bottom 411 may both chemically react with the reactive ions.
- the first length 402 of the trench 416 may be reduced by the growth of the round bottom feature 412 to a second length 404 .
- the carbon and halogen containing gas supplied in the etching gas mixture may provide a source of polymer protection, protecting sidewalls 410 of the trench 416 from being overly attacked.
- a desired vertical sidewall 410 of the trench 416 may be maintained even the length 404 of the trench 416 is shortened.
- the pulsed mode of the RF bias power continues going on and off to interchangeably perform the anisotropic etching and isotropic etching process to the substrate 101 .
- the RF bias power switching causes a vertical width 420 along with the lateral width 408 of the round bottom feature 412 to grow until a desired dimension of the vertical width 420 and the lateral width 408 is reached, as shown in FIG. 4C .
- the second length 404 of the trench 416 may be further reduced to a third length 414 as the growing size of the round bottom feature 412 may unavoidably erode some length 414 of the trench 416 .
- the width 418 of the trench is maintained substantially the same throughout the pulsed mode of the RF bias power etching process due to the polymer layer protection from the carbon and halogen containing gases supplied in the etching gas mixture.
- the round bottom feature 412 extending outwards from the trench 416 with vertical profile, e.g., the recess channel structure 313 , may be obtained.
- a single etching process with modulated RF bias power pulsed mode as described herein may obtain the recess channel structure 313 with the desired vertical trench 416 and the round bottom feature 412 formed in-situ in an etching processing chamber.
- the flow rate of Cl 2 gas supplied in the gas mixture may also influence the formation of the round bottom feature 412 .
- Higher chlorine gas flow ratio in the etching gas mixture e.g., a higher gas flow rate of Cl 2 gas
- the flow rate of the chlorine gas is controlled to be supplied in the etching gas mixture at about 5 percent to about 20 percent by volume to the total flow rate, including all gases supplied, in the etching gas mixture.
- the number of the RF bias power pulses provided during the etching process may be increased as many times as needed until desired dimensions of the recess channel structure 313 is formed.
- the RF bias power pulse may have a duty cycle between about 5 percent (e.g., 5 percent on and 95 percent off) to about 70 percent (e.g., 70 percent on and 50 percent off), such as between about 5 percent and about 50 percent, such as between about 15 percent to 45 percent, at a RF bias frequency between about 500 Hz and about 10 kHz.
- the cycle of the RF bias power pulsed into the processing chamber may be controlled by a predetermined number of time periods performed. For example, the RF bias power may be pulsed between about every 0.1 milliseconds and about every 10 milliseconds. It is noted that the duty cycle of the RF bias power pulsed into the processing chamber may be repeated as many times as needed.
- the RF bias power may be controlled at about less than 500 Watts, such as less than 350 Watts, and a RF bias frequency between about 500 Hz and about 10 kHz. While maintaining the RF bias power in a pulsed mode, the RF source power and the etching gas mixture may be continuously applied to maintain smooth switch/transition between the anisotropic etching process and the isotropic etching process. In one embodiment, the RF source power may be supplied at the gas mixture between about 100 Watts and about 3000 Watts and at a frequency between about 400 kHz and about 13.56 MHz.
- the RF source power is maintained at about 1500 Watts while the RF bias power is maintained at about 170 Watts.
- the RF source power frequency is controlled at about 13.56 Hz and the RF bias power frequency is controlled at about 13.56 MHz or 2 MHz.
- the pressure of the processing chamber may be controlled at between about 0.5 milliTorr and about 500 milliTorr, such as between about 1 milliTorr and about 100 milliTorr, for example about 20 milliTorr.
- the etching process is performed to etch the substrate 101 until desired dimensions of the vertical trench 318 and the round bottom feature 320 is formed, as shown in FIG. 3C .
- the vertical trench 318 may have a width 329 between about 10 nm and about 25 nm, and a length 340 between about 60 nm and about 150 nm.
- the round bottom feature 320 may have a vertical width 323 between about 15 nm and about 50 nm and a lateral width 322 between about 15 nm and about 35 nm.
- the end point of the etching process may be controlled by time mode or other suitable methods.
- the etching process may be terminated after performing between about 50 seconds and about 500 seconds.
- the etching process may be performed between about 1 seconds and about 1000 seconds.
- the etching process may be terminated by determination from an endpoint detector, such as an OES detector or other suitable detector as needed.
- the photoresist layer 308 along with the hardmask layer 306 may be removed.
- the remaining photoresist layer 308 is removed by ashing.
- the removal process may be performed in-situ in the processing chamber 100 in which the etching method was performed.
- the ashing or photoresist layer removal process may be eliminated.
- a gate structure 350 may then be formed on the recess channel structure 313 as needed, as shown in FIG. 3D . It is noted that although the recess structure as described herein is utilized to form a channel recess under a gate structure, it is contemplated that the recess structure may be used in any structure, substrates, or any applications as needed.
- a method for manufacturing a recess channel structure in a semiconductor substrate has been provided that advantageously improves manufacture productivity, process control, and feature dimension accuracy.
- a channel recess structure may be formed in a semiconductor substrate in a single processing chamber.
- the method of forming the channel recess structure advantageously facilitates fabrication of channel recess structure to be connected to a gate structure with accurate critical dimensions for advanced memory fabrication and applications.
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Abstract
Description
- 1. Field
- Embodiments of the present invention generally relate to a method for forming a round bottom silicon trench recess, more specifically, to a method for forming a round bottom silicon trench recess in semiconductor fabrication applications.
- 2. Description of the Related Art
- Reliably producing submicron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
- As circuit densities increase for next generation devices, the integration densities have been increased by decreasing transistor feature sizes, including gate length and channel length. Decreased channel length may result in short channel effects, which may increase an off-current threshold of the transistors ad can deteriorate refresh characteristics of memory devices having such transistors. In order to eliminate such problems, forming a recess channel for semiconductor device manufacture has been introduced to extend the channel length of the transistors. The recess channel increases a channel length and reduces an ion-implantation concentration, thereby improving a refresh property of the semiconductor device.
- In some instances, recess channels may also be configured to have different shapes or features formed within a trench, instead of conventional vertical only trench shapes, so as to further increase surface area or length of the channels to further improve refresh properties. However, formation of such shapes or features often require complicated and multiple process steps to complete the manufacture process, resulting in increases of manufacturing cycle time and cost with decreased process throughput. Furthermore, poor etching selectivity and control occurring during manufacturing processes for such shapes or features in the recess channels may undesirably result in an inaccurate profile control, thereby eventually leading to device failure.
- Thus, there is a need for a channel recess etch process for etching a recess area in a semiconductor substrate with low cost and precise process control.
- Embodiments of the present invention provide methods for etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
- In another embodiment, a method of forming a recess structure in a semiconductor substrate includes providing a silicon substrate into a processing chamber, wherein the silicon substrate has a patterned photoresist layer disposed thereon, exposing an active region formed in the silicon substrate, wherein the active region is defined between shallow trench isolations (STI) in the silicon substrate, supplying an etching gas mixture in the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, performing an anisotropic etching process by applying a RF bias power in the etching gas mixture, and performing an isotropic etching process by turning off the RF bias power in the etching gas mixture.
- In yet another embodiment, a method of forming a recess structure in a semiconductor substrate includes providing a silicon substrate into a processing chamber, wherein the silicon substrate has a patterned photoresist layer disposed thereon, exposing an active region formed in the silicon substrate, wherein the active region is defined between shallow trench isolations (STI) in the silicon substrate, etching the active region in the silicon substrate with a RF bias power on to form a trench in the active region, and continuously etching the active region in the silicon substrate with the RF bias off to form a round feature to a bottom of the trench in the active region.
- So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
-
FIG. 1 depicts a schematic cross-sectional view of a processing chamber that may be utilized to fabricate a recess channel structure in a semiconductor substrate in accordance with embodiments of the present invention; -
FIG. 2 depicts a flow diagram of a method for manufacturing a recess channel structure in a semiconductor substrate in accordance with embodiments of the present invention; and -
FIGS. 3A-3D depict a sequence for manufacturing a recess channel structure in a semiconductor substrate ofFIG. 2 ; and -
FIGS. 4A-4C depicts a flow diagram of magnified views of the recess channel structure formed in the semiconductor substrate depicted inFIGS. 3A-3C . - To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
- It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
- The present invention provides a method and apparatus for manufacturing a recess channel structure in a semiconductor substrate. More specifically, the invention relates to methods of utilizing a single etching step to manufacture a recess channel structure in a semiconductor substrate in semiconductor device applications. In one embodiment, the recess channel structure with a round bottom feature, e.g., a spherical-like structure, formed at a bottom of a trench is formed by using a single etching step to etch a silicon material defining the semiconductor substrate. The single etching step utilizes a pulsed RF bias power mode to incrementally etch the round bottom feature at the bottom of the trench, thereby forming a channel recess with round bottom feature, e.g., a spherical-like structure, in the semiconductor substrate.
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FIG. 1 is a sectional view of one embodiment of aprocessing chamber 100 suitable for manufacturing a recess channel structure in a semiconductor substrate. Suitable processing chambers that may be adapted for use with the teachings disclosed herein include, for example, a ENABLER® processing chamber, Decoupled Plasma Source (DPS®) II reactor, or other suitable reactors, available from Applied Materials, Inc. of Santa Clara, Calif. The particular embodiment of theprocessing chamber 100 shown herein is provided for illustrative purposes and should not be used to limit the scope of the invention. It is contemplated that the invention may be utilized in other plasma processing chambers, including those from other manufacturers. - The
processing chamber 100 includes achamber body 102 and alid 104 which together enclose aninterior volume 106. Thechamber body 102 is typically fabricated from aluminum, stainless steel or other suitable material. Thechamber body 102 generally includessidewalls 108 and abottom 110. A substrate access port (not shown) is generally defined in asidewall 108 and a selectively sealed by a slit valve to facilitate entry and egress of asubstrate 101 from theprocessing chamber 100. Anexhaust port 126 is defined in thechamber body 102 and couples theinterior volume 106 to apump system 128. Thepump system 128 generally includes one or more pumps and throttle valves utilized to evacuate and regulate the pressure of theinterior volume 106 of theprocessing chamber 100. In one embodiment, thepump system 128 maintains the pressure inside theinterior volume 106 at operating pressures typically between about 10 mTorr to about 20 Torr. - The
lid 104 is sealingly supported on thesidewall 108 of thechamber body 102. Thelid 104 may be opened to allow excess to theinterior volume 106 of theprocessing chamber 100. Thelid 104 includes awindow 142 that facilitates optical process monitoring. In one embodiment, thewindow 142 is comprised of quartz or other suitable material that is transmissive to a signal utilized by anoptical monitoring system 140. - The
optical monitoring system 140 is positioned to view at least one of theinterior volume 106 of thechamber body 102 and/or the substratesupport pedestal assembly 148 positioned on a substratesupport pedestal assembly 148 through thewindow 142. In one embodiment, theoptical monitoring system 140 is coupled to thelid 104 and facilitates an integrated deposition process that uses optical metrology to provide information that enables process adjustment to compensate for incoming substrate pattern feature inconsistencies (such as thickness, and the like), provide process state monitoring (such as plasma monitoring, temperature monitoring, and the like) as needed. One optical monitoring system that may be adapted to benefit from the invention is the EyeD® full-spectrum, interferometric metrology module, available from Applied Materials, Inc., of Santa Clara, Calif. - A
gas panel 158 is coupled to theprocessing chamber 100 to provide process and/or cleaning gases to theinterior volume 106. In the embodiment depicted inFIG. 1 ,inlet ports 132′, 132″ are provided in thelid 104 to allow gases to be delivered from thegas panel 158 to theinterior volume 106 of theprocessing chamber 100. - A
showerhead assembly 130 is coupled to aninterior surface 114 of thelid 104. Theshowerhead assembly 130 includes a plurality of apertures that allow the gases flowing through theshowerhead assembly 130 from theinlet ports 132′, 132″ into theinterior volume 106 of theprocessing chamber 100 in a predefined distribution across the surface of the substratesupport pedestal assembly 148 being processed in theprocessing chamber 100. - A
remote plasma source 177 may be coupled to thegas panel 158 to facilitate dissociating gas mixture from a remote plasma prior to entering into theinterior volume 106 for processing. ARF source power 143 is coupled through amatching network 141 to theshowerhead assembly 130. TheRF source power 143 typically is capable of producing up to about 3000 W at a tunable frequency in a range from about 50 kHz to about 13.56 MHz. - The
showerhead assembly 130 additionally includes a region transmissive to an optical metrology signal. The optically transmissive region orpassage 138 is suitable for allowing theoptical monitoring system 140 to view theinterior volume 106 and/orsubstrate 101 positioned on the substratesupport pedestal assembly 148. Thepassage 138 may be a material, an aperture or plurality of apertures formed or disposed in theshowerhead assembly 130 that is substantially transmissive to the wavelengths of energy generated by, and reflected back to, theoptical monitoring system 140. In one embodiment, thepassage 138 includes awindow 142 to prevent gas leakage from thepassage 138. Thewindow 142 may be a sapphire plate, quartz plate or other suitable material. Thewindow 142 may alternatively be disposed in thelid 104. - In one embodiment, the
showerhead assembly 130 is configured with a plurality of zones that allow for separate control of gas flowing into theinterior volume 106 of theprocessing chamber 100. In the embodimentFIG. 1 , theshowerhead assembly 130 has aninner zone 134 and anouter zone 136 that are separately coupled to thegas panel 158 throughseparate inlets 132′, 132″. - The substrate
support pedestal assembly 148 is disposed in theinterior volume 106 of theprocessing chamber 100 below theshowerhead assembly 130. The substratesupport pedestal assembly 148 holds thesubstrate 101 during processing. The substratesupport pedestal assembly 148 generally includes a plurality of lift pins (not shown) disposed therethrough that are configured to lift the 101 from the substratesupport pedestal assembly 148 and facilitate exchange of thesubstrate 101 with a robot (not shown) in a conventional manner. Aninner liner 118 may closely circumscribe the periphery of the substratesupport pedestal assembly 148. - In one embodiment, the substrate
support pedestal assembly 148 includes a mountingplate 162, abase 164 and anelectrostatic chuck 166. The mountingplate 162 is coupled to thebottom 110 of thechamber body 102 and includes passages for routing utilities, such as fluids, power lines and sensor leads, among others, to thebase 164 and theelectrostatic chuck 166. Theelectrostatic chuck 166 comprises at least oneclamping electrode 180 for retaining a substratesupport pedestal assembly 148 belowshowerhead assembly 130. Theelectrostatic chuck 166 is driven by a chuckingpower source 182 to develop an electrostatic force that holds the substratesupport pedestal assembly 148 to the chuck surface, as is conventionally known. Alternatively, the substratesupport pedestal assembly 148 may be retained to the substratesupport pedestal assembly 148 by clamping, vacuum or gravity. - At least one of the base 164 or
electrostatic chuck 166 may include at least one optional embeddedheater 176, at least one optional embedded isolator 174 and a plurality ofconduits 168, 170 to control the lateral temperature profile of the substratesupport pedestal assembly 148. Theconduits 168, 170 are fluidly coupled to afluid source 172 that circulates a temperature regulating fluid therethrough. Theheater 176 is regulated by apower source 178. Theconduits 168, 170 andheater 176 are utilized to control the temperature of thebase 164, thereby heating and/or cooling theelectrostatic chuck 166, and thereby facilitating the operative control of thesubstrate 101. The temperature of theelectrostatic chuck 166 and the base 164 may be monitored using a plurality oftemperature sensors electrostatic chuck 166 may further comprise a plurality of gas passages (not shown), such as grooves, that are formed in a substrate support pedestal supporting surface of thechuck 166 and fluidly coupled to a source of a heat transfer (or backside) gas, such as He. In operation, the backside gas is provided at controlled pressure into the gas passages to enhance the heat transfer between theelectrostatic chuck 166 and the substratesupport pedestal assembly 148. - In one embodiment, the substrate
support pedestal assembly 148 is configured as a cathode and includes anelectrode 180 that is coupled to a RFpower bias source 184. The RF biaspower source 184 is coupled between theelectrode 180 disposed in thepedestal assembly 148 and another electrode, such as theshowerhead assembly 130 orlid 104 of thechamber body 102. The RF bias power excites and sustains a plasma discharge formed from the gases disposed in the processing region of thechamber body 102. In the embodiment depicted inFIG. 1 , the RFbias power source 184 is coupled to theelectrode 180 disposed in thepedestal assembly 148 through amatching network 188. The signal generated by the RFbias power source 184 is delivered throughmatching network 188 to the substratesupport pedestal assembly 148 through a single feed to ionize the gas mixture provided in theplasma processing chamber 100, thereby providing ion energy necessary for performing a deposition or other plasma enhanced process. The RF biaspower source 184 is generally capable of producing an RF signal having a frequency of from about 50 kHz to about 200 MHz and a power between about 0 Watts and about 5000 Watts. An additionalbias power source 189 may be coupled to theelectrode 180 to control the characteristics of the plasma. It is noted that although the example depicted inFIG. 1 includes one RFbias power source 184 and an additional optional RF biaspower source 189, it is noted that the RF bias power included in theprocessing chamber 100 may be in any number as needed. - In one mode of operation, the
substrate 101 is disposed on the substratesupport pedestal assembly 148 in theplasma processing chamber 100. A process gas and/or gas mixture is introduced into thechamber body 102 through theshowerhead assembly 130 from thegas panel 158. Furthermore, additional gases may be supplied from theremote plasma source 177 through theshowerhead assembly 130 to theprocessing chamber 100. Avacuum pump system 128 maintains the pressure inside thechamber body 102 while removing deposition by-products. Thevacuum pump system 128 typically maintains an operating pressure between about 10 mTorr to about 20 Torr. - The
RF source power 143 and the RF biaspower sources matching network chamber body 102 into ions to perform a plasma process. - A
controller 150 is coupled to theprocessing chamber 100 to control operation of theprocessing chamber 100. Thecontroller 150 includes a central processing unit (CPU) 152, amemory 154, and asupport circuit 156 utilized to control the process sequence and regulate the gas flows from thegas panel 158. TheCPU 152 may be any form of general purpose computer processor that may be used in an industrial setting. The software routines can be stored in thememory 154, such as random access memory, read only memory, floppy, or hard disk drive, or other form of digital storage. Thesupport circuit 156 is conventionally coupled to theCPU 152 and may include cache, clock circuits, input/output systems, power supplies, and the like. Bi-directional communications between thecontroller 150 and the various components of theprocessing chamber 100 are handled through numerous signal cables. -
FIG. 1 only shows one exemplary configuration of various types of plasma processing chamber that can be used to practice the invention. For example, different types of microwave power, magnetic power and bias power can be coupled into the plasma chamber using different coupling mechanisms. In some applications, different types of plasma may be generated in a different chamber from the one in which the substrate is located, e.g., remote plasma source, and the plasma subsequently guided into the chamber using techniques known in the art. -
FIG. 2 is a flow diagram of amethod 200 for manufacturing arecess channel structure 313 in a semiconductor substrate, which may be performed in a processing chamber, such as theprocessing chamber 100 depicted inFIG. 1 .FIGS. 3A-3D are schematic cross-sectional views illustrating a sequence for manufacturing the recess channel structure in the semiconductor substrate, such as thesubstrate 101, depicted inFIG. 1 , according to themethod 200. Although themethod 200 is described below with reference to a semiconductor substrate utilized to fabricate a channel recess structure with round bottom features, themethod 200 may also be used to advantage in other trench recess process, such as recess for shallow trench isolations (STI) or any other suitable structures for semiconductor device fabrications. - The
method 200, which may be stored in computer readable form in thememory 154 of thecontroller 150 or other storage medium, begins atblock 202 when thesubstrate 101 is transferred to and placed on the substratesupport pedestal assembly 148 disposed in theprocessing chamber 100, as depicted inFIG. 1 . - The
substrate 101 may have shallow trench isolation (STI) 302 formed in thesubstrate 101 defining anactive region 304 in between the shallow trench isolation (STI) 302, as shown inFIG. 3A . Theactive region 304 may include different types of active dopants doped in silicon materials, such as a single crystalline silicon, from thesubstrate 101. A patternedphotoresist layer 308 along with a patternedhardmask layer 306 may be disposed on thesubstrate 101 with definedopenings 310 in the patternedphotoresist layer 308 and the patternedhardmask layer 306, exposing asurface 312 of theactive region 304 for processing. The patternedphotoresist layer 308 may comprise any suitable photosensitive resist materials, such as an e-beam resist (for example, a chemically amplified resist (CAR)), and deposited and patterned in any suitable manner. The patternedphotoresist layer 308 may be deposited to a thickness between about 100 nm and about 3000 nm. Thehardmask layer 306 may be any suitable dielectric materials, such as amorphous carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and the like. In one particular embodiment, thehardmask layer 306 may include an amorphous carbon layer, or combinations of amorphous carbon layer and silicon oxide layer. - In one embodiment, the
substrate 101 may have a substantially planar surface, an uneven surface, or a substantially planar surface having a structure formed thereon. Thesubstrate 101 may be a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire. Thesubstrate 101 may have various dimensions, such as 200 mm, 300 mm, 450 mm or other diameter wafers, as well as rectangular or square panels. Unless otherwise noted, embodiments and examples described herein are conducted on substrates having a diameter between about 200 mm and about 500 mm. In the embodiment wherein a SOI structure is utilized for thesubstrate 101, thesubstrate 101 may include a buried dielectric layer disposed on a silicon crystalline substrate. In the embodiment depicted herein, thesubstrate 101 may be a crystalline silicon substrate. Thephotoresist layer 308 and thehardmask layer 306 may be patterned by any suitable patterning techniques. - At
block 204, an etching gas mixture is supplied into theprocessing chamber 100 to etch portions of thesurface 312 of theactive region 304 defined in thesubstrate 101 exposed by the patternedphotoresist layer 308 and thehardmask layer 306, as shown inFIG. 3B . In some embodiments, thehardmask layer 306 may be patterned/etched together with theactive region 304 continuously in a single chamber with the same process step, such as a single etchant chemistry, or separately etched by multiple steps in one or different etching processes as needed. The patterns/openings 310 from thephotoresist layer 308 and thehardmask layer 306 are then transferred into theactive region 304 through the etching process. - In one embodiment, the etching gas mixture supplied to etch the
active region 304 in thesemiconductor substrate 101 includes at least one halogen containing gas and a chlorine containing gas. Suitable examples of the halogen containing gas include HBr, CF4, CHF3, CH2F2, C2F6, C2F8, C4F6, SF6, NF3, and the like. Suitable examples of the chlorine containing gas include HCl, Cl2, and the like. In some embodiments, HBr and Cl2 are supplied in the etching gas mixture. Some halogen containing gases with carbon elements formed therein may also be utilized in the etching gas mixture. Halogen containing gases with carbon elements (e.g., a carbon and halogen containing gas) formed therein that may be supplied in the etching gas mixture include CF4, CHF3, CH2F2, C2F6, C2F8, C4F6 and the like. - In one example, CF4, CHF3 may be supplied with the HBr and Cl2 gas in the etching gas mixture to etch the
active region 304 to form desired features/openings, such as atrench 318, as part of arecess channel structure 313 in thesubstrate 101. As the fluorine, bromide and chlorine elements are aggressive etchants, these elements, included in the etching gas mixture, are utilized to etch away portions of theactive region 304, forming thetrench 318 in theactive region 304 of thesemiconductor substrate 101, as shown inFIG. 3B . Carbon elements from the CF4, CHF3 gas may provide a polymer source to assist passivatingsidewalls 330 of thetrench 318. - In an alternative embodiment, an inert gas may also be supplied as part of the etching gas mixture to assist the profile control as needed. Examples of the inert gas supplied in the gas mixture include Ar, He, Ne, Kr, Xe or the like.
- In one embodiment, HBr gas and Cl2 gas supplied in the etching gas mixture may be maintained at a predetermined ratio to yield an efficient etching rate. Carbon and halogen containing gas are supplied to protect the sidewalls from undesired etching. In an exemplary embodiment, the HBr gas and Cl2 gas are supplied in the etching gas mixture at a HBr:Cl2 ratio of between about 5:1 and about 1:5. Alternatively, HBr gas may be supplied at a flow rate by volume between about 5 sccm and about 70 sccm. Cl2 gas may be supplied at a flow rate by volume between about 5 sccm and about 70 sccm.
- Additionally, CF4 gas and CHF3 gas are supplied in the etching gas mixture at a CHF3:CF4 ratio of between about 5:1 to about 10:1. Alternatively, CF4 gas may be supplied at a flow rate by volume between about 10 sccm and about 100 sccm. CHF3 gas may be supplied at a flow rate by volume between about 30 sccm and about 200 sccm.
- At
block 206, after the etching gas mixture is supplied into the etching gas mixture, a RF source power and a pulsed RF bias power are supplied to form a plasma from the gas mixture to form thetrenches 318 in theactive region 304 of thesubstrate 101. The RF power, including source and bias power, may be applied to the processing chamber to ignite a plasma in the etching gas mixture. In one embodiment, the RF bias power may be set to a pulsed mode, intermittently applying RF bias power over different time periods during the etching process. The RF bias power may maintain in the pulsed mode and intermittently applied into the processing chamber until the predetermined process time period is expired. - It is believed that utilizing pulse mode for applying RF bias power to produce plasma in the gas mixture may assist producing alternating isotropic and anisotropic etching process during the overall etching process. Pulsed RF bias power mode may maintain the RF bias power in an “on-off” pulsed mode. In the period when the RF bias power is on, ions, radicals, or active species generated in the plasma become directional and may be accelerated toward the substrate, performing an anisotropic etching process, e.g., with directional ions, radicals, or active species generated in the plasma, to etch the
trench 318 with substantially vertical sidewalls 330 (i.e., with a specific controlled direction) at apredetermined length 316, as shown inFIG. 3B . Subsequently, in the period when the RF bias power is off, ions, radicals, or active species may be uniformly distributed in the plasma, gradually falling onto the substrate without specific directionality, performing an isotropic etching process, e.g., with non-directional ions, to etch thesubstrate 101. The isotropic etching process further etches therecess channel structure 313 outward of thesidewalls 330, forming around bottom feature 320 connecting to thevertical sidewall 330 of therecess channel structure 313, as shown inFIG. 3C . As the ions, radicals, or active species generated by the isotropic etching process (e.g., with RF pulsed power off) are with no specific directions, the reactive ions may scatter radially and symmetrically to chemically react with the silicon materials in theactive region 304. Thus, the resultant roundbottom feature 320 formed at the end of therecess channel structure 313 may have alateral width 322 from afeature corner 325 of theround bottom feature 320 substantially similar to thevertical width 323 from abottom 326 of theround bottom feature 320, due the isotropic nature of the non-directional etching process. - Referring first to
FIGS. 4A-4C , the etching process with pulsed RF bias mode is performed to form arecess channel structure 313 in thesubstrate 101. When the etching process first starts, an anisotropic etching process with RF bias power on is performed for a first period of time to form atrench 416 with substantiallyvertical sidewalls 410 and aplanar bottom 411 in thesubstrate 101 with afirst width 418 and afirst length 402, as shown inFIG. 4A . After the first predetermined period of time, the RF bias power is then switched to be maintained in an off state to perform an isotropic etching process. As discussed above, the isotropic etching process etches thesubstrate 101 radially and symmetrically from thebottom 411 of thetrench 416, forming a bulb type, e.g., a sphere-like, roundbottom feature 412 from thebottom 411 of thetrench 416 with afirst lateral width 406 that extends outward of thesidewalls 410, as shown inFIG. 4B . - During the isotropic etching process (e.g., with RF bias power off), as the reactive ions randomly attack silicon materials in the
substrate 101 without specific directionality, the silicon materials from thesidewall 410 of therecess channel structure 313 along with the bottom 411 may both chemically react with the reactive ions. As thelateral width 406 of theround bottom feature 412 increases during the isotropic etching process, thefirst length 402 of thetrench 416 may be reduced by the growth of theround bottom feature 412 to asecond length 404. In the mean while, the carbon and halogen containing gas supplied in the etching gas mixture may provide a source of polymer protection, protectingsidewalls 410 of thetrench 416 from being overly attacked. Thus, a desiredvertical sidewall 410 of thetrench 416 may be maintained even thelength 404 of thetrench 416 is shortened. - Subsequently, the pulsed mode of the RF bias power continues going on and off to interchangeably perform the anisotropic etching and isotropic etching process to the
substrate 101. The RF bias power switching causes avertical width 420 along with thelateral width 408 of theround bottom feature 412 to grow until a desired dimension of thevertical width 420 and thelateral width 408 is reached, as shown inFIG. 4C . Similarly, thesecond length 404 of thetrench 416 may be further reduced to athird length 414 as the growing size of theround bottom feature 412 may unavoidably erode somelength 414 of thetrench 416. Thewidth 418 of the trench is maintained substantially the same throughout the pulsed mode of the RF bias power etching process due to the polymer layer protection from the carbon and halogen containing gases supplied in the etching gas mixture. - Thus, by modulating the pulsed mode of the RF power applied to the etching gas mixture, the
round bottom feature 412 extending outwards from thetrench 416 with vertical profile, e.g., therecess channel structure 313, may be obtained. Unlike the conventional practice utilizing several process steps, likely including deposition processes and several steps of etching processes, to fabricate both thevertical trench 416 and theround bottom feature 412, a single etching process with modulated RF bias power pulsed mode as described herein may obtain therecess channel structure 313 with the desiredvertical trench 416 and theround bottom feature 412 formed in-situ in an etching processing chamber. - Furthermore, it is believed that the flow rate of Cl2 gas supplied in the gas mixture may also influence the formation of the
round bottom feature 412. Higher chlorine gas flow ratio in the etching gas mixture (e.g., a higher gas flow rate of Cl2 gas) assists providing aggressive etchants, e.g., chlorine ions, during the isotropic etching process, thereby expediting the round bottom feature formation process. In one embodiment, the flow rate of the chlorine gas is controlled to be supplied in the etching gas mixture at about 5 percent to about 20 percent by volume to the total flow rate, including all gases supplied, in the etching gas mixture. - Referring back to
FIG. 3C , the number of the RF bias power pulses provided during the etching process may be increased as many times as needed until desired dimensions of therecess channel structure 313 is formed. In one embodiment, the RF bias power pulse may have a duty cycle between about 5 percent (e.g., 5 percent on and 95 percent off) to about 70 percent (e.g., 70 percent on and 50 percent off), such as between about 5 percent and about 50 percent, such as between about 15 percent to 45 percent, at a RF bias frequency between about 500 Hz and about 10 kHz. Alternatively, the cycle of the RF bias power pulsed into the processing chamber may be controlled by a predetermined number of time periods performed. For example, the RF bias power may be pulsed between about every 0.1 milliseconds and about every 10 milliseconds. It is noted that the duty cycle of the RF bias power pulsed into the processing chamber may be repeated as many times as needed. - In one embodiment, the RF bias power may be controlled at about less than 500 Watts, such as less than 350 Watts, and a RF bias frequency between about 500 Hz and about 10 kHz. While maintaining the RF bias power in a pulsed mode, the RF source power and the etching gas mixture may be continuously applied to maintain smooth switch/transition between the anisotropic etching process and the isotropic etching process. In one embodiment, the RF source power may be supplied at the gas mixture between about 100 Watts and about 3000 Watts and at a frequency between about 400 kHz and about 13.56 MHz.
- In one particular embodiment, the RF source power is maintained at about 1500 Watts while the RF bias power is maintained at about 170 Watts. The RF source power frequency is controlled at about 13.56 Hz and the RF bias power frequency is controlled at about 13.56 MHz or 2 MHz.
- Several process parameters may also be controlled while supplying the etching gas mixture and the pulsed RF bias power mode to perform the etching process. The pressure of the processing chamber may be controlled at between about 0.5 milliTorr and about 500 milliTorr, such as between about 1 milliTorr and about 100 milliTorr, for example about 20 milliTorr.
- The etching process is performed to etch the
substrate 101 until desired dimensions of thevertical trench 318 and theround bottom feature 320 is formed, as shown inFIG. 3C . In one embodiment, thevertical trench 318 may have awidth 329 between about 10 nm and about 25 nm, and alength 340 between about 60 nm and about 150 nm. Theround bottom feature 320 may have avertical width 323 between about 15 nm and about 50 nm and alateral width 322 between about 15 nm and about 35 nm. The end point of the etching process may be controlled by time mode or other suitable methods. For example, the etching process may be terminated after performing between about 50 seconds and about 500 seconds. In this particular embodiment, the etching process may be performed between about 1 seconds and about 1000 seconds. In another embodiment, the etching process may be terminated by determination from an endpoint detector, such as an OES detector or other suitable detector as needed. - After the desired profile and/or the structure is formed in the
active region 304 of thesubstrate 101, thephotoresist layer 308 along with thehardmask layer 306 may be removed. In one embodiment, the remainingphotoresist layer 308 is removed by ashing. The removal process may be performed in-situ in theprocessing chamber 100 in which the etching method was performed. In the embodiment wherein thephotoresist layer 314 is completely consumed during the etching process, the ashing or photoresist layer removal process may be eliminated. - After the
photoresist layer 308 is removed, agate structure 350 may then be formed on therecess channel structure 313 as needed, as shown inFIG. 3D . It is noted that although the recess structure as described herein is utilized to form a channel recess under a gate structure, it is contemplated that the recess structure may be used in any structure, substrates, or any applications as needed. - Thus, a method for manufacturing a recess channel structure in a semiconductor substrate has been provided that advantageously improves manufacture productivity, process control, and feature dimension accuracy. By using one single etching step, a channel recess structure may be formed in a semiconductor substrate in a single processing chamber. The method of forming the channel recess structure advantageously facilitates fabrication of channel recess structure to be connected to a gate structure with accurate critical dimensions for advanced memory fabrication and applications.
- While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (20)
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