US20140368261A1 - Semiconductor devices and semiconductor systems including the same - Google Patents
Semiconductor devices and semiconductor systems including the same Download PDFInfo
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- US20140368261A1 US20140368261A1 US14/156,904 US201414156904A US2014368261A1 US 20140368261 A1 US20140368261 A1 US 20140368261A1 US 201414156904 A US201414156904 A US 201414156904A US 2014368261 A1 US2014368261 A1 US 2014368261A1
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- signal
- fuse
- pulse
- generated
- selection
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
Definitions
- Embodiments of the present disclosure relate to semiconductor integrated circuits and, more particularly, to semiconductor devices and semiconductor systems including the same.
- the option processing method may include a bonding option, a metal option and a fuse option.
- the fuse option may be widely used to replace failed memory cells abnormally formed during fabrication processes with redundancy memory cells. Further, the fuse option may also be widely used to change design schemes of the semiconductor devices.
- the fuse option may be performed by irradiating a laser beam onto the corresponding fuse or forcing an over-current into the corresponding fuse to cut the corresponding fuse.
- Each of the semiconductor devices may have a plurality of fuses, and the fuse option may be performed by a fuse signal which is generated according to the cut states of the plurality of fuses.
- Various embodiments are directed to semiconductor devices and semiconductor systems including the same.
- a semiconductor system includes a controller and a semiconductor device.
- the controller generates a power voltage signal.
- the semiconductor device generates a power-up signal in response to the power voltage signal and generates a first selection pulse, a second selection pulse and an initialization pulse signal. Further, the semiconductor device generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.
- a semiconductor device includes a pre-fuse signal generator and a selection transmitter.
- the pre-fuse signal generator generates a pre-fuse signal whose level is determined according to a cut state of a first fuse and generates the pre-fuse signal whose level is determined according to a cut state of a second fuse.
- the selection transmitter outputs the pre-fuse signal as a first fuse signal when a first selection pulse is generated and outputs the pre-fuse signal as a second fuse signal when a second selection pulse is generated.
- a semiconductor system includes a controller and a semiconductor device.
- the controller suitable for generating a period signal.
- the semiconductor device generates a first selection pulse, a second selection pulse and an initialization pulse signal in response to the period signal.
- the semiconductor device generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse in response to the first selection pulse and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse in response to the second selection pulse.
- a system comprises: a processor; a controller suitable for receiving a request and a data from the processor; and a memory unit suitable for receiving the request and the data from the controller, wherein the controller is suitable for generating a power voltage signal, suitable for generating a power-up signal in response to the power voltage signal, suitable for generating a first selection pulse, a second selection pulse and an initialization pulse, suitable for generating a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and suitable for generating a second fuse signal for controlling the internal operation according to a cut state of a second fuse.
- FIG. 1 is a circuit diagram illustrating a fuse signal generator according to the general inventive concept
- FIG. 2 is a block diagram illustrating a semiconductor system according to various embodiments of the present invention.
- FIG. 3 is a block diagram illustrating a pulse generator included in the semiconductor system of FIG. 2 ;
- FIG. 4 is a circuit diagram illustrating a fuse signal generator included in the semiconductor system of FIG. 2 ;
- FIG. 5 is a timing diagram illustrating an operation of the semiconductor system shown in FIG. 2 ;
- FIG. 6 is a block diagram illustrating another semiconductor system according to various embodiments of the present invention.
- FIG. 7 illustrates a block diagram of a system in accordance with an embodiment of the invention.
- a fuse signal generator may include fuses F 11 , F 12 and F 13 , PMOS transistors P 11 , P 12 and P 13 , NMOS transistors N 11 , N 12 and N 13 , and latch units 11 , 12 and 13 .
- the fuse F 11 may be coupled between a power voltage VDD terminal and a node ND 11
- the fuse F 12 may be coupled between the power voltage VDD terminal and a node ND 13
- the fuse F 13 may be coupled between the power voltage VDD terminal and a node ND 15 .
- the PMOS transistor P 11 may be coupled between the node ND 11 and a node ND 12 and may be turned on or turned off in response to a power-up signal PWRUP.
- the NMOS transistor N 11 may be coupled between the node ND 12 and a ground voltage terminal VSS and may be turned on or turned off in response to the power-up signal PWRUP.
- the PMOS transistor P 12 may be coupled between the node ND 13 and a node ND 14 and may be turned on or turned off in response to the power-up signal PWRUP.
- the NMOS transistor N 12 may be coupled between the node ND 14 and the ground voltage terminal VSS and may be turned on or turned off in response to the power-up signal PWRUP.
- the PMOS transistor P 13 may be coupled between the node ND 15 and a node ND 16 and may be turned on or turned off in response to the power-up signal PWRUP.
- the NMOS transistor N 13 may be coupled between the node ND 16 and the ground voltage terminal VSS and may be turned on or turned off in response to the power-up signal PWRUP.
- the latch unit 11 may buffer a signal on the node ND 12 to output the buffered signal as a first fuse signal FUSE 1 through a node ND 17 .
- the latch unit 11 also illustrates the ground voltage terminal VSS.
- the latch unit 11 may latch a data having a logic “high” level at the node ND 17 .
- the latch unit 12 may buffer a signal on the node ND 14 to output the buffered signal as a second fuse signal FUSE 2 through a node ND 18 .
- the latch unit 12 may also illustrate the ground voltage terminal VSS.
- the latch unit 12 may latch a data having a logic “high” level at the node ND 18 .
- the latch unit 13 may buffer a signal on the node ND 16 to output the buffered signal as a third fuse signal FUSE 3 through a node ND 19 .
- the latch unit 13 may latch a data having a logic “high” level at the node ND 19 .
- the latch unit 13 may also illustrate the ground voltage terminal VSS.
- the aforementioned fuse signal generator may generate the first, second and third fuse signals FUSE 1 , FUSE 2 and FUSE 3 in response to the power-up signal PWRUP changing from a logic “high” level into a logic “low” level when a level of the power voltage VDD reaches a predetermined level.
- An operation of the fuse signal generator shown in FIG. 1 will be described more fully hereinafter.
- the NMOS transistors N 11 , N 12 and N 13 may be turned on by the power-up signal PWRUP having a logic “high” level and the nodes ND 12 , ND 14 and ND 16 may be driven to have a logic “low” level.
- all the first, second and third fuse signals FUSE 1 , FUSE 2 and FUSE 3 may be initialized to have a logic “high” level.
- logic levels of the first, second and third fuse signals FUSE 1 , FUSE 2 and FUSE 3 may be determined according to whether the fuses are cut or not. For example, if the fuses F 11 and F 12 are cut and the fuse F 13 is not cut, the first and second fuse signals FUSE 1 and FUSE 2 may still maintain a logic “high” level and the third fuse signal FUSE 3 may change from a logic “high” level into a logic “low” level.
- a semiconductor system may include a controller 1 and a semiconductor device 2 .
- the controller 1 may generate a power voltage signal VDD.
- the semiconductor device 2 may include a power-up signal generator 21 , a pulse generator 22 , a fuse signal generator 23 and an internal circuit 24 .
- the power-up signal generator 21 may generate a power-up signal PWRUP which is ramped up to have the same level as the power voltage signal VDD in response to the power voltage signal VDD.
- the power-up signal PWRUP may change from a logic “high” level into a logic “low” level at a point of time that the power-up period terminates. That is, the power-up signal PWRUP may change from a logic “high” level into a logic “low” level after the power voltage signal VDD reaches the predetermined level.
- the pulse generator 22 may generate a first selection pulse SELP 1 , a second selection pulse SELP 2 , a third selection pulse SELP 3 and an initialization pulse signal INTP from a point of time that the power-up signal PWRUP is changed from a logic “high” level into a logic “low” level.
- the first, second and third selection pulses SELP 1 , SELP 2 and SELP 3 may be sequentially generated.
- the initialization pulse signal INTP may include first to third pulses (not shown). The first pulse may be generated after the first selection pulse SELP 1 is generated, and the second pulse may be generated after the second selection pulse SELP 2 is generated. Further, the third pulse may be generated after the third selection pulse SELP 3 is generated.
- the fuse signal generator 23 may initialize a level of a predetermined node (not shown) using the first pulse included in the initialization pulse signal INTP after setting a level of a first fuse signal FUSEN 1 , wherein the level of the predetermined node may be controlled according to cut states of a first and second fuse. If the second selection pulse SELP 2 is generated, the fuse signal generator 23 may initialize a level of the predetermined node using the second pulse included in the initialization pulse signal INTP after setting a level of a second fuse signal FUSEN 2 .
- the fuse signal generator 23 may initialize a level of the predetermined node using the third pulse included in the initialization pulse signal INTP after setting a level of a third fuse signal FUSEN 3 .
- the semiconductor device 2 may be suitable for generating a power-up signal PWRUP in response to the power voltage signal VDD; suitable for generating a first selection pulse SELP 1 , a second selection pulse SELP 2 and an initialization pulse signal INTP in response to the power-up signal PWRUP; suitable for generating a first fuse signal FUSEN 1 for controlling an internal operation according to a cut state of a first fuse in response to the first selection pulse SELP 1 ; and suitable for generating a second fuse signal FUSEN 1 for controlling the internal operation according to a cut state of a second fuse in response to the second selection pulse SELP 2 .
- the internal circuit 24 may perform an internal operation thereof according to a level combination of the first, second and third fuse signals FUSEN 1 , FUSEN 2 and FUSEN 3 .
- the internal operation of the internal circuit 24 may include a repair operation for replacing failed memory cells with redundancy memory cells, an operation for changing a design scheme, and an operation for changing a mode.
- the pulse generator 22 may include an oscillator 221 , a selection pulse generator 222 and an initialization pulse generator 223 .
- the oscillator 221 may generate an oscillation signal OSC having a predetermined cycle time in response to the power-up signal PWRUP which is changed from a logic “high” level into a logic “low” level at a point of time that the power-up period (i.e., a period from a moment that the power voltage signal VDD is applied until a moment that the power voltage signal VDD reaches a predetermined level) terminates.
- OSC oscillation signal
- the selection pulse generator 222 may generate the first selection pulse SELP 1 in synchronization with a first rising edge of the oscillation signal OSC.
- the selection pulse generator 222 may generate the second selection pulse SELP 2 in synchronization with a second rising edge of the oscillation signal OSC.
- the selection pulse generator 222 may generate the third selection pulse SELP 3 in synchronization with a third rising edge of the oscillation signal OSC.
- the initialization pulse generator 223 may generate the initialization pulse signal INTP including first to third pulses in response to the oscillation signal OSC.
- the first pulse of the initialization pulse signal INTP may be generated in synchronization with a first falling edge of the oscillation signal OSC
- the second pulse of the initialization pulse signal INTP may be generated in synchronization with a second falling edge of the oscillation signal OSC.
- the third pulse of the initialization pulse signal INTP may be generated in synchronization with a third falling edge of the oscillation signal OSC.
- the fuse signal generator 23 may include a pre-fuse signal generator 231 and a selection transmitter 232 .
- the pre-fuse signal generator 231 may include first to third fuses F 21 , F 22 and F 23 , first to third switching elements P 21 , P 22 and P 23 , a driving element N 21 , and a latch unit 233 .
- the first fuse F 21 may be coupled between a power voltage terminal VDD and a node ND 21
- the second fuse F 22 may be coupled between the power voltage terminal VDD and a node ND 22
- the third fuse F 23 may be coupled between the power voltage terminal VDD and a node ND 23 .
- the first switching element P 21 may be coupled between the node ND 21 , the first fuse F 21 and a predetermined node ND 24 and may be turned on when the first selection pulse SELP 1 is generated to determine a level of the predetermined node ND 24 .
- the second switching element P 22 may be coupled between the node ND 22 , the second fuse F 22 and the predetermined node ND 24 and may be turned on when the second selection pulse SELP 2 is generated to determine a level of the predetermined node ND 24 .
- the third switching element P 23 may be coupled between the node ND 23 , the third fuse F 23 and the predetermined node ND 24 and may be turned on when the third selection pulse SELP 3 is generated.
- the driving element N 21 may be coupled between the predetermined node ND 24 and a ground voltage terminal VSS and may be turned on in response to the initialization pulse signal INTP.
- the driving element N 21 may drive a level of the predetermined node ND 24 whenever the first pulse and second pulse of the initialization pulse signal INTP are inputted.
- the latch unit 233 may buffer a voltage signal of the predetermined node ND 24 to output the buffered voltage signal as a pre-fuse signal FUSE_PRE through a node ND 25 .
- the latch unit 233 may include an NMOS transistor N 22 coupled between the node ND 24 and the ground voltage terminal VSS, and the NMOS transistor N 22 may be turned on when the pre-fuse signal FUSE_PRE has a logic “high” level.
- the latch unit 233 may latch levels of the nodes ND 24 and ND 25 and may include an inverter IV 21 .
- the pre-fuse signal generator 231 may be suitable for generating a pre-fuse signal FUSE_PRE whose level may be determined according to a cut state of a first fuse when the first selection pulse SELP 1 is generated; and suitable for generating the pre-fuse signal FUSE_PRE whose level may be determined according to a cut state of the second fuse when the second selection pulse SELP 2 is generated.
- the selection transmitter 232 may include transfer elements T 21 , T 22 and T 23 and latch units 234 , 235 and 236 . If the first selection pulse SELP 1 is generated, the transfer element T 21 may be turned on to transmit the pre-fuse signal FUSE_PRE to a node ND 26 . If the second selection pulse SELP 2 is generated, the transfer element T 22 may be turned on to transmit the pre-fuse signal FUSE_PRE to a node ND 27 . If the third selection pulse SELP 3 is generated, the transfer element T 23 may be turned on to transmit the pre-fuse signal FUSE_PRE to a node ND 28 .
- the latch unit 234 may buffer and latch a signal of the node ND 26 to generate the first fuse signal FUSEN 1 .
- the latch unit 235 may buffer and latch a signal of the node ND 27 to generate the second fuse signal FUSEN 2 .
- the latch unit 236 may buffer and latch a signal of the node ND 28 to generate the third fuse signal
- the aforementioned fuse signal generator 23 may generate the first fuse signal FUSEN 1 according to whether the first fuse F 21 is cut or not when the first selection pulse SELP 1 is inputted. Further, the aforementioned fuse signal generator 23 may generate the second fuse signal FUSEN 2 according to whether the second fuse F 22 is cut or not when the second selection pulse SELP 2 is inputted. Moreover, the aforementioned fuse signal generator 23 may generate the third fuse signal FUSEN 3 according to whether the third fuse F 23 is cut or not when the third selection pulse SELP 3 is inputted.
- the fuse signal generator 23 may generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the first fuse signal FUSEN 1 having a logic “low” level if the first selection pulse SELP 1 is inputted. Further, when the first and second fuses F 21 and F 22 are cut and the third fuse F 23 is not cut, the fuse signal generator 23 may generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the second fuse signal FUSEN 2 having a logic “low” level if the second selection pulse SELP 2 is inputted.
- the fuse signal generator 23 may generate the pre-fuse signal FUSE_PRE having a logic “low” level to output the third fuse signal FUSEN 3 having a logic “high” level if the third selection pulse SELP 3 is inputted.
- the power-up signal PWRUP may ramp up to have the same level as the power voltage signal VDD and may changes from a logic “high” level into a logic “low” level at a point of time “T 11 ” that the power-up period terminates.
- the oscillation signal OSC having a predetermined cycle time may be generated by the power-up signal PWRUP at the point of time “T 11 ” that the power-up period terminates.
- the first, second and third selection pulses SELP 1 , SELP 2 and SELP 3 and the initialization pulse signal INTP may be generated in response to the oscillation signal OSC.
- the first selection pulse SELP 1 may be generated at the point of time “T 11 ” that is synchronized with a first rising edge of the oscillation signal OSC
- the second selection pulse SELP 2 may be generated at a point of time “T 13 ” that is synchronized with a second rising edge of the oscillation signal OSC
- the third selection pulse SELP 3 may be generated at a point of time “T 15 ” that is synchronized with a third rising edge of the oscillation signal OSC.
- the initialization pulse signal INTP may include first, second and third pulses.
- the first pulse of the initialization pulse signal INTP may be generated at a point of time “T 12 ” that is synchronized with a first falling edge of the oscillation signal OSC
- the second pulse of the initialization pulse signal INTP may be generated at a point of time “T 14 ” that is synchronized with a second falling edge of the oscillation signal OSC
- the third pulse of the initialization pulse signal INTP may be generated at a point of time “T 16 ” that is synchronized with a third falling edge of the oscillation signal OSC.
- the first, second and third fuse signals FUSEN 1 , FUSEN 2 and FUSEN 3 may be sequentially generated in response to the first, second and third selection pulses SELP 1 , SELP 2 and SELP 3 and the initialization pulse signal INTP.
- the fuse signal generator 23 may internally generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the first fuse signal FUSEN 1 having a logic “low” level if the first selection pulse SELP 1 is inputted and may internally generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the second fuse signal FUSEN 2 having a logic “low” level if the second selection pulse SELP 2 is inputted.
- the fuse signal generator 23 may internally generate the pre-fuse signal FUSE_PRE having a logic “low” level to output the third fuse signal FUSEN 3 having a logic “high” level if the third selection pulse SELP 3 is inputted.
- the semiconductor system may sequentially generate the first, second and third fuse signals FUSEN 1 , FUSEN 2 and FUSEN 3 that control an operation of the internal circuit using the first, second and third selection pulses SELP 1 , SELP 2 and SELP 3 which are sequentially generated. Because the first, second and third fuse signals FUSEN 1 , FUSEN 2 and FUSEN 3 are sequentially generated, abrupt power consumption may be prevented. This may lead to a stable supply of the power voltage VDD without any voltage level drops. Further, the first, second and third fuses F 21 , F 22 and F 23 may share the latch unit 233 to reduce a planar area that a circuit generating the first, second and third fuses F 21 , F 22 and F 23 occupies.
- another semiconductor system may include a controller 3 and a semiconductor device 4 .
- the controller 3 may generate a period signal PD.
- the period signal PD may be enabled for a predetermined period.
- the enabled period of the period signal PD may vary according to the embodiments.
- the enabled period of the period signal PD may be set to be a power-up period from a moment that the power voltage signal VDD is applied until a moment that the power voltage signal VDD reaches a predetermined level.
- the semiconductor device 4 may include a pulse generator 41 , a fuse signal generator 42 and an internal circuit 43 .
- the pulse generator 41 may generate a first selection pulse SELP 1 , a second selection pulse SELP 2 , a third selection pulse SELP 3 and an initialization pulse signal INTP from a point of time that the enabled period of the period signal PD terminates.
- the first, second and third selection pulses SELP 1 , SELP 2 and SELP 3 may be sequentially generated.
- the initialization pulse signal INTP may include first to third pulses (not shown). The first pulse may be generated after the first selection pulse SELP 1 is generated, and the second pulse may be generated after the second selection pulse SELP 2 is generated. Further, the third pulse may be generated after the third selection pulse SELP 3 is generated.
- the fuse signal generator 42 may initialize a level of a predetermined node (not shown) using the first pulse included in the initialization pulse signal INTP after setting a level of a first fuse signal FUSEN 1 . If the second selection pulse SELP 2 is generated, the fuse signal generator 42 may initialize a level of the predetermined node using the second pulse included in the initialization pulse signal INTP after setting a level of a second fuse signal FUSEN 2 . If the third selection pulse SELP 3 is generated, the fuse signal generator 42 may initialize a level of the predetermined node using the third pulse included in the initialization pulse signal INTP after setting a level of a third fuse signal FUSEN 3 .
- the semiconductor device 4 may be suitable for generating a first selection pulse SELP 1 , a second selection pulse SELP 2 and an initialization pulse INTP in response to the period signal PD; suitable for generating a first fuse signal FUSEN 1 for controlling an internal operation according to a cut state of a first fuse in response to the first selection pulse SELP 1 ; and suitable for generating a second fuse signal FUSEN 1 for controlling the internal operation according to a cut state of a second fuse in response to the second selection pulse SELP 2 .
- the internal circuit 43 may perform an internal operation thereof according to a level combination of the first, second and third fuse signals FUSEN 1 , FUSEN 2 and FUSEN 3 .
- the internal operation of the internal circuit 43 may include a repair operation for replacing failed memory cells with redundancy memory cells, an operation for changing a design scheme, and an operation for changing a mode.
- a system 1000 may include one or more processors or central processing units (“CPUs”) 1100 .
- the processor 1100 may be used individually or in combination with other CPUs.
- a chipset 1150 may be operably coupled to the CPU 1100 .
- the chipset 1150 is a communication pathway for signals between the CPU 1100 and other components of the system 1000 , which may include a memory controller 1200 , an input/output (“I/O”) bus 1250 , and a disk drive controller 1300 .
- I/O input/output
- disk drive controller 1300 a disk drive controller
- the memory controller 1200 may be operably coupled to the chipset 1150 .
- the memory controller 1200 may include at least one memory controller which delays the generation of the address signal, and blocks consecutive accesses, of which the number exceeds the predetermined critical value, to the same word line or the same bit line of a selected memory bank of a memory unit.
- the memory controller 1200 may include the semiconductor system described above, and can receive a request provided from the CPU 1100 through the chipset 1150 .
- the memory controller 1200 may be operably coupled to one or more memory devices 1350 .
- the chipset 1150 may also be coupled to the I/O bus 1250 .
- the I/O bus 1250 may serve as a communication pathway for signals from the chipset 1150 to I/O devices 1410 , 1420 and 1430 .
- the I/O devices 1410 , 1420 and 1430 may include a mouse 1410 , a video display 1420 , or a keyboard 1430 .
- the I/O bus 1250 may employ any one of a number of communications protocols to communicate with the I/O devices 1410 , 1420 and 1430 .
- the disk drive controller 1300 may also be operably coupled to the chipset 1150 .
- the disk drive controller 1300 may serve as the communication pathway between the chipset 1150 and one or more internal disk drives 1450 .
- the internal disk drive 1450 may facilitate disconnection of the external data storage devices by storing both instructions and data.
- the disk drive controller 1300 and the internal disk drives 1450 may communicate with each other or with the chipset 1150 using virtually any type of communication protocol, including all of those mentioned above with regard to the I/O bus 1250 .
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Abstract
Description
- The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2013-0069279, filed on Jun. 17, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.
- 1. Technical Field
- Embodiments of the present disclosure relate to semiconductor integrated circuits and, more particularly, to semiconductor devices and semiconductor systems including the same.
- 2. Description of Related Art
- Semiconductor devices may operate in various modes and utilize an option processing method to change the mode. In general, the option processing method may include a bonding option, a metal option and a fuse option. The fuse option may be widely used to replace failed memory cells abnormally formed during fabrication processes with redundancy memory cells. Further, the fuse option may also be widely used to change design schemes of the semiconductor devices. The fuse option may be performed by irradiating a laser beam onto the corresponding fuse or forcing an over-current into the corresponding fuse to cut the corresponding fuse. Each of the semiconductor devices may have a plurality of fuses, and the fuse option may be performed by a fuse signal which is generated according to the cut states of the plurality of fuses.
- Various embodiments are directed to semiconductor devices and semiconductor systems including the same.
- According to various embodiments, a semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal and generates a first selection pulse, a second selection pulse and an initialization pulse signal. Further, the semiconductor device generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.
- According to various embodiments, a semiconductor device includes a pre-fuse signal generator and a selection transmitter. The pre-fuse signal generator generates a pre-fuse signal whose level is determined according to a cut state of a first fuse and generates the pre-fuse signal whose level is determined according to a cut state of a second fuse. The selection transmitter outputs the pre-fuse signal as a first fuse signal when a first selection pulse is generated and outputs the pre-fuse signal as a second fuse signal when a second selection pulse is generated.
- According to various embodiments, a semiconductor system includes a controller and a semiconductor device. The controller suitable for generating a period signal. The semiconductor device generates a first selection pulse, a second selection pulse and an initialization pulse signal in response to the period signal. In addition, the semiconductor device generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse in response to the first selection pulse and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse in response to the second selection pulse.
- In accordance with an embodiment, a system comprises: a processor; a controller suitable for receiving a request and a data from the processor; and a memory unit suitable for receiving the request and the data from the controller, wherein the controller is suitable for generating a power voltage signal, suitable for generating a power-up signal in response to the power voltage signal, suitable for generating a first selection pulse, a second selection pulse and an initialization pulse, suitable for generating a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and suitable for generating a second fuse signal for controlling the internal operation according to a cut state of a second fuse.
- Embodiments of the present invention will become more apparent in view of the attached drawings and accompanying detailed description, in which:
-
FIG. 1 is a circuit diagram illustrating a fuse signal generator according to the general inventive concept; -
FIG. 2 is a block diagram illustrating a semiconductor system according to various embodiments of the present invention; -
FIG. 3 is a block diagram illustrating a pulse generator included in the semiconductor system ofFIG. 2 ; -
FIG. 4 is a circuit diagram illustrating a fuse signal generator included in the semiconductor system ofFIG. 2 ; -
FIG. 5 is a timing diagram illustrating an operation of the semiconductor system shown inFIG. 2 ; and -
FIG. 6 is a block diagram illustrating another semiconductor system according to various embodiments of the present invention; and -
FIG. 7 illustrates a block diagram of a system in accordance with an embodiment of the invention. - Embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.
- Referring to
FIG. 1 , a fuse signal generator according to a general inventive concept may include fuses F11, F12 and F13, PMOS transistors P11, P12 and P13, NMOS transistors N11, N12 and N13, andlatch units latch unit 11 may buffer a signal on the node ND12 to output the buffered signal as a first fuse signal FUSE1 through a node ND17. Thelatch unit 11 also illustrates the ground voltage terminal VSS. Thelatch unit 11 may latch a data having a logic “high” level at the node ND17. Thelatch unit 12 may buffer a signal on the node ND14 to output the buffered signal as a second fuse signal FUSE2 through a node ND18. Thelatch unit 12 may also illustrate the ground voltage terminal VSS. Thelatch unit 12 may latch a data having a logic “high” level at the node ND18. Thelatch unit 13 may buffer a signal on the node ND16 to output the buffered signal as a third fuse signal FUSE3 through a node ND19. Thelatch unit 13 may latch a data having a logic “high” level at the node ND19. Thelatch unit 13 may also illustrate the ground voltage terminal VSS. - The aforementioned fuse signal generator may generate the first, second and third fuse signals FUSE1, FUSE2 and FUSE3 in response to the power-up signal PWRUP changing from a logic “high” level into a logic “low” level when a level of the power voltage VDD reaches a predetermined level. An operation of the fuse signal generator shown in
FIG. 1 will be described more fully hereinafter. - First, in a power-up period before the power voltage VDD reaches the predetermined level, the NMOS transistors N11, N12 and N13 may be turned on by the power-up signal PWRUP having a logic “high” level and the nodes ND12, ND14 and ND16 may be driven to have a logic “low” level. Thus, all the first, second and third fuse signals FUSE1, FUSE2 and FUSE3 may be initialized to have a logic “high” level.
- Next, if the power voltage VDD reaches the predetermined level and the power-up signal PWRUP changes from a logic “high” level into a logic “low” level, logic levels of the first, second and third fuse signals FUSE1, FUSE2 and FUSE3 may be determined according to whether the fuses are cut or not. For example, if the fuses F11 and F12 are cut and the fuse F13 is not cut, the first and second fuse signals FUSE1 and FUSE2 may still maintain a logic “high” level and the third fuse signal FUSE3 may change from a logic “high” level into a logic “low” level.
- Referring to
FIG. 2 , a semiconductor system according to various embodiments of the present invention may include acontroller 1 and a semiconductor device 2. Thecontroller 1 may generate a power voltage signal VDD. The semiconductor device 2 may include a power-up signal generator 21, apulse generator 22, afuse signal generator 23 and aninternal circuit 24. - In a power-up period from a moment that the power voltage signal VDD is applied until a moment that the power voltage signal VDD reaches a predetermined level, the power-
up signal generator 21 may generate a power-up signal PWRUP which is ramped up to have the same level as the power voltage signal VDD in response to the power voltage signal VDD. The power-up signal PWRUP may change from a logic “high” level into a logic “low” level at a point of time that the power-up period terminates. That is, the power-up signal PWRUP may change from a logic “high” level into a logic “low” level after the power voltage signal VDD reaches the predetermined level. - The
pulse generator 22 may generate a first selection pulse SELP1, a second selection pulse SELP2, a third selection pulse SELP3 and an initialization pulse signal INTP from a point of time that the power-up signal PWRUP is changed from a logic “high” level into a logic “low” level. The first, second and third selection pulses SELP1, SELP2 and SELP3 may be sequentially generated. The initialization pulse signal INTP may include first to third pulses (not shown). The first pulse may be generated after the first selection pulse SELP1 is generated, and the second pulse may be generated after the second selection pulse SELP2 is generated. Further, the third pulse may be generated after the third selection pulse SELP3 is generated. - If the first selection pulse SELP1 is generated, the
fuse signal generator 23 may initialize a level of a predetermined node (not shown) using the first pulse included in the initialization pulse signal INTP after setting a level of a first fuse signal FUSEN1, wherein the level of the predetermined node may be controlled according to cut states of a first and second fuse. If the second selection pulse SELP2 is generated, thefuse signal generator 23 may initialize a level of the predetermined node using the second pulse included in the initialization pulse signal INTP after setting a level of a second fuse signal FUSEN2. If the third selection pulse SELP3 is generated, thefuse signal generator 23 may initialize a level of the predetermined node using the third pulse included in the initialization pulse signal INTP after setting a level of a third fuse signal FUSEN3. Accordingly, the semiconductor device 2 may be suitable for generating a power-up signal PWRUP in response to the power voltage signal VDD; suitable for generating a first selection pulse SELP1, a second selection pulse SELP2 and an initialization pulse signal INTP in response to the power-up signal PWRUP; suitable for generating a first fuse signal FUSEN1 for controlling an internal operation according to a cut state of a first fuse in response to the first selection pulse SELP1; and suitable for generating a second fuse signal FUSEN1 for controlling the internal operation according to a cut state of a second fuse in response to the second selection pulse SELP2. - The
internal circuit 24 may perform an internal operation thereof according to a level combination of the first, second and third fuse signals FUSEN1, FUSEN2 and FUSEN3. The internal operation of theinternal circuit 24 may include a repair operation for replacing failed memory cells with redundancy memory cells, an operation for changing a design scheme, and an operation for changing a mode. - Referring to
FIG. 3 , thepulse generator 22 may include anoscillator 221, aselection pulse generator 222 and aninitialization pulse generator 223. - The
oscillator 221 may generate an oscillation signal OSC having a predetermined cycle time in response to the power-up signal PWRUP which is changed from a logic “high” level into a logic “low” level at a point of time that the power-up period (i.e., a period from a moment that the power voltage signal VDD is applied until a moment that the power voltage signal VDD reaches a predetermined level) terminates. - The
selection pulse generator 222 may generate the first selection pulse SELP1 in synchronization with a first rising edge of the oscillation signal OSC. Theselection pulse generator 222 may generate the second selection pulse SELP2 in synchronization with a second rising edge of the oscillation signal OSC. Further, theselection pulse generator 222 may generate the third selection pulse SELP3 in synchronization with a third rising edge of the oscillation signal OSC. - The
initialization pulse generator 223 may generate the initialization pulse signal INTP including first to third pulses in response to the oscillation signal OSC. The first pulse of the initialization pulse signal INTP may be generated in synchronization with a first falling edge of the oscillation signal OSC, and the second pulse of the initialization pulse signal INTP may be generated in synchronization with a second falling edge of the oscillation signal OSC. In addition, the third pulse of the initialization pulse signal INTP may be generated in synchronization with a third falling edge of the oscillation signal OSC. - Referring to
FIG. 4 , thefuse signal generator 23 may include apre-fuse signal generator 231 and aselection transmitter 232. - The
pre-fuse signal generator 231 may include first to third fuses F21, F22 and F23, first to third switching elements P21, P22 and P23, a driving element N21, and alatch unit 233. The first fuse F21 may be coupled between a power voltage terminal VDD and a node ND21, and the second fuse F22 may be coupled between the power voltage terminal VDD and a node ND22. Further, the third fuse F23 may be coupled between the power voltage terminal VDD and a node ND23. The first switching element P21 may be coupled between the node ND21, the first fuse F21 and a predetermined node ND24 and may be turned on when the first selection pulse SELP1 is generated to determine a level of the predetermined node ND24. The second switching element P22 may be coupled between the node ND22, the second fuse F22 and the predetermined node ND24 and may be turned on when the second selection pulse SELP2 is generated to determine a level of the predetermined node ND24. The third switching element P23 may be coupled between the node ND23, the third fuse F23 and the predetermined node ND24 and may be turned on when the third selection pulse SELP3 is generated. The driving element N21 may be coupled between the predetermined node ND24 and a ground voltage terminal VSS and may be turned on in response to the initialization pulse signal INTP. The driving element N21 may drive a level of the predetermined node ND24 whenever the first pulse and second pulse of the initialization pulse signal INTP are inputted. Thelatch unit 233 may buffer a voltage signal of the predetermined node ND24 to output the buffered voltage signal as a pre-fuse signal FUSE_PRE through a node ND25. Thelatch unit 233 may include an NMOS transistor N22 coupled between the node ND24 and the ground voltage terminal VSS, and the NMOS transistor N22 may be turned on when the pre-fuse signal FUSE_PRE has a logic “high” level. Thus, thelatch unit 233 may latch levels of the nodes ND24 and ND25 and may include an inverter IV21. Thepre-fuse signal generator 231 may be suitable for generating a pre-fuse signal FUSE_PRE whose level may be determined according to a cut state of a first fuse when the first selection pulse SELP1 is generated; and suitable for generating the pre-fuse signal FUSE_PRE whose level may be determined according to a cut state of the second fuse when the second selection pulse SELP2 is generated. - The
selection transmitter 232 may include transfer elements T21, T22 and T23 andlatch units latch unit 234 may buffer and latch a signal of the node ND26 to generate the first fuse signal FUSEN1. Thelatch unit 235 may buffer and latch a signal of the node ND27 to generate the second fuse signal FUSEN2. Thelatch unit 236 may buffer and latch a signal of the node ND28 to generate the third fuse signal FUSEN3. - The aforementioned
fuse signal generator 23 may generate the first fuse signal FUSEN1 according to whether the first fuse F21 is cut or not when the first selection pulse SELP1 is inputted. Further, the aforementionedfuse signal generator 23 may generate the second fuse signal FUSEN2 according to whether the second fuse F22 is cut or not when the second selection pulse SELP2 is inputted. Moreover, the aforementionedfuse signal generator 23 may generate the third fuse signal FUSEN3 according to whether the third fuse F23 is cut or not when the third selection pulse SELP3 is inputted. For example, when the first and second fuses F21 and F22 are cut and the third fuse F23 is not cut, thefuse signal generator 23 may generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the first fuse signal FUSEN1 having a logic “low” level if the first selection pulse SELP1 is inputted. Further, when the first and second fuses F21 and F22 are cut and the third fuse F23 is not cut, thefuse signal generator 23 may generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the second fuse signal FUSEN2 having a logic “low” level if the second selection pulse SELP2 is inputted. Moreover, when the first and second fuses F21 and F22 are cut and the third fuse F23 is not cut, thefuse signal generator 23 may generate the pre-fuse signal FUSE_PRE having a logic “low” level to output the third fuse signal FUSEN3 having a logic “high” level if the third selection pulse SELP3 is inputted. - An operation of the semiconductor system set forth above will be described with reference to
FIGS. 2 , 3, 4 and 5 in conjunction with an example that the first and second fuses F21 and F22 are cut and the third fuse F23 is not cut. - First, if the power voltage signal VDD is generated, the power-up signal PWRUP may ramp up to have the same level as the power voltage signal VDD and may changes from a logic “high” level into a logic “low” level at a point of time “T11” that the power-up period terminates. The oscillation signal OSC having a predetermined cycle time may be generated by the power-up signal PWRUP at the point of time “T11” that the power-up period terminates.
- Next, the first, second and third selection pulses SELP1, SELP2 and SELP3 and the initialization pulse signal INTP may be generated in response to the oscillation signal OSC. In more detail, the first selection pulse SELP1 may be generated at the point of time “T11” that is synchronized with a first rising edge of the oscillation signal OSC, and the second selection pulse SELP2 may be generated at a point of time “T13” that is synchronized with a second rising edge of the oscillation signal OSC. Further, the third selection pulse SELP3 may be generated at a point of time “T15” that is synchronized with a third rising edge of the oscillation signal OSC. The initialization pulse signal INTP may include first, second and third pulses. The first pulse of the initialization pulse signal INTP may be generated at a point of time “T12” that is synchronized with a first falling edge of the oscillation signal OSC, and the second pulse of the initialization pulse signal INTP may be generated at a point of time “T14” that is synchronized with a second falling edge of the oscillation signal OSC. In addition, the third pulse of the initialization pulse signal INTP may be generated at a point of time “T16” that is synchronized with a third falling edge of the oscillation signal OSC.
- Subsequently, the first, second and third fuse signals FUSEN1, FUSEN2 and FUSEN3 may be sequentially generated in response to the first, second and third selection pulses SELP1, SELP2 and SELP3 and the initialization pulse signal INTP. Specifically, when the first and second fuses F21 and F22 are cut and the third fuse F23 is not cut, the
fuse signal generator 23 may internally generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the first fuse signal FUSEN1 having a logic “low” level if the first selection pulse SELP1 is inputted and may internally generate the pre-fuse signal FUSE_PRE having a logic “high” level to output the second fuse signal FUSEN2 having a logic “low” level if the second selection pulse SELP2 is inputted. In addition, when the first and second fuses F21 and F22 are cut and the third fuse F23 is not cut, thefuse signal generator 23 may internally generate the pre-fuse signal FUSE_PRE having a logic “low” level to output the third fuse signal FUSEN3 having a logic “high” level if the third selection pulse SELP3 is inputted. - As described above, the semiconductor system according to the embodiments may sequentially generate the first, second and third fuse signals FUSEN1, FUSEN2 and FUSEN3 that control an operation of the internal circuit using the first, second and third selection pulses SELP1, SELP2 and SELP3 which are sequentially generated. Because the first, second and third fuse signals FUSEN1, FUSEN2 and FUSEN3 are sequentially generated, abrupt power consumption may be prevented. This may lead to a stable supply of the power voltage VDD without any voltage level drops. Further, the first, second and third fuses F21, F22 and F23 may share the
latch unit 233 to reduce a planar area that a circuit generating the first, second and third fuses F21, F22 and F23 occupies. - Referring to
FIG. 6 , another semiconductor system according to various embodiments of the present invention may include acontroller 3 and a semiconductor device 4. Thecontroller 3 may generate a period signal PD. The period signal PD may be enabled for a predetermined period. The enabled period of the period signal PD may vary according to the embodiments. In an embodiment, the enabled period of the period signal PD may be set to be a power-up period from a moment that the power voltage signal VDD is applied until a moment that the power voltage signal VDD reaches a predetermined level. The semiconductor device 4 may include apulse generator 41, afuse signal generator 42 and aninternal circuit 43. - The
pulse generator 41 may generate a first selection pulse SELP1, a second selection pulse SELP2, a third selection pulse SELP3 and an initialization pulse signal INTP from a point of time that the enabled period of the period signal PD terminates. The first, second and third selection pulses SELP1, SELP2 and SELP3 may be sequentially generated. The initialization pulse signal INTP may include first to third pulses (not shown). The first pulse may be generated after the first selection pulse SELP1 is generated, and the second pulse may be generated after the second selection pulse SELP2 is generated. Further, the third pulse may be generated after the third selection pulse SELP3 is generated. - If the first selection pulse SELP1 is generated, the
fuse signal generator 42 may initialize a level of a predetermined node (not shown) using the first pulse included in the initialization pulse signal INTP after setting a level of a first fuse signal FUSEN1. If the second selection pulse SELP2 is generated, thefuse signal generator 42 may initialize a level of the predetermined node using the second pulse included in the initialization pulse signal INTP after setting a level of a second fuse signal FUSEN2. If the third selection pulse SELP3 is generated, thefuse signal generator 42 may initialize a level of the predetermined node using the third pulse included in the initialization pulse signal INTP after setting a level of a third fuse signal FUSEN3. Accordingly, the semiconductor device 4 may be suitable for generating a first selection pulse SELP1, a second selection pulse SELP2 and an initialization pulse INTP in response to the period signal PD; suitable for generating a first fuse signal FUSEN1 for controlling an internal operation according to a cut state of a first fuse in response to the first selection pulse SELP1; and suitable for generating a second fuse signal FUSEN1 for controlling the internal operation according to a cut state of a second fuse in response to the second selection pulse SELP2. - The
internal circuit 43 may perform an internal operation thereof according to a level combination of the first, second and third fuse signals FUSEN1, FUSEN2 and FUSEN3. The internal operation of theinternal circuit 43 may include a repair operation for replacing failed memory cells with redundancy memory cells, an operation for changing a design scheme, and an operation for changing a mode. - Referring to
FIG. 7 , asystem 1000 may include one or more processors or central processing units (“CPUs”) 1100. Theprocessor 1100 may be used individually or in combination with other CPUs. - A
chipset 1150 may be operably coupled to theCPU 1100. Thechipset 1150 is a communication pathway for signals between theCPU 1100 and other components of thesystem 1000, which may include amemory controller 1200, an input/output (“I/O”)bus 1250, and adisk drive controller 1300. Depending on the configuration of the system, any one of a number of different signals may be transmitted through thechipset 1150. - The
memory controller 1200 may be operably coupled to thechipset 1150. Thememory controller 1200 may include at least one memory controller which delays the generation of the address signal, and blocks consecutive accesses, of which the number exceeds the predetermined critical value, to the same word line or the same bit line of a selected memory bank of a memory unit. Thememory controller 1200 may include the semiconductor system described above, and can receive a request provided from theCPU 1100 through thechipset 1150. Thememory controller 1200 may be operably coupled to one ormore memory devices 1350. - The
chipset 1150 may also be coupled to the I/O bus 1250. The I/O bus 1250 may serve as a communication pathway for signals from thechipset 1150 to I/O devices O devices mouse 1410, avideo display 1420, or akeyboard 1430. The I/O bus 1250 may employ any one of a number of communications protocols to communicate with the I/O devices - The
disk drive controller 1300 may also be operably coupled to thechipset 1150. Thedisk drive controller 1300 may serve as the communication pathway between thechipset 1150 and one or more internal disk drives 1450. Theinternal disk drive 1450 may facilitate disconnection of the external data storage devices by storing both instructions and data. Thedisk drive controller 1300 and theinternal disk drives 1450 may communicate with each other or with thechipset 1150 using virtually any type of communication protocol, including all of those mentioned above with regard to the I/O bus 1250.
Claims (20)
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US5929691A (en) * | 1996-06-19 | 1999-07-27 | Samsung Eelectronics, Co., Ltd. | Mode setting circuit for a memory device |
US7825704B2 (en) * | 2006-04-10 | 2010-11-02 | Stmicroelectronics, Inc. | Threshold personalization testmode |
US7940116B2 (en) * | 2009-06-03 | 2011-05-10 | Samsung Electronics Co., Ltd. | Fuse circuit and semiconductor device including the same |
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JP2010206114A (en) | 2009-03-05 | 2010-09-16 | Renesas Electronics Corp | Method of testing electric fuse, and electric fuse circuit |
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US5929691A (en) * | 1996-06-19 | 1999-07-27 | Samsung Eelectronics, Co., Ltd. | Mode setting circuit for a memory device |
US7825704B2 (en) * | 2006-04-10 | 2010-11-02 | Stmicroelectronics, Inc. | Threshold personalization testmode |
US7940116B2 (en) * | 2009-06-03 | 2011-05-10 | Samsung Electronics Co., Ltd. | Fuse circuit and semiconductor device including the same |
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