US20140360915A1 - Wafer container with recessed latch - Google Patents

Wafer container with recessed latch Download PDF

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Publication number
US20140360915A1
US20140360915A1 US14468240 US201414468240A US2014360915A1 US 20140360915 A1 US20140360915 A1 US 20140360915A1 US 14468240 US14468240 US 14468240 US 201414468240 A US201414468240 A US 201414468240A US 2014360915 A1 US2014360915 A1 US 2014360915A1
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Prior art keywords
latch
housing
wafer container
rib
top
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Abandoned
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US14468240
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James D. Pylant
Alan L. Waber
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Texchem Advanced Products Inc Sdn Bhd
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Texchem Advanced Products Inc Sdn Bhd
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67353Closed carriers specially adapted for a single substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67373Closed carriers characterised by locking systems
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67379Closed carriers characterised by coupling elements, kinematic members, handles or elements to be externally gripped
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67386Closed carriers characterised by the construction of the closed carrier

Abstract

Improvements in a semiconductor wafer container including improvements in side protection to the wafers, improved cover design to minimize rotation, a simplified top cover orientation mechanism and an improved bottom holding mechanism for automation. The side protection to the wafers is with multiple staggered inner and outer walls. The improved cover design improves alignment of the top and bottom housings and minimizes rotation of the housings in transit or motion. The housings have a recessed tab ramp feature with bi-directional locking that also increases the rigidity of the containment device when the two housings are assembled. The latching mechanism is located in a protective latch well that minimizes accidental opening of the latch(s). The improved bottom holding mechanism for automation is an integrated feature that is molded into the bottom housing and not assembled in a secondary operation.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application is a continuation of U.S. patent application Ser. No. 12/606,921, filed Oct. 27, 2009, now U.S. Pat. No. 8,813,964, issued Aug. 26, 2014, which is a continuation-in-part of U.S. patent application Ser. No. 12/548,368, filed Aug. 26, 2009, now U.S. Pat. No. 8,109,390, issued Feb. 7, 2012, all of which are hereby incorporated in its entirety including all tables, figures, and claims.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates to improvements in a container for the transportation of semiconductor wafers. More particularly, the present wafer container includes improvements in side protection to the wafers, improved cover design to minimize rotation, a simplified top cover orientation mechanism and an improved bottom holding mechanism for automation.
  • 2. Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98
  • In the processing of semiconductor wafers the typically must be transported either between processes or to other facilities. The semiconductor wafers are fragile and damage to the surface of the wafers can make the wafer useless for the intended purpose. Because of the high potential for damage to the wafer the semiconductors must be packaged and transported to minimize harm. In transportation, multiple semiconductor wafers are stacked into a transportation container. There have been a number of containment products and patents have been sold and patented to try and minimize damage to these silicon wafers. Exemplary examples of patents covering these products are disclosed herein.
  • U.S. Pat. No. 6,193,068 issued Feb. 27, 2001 to Lee Lewis et al., and U.S. Pat. No. 6,341,695 issued Jan. 29, 2002 to Lee Lewis et al., disclose a containment device for retaining semiconductor wafers. This patent discloses two concentric walls on the top and bottom housings that nest to protect the semiconductor wafers. Double walls were designed to protect the wafers from the direct transmission of forces that may contact the outer wall. While the nesting walls provide protection from side impacts they do not provide flexibility to absorb and cushion a side impact or drop. The combination of an outer wall and a gap provide the protection. Damage may also occur if the force is such that the outer wall flexes enough to interfere with the inner wall, thereby damaging the wafers. That can cause the semiconductor wafers to shift and scratch.
  • U.S. Patent Publication Number US2009/0095650 that was published on Apr. 16, 2009 to James D. Pylant et al., discloses a wafer container with staggered wall structure. In this published application the design is limited by the amount overlap of the inner and outer walls by the design of its staggered walls. The walls were limited to 5% overlap, with 95 percent of the outer wall not located in adjoining angular sectors. This and other top cover rotation locating mechanisms use either an inner surface of a feature on the top cover or an exterior surface of a feature on the top cover to secure the top cover in place and prevent rotation.
  • U.S. Pat. No. 6,550,619 issued Apr. 22, 2003 to Gregory W. Bores et al., discloses a shock resistant variable load tolerant wafer shipper. This patent uses four inner tapers walls with a variable amount of cushions placed between the semiconductor wafers to pack and cushion the semiconductor wafer. While this patent allows for a variable amount of semiconductor wafers to be packed within the shipper the cushioning relies on the variable amount of cushions placed between the semiconductor wafers to reduce damage.
  • U.S. Pat. No. 7,040,487 issued on May 9, 2006 to Michael Zabka et al., discloses a protective shipper with a corrugates inner containment lip. The corrugated inner lip provides multiple surfaces for the edges if the semiconductor wafers to make contact with, but because the edges are corrugated the tangential walls of the corrugation limit the flexing of the inner lips.
  • Some semiconductor wafer containers use a rotation locking design where the locating mechanism with an exclusive inner surface or exterior surface do not securely capture the wall that they are adjacent to in both directions of rotation. These features only stop rotation in only one direction. The features must rely on a sister feature to stop rotation in the opposite direction which is generally located farther away and allows for more manufacturing tolerance to build up since it is located at a greater distance. These deficiencies result in larger gaps between the plus and minus rotational limiting surfaces, thereby leading to more rotational movement.
  • There are a number of prior designs that use top cover orientation features with differing wall engagement angles or large latches as opposed to small slots. The new feature in this proposed wafer container allows improved orientation that is not found in the prior art.
  • Prior art designs have left the latch exposed to accidental contact that can open one or more of the latches that holds the two halves of the enclosure together. These designs all fail to address placing the latch in s well to prevent accidental opening during handling and shipping. In this application the locking tab is placed within a recessed pocket where the latches are protected and enclosed in a powered well.
  • There are a number of different holding and clamping features in wafer shipping containers. All of these prior designs rely on multiple parts to create a clamping lip. These designs have several drawbacks including but not limited to the parts not being rigid with respect to the bottom assembly because they must be sonic welded, bonded or snapped together and that secondary parts or assembly operations are more expensive to produce.
  • The engagement of latches that secure the top and bottom housings together have a number of limitations. Specifically, prior art latches provide a raised straight slope ramp. The raise straight sloped surface is susceptible to damage and also, the straight slope does not provide an ideal self gripping to engage between the top and bottom housings. The top cover orientation features use differing wall engagement angles or large latches as opposed to small slots as presented in this pending application.
  • What is needed is a semiconductor wafer container with improvements in side protection to the wafers, improved cover design to minimize rotation, a simplified top cover orientation mechanism and an improved bottom holding mechanism for automation. This pending application satisfies these requirements with novel improvements in the identified areas.
  • BRIEF SUMMARY OF THE INVENTION
  • It is an object of the semiconductor wafer container that has an overlapping double wall. The wall structure comprises multiple outer walls and multiple inner walls. The overlapping double containment wall increases semiconductor wafer protection during impact or shipping. Each inner wall shares a minimal percentage of a common angular sector with each adjacent outer wall. The inner wall is generally very stiff and does not absorb and cushion the wafers if the container is dropped or subject to impact. On the bottom assembly, the inner walls and outer walls are positioned in an offset and overlapping configuration provides maximum protection to the semiconductor wafers.
  • It is an object of the semiconductor wafer container to improve alignment of the top cover with the base. The alignment system includes reference tabs that are received by the cover and a visual identifier for guiding an operator in the proper alignment of the two halves of the container. The top cover orientation features prevent improper installation of the top cover to the bottom member. The top cover orientation feature is incorporated into the top cover that mates with the features of the double locking location feature. This orientation feature prevents installation of the top cover in plus or minus 90 degree locations about the central axis.
  • It is an object of the semiconductor wafer container to provide an improved locking mechanism for securing two halves of a wafer container together. The bottom half comprises a wall structure perpendicular to the base. The wall structure comprises segmented inner and outer walls, where each portion of the wall structure has a distinctive arc length. The arc length of each inner wall does not completely overlap with the arc length of any outer wall.
  • It is an object of the semiconductor wafer container to provide an improved engagement feature for the locking tabs. These improved tabs include a cover for a wafer container that engages to a base. The cover includes one or more notches, each having a ramp that easily receive latches from the base.
  • It is another object of the semiconductor wafer container to incorporate bi-directional rotation locking feature(s). These features improve orienting, the top member on the bottom member that decreases the amount of top cover rotation and movement with respect to the bottom member. This feature creates a double locking location that securely locates and locks the top cover in place during top cover assembly. The bi-directional rotation locking feature is located on both sides of the perpendicular top cover surfaces of a single wall on both the interior and the exterior simultaneously. This improvement provides bi-directional locking of the captured surface decreases the amount of top cover rotation and movement with respect to the bottom member and increases the rigidity of the containment device when the members are assembled.
  • It is another object of the semiconductor wafer container to incorporate a protective latch well. The latch well is a recess that is incorporated into the top cover which protects the latch arm from being accidentally bumped or inadvertently opened. The tip of the latch surrounded by a wall that protects the latch by lowering the tip of the latch below the planar surface of the Top Cover by at least 2 mm. This recess distance or greater is considered to be adequate to protect the latch from accidental opening.
  • It is still another object of the semiconductor wafer container to include an improved holding and clamping feature to allow for automated machinery to latch onto and hold the bottom member and secure it firmly to the machinery nesting locations. This mechanism is comprised of a single piece feature that is molded into the bottom member. The holding and clamping feature on the bottom member improves equipment interface where these containers are used. The feature is a holding mechanism to allow for automated machinery to latch onto and hold the bottom member and secure it firmly to the machinery nesting locations.
  • It is still another object of the semiconductor wafer container to include an improved curved latch recess for improved closure and retention of the containment device latches. In the improved latch and latch recess the height of the latch is equal to or lower than the inner wall structure. This allows equipment to interface with the bottom member of the container without interference with the equipment and latch height. A curvature on the mating surface provides superior holding and self centering and gripping during handling and after impact. This recessed feature also protects the mating surface from damage when the top cover is disassembled from the bottom member. The latch recess and curved surface also provides increased latch retention and container integrity during impact or shipping. This includes a lowered latch equal to or less than the inner wall height.
  • Various objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention, along with the accompanying drawings in which like numerals represent like components.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)
  • FIG. 1 shows a perspective exploded view of the wafer container with a plurality of wafers disposed between the two wafer container halves.
  • FIG. 2 shows a top view of the bottom housing with the overlapping rib wall pattern.
  • FIG. 3 shows a detailed perspective view of the overlapping inner rib walls.
  • FIG. 4 shows a top view of the bi-directional locking feature in the bottom housing.
  • FIG. 5 shows a perspective view of the bi-directional locking feature on the bottom housing.
  • FIG. 6 shows a perspective view of the bi-directional locking feature on the top housing.
  • FIG. 7 shows an inside plan view of the top housing showing the orientation features.
  • FIG. 8 shows inside plan view of the bottom housing showing the orientation features.
  • FIG. 9 shows a detail perspective view of the orientation key in the top housing.
  • FIG. 10 shows a detail perspective view without the orientation key in the top housing
  • FIG. 11 shows a detail perspective view of the clearance for the orientation key in the bottom housing.
  • FIG. 12 shows a detail perspective view of the interference for the orientation key in the bottom housing.
  • FIG. 13 shows a top perspective view of the bottom housing.
  • FIG. 14 shows a detailed perspective view of the hold down latch.
  • FIG. 15 shows a perspective cross section of the hold down latch.
  • FIG. 16 shows a perspective view of the top and bottom latch tab engaged.
  • FIG. 17 shows a side view of the bottom latch tab.
  • FIG. 18 shows a sectional view of the latch engaged between the top and bottom housings.
  • FIG. 19 shows a detailed view of the engaged between the top and bottom housings.
  • FIG. 20 shows a perspective view of the top and bottom housings in an open exploded view for reference of the internal components.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 shows a perspective exploded view of the wafer container with a plurality of wafers disposed between the two wafer container clam shells. A plurality of semiconductor wafers 20, 21 and 22 are shown between the top 50 and bottom 100 housing with wafer separators 25. The top housing 50 has a planar top surface 105. The inside base surface 102 extends to the outside of the base surface 103 where the bottom housing has a ribbed pattern 101 that supports the bottom of the bottom most semiconductor wafer 20 and provides increased structural strength to the fairly plainer base surface 102 and 103. Both the top 50 and the bottom housings 100 have essentially planar rectangular or square bases. A plurality of inner rib walls 110 and 111 of the bottom housing 100 protect the semiconductor wafers from shifting side damage. These walls can flex to cushion side impact. They are formed in a segmented pattern in the bottom housing. The segmented ribs are shown and described in more detail with FIG. 2. A second set of segmented outer ribs 112 and 113 exist outside of the inner rib walls 110 and 111. The rib walls exist in an overlapped 120 and 121 pattern to prevent debris from passing directly through the segmented ribs.
  • FIG. 2 shows a top view of the bottom housing with the overlapping rib wall pattern. Note that some features, such as bottom ribs, have been deleted from the bottom surface 102 and 103 and the overlapping ribs have been moved slightly to improve clarity of the overlapping rib features being discussed herein. FIG. 3 shows a detailed perspective view of the overlapping inner rib walls. While in FIGS. 2 and 3 only one section of overlapping ribs is identified, the overlapping condition exists in eight places in the bottom housing 100. While the preferred embodiment shows four inner rib walls 110-113 and four outer rib walls 114-117 it is contemplated that a greater or lesser number of overlapping can be used. In FIGS. 2 and 3 the overlap 120 is labeled, and in the preferred embodiment the overlap angle is between 5 and 15 degrees, but prototypes have been made using an overlap angle 120 of 7.5 degrees. The ribs 110-117 are arc segments that extend perpendicular from the essentially planar base 102 and 103. These angles are variable based upon the height of the rib, the material, the thickness of the rib, the desired cushion and the distance between the inner and outer ribs. In general the distance between the inner and outer ribs is controlled based upon the annular rib in the top clam shell housing.
  • The overlapping double wall provides maximum protection from shock or impact to the exterior of the containment device by positioning the inner and outer wall in an offset and overlapping configuration as to increase the protection of the semiconductor wafers from direct transmission forces by increasing the amount of flex movement allowed by the outer wall. Increasing the flex tolerance of the outer wall increases the overall shock absorbing ability of the containment device. This design also allows for a greater percentage of “wrap” around the semiconductor wafer and therefore minimize lateral shift into the gaps between inner wall segments. Segmenting the inner wall makes it more flexible and thus able to absorb and cushion the wafers if the container is dropped or subject to impact.
  • As shown in FIGS. 1 and 3. The outer rib walls 114-117 need not be the same height as the inner rib 110-113 walls. In some cases, the lowered exterior wall allows for greater top cover deflection during impact before it touches the inner wall. The image in the figures shows the exterior rib walls 114-117 at approximately ⅔rds the height of the inner rib walls 110-113 as shown in FIG. 1.
  • FIG. 4 shows a top view of the bi-directional locking feature in the bottom housing 100. FIG. 5 shows a perspective view of the bi-directional locking feature on the bottom housing 100. FIG. 6 shows a perspective view of the bi-directional locking feature on the top housing 50. Starting with FIG. 6 the circular rib 51 is shown extending from the planar base of the top housing 50. A “U” shaped rib extends from the circular rib 51 to the outer edge 55 of the top housing 50 and around to join back with the circular rib 51. This “U” shaped rib can exist in a variety of shapes to provide a key to ensure that it locks into only one of four possible orientations with the bottom housing 100. This “U” shaped rib that extends to the outer edge 55 has an inside face 53 and an outside face 52. Where the “U” shaped rib joins with the outer edge 55 there is an outside protection and support rib 54.
  • A pair of securing ribs consisting of an outer locking rib 131 and an inner locking rib 132 on the bottom housing 100 are configured to engage onto the opposing sides of the inside face 53 and an outside face 52 of the “U” shaped rib when the “U” shaped rib is engaged into the locking cavity 130. Circular lock rib 133 is configured to fit within cavity 56 on the top housing 50 along with the inner lock rib 132. When the rib defined by items 52/53 is engaged into the locking cavity 130 these features improve orienting, the top housing 50 on the bottom housing 100 that decreases the amount of top cover 50 rotation and movement with respect to the bottom member 100. This feature creates a double locking location that securely locates and locks the top cover 50 in place during top cover assembly. The bi-directional rotation locking further increases the rigidity of the containment device when the members are assembled. The “U” shaped and is shown in an approximate orthogonal relationship to three sides of the bottom housing 100. While only one location of the bi-directional lock is shown and described in detail, the feature exists on all four sides of the top and bottom housings.
  • FIG. 7 shows an inside plan view of the top housing showing the orientation features and FIG. 8 shows inside plan view of the bottom housing showing the orientation features. FIG. 9 shows a detail perspective view of the orientation key in the top housing. FIG. 10 shows a detail perspective view without the orientation key in the top housing. FIG. 11 shows a detail perspective view of the clearance for the orientation key in the bottom housing. FIG. 12 shows a detail perspective view of the interference for the orientation key in the bottom housing. For perspective, the area's 90, 91, 92 and 93 are shown enlarged and in perspective in FIGS. 9, 10, 11 and 12 to show the orientation tab 60 and how in allows or blocks seating of the top and bottom housings 50 and 100.
  • In FIG. 9 the orientation rib 60 is shown extending essentially normal from the circular rib 51 at a particular distance 62 from the corner of the “U” shaped rib 54 and 57. In FIG. 10 the orientation rib is not present in area 61 in the corner of the “U” shaped rib 54 and 58. Now refer to FIGS. 11 and 12 to see where the orientation rib 60 would be blocked or bypassed by the details. In FIG. 11 the dimension 106 between the corner radius of curved lock rib 133 and the inner lock rib 132 is shorter than the distance 107 between the curved lock rib 134 and the inner lock rib 132 in FIG. 12. Upon placement of the top housing onto the bottom in an out of proper orientation arrangement the longer circular block rib 134 would interfere with the orientation rib 60. In the correct orientation the shorter circular lock rib 133 would clear the orientation tab 60.
  • From FIG. 7, a total of four orientation tabs are shown to allow the housings to sit flat on the orientation tabs when the housings are not properly aligned. The orientation tabs 60 prevent improper assembly of said top housing and said bottom housing members from being installed 90 degrees out of alignment.
  • FIG. 13 shows a top perspective view of the bottom housing. FIG. 14 shows a detailed perspective view of the hold down latch. FIG. 15 shows a perspective cross section of the hold down latch. In views 13 and 15 some parts of the circular ribs 110, 111, 114 and 115 are visible to help to provide a visual orientation for the pocket 80 and latch features. The bottom housing 100 has an undercut hold down recessed pocket 80 with a latch surface tab 81 for a retention mechanism to hold the housing in automated assembly. The latch surface is formed in a molding process with the molding of said bottom housing 100. The latch surface 81 is located at a height that is equal to or lower than the planar bottom surface 103 of said bottom housing 100. The latch surface 81 further has an angled or curved entry surface 82. The pocket further has at least two essentially vertical side walls 83 to self center said bottom housing on said retention mechanism.
  • The height of the latch is equal to or lower than the inner wall structure to allow equipment to interface with the bottom member of the container without interference with the equipment and recess pocket 80 and the latch surface 81. This recessed feature also protects the mating surface from damage when the top cover is disassembled from the bottom member. In FIGS. 13 and 15 housing latches 70, 71 and 72 are shown. These latches secured the top and bottom housings together.
  • In FIGS. 13 and 15 a plurality of bearing ribs 85 are shown. These ribs are configured to distribute the load from a bottom housing stacked on top of the top housing. Looking briefly at FIG. 18, it can be seen that the annular lip 87 of the bottom housing 100 is placed at a different dimension from the annular lip 86 of the top housing 50. This allows the housings to stack or nest. When stacking multiple wafer containers together the weight of the container when filled with wafers is significant. Some wafer containers are enclosed in a protective plastic bag, and when the stacked bearing surface is small this creates a high bearing load which damages or punctures the protective bag. Calculation and testing has identified that multiple bearing surfaces 85 of greater than 2.25 mm2 each with more than 4 bearing ribs 85 per quadrant will adequately protect the containers from damage and will also prevent the protective plastic bags from being punctured or damaged.
  • FIG. 16 shows a perspective view of the top and bottom latch tab engaged. FIG. 17 shows a side view of the bottom latch tab. FIG. 18 shows a sectional view of the latch engaged between the top and bottom housings. FIG. 19 shows a detailed view of the engaged between the top and bottom housings. The bottom housing 100 has at least one latch that engages in a corresponding notch 75 located on the top housing 50.
  • The top surface 74 of said latch 70 is located at a height 76 that is below the top surface of said at least one rib 141. The height 76 of the latch 70 is equal to or lower than the inner wall 141 structure. This allows equipment to interface with the bottom member of the container without interference with the equipment and latch height. This further reduces the possibility of damage to the latch 70 if the bottom housing 100 is dragged on a surface. In the preferred embodiment there are four latches 70 and four corresponding notches 75 located in each corner region of said top housing 50 or said bottom 100 housing, but as few as one or two are contemplate as well as four or more latches. FIG. 19 shows that the notch 70 has a curve entry ramp 77 and a recess 78 that elevates the latch 70 above said entry ramp 77 and lowers said latch 70 into the recess 78 to retain the latch 70 in the recess 78. When the latch(s) are secured the top of the inner rib wall 111 is tightly engaged and captured on the corresponding surface 84 of the top housing 50. The notch 75 is located in a protective latch well 140 that protects the latch 70 during handling and impact. The protective latch well 140 exists below the planar rectangular surface 105 of the top housing 50. The protective latch well is sufficiently sized to limit accidental opening of the latch, and is also sufficiently sized to allows access for human fingers and automated machines that will open the housings. The side walls 142 protective latch well provides only limited clearance between the side walls 142 and the hook 74/notch 75.
  • FIG. 20 shows a perspective view of the top and bottom housings in an open exploded view for reference of the internal components. This view provides a view into the open cavity of the top housing 50 and the bottom housing 100 without obstruction of the semiconductor wafers.
  • Thus, specific embodiments of a semiconductor wafer container have been disclosed. It should be apparent, however, to those skilled in the art that many more modifications besides those described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims.

Claims (20)

  1. 1. A wafer container comprising:
    a top housing and a bottom housing that nest together to form a clam shell housing with an inner cavity for storage for at least one semiconductor wafer;
    said top housing having an essentially planar rectangular base with least one rib that extends perpendicular from said base in an essentially circular orientation;
    said bottom housing having an essentially planar rectangular base with at least one rib that extends perpendicular from said base wherein said at least one rib on said bottom housing is arranged concentric and at a different radius from said at least one rib that extends perpendicular from said base of said top housing;
    said bottom housing further having an undercut recessed pocket with a latch surface for a retention mechanism;
    said latch surface being formed in a molding process with the molding of said bottom housing.
  2. 2. The wafer container according to claim 1 wherein said latch surface is located at a height that is equal to or lower than the planar bottom surface of said top housing.
  3. 3. The wafer container according to claim 1 wherein said latch surface further has an angled or curved entry surface.
  4. 4. The wafer container according to claim 1 wherein said pocket further has at least two essentially vertical side walls to self center said bottom housing on said retention mechanism.
  5. 5. The wafer container according to claim 1 wherein the latch exists in a protective latch well located below said planar rectangular base on said top housing.
  6. 6. The wafer container according to claim 1 wherein said at least one latch surface includes at least four latches surfaces located in each corner region of said top housing.
  7. 7. The wafer container according to claim 1 wherein said notch latch surface has a curve entry ramp and recess that elevates a latch above said entry ramp and lowers said latch into said recess to retain said latch in said recess.
  8. 8. A wafer container comprising:
    a top housing and a bottom housing that nest together to form a clam shell housing with an inner cavity for storage for at least one semiconductor wafer;
    said top housing having an essentially planar rectangular base with least one rib that extends perpendicular from said base in an essentially circular orientation;
    said bottom housing having an essentially planar rectangular base with at least one rib that extends perpendicular from said base wherein said at least one rib on said bottom housing is arranged concentric and at a different radius from said at least one rib that extends perpendicular from said base of said top housing;
    said bottom housing having at least one latch that engages in a corresponding notch located on said top housing, wherein
    a top surface of said latch is located at a height that is below a top surface of said all ribs.
  9. 9. The wafer container according to claim 8 wherein said at least one latch includes at least four latches and four corresponding notches located in each corner region of said top housing or said bottom housing.
  10. 10. The wafer container according to claim 8 wherein said notch has a curve entry ramp and recess that elevates said latch above said entry ramp and lowers said latch into said recess to retain said latch in said recess.
  11. 11. The wafer container according to claim 8 wherein said notch is located in a pocket that protects said latch during handling and impact.
  12. 12. The wafer container according to claim 8 that further has an undercut recessed pocket with a latch surface for a retention mechanism.
  13. 13. The wafer container according to claim 8 wherein said at least one latch is located in a protective latch well.
  14. 14. The wafer container according to claim 13 wherein said protective latch well exists below said essentially planar rectangular base.
  15. 15. A wafer container comprising:
    a top housing and a bottom housing that nest together to form a clam shell housing with an inner cavity for storage for at least one semiconductor wafer;
    said top housing having an essentially planar rectangular base with least one rib that extends perpendicular from said base in an essentially circular orientation;
    said bottom housing having an essentially planar rectangular base with at least one rib that extends perpendicular from said base wherein said at least one rib on said bottom housing is arranged concentric and at a different radius from said at least one rib that extends perpendicular from said base of said top housing;
    said top housing having a protective latch well;
    said bottom housing having at least one latch that engages in a corresponding notch located within said protective latch well, wherein
    said protective latch well exists below said essentially planar rectangular base.
  16. 16. The wafer container according to claim 15 that further includes at least one latch that extends from said bottom housing.
  17. 17. The wafer container according to claim 16 that further includes a notch in said protective latch well.
  18. 18. The wafer container according to claim 16 wherein said protective latch well provides limited access to said latch.
  19. 19. The wafer container according to claim 17 wherein said protective latch well provides clearance for a human finger or automated machine to disengage said at least one latch from said notch.
  20. 20. The wafer container according to claim 16 wherein a top surface of said latch is located at a height that is below a top surface of said at least one rib.
US14468240 2009-08-26 2014-08-25 Wafer container with recessed latch Abandoned US20140360915A1 (en)

Priority Applications (3)

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US12548368 US8109390B2 (en) 2009-08-26 2009-08-26 Wafer container with overlapping wall structure
US12606921 US8813964B2 (en) 2009-08-26 2009-10-27 Wafer container with recessed latch
US14468240 US20140360915A1 (en) 2009-08-26 2014-08-25 Wafer container with recessed latch

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US14468240 US20140360915A1 (en) 2009-08-26 2014-08-25 Wafer container with recessed latch

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EP (1) EP2470455A4 (en)
JP (2) JP5727495B2 (en)
KR (1) KR20120115207A (en)
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US20110049006A1 (en) 2011-03-03 application
CN102666314B (en) 2015-01-28 grant
JP2013508997A (en) 2013-03-07 application
US8813964B2 (en) 2014-08-26 grant
JP5727495B2 (en) 2015-06-03 grant
EP2470455A4 (en) 2014-01-22 application
JP2015149498A (en) 2015-08-20 application
EP2470455A1 (en) 2012-07-04 application
CN102666314A (en) 2012-09-12 application
KR20120115207A (en) 2012-10-17 application
WO2011053109A1 (en) 2011-05-05 application

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