US20140348652A1

US20140348652A1 - Device for testing fan

Info

Publication number: US20140348652A1
Application number: US14/283,313
Authority: US
Inventors: Bo Tian; Kang Wu
Original assignee: Hongfujin Precision Industry Shenzhen Co Ltd; Hon Hai Precision Industry Co Ltd
Current assignee: Hongfujin Precision Industry Shenzhen Co Ltd; Hon Hai Precision Industry Co Ltd
Priority date: 2013-05-24
Filing date: 2014-05-21
Publication date: 2014-11-27
Also published as: CN104179705A

Abstract

A fan test device to connect a motherboard and a fan includes a control chip, a first connector, a second connector, a first switch chip, a second switch chip, a first electronic switch, and a second electronic switch. The control chip is connected to sensing pins of the first and second connectors. The first electronic switch is connected between a power terminal and a power pin of the first connector. The second electronic switch is connected between the power terminal and a power pin of the second connector. The control chip outputs different signals corresponding to the connection of the first and second connectors to control the first and second switch chips.

Description

FIELD

The present disclosure relates to a fan test device.

BACKGROUND

Typically, a fan test device has a first connector to connect to a motherboard and a second connector to connect a fan.

BRIEF DESCRIPTION OF THE DRAWING

Many aspects of the present disclosure can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing, like reference numerals designate corresponding parts throughout the several views.

The FIGURE is a circuit diagram of an embodiment of a fan test device of the present disclosure.

DETAILED DESCRIPTION

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
The FIGURE illustrates an embodiment of a fan test device 10 of the present disclosure.
The fan test device 10 can comprise a first connector J1, a second connector J2, a control chip U, a switch chip U1, a switch chip U2, a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a light-emitting diode (LED) D3, a first fuse FS1, a second fuse FS2, a first electronic switch Q1, and a second electronic switch Q2.
A first terminal of the first electronic switch Q1 is connected to a control terminal C1 of the control chip U. A power pin 1 of the first connector J1 is connected to the second terminal of the first electronic switch Q1. A third terminal of the electronic switch Q1 is connected to a first power terminal P12V_FB. The third terminal of the electronic switch Q1 is also connected to a cathode of the first diode D1. An anode of the first diode D1 is coupled to the power pin 1 of the first connector J1 through the first fuse FS1. A signal pin 2 of the first connector J1 is coupled to a signal pin A1 of the first switch chip U1. A sense pin 3 of the first connector J1 is connected to an input pin I1 of the control chip U. A ground pin 4 of the first connector J1 is grounded.
A first terminal of the second electronic switch Q2 is connected to a control pin C2 of the control chip U. A power pin 1 of the second connector J2 is connected to a second terminal of the second electronic switch Q2. A third terminal of the second electronic switch Q2 is connected to the first power terminal P12V_FB. The third terminal of the second electronic switch Q2 is also connected to a cathode of the second diode D2. An anode of the second diode D2 is coupled to the power pin 1 of the second connector J2 through the second fuse FS2. A signal pin 2 of the second connector J2 is coupled to a signal pin A2 of the second switch chip U2 through the second resistor R2. A sense pin 3 of the second connector J2 is connected to an input pin I2 of the control chip U. A ground pin 4 of the second connector J2 is grounded.
A power pin VCC of the first switch chip U1 is connected to a second power terminal P5V. A signal pin S1, a signal pin B1, and a signal pin B2 of the first switch chip U1 are connected to an output pin O1, a speed pin TACH1, and an alarm pin Alarm1 of the control chip U respectively. A ground pin OE and a ground pin GND of the first switch U1 are grounded.
A power pin VCC of the second switch chip U1 is connected to the second power terminal P5V. A signal pin S2, a signal pin B3, and a signal pin B4 are connected to an output pin O2, a speed pin TACH2, and an alarm pin Alarm2 of the control chip U respectively. A ground pin OE and a ground pin GND of the second switch U2 are grounded.
When the first connector is connected to the motherboard and the second connector is connected to the fan, the motherboard outputs a first signal to the input pin I1 of the control chip U through the sense pin 3 of the first connector J1. The control chip U outputs a low level signal, such as logic 0, to the first terminal of the first electronic switch Q1 through the control pin C1. The first electronic switch Q1 is turned off The motherboard outputs a first voltage to the first power terminal P12V_FB through the first fuse FS1 and the first diode D1 in that order. The fan outputs a second signal to the input pin I2 of the control chip U through the sense pin 3 of the second connector J2. The control chip outputs a high level signal, such as logic 1, to the first terminal of the second electronic switch Q2 through the control pin C2. The second electronic switch is turned on. The first power terminal P12V_FB supplies power for the fan that is connected to the second connector J2. The control chip U outputs a first control signal to a signal pin S1 of the first switch chip U1 through the output pin O1 to couple the signal pin A1 of the first switch chip U1 and the signal pin B2 of the first switch chip U1. The control chip U outputs a second control signal to a signal pin S2 of the second switch chip U2 through the output pin O2 to connect the signal pin A2 and the signal pin B3. The control chip U receives a speed signal of the fan through the speed pin TACH2. When the control chip U determines the speed of the fan is abnormal, the control chip U outputs an alarm signal to the motherboard through the alarm pin Alarm1, the signal pin B2 of the first switch chip U1, the signal pin A1 of the first switch chip U1, and the signal pin 2 of the first connector J1 in that order. The fuse FS1 can protect the circuit.
When the first connector J1 is connected to the fan and the second connector J2 is connected to the motherboard, the motherboard outputs the first signal to the input pin I2 of the control chip U through the sense pin 3 of the second connector J2. The control chip U outputs a low level signal to the first terminal of the second electronic switch Q2 through the control pin C2. The second electronic switch Q2 is turned off. The motherboard outputs the first voltage to the first power terminal P12V_FB through the second fuse FS2, and the second diode D2 in that order. The fan outputs the second signal to the input pin I1 of the control chip U through the sense pin 3 of the first connector J1. The control chip U outputs a high level signal to the first terminal of the first electronic switch Q1 through the control pin C1. The first power terminal P12V_FB supplies power for the fan through the first connector J1. The control chip U outputs the second control signal to the signal pin S1 of the first switch chip U1 connecting the signal pin A1 of the first switch chip U1 and the signal pin B1 of the first switch chip U1. The control chip U outputs the first control signal to the signal pin S2 of the second switch chip U2 connecting the signal pin A2 of the second switch chip U2 and the signal pin B4 of the second switch chip U2. The control chip U receives a speed signal of the fan through the speed pin TACH1. When the control chip U determines the speed of the fan is abnormal, the control chip U outputs an alarm signal to the motherboard through the alarm pin Alarm2, the signal pin B4 of the second switch chip U2, the signal pin A2 of the second switch chip U2, and the signal pin 2 of the second connector J2 in that order. The fuse FS2 can protect the circuit.
The fan test device 10 further comprises an alarm module 20 connected to the control chip U. The alarm module 20 can comprise the third resistor R3 and the LED D3. An anode of the LED D3 is connected to the second power terminal PSV. A cathode of the LED D3 is coupled to the output pin O3 of the control chip U through the third resistor R3. When the control chip U determines the speed of the fan is abnormal, the control chip U outputs a low level signal through the output pin O3. The LED is lit up to warn a user that the speed of the fan is abnormal.
In the embodiment, the first electronic switch Q1 and the second electronic switch Q2 are n-channel field effect transistors.
The fan test device operates normally either when the first connector J1 is connected to the motherboard and the second connector J2 is connected to the fan or when the first connector J1 is connected to the fan and the second connector J2 is connected to the motherboard.
While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

What is claimed is:

1. A fan test device connected between a fan and a motherboard, comprising:

a first diode and a second diode;

a first connector and a second connector;

a first switch chip comprising a first pin connected to a signal pin of the first connector;

a second switch chip comprising a first pin connected to a signal pin of the second connector;

a control chip, wherein a first input pin of the control chip is connected to a sense pin of the first connector, a first output pin of the control chip is connected to a second pin of the first switch chip, a first alarm pin of the control chip is connected to a third pin of the first switch chip, a first speed pin of the control chip is connected to a fourth pin of the first switch chip, a second input pin of the control chip is connected to a sense pin of the second switch chip, s second output pin of the control chip is connected to a second pin of the second switch chip, a second alarm pin of the control chip is connected to a third pin of the second switch chip, and a second speed pin of the control chip is connected to a fourth pin of the second switch chip;

a first electronic switch and a second electronic switch, wherein a first terminal of the first electronic switch is connected to a first control pin of the control chip, a second terminal of the first electronic switch is connected to the a first power terminal, a third terminal of the first electronic switch is connected to a power pin of the first connector, the second terminal of the first electronic switch is connected to an anode of the first diode, the third terminal of the first electronic switch is connected to a cathode of the first diode, a first terminal of the second electronic switch is connected to a second control pin of the control chip, a second terminal of the second electronic switch is connected to the first power terminal, a third terminal of the second electronic switch is connected to a power pin of the second connector, the second terminal of the second electronic switch is connected to an anode of the second diode, the third terminal of the second electronic switch is connected to a cathode of the second diode, the third terminal of the first electronic is connected to the second terminal of the first electronic switch when the first terminal of the first electronic switch is at a high level, the third terminal of the second electronic is disconnected from the second terminal of the second electronic switch when the first terminal of the second electronic switch is at a low level, the third terminal of the second electronic is connected to the second terminal of the second electronic switch when the first terminal of the second electronic switch is at a high level;

wherein when the second pin of the first switch chip receives a first control signal from the control chip, the first pin of the first switch chip is connected to the fourth pin of the first switch chip, when the second pin of the second switch chip receives the first control signal from the control chip, the first pin of the second switch chip is connected to the fourth pin of the second switch chip, when the second pin of the first switch chip receives a second control signal from the control chip, the first pin of the first switch chip is connected to the third pin of the first switch chip, when the second pin of the second switch chip receives the second control signal, the first pin of the second switch chip is connected to the third pin of the first switch chip;

wherein the control chip receives signals of speed of the fan from one of the first connector or the second connector, and when the control chip determines the speed of the fan is abnormal, the control chip outputs an alarm signal to the motherboard.

2. The fan test device of claim 1, wherein the first and second electronic switches are n-channel field effect transistors.

3. The fan test device of claim 1, further comprising an alarm module, wherein the alarm module comprises a first resistor and a light-emitting diode (LED), an anode of the LED is connected to a second power terminal, and a cathode of the LED is coupled to a third output pin of the control chip through the first resistor.

4. The fan test device of claim 1, further comprising a first fuse and a second fuse, wherein the first fuse is connected between the power pin of the first connector and the anode of the first diode, and the second fuse is connected between the power pin of the second connector and the anode of the second diode.

5. The fan test device of claim 1, further comprising a second resistor and a third resistor, wherein the second resistor is connected between the signal pin of the first connector and the first pin of the first switch chip, and the third resistor is connected between the signal pin and the first pin of the second switch chip.

6. The fan test device of claim 3, wherein the anode of the LED is connected to a second power terminal to receive a high level signal, when the control chip determines the speed of the fan is abnormal, the control chip outputs a low level signal through the third output pin to light the LED.