US20140339625A1 - Pseudo self aligned radhard mosfet and process of manufacture - Google Patents
Pseudo self aligned radhard mosfet and process of manufacture Download PDFInfo
- Publication number
- US20140339625A1 US20140339625A1 US14/337,865 US201414337865A US2014339625A1 US 20140339625 A1 US20140339625 A1 US 20140339625A1 US 201414337865 A US201414337865 A US 201414337865A US 2014339625 A1 US2014339625 A1 US 2014339625A1
- Authority
- US
- United States
- Prior art keywords
- region
- source
- substrate
- layer
- vdmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title abstract description 26
- 230000008569 process Effects 0.000 title abstract description 20
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 11
- 210000000746 body region Anatomy 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 abstract description 14
- 230000005855 radiation Effects 0.000 abstract description 8
- 239000007858 starting material Substances 0.000 abstract description 2
- 239000007943 implant Substances 0.000 description 22
- 230000015556 catabolic process Effects 0.000 description 16
- 238000013461 design Methods 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 230000005865 ionizing radiation Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- This invention relates to Vertical Power MOSFETs (VDMOS hereinafter) suitable for space or military applications , where the radiation environment (light or heavy ions) creates conditions for severe degradation of electrical parameters of the MOSFET or even total destruction of the device.
- VDMOS Vertical Power MOSFETs
- the invention addresses the main phenomenon known to date to deteriorate or destroy a Power MOSFET operating in space, namely the Single Event Burnout due to heavy ion bombardment.
- VDMOS transistors of various voltage and current ratings are these days the device of choice for high-frequency switching power supplies as they are incorporated in a wide variety of power control and conversion applications for space and military systems.
- Outer space applications such as communication satellites, weather satellites, GPS (Global Positioning Systems) and earth observations use many Power MOSFETs due to their high switching speed, low conduction losses and small foot print.
- MOS Metal Oxide Semiconductor
- Vth threshold voltage
- BVdss blocking voltage
- Idss leakage current
- Gm transconductance
- Rdson On Resistance
- SEB Single Event Burnout
- the drain bias of the VDMOS device exceeds certain values (or the electric field in the device approaches critical values) then, locally and within diameters smaller than one micron, the hole-electron density is increased, inducing current densities in excess of 104 A/cm2. Holes will be driven toward the surface for an N-Channel MOSFET and underneath the source layer of the VDMOS device and can easily develop a voltage drop close to or higher than 0.7V, turning on the parasitic bipolar transistor inherent to any VDMOS structure.
- the doping of the P-Well underneath the source, the length of the source and the length of the channel are the main design and process parameters one has to optimize and control in order to increase the survivability of VDMOS transistor to heavy ions. Therefore, the placement of the heavy doping underneath the source or the alignment of the source inside of the P-Wells are of the utmost importance as slight lateral variations in the placement of these heavily doped layers can create uneven turn-on (sooner than desired) of the parasitic NPN transistor and lead to destruction of the Power MOSFET.
- the parasitic bipolar transistor When the parasitic bipolar transistor gets turned on, it enters in what is called secondary breakdown of the NPN (for a N-Channel VDMOS), or the “snap back” mode of operation. Once the secondary breakdown phenomenon has been triggered, the entire energy of the power supply gets “dumped” at the location on the die where this mode of operation has been initiated. Following that, the local temperature of the die increases tremendously and the junctions of the device become shorted due to diffusion of the top metals into semiconductor.
- secondary breakdown of the NPN for a N-Channel VDMOS
- the most common way to reduce the propensity of the parasitic NPN to turn on is to increase the doping of the P-Well underneath the source.
- Increasing the doping of what is called the UIS (Unclamped Inductive Switching) implant layer has its own limitations as the doping of this layer can easily reach the silicon-silicon dioxide interface (channel region) and, when it does that, the threshold voltage of the part, at that location, has a sharp increase, virtually making a “dead” MOSFET at that location.
- the diffusion of the UIS layer into the channel is exacerbated if the location of the implant is improperly placed, in other words, if one side of the implant is closer to the channel region. Therefore, as important as the doping level, perfect placement (or perfect “alignment”) of the UIS layer in relationship to the source or the P-Well is the goal of any manufacturer of radhard MOSFETs.
- the gate of a lateral semiconductor device can be “self-aligned” to its corresponding source and drain regions.
- the gate is used to mask a dopant implantation step that is performed to create the source and drain regions.
- Dopant is implanted in regions not blocked by the gate, and dopant is not implanted in regions blocked by the gate.
- an edge of the source region and an edge of the drain region are tightly aligned with edges of the gate, and subsequent drive or diffusion steps will ensure that the gate overlaps the edge of the source and drain regions. Therefore, in lateral devices, by ensuring the critical characteristic of the gate's overlap of the source and drain regions, this gate “self-alignment” technique may result in improved device performance.
- One aspect of the invention is a manufacturing method of making a VDMOS power transistor in which all essential implanted and diffused layers are self aligned to a sacrificial masking layer such as polysilicon (“poly”), which later in the process is stripped off and a late gate oxide is grown.
- a sacrificial masking layer such as polysilicon (“poly”)
- body regions and source regions in a substrate are tightly aligned with each other due to being implanted through the same openings in a sacrificial layer.
- a spacer layer is formed in the openings of the sacrificial layer and is largely removed, but spacer walls are left adjoining the walls of the sacrificial layer at the edges of the openings.
- UIS regions in the substrate are tightly aligned to the source regions due to being implanted through the remaining openings between the spacer walls.
- a gate oxide is formed late in the process, after the high temperature dopant implantation and diffusion steps, preventing the degradation of a radiation resistance of the gate oxide. Tight alignment of all three regions results in transistors that are substantially symmetric, which may increase a performance characteristic of the resulting high-voltage radiation-hardened semiconductor device.
- the VDMOS device is made on an epitaxial (“epi”) layer with a graded doping profile.
- epi epitaxial
- One advantage is that a “graded epi” has a significantly higher secondary breakdown of the parasitic NPN transistor in comparison to step epi and, if properly designed, will produce a MOSFET with a lower Rdson.
- FIG. 1 is a cross section of a gate finger of an embodiment of a VDMOS device with perfectly aligned diffusion layers, as result of the pseudo self-aligned process flow of the invention.
- FIG. 2 shows in a generic way a “graded epi” doping profile according to this invention.
- FIGS. 3-18 are cross-sectional views of the VDMOS transistor, illustrating an embodiment of a process flow to manufacture the device, according to the principles of this invention, in the following steps:
- FIG. 3 shows sacrificial oxide and sacrificial poly layers as deposited.
- FIG. 4 shows patterning of sacrificial poly layer for the “self aligned” implantations.
- FIG. 5 shows a P-well ion implantation using the patterned sacrificial poly (active area and termination) as a mask.
- FIG. 6 shows a P-well diffusion (active area and termination).
- FIG. 7 shows a sacrificial oxide patterning for source implantation.
- FIG. 8 shows thin spacer deposition and etch.
- FIG. 9 shows a UIS 1 implant.
- FIG. 10 shows a “co-diffusion” of the source and UIS implants.
- FIG. 11 shows a photo thin process (photo resist recessed and exposing the top of the poly).
- FIG. 12 shows a sacrificial poly etch (dry etch, isotropic, low oxide/silicon selectivity).
- FIG. 13 shows an oxide etch (the entire surface of wafers is cleared of oxide).
- FIG. 14 shows a blow up cross section of the center part of FIG. 13 , with emphasis on perfect symmetry (left and right) of the structure around the geometrical center.
- FIG. 15 shows a “late gate oxide” process.
- FIG. 16 shows a final poly deposition and etch and BPSG deposition, reflow and patterning.
- FIG. 17 shows a front metal deposition and patterning.
- FIG. 18 shows a passivation (oxynitride) deposition and patterning.
- FIG. 19 is a graph which represents a comparison of the secondary breakdown voltage of a “step epi” and “graded epi” design of a 200V VDMOS.
- FIG. 20 is a plot which compares the secondary breakdown of a “single epi”, “step epi” and “graded epi” design for a 100V VDMOS.
- the cross sections represent a small section of the active area and a portion of the termination, surrounding the active area.
- the active area is formed by “repeating” a “basic” cell, which can be either “stripes” of gate fingers or “closed” cells of various shapes (squares, rectangles, hexagons, crosses, and so on).
- This invention in concept and substance, is applicable to any top layout design of a Vertical Power MOSFET.
- the process flow of a VDMOS according to this invention starts with epitaxial wafers of any type of doping (either N-type or P-Type) 101 , 102 , 103 grown on a substrate 100 of the same polarity as the epitaxial layer.
- FIG. 2 shows a preferred gradient doping profile in which the substrate doping at the right has a first doping in the wafer and the upper epitaxial layer has a less second doping that is least near the upper surface on the left and increases in a gradient proceeding depthwise (rightward in FIG. 2 ) toward the wafer layer and substrate doping.
- This graded doping profile is substantially continuous.
- a sacrificial oxide layer 117 and a sacrificial polysilicon (“poly”) layer 118 are deposited.
- the sacrificial oxide layer can be around 1000 A (750 A-1500 A) thick and the sacrificial poly layer can be around 12000 A (10,000 A-15000 A) thick.
- the sacrificial poly layer can be referred to more generally as a sacrificial masking layer, and can be formed of other materials with slow etch rate in hydrofluoric solutions, such as Oxynitride or Nitride.
- a light doping enhancement implantation usually called “Jfet” implant, 104 ) can be performed either through a mask or across the entire surface of the wafers.
- the sacrificial poly 118 is patterned according to the designed layout of the structure ( FIG. 4 ), for example as stripes.
- the central area above the JFET region 104 is referred to as the active area.
- FIG. 5 is a cross-sectional view of the device after P-Well implants 105 are placed inside of the windows created in the sacrificial Poly. The remaining oxide 117 on the wafers is easily penetrated by the implantation ions if the proper implant energy is chosen.
- the implanted P-Wells 105 are driven to the desired depth and then, using a properly designed mask, at FIG. 7 the sacrificial oxide 117 is patterned such that a source ion implantation layer 113 is placed inside of the P-Wells.
- the remaining oxide 117 A masks a central body contact region 119 of the substrate spaced between the polysilicon strips 118 to permit later metal contact by metal 122 ( FIG. 17 ) to the P-well body 105 and the source implants 113 to enable forming a source-body short.
- the laterally outward ends of the source implant is perfectly aligned to the P-Wells as the sacrificial poly 118 acts as an implant barrier for both the P-Well and Source implants and its edge defines the starting point of the implanted layer. (Note: the laterally inward ends of the source implant regions adjoining region 119 are non-critical, region 119 need not be exactly centered. See FIG. 14 .)
- the same sacrificial poly 118 is used now for the creation of oxide spacers 110 ( FIG. 8 ), placed along the edges of the sacrificial poly pseudo-gates 118 to offset the next heavy ion implantation 106 ( FIG. 9 ) , which has the same polarity as the P-Wells (and opposite polarity as the source implants).
- These high dose implants 106 are to minimize the base resistance of the parasitic NPN transistor and therefore their dose level and their placement is essential in improving the survivability of the Power MOSFET under heavy cosmic ion bombardment ( FIG. 9 ).
- These heavy dose layers are usually called UIS implants as they significantly increase the capability of the power MOSFET to withstand high currents while in avalanche mode (Unclamped Inductive Switching test).
- boron is used for the N-channel device, phosphorus for a P-channel device.
- a suitable dose is in the range of 1E15 to 3E15/cm2, with a target of 2E15/cm2.
- Energy levels for depth placement can be around 160 Key (120-180 Key) for sacrificial poly thickness of around 13000 Angstroms (Range: 10,000-15,000 Angstroms).
- the next step is co-diffusion of the source 113 and the UIS layers 106 ( FIG. 10 ), after which the wafers are coated with a thin layer of photo-resist 116 .
- Thickness and uniformity of the resist layer 116 are important as they determine the amount of resist to be removed in the next process step in FIG. 11 .
- a suitable photoresist thickness can be 1.5 to 2 micrometers. The teachings of this process are described in applicant's U.S. Pat. No. 5,019,522.
- the resist is “thinned” during a plasma resist etching process such that only the top of the sacrificial poly layer 118 and the tops of the side wall oxide spacers are exposed ( FIG. 11 ).
- this layer is removed using an isotropic plasma etch of silicon, shown in FIG. 12 .
- Any silicon dry etch process with a reasonable isotropy and selectivity (silicon to oxide etch rates) is suitable for this step.
- Wafers prepared in this way have all desired layers embedded in silicon at the desired depth in vertical direction and with virtually perfect alignment in the lateral/horizontal direction of various implanted layers.
- the laterally outer edges of the P-well (body), the source implants and the UIS region are substantially symmetrical about centerline C/L ( FIG. 14 ), as are the channel regions adjoining the outer edges of the source implants.
- FIG. 14 is a close up cross section of a P-Well region with all the required layers to create a VDMOS transistor, perfectly aligned inside of the P-Well.
- threshold voltage across the entire die is uniform and therefore a uniform temperature across the entire active area is maintained for any drain current.
- Having the UIS implants 106 aligned laterally underneath the source implants 113 creates the same turn-on conditions for the parasitic NPN over the entire die area, with obvious beneficial results for SEB tests.
- a late gate oxidation process is now performed ( 108 , FIG. 15 ), with all the specifics of a thermal oxidation process specially tailored for radiation hardened MOSFETs, specifics that will not be disclosed here as they are well-known and not relevant to the teaching of this invention.
- the resulting gate oxide is substantially free from interface and oxide traps.
- the final poly layer 119 is then deposited on the late gate oxide layer 108 , doped and patterned on the wafers. ( FIG. 16 ).
- An inter-dielectric layer 112 of choice (most commonly used being a boro-phospho-silicate glass BPSG layer) is deposited and re-flowed at relatively low temperatures, such that the anti-radiation properties of the gate oxide layer are not degraded by the reflow thermal process step.
- This inter-dielectric layer 112 is then patterned to expose the source and the P-Wells.
- a top metal layer 122 is now deposited , patterned and etched ( FIG. 17 ).
- Patterning of the final poly layer 119 and the inter-dielectric layer are noncritical.
- the critical lateral alignments have already been established in prior steps, as shown in FIG. 14 .
- next steps are standard for any VDMOS transistors, namely passivation 123 deposition and etch ( FIG. 18 ), backside grinding, optional backside implantation and implant activation and backside metallization of wafers.
- VDMOS transistor can benefit for SEB test if the device, made using state of the art process (i.e. pseudo self aligned process flow) is manufactured on wafers with a graded doping profile.
- Advanced TCAD simulation tools like Silvaco, allows one to “create” a VDMOS structure identical with the unit cell of the real device. All main elements of the VDMOS cell are present in the simulated structure, and the electrical performance of such a device can be analyzed and compared changing only one variable.
- Vbr2 is the secondary breakdown of the parasitic NPN transistor
- FIG. 19 shows a direct comparison of the Id-BV characteristics of a step epi and a graded epi design for a 200V rated MOSFET.
- Vbr2 denotes the secondary breakdown point
- FIG. 20 shows the same comparison, this time for a 100V rated MOSFET.
- Gold Ions Gold Ions
- Energy 1500 MeV
- Fluency 1.0E6 ions/cm2.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- This application is a division of copending U.S. patent application Ser. No. 13/742,253, filed Jan. 15, 2013, now U.S. Pat. No. , which claims the benefit of U.S. provisional patent application Ser. No. 61/586,888, filed Jan. 16, 2012, incorporated by reference herein.
- This invention relates to Vertical Power MOSFETs (VDMOS hereinafter) suitable for space or military applications , where the radiation environment (light or heavy ions) creates conditions for severe degradation of electrical parameters of the MOSFET or even total destruction of the device. The invention addresses the main phenomenon known to date to deteriorate or destroy a Power MOSFET operating in space, namely the Single Event Burnout due to heavy ion bombardment.
- VDMOS transistors of various voltage and current ratings are these days the device of choice for high-frequency switching power supplies as they are incorporated in a wide variety of power control and conversion applications for space and military systems. Outer space applications such as communication satellites, weather satellites, GPS (Global Positioning Systems) and earth observations use many Power MOSFETs due to their high switching speed, low conduction losses and small foot print. One extra requirement for MOS (Metal Oxide Semiconductor) devices operating in outer space is long term reliability, with high tolerance to ionizing radiation, high energy particles and the like. For VDMOS Power Transistors, threshold voltage (Vth), blocking voltage (BVdss), leakage current (Idss), transconductance (Gm) and On Resistance (Rdson) are all affected by the ionizing radiation and therefore a Power MOSFET suitable for such an application has to be “radiation hardened” by design and fabrication process.
- From the very beginning of using VDMOS devices in space applications, Single Event Burnout (SEB) was immediately identified as one of the main limitations of using commercial VDMOS devices in environments with increased flux of heavy ions. Much research has been devoted to SEB and to means to improve the capability of a VDMOS device under the bombardment of heavy ions. In summary, a high energy ion creates a “sheath” of electric charge along its path inside the semiconductor, proportional with its LET (Linear Energy Transfer).
- If the drain bias of the VDMOS device exceeds certain values (or the electric field in the device approaches critical values) then, locally and within diameters smaller than one micron, the hole-electron density is increased, inducing current densities in excess of 104 A/cm2. Holes will be driven toward the surface for an N-Channel MOSFET and underneath the source layer of the VDMOS device and can easily develop a voltage drop close to or higher than 0.7V, turning on the parasitic bipolar transistor inherent to any VDMOS structure.
- The doping of the P-Well underneath the source, the length of the source and the length of the channel are the main design and process parameters one has to optimize and control in order to increase the survivability of VDMOS transistor to heavy ions. Therefore, the placement of the heavy doping underneath the source or the alignment of the source inside of the P-Wells are of the utmost importance as slight lateral variations in the placement of these heavily doped layers can create uneven turn-on (sooner than desired) of the parasitic NPN transistor and lead to destruction of the Power MOSFET.
- When the parasitic bipolar transistor gets turned on, it enters in what is called secondary breakdown of the NPN (for a N-Channel VDMOS), or the “snap back” mode of operation. Once the secondary breakdown phenomenon has been triggered, the entire energy of the power supply gets “dumped” at the location on the die where this mode of operation has been initiated. Following that, the local temperature of the die increases tremendously and the junctions of the device become shorted due to diffusion of the top metals into semiconductor.
- The most common way to reduce the propensity of the parasitic NPN to turn on is to increase the doping of the P-Well underneath the source. Increasing the doping of what is called the UIS (Unclamped Inductive Switching) implant layer has its own limitations as the doping of this layer can easily reach the silicon-silicon dioxide interface (channel region) and, when it does that, the threshold voltage of the part, at that location, has a sharp increase, virtually making a “dead” MOSFET at that location. The diffusion of the UIS layer into the channel is exacerbated if the location of the implant is improperly placed, in other words, if one side of the implant is closer to the channel region. Therefore, as important as the doping level, perfect placement (or perfect “alignment”) of the UIS layer in relationship to the source or the P-Well is the goal of any manufacturer of radhard MOSFETs.
- As is known in the art, the gate of a lateral semiconductor device can be “self-aligned” to its corresponding source and drain regions. In such cases, the gate is used to mask a dopant implantation step that is performed to create the source and drain regions. Dopant is implanted in regions not blocked by the gate, and dopant is not implanted in regions blocked by the gate. As a result, an edge of the source region and an edge of the drain region are tightly aligned with edges of the gate, and subsequent drive or diffusion steps will ensure that the gate overlaps the edge of the source and drain regions. Therefore, in lateral devices, by ensuring the critical characteristic of the gate's overlap of the source and drain regions, this gate “self-alignment” technique may result in improved device performance.
- In vertical DMOS semiconductor device fabrication, self-alignment of the source and body diffusions is itself important to providing symmetrical channel lengths and uniform channel structures. Both lateral MOS and vertical DMOS self-aligned processes rely on early formation of the gate structure, to which the body and source diffusions are self-aligned. As described in U.S. Pat. No. 4,259,779, however, forming a gate oxide after relatively high-temperature fabrication steps (such as those used to create doped regions in a substrate) may prevent substantial degradation of the radiation resistance of vertical DMOS semiconductor devices. This procedure, referred to as late-gate formation, is inconsistent with the foregoing self-alignment procedures.
- Recent research, simulation and experimental work have demonstrated that increasing the secondary breakdown of the parasitic NPN transistor can be achieved if the electric field at the transition region between the epitaxial (“epi”) layer and the substrate is “tailored” by using two epi layers (Liu, Sandra, “Effect of Buffer Layer on Single Event Burnout of Power DMOSFETs”, IEEE 2007, NSREC Paper No PJ-5 and Liu, Sandra, “Single-Event Burnout and Avalanche Characteristics of Power DMOSFETs,” IEEE 2006, NSREC Paper No. 6, Vol. 53, December 2006). By increasing the doping of the first epi layer (the one closer to the substrate), the carrier multiplication in the presence of high electric field and in the presence of charge generated by the heavy ion is minimized (“avalanche injection” effect is minimized, see Beatty, Brent A, “Second Breakdown in Power Transistor due to Avalanche Injection, IEEE Transactions on Electron Devices, Vol. ED-23, No. 8, August 1976). By creating a lower electric field “charge multiplication effect” is also lower and therefore less carriers are driven toward the ground terminal, with lower chances that the NPN parasitic bipolar will be turned on.
- As shown by the work of Sandra Liu, the addition of a buffer epitaxial layer is an improvement but the “snap back” phenomenon is still present, nevertheless at higher voltages, but it is still there. This approach has the drawback that any additional epitaxial layers, regardless of their doping, are detrimental to the Rdson of the VDMOS and therefore a tradeoff between the secondary breakdown and the On Characteristics of the device has to be accepted.
- Accordingly, a need remains for a better way to make radiation resistant (“radhard”) power MOSFET devices.
- One aspect of the invention is a manufacturing method of making a VDMOS power transistor in which all essential implanted and diffused layers are self aligned to a sacrificial masking layer such as polysilicon (“poly”), which later in the process is stripped off and a late gate oxide is grown.
- In a radiation hardened high voltage semiconductor device, body regions and source regions in a substrate are tightly aligned with each other due to being implanted through the same openings in a sacrificial layer. A spacer layer is formed in the openings of the sacrificial layer and is largely removed, but spacer walls are left adjoining the walls of the sacrificial layer at the edges of the openings. UIS regions in the substrate are tightly aligned to the source regions due to being implanted through the remaining openings between the spacer walls. Finally, a gate oxide is formed late in the process, after the high temperature dopant implantation and diffusion steps, preventing the degradation of a radiation resistance of the gate oxide. Tight alignment of all three regions results in transistors that are substantially symmetric, which may increase a performance characteristic of the resulting high-voltage radiation-hardened semiconductor device.
- In another aspect of the invention, the VDMOS device is made on an epitaxial (“epi”) layer with a graded doping profile. One advantage is that a “graded epi” has a significantly higher secondary breakdown of the parasitic NPN transistor in comparison to step epi and, if properly designed, will produce a MOSFET with a lower Rdson.
- While we refer to a MOSFET, this invention also extends to IGBT devices and the like which include a MOSFET structure.
- The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.
-
FIG. 1 is a cross section of a gate finger of an embodiment of a VDMOS device with perfectly aligned diffusion layers, as result of the pseudo self-aligned process flow of the invention. -
FIG. 2 shows in a generic way a “graded epi” doping profile according to this invention. -
FIGS. 3-18 are cross-sectional views of the VDMOS transistor, illustrating an embodiment of a process flow to manufacture the device, according to the principles of this invention, in the following steps: -
FIG. 3 shows sacrificial oxide and sacrificial poly layers as deposited. -
FIG. 4 shows patterning of sacrificial poly layer for the “self aligned” implantations. -
FIG. 5 shows a P-well ion implantation using the patterned sacrificial poly (active area and termination) as a mask. -
FIG. 6 shows a P-well diffusion (active area and termination). -
FIG. 7 shows a sacrificial oxide patterning for source implantation. -
FIG. 8 shows thin spacer deposition and etch. -
FIG. 9 shows a UIS 1 implant. -
FIG. 10 shows a “co-diffusion” of the source and UIS implants. -
FIG. 11 shows a photo thin process (photo resist recessed and exposing the top of the poly). -
FIG. 12 shows a sacrificial poly etch (dry etch, isotropic, low oxide/silicon selectivity). -
FIG. 13 shows an oxide etch (the entire surface of wafers is cleared of oxide). -
FIG. 14 shows a blow up cross section of the center part ofFIG. 13 , with emphasis on perfect symmetry (left and right) of the structure around the geometrical center. -
FIG. 15 shows a “late gate oxide” process. -
FIG. 16 shows a final poly deposition and etch and BPSG deposition, reflow and patterning. -
FIG. 17 shows a front metal deposition and patterning. -
FIG. 18 shows a passivation (oxynitride) deposition and patterning. -
FIG. 19 is a graph which represents a comparison of the secondary breakdown voltage of a “step epi” and “graded epi” design of a 200V VDMOS. -
FIG. 20 is a plot which compares the secondary breakdown of a “single epi”, “step epi” and “graded epi” design for a 100V VDMOS. - For simplicity only the process flow pertaining to a N-Channel VDMOS will be described, for people familiar with the subject it will be readily apparent that the polarity of all doped layers of the device should be changed if a P-Channel Power VDMOS is to be made. The described inventions can also be used to make rad-hard IGBT devices of either polarity.
- For the person familiar with the subject, it will become apparent that the cross sections represent a small section of the active area and a portion of the termination, surrounding the active area. For a real VDMOS transistor, the active area is formed by “repeating” a “basic” cell, which can be either “stripes” of gate fingers or “closed” cells of various shapes (squares, rectangles, hexagons, crosses, and so on). This invention, in concept and substance, is applicable to any top layout design of a Vertical Power MOSFET.
- The process flow of a VDMOS according to this invention starts with epitaxial wafers of any type of doping (either N-type or P-Type) 101,102,103 grown on a
substrate 100 of the same polarity as the epitaxial layer. -
FIG. 2 shows a preferred gradient doping profile in which the substrate doping at the right has a first doping in the wafer and the upper epitaxial layer has a less second doping that is least near the upper surface on the left and increases in a gradient proceeding depthwise (rightward inFIG. 2 ) toward the wafer layer and substrate doping. This graded doping profile is substantially continuous. - After standard cleaning, a
sacrificial oxide layer 117 and a sacrificial polysilicon (“poly”)layer 118 are deposited. (FIG. 3 ). The sacrificial oxide layer can be around 1000 A (750 A-1500 A) thick and the sacrificial poly layer can be around 12000 A (10,000 A-15000 A) thick. The sacrificial poly layer can be referred to more generally as a sacrificial masking layer, and can be formed of other materials with slow etch rate in hydrofluoric solutions, such as Oxynitride or Nitride. Optionally, prior to this step, a light doping enhancement implantation (usually called “Jfet” implant, 104) can be performed either through a mask or across the entire surface of the wafers. - Following a standard photo masking step the
sacrificial poly 118 is patterned according to the designed layout of the structure (FIG. 4 ), for example as stripes. The central area above theJFET region 104 is referred to as the active area. -
FIG. 5 is a cross-sectional view of the device after P-Well implants 105 are placed inside of the windows created in the sacrificial Poly. The remainingoxide 117 on the wafers is easily penetrated by the implantation ions if the proper implant energy is chosen. - The implanted P-
Wells 105 are driven to the desired depth and then, using a properly designed mask, atFIG. 7 thesacrificial oxide 117 is patterned such that a sourceion implantation layer 113 is placed inside of the P-Wells. The remainingoxide 117A masks a centralbody contact region 119 of the substrate spaced between the polysilicon strips 118 to permit later metal contact by metal 122 (FIG. 17 ) to the P-well body 105 and thesource implants 113 to enable forming a source-body short. As one can see, the laterally outward ends of the source implant is perfectly aligned to the P-Wells as thesacrificial poly 118 acts as an implant barrier for both the P-Well and Source implants and its edge defines the starting point of the implanted layer. (Note: the laterally inward ends of the source implantregions adjoining region 119 are non-critical,region 119 need not be exactly centered. SeeFIG. 14 .) - From that starting point, the vertical and lateral diffusion of the implanted species is governed by the physics of the diffusion and it is virtually identical on both sides of the
sacrificial poly pseudo-gates 118. (Structures 118 are called “pseudo-gates” to distinguish from the real gates formed atFIG. 16 .) - The same
sacrificial poly 118 is used now for the creation of oxide spacers 110 (FIG. 8 ), placed along the edges of thesacrificial poly pseudo-gates 118 to offset the next heavy ion implantation 106 (FIG. 9 ) , which has the same polarity as the P-Wells (and opposite polarity as the source implants). - The role of these
high dose implants 106 is to minimize the base resistance of the parasitic NPN transistor and therefore their dose level and their placement is essential in improving the survivability of the Power MOSFET under heavy cosmic ion bombardment (FIG. 9 ). These heavy dose layers are usually called UIS implants as they significantly increase the capability of the power MOSFET to withstand high currents while in avalanche mode (Unclamped Inductive Switching test). - In an example of the UIS implant, boron is used for the N-channel device, phosphorus for a P-channel device. A suitable dose is in the range of 1E15 to 3E15/cm2, with a target of 2E15/cm2. Energy levels for depth placement can be around 160 Key (120-180 Key) for sacrificial poly thickness of around 13000 Angstroms (Range: 10,000-15,000 Angstroms).
- The next step is co-diffusion of the
source 113 and the UIS layers 106 (FIG. 10 ), after which the wafers are coated with a thin layer of photo-resist 116. Thickness and uniformity of the resistlayer 116 are important as they determine the amount of resist to be removed in the next process step inFIG. 11 . A suitable photoresist thickness can be 1.5 to 2 micrometers. The teachings of this process are described in applicant's U.S. Pat. No. 5,019,522. - As mentioned, the resist is “thinned” during a plasma resist etching process such that only the top of the
sacrificial poly layer 118 and the tops of the side wall oxide spacers are exposed (FIG. 11 ). - Once the
sacrificial poly 118 is fully exposed this layer is removed using an isotropic plasma etch of silicon, shown inFIG. 12 . Any silicon dry etch process with a reasonable isotropy and selectivity (silicon to oxide etch rates) is suitable for this step. - Following total removal of the sacrificial poly, the wafers are cleared of any residual oxide by immersing them in hydrofluoric etching solution (
FIG. 13 ). Wafers prepared in this way have all desired layers embedded in silicon at the desired depth in vertical direction and with virtually perfect alignment in the lateral/horizontal direction of various implanted layers. In other words, the laterally outer edges of the P-well (body), the source implants and the UIS region are substantially symmetrical about centerline C/L (FIG. 14 ), as are the channel regions adjoining the outer edges of the source implants. -
FIG. 14 is a close up cross section of a P-Well region with all the required layers to create a VDMOS transistor, perfectly aligned inside of the P-Well. By achieving identical channel length (130, 131), threshold voltage across the entire die is uniform and therefore a uniform temperature across the entire active area is maintained for any drain current. Having theUIS implants 106 aligned laterally underneath thesource implants 113 creates the same turn-on conditions for the parasitic NPN over the entire die area, with obvious beneficial results for SEB tests. - A late gate oxidation process is now performed (108,
FIG. 15 ), with all the specifics of a thermal oxidation process specially tailored for radiation hardened MOSFETs, specifics that will not be disclosed here as they are well-known and not relevant to the teaching of this invention. The resulting gate oxide is substantially free from interface and oxide traps. - The
final poly layer 119 is then deposited on the lategate oxide layer 108, doped and patterned on the wafers. (FIG. 16 ). - An
inter-dielectric layer 112 of choice (most commonly used being a boro-phospho-silicate glass BPSG layer) is deposited and re-flowed at relatively low temperatures, such that the anti-radiation properties of the gate oxide layer are not degraded by the reflow thermal process step. Thisinter-dielectric layer 112 is then patterned to expose the source and the P-Wells. Atop metal layer 122 is now deposited , patterned and etched (FIG. 17 ). - Patterning of the
final poly layer 119 and the inter-dielectric layer are noncritical. The critical lateral alignments have already been established in prior steps, as shown inFIG. 14 . - The next steps are standard for any VDMOS transistors, namely passivation 123 deposition and etch (
FIG. 18 ), backside grinding, optional backside implantation and implant activation and backside metallization of wafers. - The process steps outlined so far can produce a Radhard MOSFET with increased ruggedness for SEB tests, regardless of the type of starting material. In the following paragraphs we document that the use of graded epi, another aspect of this invention, further increases the capability of a VDMOS to survive an SEB test.
- Simulation work on graded epi has been done before but only as an effort to reduce the On Resistance of the Power MOSFET.
- Xing-Bi Cheng and Chenming Hu, using analytical equations, published in IEEE Transactions on Electron Devices, June, 1982, indicate that a graded epi profile (variable doping between the top part of the wafers toward the heavily doped substrate) can lower Rdson of a Vertical Power MOSFET at least by about 6%, for the same primary breakdown voltage BVdss.
- Using this as a starting point and employing advanced simulation tools we have discovered that a VDMOS transistor can benefit for SEB test if the device, made using state of the art process (i.e. pseudo self aligned process flow) is manufactured on wafers with a graded doping profile.
- Advanced TCAD simulation tools , like Silvaco, allows one to “create” a VDMOS structure identical with the unit cell of the real device. All main elements of the VDMOS cell are present in the simulated structure, and the electrical performance of such a device can be analyzed and compared changing only one variable.
- In our study we optimized the top side of the Power MOSFET for the best electrical characteristics (Rdson, Vth) for a given voltage rating and then we changed only the epitaxial layers of the structure, and compared the blocking capability of such structures under very high drain currents.
- The conclusion of such optimization work of the secondary breakdown voltage of such a VDMOS clearly pointed out that a graded epi design has a tremendous potential to increase the secondary breakdown of the device.
- The table below is a snapshot of various simulation results and shows that a graded epi profile has a Vbr2 (where Vbr2 is the secondary breakdown of the parasitic NPN transistor) more than twice that of a step epi design, while the On Resistance of the MOSFET is still low.
-
Epi design Vth BVdss (V) Vbr2 (V) Rdson (mohms) Step Epi 3.75 288 85 110.6 Graded Epi 3.75 240.9 280 77.8 -
FIG. 19 shows a direct comparison of the Id-BV characteristics of a step epi and a graded epi design for a 200V rated MOSFET. Vbr2 denotes the secondary breakdown point, whileFIG. 20 shows the same comparison, this time for a 100V rated MOSFET. - Based on TCAD work described above, VDMOS transistors with step epi and graded epi designs were manufactured and tested for SEB under the following conditions : Gold Ions, LET=89.9 MeV cm2/mg, Range=81.4 um, Energy=1500 MeV, Fluency=1.0E6 ions/cm2. The results, summarized in the table below clearly show that the graded epi design has improved SEB capability.
-
Epi Design Max Vds (V) Max Vgs (V) Comments Step Epi 90 0 Fails requirements Graded Epi 100 −5 Meets requirements - For the person skilled in this field of expertise the benefits of a graded epi design are apparent from the foregoing data.
- Having described and illustrated the principles of the invention in various embodiments thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications and variations coming within the spirit and scope of the following claims.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/337,865 US20140339625A1 (en) | 2012-01-16 | 2014-07-22 | Pseudo self aligned radhard mosfet and process of manufacture |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261586888P | 2012-01-16 | 2012-01-16 | |
US13/742,253 US8841718B2 (en) | 2012-01-16 | 2013-01-15 | Pseudo self aligned radhard MOSFET and process of manufacture |
US14/337,865 US20140339625A1 (en) | 2012-01-16 | 2014-07-22 | Pseudo self aligned radhard mosfet and process of manufacture |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/742,253 Division US8841718B2 (en) | 2012-01-16 | 2013-01-15 | Pseudo self aligned radhard MOSFET and process of manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140339625A1 true US20140339625A1 (en) | 2014-11-20 |
Family
ID=48779392
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/742,253 Active 2033-02-24 US8841718B2 (en) | 2012-01-16 | 2013-01-15 | Pseudo self aligned radhard MOSFET and process of manufacture |
US14/337,865 Abandoned US20140339625A1 (en) | 2012-01-16 | 2014-07-22 | Pseudo self aligned radhard mosfet and process of manufacture |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/742,253 Active 2033-02-24 US8841718B2 (en) | 2012-01-16 | 2013-01-15 | Pseudo self aligned radhard MOSFET and process of manufacture |
Country Status (1)
Country | Link |
---|---|
US (2) | US8841718B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109979801A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9478606B2 (en) | 2014-02-13 | 2016-10-25 | Microsemi Corporation | SiC transient voltage suppressor |
US9899529B2 (en) | 2015-11-09 | 2018-02-20 | Samsung Electronics Co., Ltd. | Method to make self-aligned vertical field effect transistor |
TWI581425B (en) * | 2015-11-24 | 2017-05-01 | Macroblock Inc | And a power semiconductor device having an edge terminal structure having a gradation concentration |
CN106098782B (en) * | 2016-08-19 | 2019-10-18 | 华越微电子有限公司 | A kind of P-channel VDMOS device production method |
CN107785367B (en) | 2016-08-31 | 2021-10-15 | 无锡华润上华科技有限公司 | Device integrated with depletion type junction field effect transistor and manufacturing method thereof |
CN109003900B (en) * | 2018-07-12 | 2021-05-04 | 中国电子科技集团公司第五十八研究所 | Process method for manufacturing stable VDMOS power device |
CN109887846A (en) * | 2019-01-16 | 2019-06-14 | 无锡浩真微电子有限公司 | The preparation process of anti-radiation power MOSFET |
CN111863606B (en) * | 2020-07-28 | 2023-05-05 | 哈尔滨工业大学 | Anti-radiation power transistor and preparation method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5897355A (en) * | 1994-08-03 | 1999-04-27 | National Semiconductor Corporation | Method of manufacturing insulated gate semiconductor device to improve ruggedness |
US5923065A (en) * | 1996-06-12 | 1999-07-13 | Megamos Corporation | Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings |
US20070096237A1 (en) * | 2003-01-15 | 2007-05-03 | Microsemi Corp. -Power Products Group | Design and fabrication of rugged fred, power mosfet or igbt |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4259779A (en) | 1977-08-24 | 1981-04-07 | Rca Corporation | Method of making radiation resistant MOS transistor |
US4591890A (en) | 1982-12-20 | 1986-05-27 | Motorola Inc. | Radiation hard MOS devices and methods for the manufacture thereof |
US4789882A (en) | 1983-03-21 | 1988-12-06 | International Rectifier Corporation | High power MOSFET with direct connection from connection pads to underlying silicon |
US4837606A (en) * | 1984-02-22 | 1989-06-06 | General Electric Company | Vertical MOSFET with reduced bipolar effects |
US5019522A (en) | 1986-03-21 | 1991-05-28 | Advanced Power Technology, Inc. | Method of making topographic pattern delineated power MOSFET with profile tailored recessed source |
US5262336A (en) | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
US5338693A (en) | 1987-01-08 | 1994-08-16 | International Rectifier Corporation | Process for manufacture of radiation resistant power MOSFET and radiation resistant power MOSFET |
US6236099B1 (en) | 1996-04-22 | 2001-05-22 | International Rectifier Corp. | Trench MOS device and process for radhard device |
US5831318A (en) | 1996-07-25 | 1998-11-03 | International Rectifier Corporation | Radhard mosfet with thick gate oxide and deep channel region |
US6165821A (en) | 1998-02-09 | 2000-12-26 | International Rectifier Corp. | P channel radhard device with boron diffused P-type polysilicon gate |
US6707103B1 (en) | 1998-03-05 | 2004-03-16 | International Rectifier Corporation | Low voltage rad hard MOSFET |
US6476456B1 (en) | 1999-06-10 | 2002-11-05 | International Rectifier Corporation | Integrated radiation hardened power mosgated device and schottky diode |
US6380004B2 (en) | 2000-02-02 | 2002-04-30 | International Rectifier Corp. | Process for manufacturing radhard power integrated circuit |
US7091080B2 (en) * | 2001-02-26 | 2006-08-15 | International Rectifier Corporation | Depletion implant for power MOSFET |
DE10117483A1 (en) * | 2001-04-07 | 2002-10-17 | Bosch Gmbh Robert | Semiconductor power component and corresponding manufacturing process |
US6747312B2 (en) | 2002-05-01 | 2004-06-08 | International Rectifier Corporation | Rad hard MOSFET with graded body diode junction and reduced on resistance |
US6894345B2 (en) | 2002-07-23 | 2005-05-17 | International Rectifier Corporation | P channel Rad Hard MOSFET with enhancement implant |
US7378317B2 (en) * | 2005-12-14 | 2008-05-27 | Freescale Semiconductor, Inc. | Superjunction power MOSFET |
US7651918B2 (en) * | 2006-08-25 | 2010-01-26 | Freescale Semiconductor, Inc. | Strained semiconductor power device and method |
US8674439B2 (en) * | 2010-08-02 | 2014-03-18 | Microsemi Corporation | Low loss SiC MOSFET |
US8643067B2 (en) * | 2011-09-30 | 2014-02-04 | Maxim Integrated Products, Inc. | Strapped dual-gate VDMOS device |
-
2013
- 2013-01-15 US US13/742,253 patent/US8841718B2/en active Active
-
2014
- 2014-07-22 US US14/337,865 patent/US20140339625A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5897355A (en) * | 1994-08-03 | 1999-04-27 | National Semiconductor Corporation | Method of manufacturing insulated gate semiconductor device to improve ruggedness |
US5923065A (en) * | 1996-06-12 | 1999-07-13 | Megamos Corporation | Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings |
US20070096237A1 (en) * | 2003-01-15 | 2007-05-03 | Microsemi Corp. -Power Products Group | Design and fabrication of rugged fred, power mosfet or igbt |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109979801A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US8841718B2 (en) | 2014-09-23 |
US20130181280A1 (en) | 2013-07-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8841718B2 (en) | Pseudo self aligned radhard MOSFET and process of manufacture | |
US7683453B2 (en) | Edge termination region for high-voltage bipolar-CMOS-DMOS integrated circuit devices | |
US7592228B2 (en) | Recessed clamping diode fabrication in trench devices | |
KR102138385B1 (en) | Low-cost semiconductor device manufacturing method | |
US20050029584A1 (en) | Semiconductor device and a method of manufacturing the same | |
WO2017211105A1 (en) | Super-junction device, chip and manufacturing method therefor | |
US8310006B2 (en) | Devices, structures, and methods using self-aligned resistive source extensions | |
TW202131515A (en) | Devices and methods for a power transistor having a schottky or schottky-like contact | |
TW201306264A (en) | Semiconductor power device and preparation method thereof | |
EP1946378A1 (en) | Method of manufacturing a semiconductor device | |
EP3509101B1 (en) | Device integrating a junction field effect transistor and manufacturing method therefor | |
EP3509110A1 (en) | Component having integrated junction field-effect transistor, and method for manufacturing same | |
US11664449B2 (en) | LDMOS architecture and method for forming | |
CN107785367B (en) | Device integrated with depletion type junction field effect transistor and manufacturing method thereof | |
US10312368B2 (en) | High voltage semiconductor devices and methods for their fabrication | |
CN108428632B (en) | Manufacturing method of super junction device | |
US20140117367A1 (en) | Devices, structures, and methods using self-aligned resistive source extensions | |
KR100360079B1 (en) | Manufacturing method of insulated gate semiconductor device to improve robustness | |
CN117673142A (en) | Trench gate superjunction device and manufacturing method thereof | |
KR20150108485A (en) | Method for reducing on resistance of Power MOSFET JFET area by double implanting ion |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICROSEMI CORPORATION, OREGON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SDRULLA, DUMITRU;VANDENBERG, MARC H.;KARLSSON, ERIC;REEL/FRAME:033365/0677 Effective date: 20130125 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: SECURITY AGREEMENT;ASSIGNORS:MICROSEMI CORPORATION;MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP;MICROSEMI SEMICONDUCTOR (U.S.) INC.;AND OTHERS;REEL/FRAME:035477/0057 Effective date: 20150421 |
|
AS | Assignment |
Owner name: MICROSEMI CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 Owner name: MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 Owner name: MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/ Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 Owner name: MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 Owner name: MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMI Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 Owner name: MICROSEMI SOC CORP., A CALIFORNIA CORPORATION, CAL Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 Owner name: MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAW Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:037558/0711 Effective date: 20160115 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:MICROSEMI CORPORATION;MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.);MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.);AND OTHERS;REEL/FRAME:037691/0697 Effective date: 20160115 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: MICROSEMI COMMUNICATIONS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 Owner name: MICROSEMI FREQUENCY AND TIME CORPORATION, CALIFORN Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 Owner name: MICROSEMI SOC CORP., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 Owner name: MICROSEMI CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 Owner name: MICROSEMI SEMICONDUCTOR (U.S.), INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 Owner name: MICROSEMI CORP. - RF INTEGRATED SOLUTIONS, CALIFOR Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 Owner name: MICROSEMI CORP. - POWER PRODUCTS GROUP, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:046251/0391 Effective date: 20180529 |