US20140329364A1 - Manufacturing method of power semiconductor - Google Patents
Manufacturing method of power semiconductor Download PDFInfo
- Publication number
- US20140329364A1 US20140329364A1 US13/974,142 US201313974142A US2014329364A1 US 20140329364 A1 US20140329364 A1 US 20140329364A1 US 201313974142 A US201313974142 A US 201313974142A US 2014329364 A1 US2014329364 A1 US 2014329364A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor substrate
- semiconductor
- manufacturing
- forming
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 229
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 174
- 238000002347 injection Methods 0.000 claims abstract description 29
- 239000007924 injection Substances 0.000 claims abstract description 29
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 11
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 30
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 238000005452 bending Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000013467 fragmentation Methods 0.000 description 2
- 238000006062 fragmentation reaction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Definitions
- the present invention relates to a manufacturing method of a semiconductor, and more particularly to a manufacturing method of a power semiconductor using multiple wafer bonding technology.
- one of the common power semiconductors is an insulated gate bipolar transistor (hereinafter “IGBT”).
- IGBT insulated gate bipolar transistor
- the basic encapsulation of an IGBT is a power semiconductor with three terminals.
- the characteristics of IGBTs include high efficiency and high switching speed.
- IGBTs are developed to replace the bipolar junction transistors (or called BJTs).
- IGBTs have both the characteristics of field effect transistors (or called FET) and bipolar transistors, so the IGBTs can withstand high current load, the gate can be easily driven and the turn-on voltage drop is low.
- FET field effect transistors
- the common uses of IGBTs are applied to high-capacity power devices like switching power supplies, motor controllers and induction cookers.
- FIG. 1 schematically illustrates the structure of a conventional insulated gate bipolar transistor of the prior art.
- a conventional trench punch-through IGBT includes a metal oxide semiconductor (or called MOS) layer 11 , a N-type buffer layer 12 and a P-type injection layer 13 .
- the MOS layer 11 is disposed between an emitter metal layer 111 and a N-type drift layer 112 for providing electron injection and controlling element switching.
- the N-type buffer layer 12 is used for conducting between the electrons and the electron holes and withstanding high voltage.
- a wafer backside thinning technology is used for reduce the resistance of the N-type drift layer 112
- a backside implant technology and a backside anneal technology are used for fabricating the N-type buffer layer 12 and the P-type injection layer 13 during the manufacturing process of the power semiconductor.
- the N-type buffer layer 12 is used for buffering the electric field and adjusting the concentration of the electron hole injection
- the P-type injection layer 13 is used for providing electron hole injection.
- the power semiconductor wafer becomes thinner so that the wafer is frangible and easy to bend.
- the metal process of the power semiconductor is done before the backside thinning process, the incoming anneal process is limited by the melting point of the surface metal, and the depth and the thickness of the N-type buffer layer and the P-type injection layer cannot be fabricated by the high-temperature drive-in process, in which the characteristics of power semiconductors and the process flexibility are limited everywhere.
- the present invention provides a manufacturing method of a power semiconductor in order to eliminate the drawbacks of the phenomenon caused by thinning the wafer thickness, the limitation of the melting point of the surface metal, the low process flexibility, and the limitation of the characteristics of power semiconductors.
- the present invention also provides a manufacturing method of a power semiconductor.
- a manufacturing method of a power semiconductor By respectively fabricating a first semiconductor substrate and a second semiconductor substrate and forming a third semiconductor substrate by combining the first semiconductor substrate and the second semiconductor substrate, a N-type buffer layer and a P-type injection layer are formed through ion implanting and high-temperature drive-in diffusion, which are not limited by the melting point of the metal. As a result, the process flexibility is enhanced, and the characteristics of the power semiconductor are un-limited.
- the present invention further provides a manufacturing method of a power semiconductor. Since a first semiconductor substrate is carried on and combined with a fourth semiconductor substrate, the phenomenon of easily bending and frangibility caused by thinning the wafer thickness is avoided, and the backside implant process and the backside anneal process are smoothly proceeded.
- a manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate.
- a manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate, combining a fifth surface of a fourth semiconductor substrate with the first surface of the first semiconductor substrate, grinding the fourth surface of the second semiconductor substrate, removing the fourth semiconductor substrate, and forming a collector metal layer on the fourth surface of the second semiconductor substrate.
- FIG. 1 schematically illustrates the structure of a conventional insulated gate bipolar transistor of the prior art
- FIG. 2A to FIG. 2G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to an embodiment of the present invention.
- FIG. 3A to FIG. 3G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to another embodiment of the present invention.
- FIG. 2A to FIG. 2G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to an embodiment of the present invention.
- a manufacturing method of a power semiconductor of the present invention includes steps as following. First, as shown in FIG. 2A and FIG. 2C , providing a first semiconductor substrate 20 and a second semiconductor substrate 30 , among which the first semiconductor substrate 20 is not limited to a N-type semiconductor wafer made of a N-type floating zone substrate, and the first semiconductor substrate 20 has a first surface S 1 and a second surface S 2 , which are for example the front surface and the back surface, but not limited thereto.
- the second semiconductor substrate 30 is not limited to a P-type semiconductor wafer and the second semiconductor substrate 30 has a third surface S 3 and a fourth surface S 4 , which are for example the front surface and the back surface, but not limited thereto.
- FIG. 2A and FIG. 2B forming a metal oxide semiconductor layer 21 on the first surface S 1 of the first semiconductor substrate 20 , and then grinding the second surface S 2 of the first semiconductor substrate 20 (i.e. a backside grinding process of the first semiconductor substrate 20 ). Further, as shown in FIG. 2C , forming a N-type buffer layer 31 and a P-type injection layer 32 on the third surface S 3 of the second semiconductor substrate 30 through ion implanting. Next, as shown in FIG. 2D , grinding the fourth surface S 4 of the second semiconductor substrate 30 (i.e. a backside thinning process of the P-type substrate 33 ). At last, as shown in FIG.
- the second surface S 2 of the first semiconductor substrate 20 with the third surface S 3 of the second semiconductor substrate 30 for forming a third semiconductor substrate 40 , among which the third semiconductor substrate 40 is a power semiconductor wafer, the first surface S 1 of the first semiconductor substrate 20 is the front surface of the power semiconductor wafer, and the fourth surface S 4 of the second semiconductor substrate 30 is the back surface of the power semiconductor wafer, but not limited thereto.
- the third semiconductor substrate 40 is a power semiconductor wafer
- the first surface S 1 of the first semiconductor substrate 20 is the front surface of the power semiconductor wafer
- the fourth surface S 4 of the second semiconductor substrate 30 is the back surface of the power semiconductor wafer, but not limited thereto.
- the second surface S 2 of the first semiconductor substrate 20 and the third surface S 3 of the second semiconductor substrate 30 are combined through direct wafer bonding.
- the combination of the second surface S 2 of the first semiconductor substrate 20 and the third surface S 3 of the second semiconductor substrate 30 is implemented by bonding the second surface S 2 of the first semiconductor substrate 20 to the third surface S 3 of the second semiconductor substrate 30 in high vacuum.
- the third semiconductor substrate 40 is formed.
- the further step of the manufacturing method of the present invention is shown in FIG. 2F , grinding the back surface of the third semiconductor substrate 40 , which is also the fourth surface S 4 of the second semiconductor substrate 30 for removing the rest P-type substrate.
- the third semiconductor substrate 40 is grinded to a target thickness so that the third semiconductor substrate 40 can be proceeded the incoming processes.
- the P-type injection layer 32 is formed on the third surface S 3 , which is the front surface, of the second semiconductor substrate 30 through ion implanting at first for providing electron hole injection.
- the electron hole injection efficiency can be adjusted by changing the implant concentration.
- the N-type buffer layer 31 is then formed on the P-type injection layer 32 through ion implanting for buffering the electric field and adjusting the concentration of electron hole injection.
- the electron hole injection efficiency and the width of the depletion region can be adjusted by changing the implant concentration. As a result, the process flexibility is enhanced.
- the P-type injection layer 32 and the N-type buffer layer 31 can be formed and implanted on the back surface of a wafer.
- the steps and the forming direction are opposite to the above-mentioned embodiment, but the concept is substantially the same, as which the present invention teaches.
- the ion implanting process of forming the N-type buffer layer 31 and the P-type injection layer 32 on the third surface S 3 of the second semiconductor substrate 30 can be synchronized with the process of forming the metal oxide semiconductor layer 21 on the first surface S 1 of the first semiconductor substrate 20 mentioned above. That is, it is no limit that forming the metal oxide semiconductor layer 21 or forming the N-type buffer layer 31 and the P-type injection layer 32 at first.
- the N-type buffer layer 31 and the P-type injection layer 32 are formed through ion implanting and high-temperature drive-in diffusion, which are not limited by the melting point of the metal. As a result, the process flexibility is enhanced, and the characteristics of the power semiconductor are un-limited.
- a fourth semiconductor substrate is applied to the manufacturing method of the power semiconductor of the present invention for carrying. Please refer to FIG. 2B again.
- a fifth surface S 5 of a fourth semiconductor substrate 50 i.e. a carrying wafer
- the further step of grinding the second surface S 2 of the first semiconductor substrate 20 is proceeded.
- the fourth semiconductor substrate 50 which is the carrying wafer, may carry the first semiconductor substrate 20 during fabricating, especially during the combination of the first semiconductor substrate 20 and the second semiconductor substrate 30 and the surface grinding process as shown in FIG. 2F , for avoiding the bending or the fragmentation of the first semiconductor substrate 20 and the second semiconductor substrate 30 .
- FIG. 3A to FIG. 3G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to another embodiment of the present invention.
- the manufacturing method of a power semiconductor includes steps as following. First of all, as shown in FIG. 3A and FIG. 3C , providing a first semiconductor substrate 20 and a second semiconductor substrate 30 , among which the first semiconductor substrate 20 has a first surface S 1 and a second surface S 2 and the second semiconductor substrate 30 has a third surface S 3 and a fourth surface S 4 .
- FIG. 3A and FIG. 3B forming a metal oxide semiconductor layer 21 on the first surface S 1 of the first semiconductor substrate 20 , and then grinding the second surface S 2 of the first semiconductor substrate 20 (i.e. a backside grinding process of the first semiconductor substrate 20 ). Furthermore, as shown in FIG. 3C , forming a N-type buffer layer 31 and a P-type injection layer 32 on the third surface S 3 of the second semiconductor substrate 30 through ion implanting. Next, as shown in FIG. 3D , grinding the fourth surface S 4 of the second semiconductor substrate 30 (i.e. a backside thinning process of the P-type substrate 33 ). Further, as shown in FIG.
- FIG. 3E combining the second surface S 2 of the first semiconductor substrate 20 with the third surface S 3 of the second semiconductor substrate 30 for forming a third semiconductor substrate 40 .
- FIG. 3F combining a fifth surface S 5 of a fourth semiconductor substrate 50 , which is a carrying wafer, with the first surface S 1 of the first semiconductor substrate 20 after the third semiconductor substrate 40 is formed, and then grinding the fourth surface S 4 of the second semiconductor substrate 30 (i.e. a backside grinding process of the third semiconductor substrate 40 ).
- FIG. 3G removing the fourth semiconductor substrate 50 , and forming a collector metal layer 41 on the fourth surface S 4 of the second semiconductor substrate 30 , which is the back surface of the third semiconductor substrate 40 .
- the power semiconductor is manufactured and the manufacturing method is done herein. That is, the concept of carrying wafer, which is the fourth semiconductor substrate, is applied to different steps of the processes of the manufacturing method of the present invention, and advantages of avoiding the bending or the fragmentation of the first semiconductor substrate 20 , the second semiconductor substrate 30 and/or the third semiconductor substrate 40 are achieved.
- the present invention provides a manufacturing method of a power semiconductor.
- a N-type buffer layer and a P-type injection layer are formed through ion implanting and high-temperature drive-in diffusion, which are not limited by the melting point of the metal. Therefore, the process flexibility is enhanced, and the characteristics of the power semiconductor are un-limited.
- a first semiconductor substrate is carried on and combined with a fourth semiconductor substrate, the phenomenon of easily bending and frangibility caused by thinning the wafer thickness is avoided, and the backside implant process and the backside anneal process are smoothly proceeded.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
- The present invention relates to a manufacturing method of a semiconductor, and more particularly to a manufacturing method of a power semiconductor using multiple wafer bonding technology.
- In recent years, with the growing of the technologies, lot types of electronic products are produced. The high-tech electronic devices are deeply combined with human's daily life. For example, each of the panels and the global positioning systems of automobiles, smart phones, tablet PCs, variety toys and remote-controlled apparatuses is part of the technology life of human nowadays. The mainly necessary elements in electronic devices are semiconductor elements, such like power semiconductors, transistors, amplifiers and switches, especially the power semiconductors are much more fabricated in industry.
- For example, one of the common power semiconductors is an insulated gate bipolar transistor (hereinafter “IGBT”). The basic encapsulation of an IGBT is a power semiconductor with three terminals. The characteristics of IGBTs include high efficiency and high switching speed. Generally, IGBTs are developed to replace the bipolar junction transistors (or called BJTs). IGBTs have both the characteristics of field effect transistors (or called FET) and bipolar transistors, so the IGBTs can withstand high current load, the gate can be easily driven and the turn-on voltage drop is low. Under this circumstance, the common uses of IGBTs are applied to high-capacity power devices like switching power supplies, motor controllers and induction cookers.
- On the other hand, even though IGBTs have been fabricated and used for tens of years, there are still some drawbacks of the process technology and semiconductor structure. Please refer to
FIG. 1 .FIG. 1 schematically illustrates the structure of a conventional insulated gate bipolar transistor of the prior art. A conventional trench punch-through IGBT includes a metal oxide semiconductor (or called MOS)layer 11, a N-type buffer layer 12 and a P-type injection layer 13. TheMOS layer 11 is disposed between anemitter metal layer 111 and a N-type drift layer 112 for providing electron injection and controlling element switching. The N-type buffer layer 12 is used for conducting between the electrons and the electron holes and withstanding high voltage. For matching the specifications of product, a wafer backside thinning technology is used for reduce the resistance of the N-type drift layer 112, and a backside implant technology and a backside anneal technology are used for fabricating the N-type buffer layer 12 and the P-type injection layer 13 during the manufacturing process of the power semiconductor. The N-type buffer layer 12 is used for buffering the electric field and adjusting the concentration of the electron hole injection, and the P-type injection layer 13 is used for providing electron hole injection. - After the backside thinning process, the power semiconductor wafer becomes thinner so that the wafer is frangible and easy to bend. Meanwhile, since the metal process of the power semiconductor is done before the backside thinning process, the incoming anneal process is limited by the melting point of the surface metal, and the depth and the thickness of the N-type buffer layer and the P-type injection layer cannot be fabricated by the high-temperature drive-in process, in which the characteristics of power semiconductors and the process flexibility are limited everywhere.
- There is a need of providing a manufacturing method of a power semiconductor to obviate the drawbacks encountered from the prior art.
- The present invention provides a manufacturing method of a power semiconductor in order to eliminate the drawbacks of the phenomenon caused by thinning the wafer thickness, the limitation of the melting point of the surface metal, the low process flexibility, and the limitation of the characteristics of power semiconductors.
- The present invention also provides a manufacturing method of a power semiconductor. By respectively fabricating a first semiconductor substrate and a second semiconductor substrate and forming a third semiconductor substrate by combining the first semiconductor substrate and the second semiconductor substrate, a N-type buffer layer and a P-type injection layer are formed through ion implanting and high-temperature drive-in diffusion, which are not limited by the melting point of the metal. As a result, the process flexibility is enhanced, and the characteristics of the power semiconductor are un-limited.
- The present invention further provides a manufacturing method of a power semiconductor. Since a first semiconductor substrate is carried on and combined with a fourth semiconductor substrate, the phenomenon of easily bending and frangibility caused by thinning the wafer thickness is avoided, and the backside implant process and the backside anneal process are smoothly proceeded.
- In accordance with an aspect of the present invention, there is provided a manufacturing method of a power semiconductor. The manufacturing method includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate.
- In accordance with another aspect of the present invention, there is provided a manufacturing method of a power semiconductor. The manufacturing method includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate, combining a fifth surface of a fourth semiconductor substrate with the first surface of the first semiconductor substrate, grinding the fourth surface of the second semiconductor substrate, removing the fourth semiconductor substrate, and forming a collector metal layer on the fourth surface of the second semiconductor substrate.
- The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
-
FIG. 1 schematically illustrates the structure of a conventional insulated gate bipolar transistor of the prior art; -
FIG. 2A toFIG. 2G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to an embodiment of the present invention; and -
FIG. 3A toFIG. 3G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to another embodiment of the present invention. - The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
- Please refer to
FIG. 2A toFIG. 2G FIG. 2A toFIG. 2G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to an embodiment of the present invention. A manufacturing method of a power semiconductor of the present invention includes steps as following. First, as shown inFIG. 2A andFIG. 2C , providing afirst semiconductor substrate 20 and asecond semiconductor substrate 30, among which thefirst semiconductor substrate 20 is not limited to a N-type semiconductor wafer made of a N-type floating zone substrate, and thefirst semiconductor substrate 20 has a first surface S1 and a second surface S2, which are for example the front surface and the back surface, but not limited thereto. Thesecond semiconductor substrate 30 is not limited to a P-type semiconductor wafer and thesecond semiconductor substrate 30 has a third surface S3 and a fourth surface S4, which are for example the front surface and the back surface, but not limited thereto. - Next, as shown in
FIG. 2A andFIG. 2B , forming a metaloxide semiconductor layer 21 on the first surface S1 of thefirst semiconductor substrate 20, and then grinding the second surface S2 of the first semiconductor substrate 20 (i.e. a backside grinding process of the first semiconductor substrate 20). Further, as shown inFIG. 2C , forming a N-type buffer layer 31 and a P-type injection layer 32 on the third surface S3 of thesecond semiconductor substrate 30 through ion implanting. Next, as shown inFIG. 2D , grinding the fourth surface S4 of the second semiconductor substrate 30 (i.e. a backside thinning process of the P-type substrate 33). At last, as shown inFIG. 2E , combining the second surface S2 of thefirst semiconductor substrate 20 with the third surface S3 of thesecond semiconductor substrate 30 for forming athird semiconductor substrate 40, among which thethird semiconductor substrate 40 is a power semiconductor wafer, the first surface S1 of thefirst semiconductor substrate 20 is the front surface of the power semiconductor wafer, and the fourth surface S4 of thesecond semiconductor substrate 30 is the back surface of the power semiconductor wafer, but not limited thereto. - In some embodiments, the second surface S2 of the
first semiconductor substrate 20 and the third surface S3 of thesecond semiconductor substrate 30 are combined through direct wafer bonding. Preferably, the combination of the second surface S2 of thefirst semiconductor substrate 20 and the third surface S3 of thesecond semiconductor substrate 30 is implemented by bonding the second surface S2 of thefirst semiconductor substrate 20 to the third surface S3 of thesecond semiconductor substrate 30 in high vacuum. - After combining the
first semiconductor substrate 20 and thesecond semiconductor substrate 30, thethird semiconductor substrate 40 is formed. The further step of the manufacturing method of the present invention is shown inFIG. 2F , grinding the back surface of thethird semiconductor substrate 40, which is also the fourth surface S4 of thesecond semiconductor substrate 30 for removing the rest P-type substrate. Under this circumstance, thethird semiconductor substrate 40 is grinded to a target thickness so that thethird semiconductor substrate 40 can be proceeded the incoming processes. - In some embodiments, the P-
type injection layer 32 is formed on the third surface S3, which is the front surface, of thesecond semiconductor substrate 30 through ion implanting at first for providing electron hole injection. By ion implanting P-type impurities likeB 11 on the third surface S3, the electron hole injection efficiency can be adjusted by changing the implant concentration. In addition, the N-type buffer layer 31 is then formed on the P-type injection layer 32 through ion implanting for buffering the electric field and adjusting the concentration of electron hole injection. By ion implanting N-type impurities like P31 or AS 75 on the P-type injection layer 32, the electron hole injection efficiency and the width of the depletion region can be adjusted by changing the implant concentration. As a result, the process flexibility is enhanced. - Certainly, in another embodiment, the P-
type injection layer 32 and the N-type buffer layer 31 can be formed and implanted on the back surface of a wafer. The steps and the forming direction are opposite to the above-mentioned embodiment, but the concept is substantially the same, as which the present invention teaches. Moreover, the ion implanting process of forming the N-type buffer layer 31 and the P-type injection layer 32 on the third surface S3 of thesecond semiconductor substrate 30 can be synchronized with the process of forming the metaloxide semiconductor layer 21 on the first surface S1 of thefirst semiconductor substrate 20 mentioned above. That is, it is no limit that forming the metaloxide semiconductor layer 21 or forming the N-type buffer layer 31 and the P-type injection layer 32 at first. By respectively fabricating thefirst semiconductor substrate 20 and thesecond semiconductor substrate 30 and forming thethird semiconductor substrate 40 by combining thefirst semiconductor substrate 20 and thesecond semiconductor substrate 30, the N-type buffer layer 31 and the P-type injection layer 32 are formed through ion implanting and high-temperature drive-in diffusion, which are not limited by the melting point of the metal. As a result, the process flexibility is enhanced, and the characteristics of the power semiconductor are un-limited. - In some embodiments, to avoid and solve the phenomenon of easily bending and frangibility caused by thinning the wafer thickness, a fourth semiconductor substrate is applied to the manufacturing method of the power semiconductor of the present invention for carrying. Please refer to
FIG. 2B again. After the metaloxide semiconductor layer 21 is formed on the first surface S1 of thefirst semiconductor substrate 20, a fifth surface S5 of a fourth semiconductor substrate 50 (i.e. a carrying wafer) is combined with the first surface S1 of thefirst semiconductor substrate 20 through temporary wafer bonding. After combining the fifth surface S5 of thefourth semiconductor substrate 50 with the first surface S1 of thefirst semiconductor substrate 20, the further step of grinding the second surface S2 of thefirst semiconductor substrate 20 is proceeded. Since thefirst semiconductor substrate 20 is carried on and combined with thefourth semiconductor substrate 50, the phenomenon of easily bending and frangibility caused by thinning the wafer thickness is avoided, and the backside implant process and the backside anneal process are smoothly proceeded. In some embodiments, thefourth semiconductor substrate 50, which is the carrying wafer, may carry thefirst semiconductor substrate 20 during fabricating, especially during the combination of thefirst semiconductor substrate 20 and thesecond semiconductor substrate 30 and the surface grinding process as shown inFIG. 2F , for avoiding the bending or the fragmentation of thefirst semiconductor substrate 20 and thesecond semiconductor substrate 30. - After the steps of combining the
first semiconductor substrate 20 with thesecond semiconductor substrate 30 and grinding the fourth surface S4 of the second semiconductor substrate 30 (i.e. after the backside grinding process of the third semiconductor substrate 40), the further steps of removing thefourth semiconductor substrate 50 and forming acollector metal layer 41 on the fourth surface S4 of thesecond semiconductor substrate 30 of the manufacturing method of the present invention are shown inFIG. 2G - Certainly, the
fourth semiconductor substrate 50 can also be applied to another embodiments. Please refer toFIG. 3A toFIG. 3G FIG. 3A toFIG. 3G schematically illustrate the structures corresponding to the steps of a manufacturing method of a power semiconductor according to another embodiment of the present invention. The manufacturing method of a power semiconductor includes steps as following. First of all, as shown inFIG. 3A andFIG. 3C , providing afirst semiconductor substrate 20 and asecond semiconductor substrate 30, among which thefirst semiconductor substrate 20 has a first surface S1 and a second surface S2 and thesecond semiconductor substrate 30 has a third surface S3 and a fourth surface S4. - Next, as shown in
FIG. 3A andFIG. 3B , forming a metaloxide semiconductor layer 21 on the first surface S1 of thefirst semiconductor substrate 20, and then grinding the second surface S2 of the first semiconductor substrate 20 (i.e. a backside grinding process of the first semiconductor substrate 20). Furthermore, as shown inFIG. 3C , forming a N-type buffer layer 31 and a P-type injection layer 32 on the third surface S3 of thesecond semiconductor substrate 30 through ion implanting. Next, as shown inFIG. 3D , grinding the fourth surface S4 of the second semiconductor substrate 30 (i.e. a backside thinning process of the P-type substrate 33). Further, as shown inFIG. 3E , combining the second surface S2 of thefirst semiconductor substrate 20 with the third surface S3 of thesecond semiconductor substrate 30 for forming athird semiconductor substrate 40. Next, as shown inFIG. 3F , combining a fifth surface S5 of afourth semiconductor substrate 50, which is a carrying wafer, with the first surface S1 of thefirst semiconductor substrate 20 after thethird semiconductor substrate 40 is formed, and then grinding the fourth surface S4 of the second semiconductor substrate 30 (i.e. a backside grinding process of the third semiconductor substrate 40). Finally, as shown inFIG. 3G , removing thefourth semiconductor substrate 50, and forming acollector metal layer 41 on the fourth surface S4 of thesecond semiconductor substrate 30, which is the back surface of thethird semiconductor substrate 40. The power semiconductor is manufactured and the manufacturing method is done herein. That is, the concept of carrying wafer, which is the fourth semiconductor substrate, is applied to different steps of the processes of the manufacturing method of the present invention, and advantages of avoiding the bending or the fragmentation of thefirst semiconductor substrate 20, thesecond semiconductor substrate 30 and/or thethird semiconductor substrate 40 are achieved. - From the above description, the present invention provides a manufacturing method of a power semiconductor. By respectively fabricating a first semiconductor substrate and a second semiconductor substrate and forming a third semiconductor substrate by combining the first semiconductor substrate and the second semiconductor substrate, a N-type buffer layer and a P-type injection layer are formed through ion implanting and high-temperature drive-in diffusion, which are not limited by the melting point of the metal. Therefore, the process flexibility is enhanced, and the characteristics of the power semiconductor are un-limited. Meanwhile, since a first semiconductor substrate is carried on and combined with a fourth semiconductor substrate, the phenomenon of easily bending and frangibility caused by thinning the wafer thickness is avoided, and the backside implant process and the backside anneal process are smoothly proceeded.
- While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims (11)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102115822A TWI527213B (en) | 2013-05-03 | 2013-05-03 | Manufacturing method of power semiconductor |
TW102115822 | 2013-05-03 | ||
TW102115822A | 2013-05-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
US8859392B1 US8859392B1 (en) | 2014-10-14 |
US20140329364A1 true US20140329364A1 (en) | 2014-11-06 |
Family
ID=51661074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/974,142 Active US8859392B1 (en) | 2013-05-03 | 2013-08-23 | Manufacturing method of power semiconductor |
Country Status (2)
Country | Link |
---|---|
US (1) | US8859392B1 (en) |
TW (1) | TWI527213B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6313251B2 (en) * | 2015-03-12 | 2018-04-18 | 東芝メモリ株式会社 | Manufacturing method of semiconductor device |
CN110767593A (en) * | 2019-10-14 | 2020-02-07 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6194290B1 (en) * | 1998-03-09 | 2001-02-27 | Intersil Corporation | Methods for making semiconductor devices by low temperature direct bonding |
-
2013
- 2013-05-03 TW TW102115822A patent/TWI527213B/en active
- 2013-08-23 US US13/974,142 patent/US8859392B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8859392B1 (en) | 2014-10-14 |
TWI527213B (en) | 2016-03-21 |
TW201444080A (en) | 2014-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5551082B2 (en) | Reverse conductive semiconductor device and method for manufacturing such reverse conductive semiconductor device | |
US9825149B2 (en) | Split gate power semiconductor field effect transistor | |
US20080237707A1 (en) | Semiconductor device | |
US9306057B2 (en) | Metal oxide semiconductor devices and fabrication methods | |
JP2011507300A (en) | Reverse conductive semiconductor device and method for manufacturing such reverse conductive semiconductor device | |
KR102228655B1 (en) | High-voltage integrated device and method of fabricating the same | |
TW201314867A (en) | Semiconductor chip integrating high and low voltage devices | |
US8557678B2 (en) | Method for manufacturing semiconductor substrate of large-power device | |
US7989921B2 (en) | Soi vertical bipolar power component | |
CN103337498A (en) | BCD semiconductor device and manufacturing method thereof | |
US20130056824A1 (en) | Semiconductor device and manufacturing method for the same | |
US9018069B2 (en) | Semiconductor structure and a method for manufacturing the same | |
US10056260B2 (en) | Schottky diode with dielectrically isolated diffusions, and method of manufacturing the same | |
US9847387B2 (en) | Field effect semiconductor component and method for producing it | |
CN108615766A (en) | Semiconductor devices and its manufacturing method | |
US10991832B2 (en) | Power diode | |
US20160133733A1 (en) | Power semiconductor component and manufacturing method thereof | |
US20160211258A1 (en) | Reverse-Conducting Gated-Base Bipolar-Conduction Devices and Methods with Reduced Risk of Warping | |
US8859392B1 (en) | Manufacturing method of power semiconductor | |
US9153574B2 (en) | Semiconductor device and method of fabricating the same | |
CN103022099A (en) | IGBT (insulated gate bipolar transistor) collector structure and production method thereof | |
TWI698017B (en) | High voltage semiconductor device and manufacturing method thereof | |
CN102623313A (en) | Ring ion injection method, semiconductor device and manufacture method thereof | |
CN109980010B (en) | Method for manufacturing semiconductor device and integrated semiconductor device | |
CN107026203B (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOSEL VITELIC INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHANG, CHIEN-PING;REEL/FRAME:031067/0917 Effective date: 20130711 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |