US20140264844A1 - Semiconductor device having a die and through substrate-via - Google Patents
Semiconductor device having a die and through substrate-via Download PDFInfo
- Publication number
- US20140264844A1 US20140264844A1 US13/930,417 US201313930417A US2014264844A1 US 20140264844 A1 US20140264844 A1 US 20140264844A1 US 201313930417 A US201313930417 A US 201313930417A US 2014264844 A1 US2014264844 A1 US 2014264844A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor wafer
- integrated circuit
- wafer
- circuit die
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 258
- 239000000463 material Substances 0.000 claims abstract description 75
- 239000000853 adhesive Substances 0.000 claims abstract description 69
- 230000001070 adhesive effect Effects 0.000 claims abstract description 69
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 238000000465 moulding Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 10
- 235000012431 wafers Nutrition 0.000 description 175
- 238000004519 manufacturing process Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 238000002161 passivation Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- -1 Aluminum (Al) Chemical class 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000012800 visualization Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- Three-dimensional integrated circuit devices are semiconductor devices that employ two or more layers of active electronic components.
- Through-substrate vias (TSV) interconnect electronic components on the different layers (e.g., different substrates) of the device allowing the devices to be integrated vertically as well as horizontally. Consequently, three-dimensional integrated circuit devices can provide increased functionality within a smaller, more compact footprint than do conventional two-dimensional integrated circuit devices.
- TSV Through-substrate vias
- the semiconductor devices are fabricated by bonding a semiconductor wafer and an integrated circuit die together using an adhesive material, such as a dielectric.
- the adhesive material allows for lateral expansion when the integrated circuit die is attached to the semiconductor wafer and during the bonding process.
- an integrated circuit die may be bonded to a semiconductor wafer by applying adhesive material to a second (e.g., backside or bottom) surface of the semiconductor wafer.
- the adhesive material may then be used to bond the integrated circuit die to the second (e.g., backside or bottom) surface of the semiconductor wafer. Vias may then be formed through the semiconductor wafer and the patterned adhesive material to furnish electrical interconnection between the semiconductor wafer and the integrated circuit die. The semiconductor wafer may then be segmented into individual semiconductor devices.
- FIG. 1A is a diagrammatic partial cross-sectional view illustrating a semiconductor device at wafer level (e.g., prior to singulation of the device) in accordance with an example implementation of the present disclosure.
- FIG. 1B is a diagrammatic partial cross-sectional view illustrating a semiconductor device at wafer level (e.g., prior to singulation of the device) in accordance with an example implementation of the present disclosure.
- FIG. 2 is a flow diagram illustrating a process in an example implementation for fabricating semiconductor devices, such as the device shown in FIG. 1 .
- FIGS. 3A through 3G are diagrammatic partial cross-sectional views illustrating the fabrication of wafer-level packaged semiconductor devices, such as the semiconductor device shown in FIGS. 1A and 1B according to the process shown in FIG. 2 , in an example implementation.
- Three-dimensional integrated circuit devices are commonly manufactured using die-on-wafer techniques wherein electronic components (e.g., circuits) are first fabricated on two or more semiconductor wafers. The individual die are aligned on and attached to semiconductor wafers and segmented to provide individual devices. Through-substrate vias (TSV) are either built into wafers before they are attached, or else created in the wafer stack after attachment.
- TSV Through-substrate vias
- the fabrication of three-dimensional integrated circuit devices requires additional manufacturing steps to join the die and wafers together. This increases the cost of the devices. Moreover, each extra manufacturing step adds a risk for inducing defects, possibly reducing device yield.
- wafer-level package devices that employ example techniques in accordance with the present disclosure include a die bonded to the backside of a semiconductor wafer with an adhesive material.
- the die and semiconductor wafer include one or more integrated circuits formed therein.
- Through-substrate vias (TSV) are formed through the semiconductor wafer and the adhesive material is disposed between the die and the semiconductor wafer.
- the through-substrate vias in the semiconductor wafer include a conductive material, such as copper, that furnishes electrical interconnection between the integrated circuits in the semiconductor wafer and the die. It is contemplated that more than one die may be provided for attaching to the semiconductor wafer.
- a wafer-level package device that employs example techniques in accordance with the present disclosure includes bonding a carrier wafer to a processed semiconductor wafer, using an adhesive material to attach an integrated circuit die to a second side of the processed semiconductor wafer, removing the carrier wafer, and forming a through-silicon via in the processed semiconductor wafer, where the through-silicon via furnishes an electrical connection between the processed semiconductor wafer and the integrated circuit die.
- the integrated circuit die may be placed in a cavity on the second side (e.g., the backside) of the semiconductor wafer or may be covered by a cap wafer placed over the integrated circuit die and on the second side of the processed semiconductor wafer.
- the processed semiconductor wafer may then be segmented into individual semiconductor devices.
- FIG. 1 illustrates a semiconductor semiconductor device 100 in accordance with example implementations of the present disclosure.
- the semiconductor semiconductor device 100 is illustrated at wafer level prior to singulation of the semiconductor semiconductor device 100 .
- the semiconductor semiconductor device 100 includes a semiconductor wafer 102 .
- the semiconductor wafer 102 includes one or more integrated circuits (not shown), which are formed within the semiconductor wafer 102 .
- the semiconductor wafer 102 further includes one or more alignment marks 106 .
- the alignment marks 106 may be utilized to align the semiconductor wafer 102 with a carrier wafer (described herein below). Additionally, the alignment marks 106 may be utilized to indicate a location for forming a through-silicon via 130 , further described below.
- the semiconductor wafer 102 includes a first (e.g., top or front) surface and a second (e.g., bottom or backside) surface.
- the integrated circuits are formed (e.g., fabricated) proximate to the first surface of the semiconductor wafer 102 . It is contemplated that the first and/or the second surface of the semiconductor wafer 102 may be planarized or unplanarized.
- the semiconductor wafer 102 include a base material utilized to form one or more integrated circuit devices through various fabrication techniques such as photolithography, ion implantation, deposition, etching, and so forth.
- the semiconductor wafer 102 may be configured in a variety of ways.
- the semiconductor wafer 102 may comprise an n-type silicon wafer or a p-type silicon wafer.
- the semiconductor wafer 102 may comprise group V elements (e.g., phosphorus, arsenic, antimony, etc.) configured to furnish n-type charge carrier elements.
- the semiconductor wafer 102 may comprise group IIIA elements (e.g., boron, etc.) configured to furnish p-type charge carrier elements.
- the integrated circuits may be configured in a variety of ways.
- the integrated circuits may include digital integrated circuits, analog integrated circuits, mixed-signal circuits, and so forth.
- the integrated circuits may include digital logic devices, analog devices (e.g., amplifiers, etc.), combinations thereof, and so forth.
- the integrated circuits may be fabricated utilizing various fabrication techniques.
- the integrated circuits may be fabricated via complimentary metal-oxide-semiconductor (CMOS) techniques, bi-polar semiconductor techniques, and so on.
- CMOS complimentary metal-oxide-semiconductor
- the semiconductor semiconductor device 100 also includes one or more area arrays of conductive layers 116 of the semiconductor wafer 102 .
- the conductive layers 116 may comprise one or more conductive (e.g., contact) pads, redistribution structures, or the like.
- the conductive layers 116 may include seed metal and/or barrier metal layers to allow for plated-line formation. The number and configuration of conductive layers 116 may vary depending on the complexity and configuration of the integrated circuits, and so forth.
- the conductive layers 116 provide electrical contacts through which the integrated circuits are interconnected to other components, such as printed circuit boards (not shown), when the semiconductor devices 100 are configured as wafer-level packaging (WLP) devices or other integrated circuits disposed within the semiconductor semiconductor device 100 .
- the conductive layers 116 may comprise an electrically conductive material, such as a metal material (e.g., aluminum, copper, etc.), or the like.
- the conductive layers 116 may furnish electrical interconnection between various electrical components associated with the semiconductor semiconductor device 100 .
- a first conductive layer 116 deployed over the semiconductor wafer 102 may furnish an electrical interconnection to a second conductive layer 116 deployed over another device (e.g., an integrated circuit die 140 ).
- a conductive layer 116 deployed over the semiconductor wafer 102 may provide electrical interconnection with one or more solder bumps 118 .
- Solder bumps 118 are provided to furnish mechanical and/or electrical interconnection between the conductive layers 116 and corresponding pads (not shown) formed on the surface of a printed circuit board (not shown) or another semiconductor device.
- the solder bumps 118 may be fabricated of a lead-free solder such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on.
- a Tin-Silver-Copper alloy solder i.e., SAC
- Tin-Silver (Sn—Ag) alloy solder Tin-Copper (Sn—Cu) alloy solder
- PbSn Tin-Lead solders
- Bump interfaces 120 may be applied to the conductive layers 116 to provide a reliable interconnect boundary between the conductive layers 116 and the solder bumps 118 .
- the bump interface 120 comprises under-bump metallization (UBM) 122 applied to the conductive layers 116 of the integrated circuit chip 102 .
- the UBM 122 may have a variety of compositions.
- the UBM 122 include multiple layers of different metals (e.g., Aluminum (Al), Nickel (Ni), Copper (Cu), etc.) that function as an adhesion layer, a diffusion barrier layer, a solderable layer, an oxidation barrier layer, and so forth.
- other UBM structures are possible.
- the semiconductor semiconductor device 100 may employ a Redistribution Layer (“RDL”) configuration.
- the RDL configuration employs a redistribution structure 124 comprised of a thin-film metal (e.g., aluminum, copper, etc.) rerouting and interconnection system that redistributes the conductive layers 116 to an area array of bump interfaces 120 (e.g., UBM pads) that may be more evenly deployed over the surface of the semiconductor semiconductor device 100 .
- the solder bumps 118 are subsequently placed over these bump interfaces 120 to form bump assemblies 126 .
- the redistribution layer 124 may include wings 124 A, 124 B to provide further structural support to the solder bumps 118 .
- the structural support may reduce the stress to the semiconductor semiconductor device 100 , which may prevent the cracking of the semiconductor semiconductor device 100 during various testing phases (e.g., temperature cycling, drop testing, etc.).
- the wings 124 A, 124 B provide a redistribution layer 124 extension that may extend to approximately the width (W) of the solder bump 118 .
- the wings 124 A, 124 B may extend beyond (e.g., greater than) the width (W) of the solder bumps 118 in some implementations and may not extend (e.g., less than) the width (W) of the solder bumps 118 in other implementations. It is contemplated that the extension of the wings 124 A, 124 B may vary depending on the various characteristics of the semiconductor semiconductor device 100 , such as the structural requirements of the semiconductor semiconductor device 100 , the power requirements of the semiconductor semiconductor device 100 , and so forth.
- FIG. 1 illustrates a semiconductor semiconductor device 100 that employs a Redistribution Layer (“RDL”) configuration
- RDL Redistribution Layer
- BOP Bump-On-Pad
- the BOP configuration may employ a conductive layer 116 disposed under the bump interface 120 (e.g., UBM pads).
- solder bumps 118 and associated bump interfaces 120 comprise bump assemblies 126 that are configured to provide mechanical and/or electrical interconnection of the integrated circuits formed in the semiconductor wafer 102 to the printed circuit board (not shown).
- the semiconductor semiconductor device 100 further includes an adhesive material 128 disposed on a second side (e.g., the backside or side opposite the formed integrated circuits) of the semiconductor wafer 102 .
- the adhesive material 128 is configured to bond the semiconductor wafer 102 and the integrated circuit die 140 once the integrated circuit die 140 is placed on the semiconductor wafer 102 .
- the adhesive material 128 may be configured in a variety of ways.
- the adhesive material 128 may be an adhesive dielectric material such as benzocyclobutene (BCB), or the like.
- the adhesive material 128 is configured to be patterned (e.g., not continuous) to allow for lateral expansion when the adhesive material 128 is pressed vertically (e.g., the integrated circuit die 140 is brought into contact with the adhesive material 128 ) for bonding purposes.
- the patterned adhesive material 128 is coated at least partially over the second surface of the semiconductor wafer 102 and then patterned to allow the adhesive material 128 to reflow laterally during the bonding procedure.
- the adhesive material 128 may function to planarize the second surface of the semiconductor wafer 102 (e.g., when the semiconductor wafer 102 is non-planarized) during reflow of the adhesive material 128 .
- the semiconductor device 100 includes an integrated circuit die 140 that is attached to the second side (e.g., backside) of the semiconductor wafer 102 .
- the integrated circuit die 140 includes a conductive pad 116 (e.g., a bond pad) that functions as an electrical connection between the integrated circuit die 140 and the electrical interconnections of the semiconductor wafer 102 .
- the conductive pad 116 may be exposed or may be covered by a passivation layer.
- the integrated circuit die 140 is attached to the adhesive material 128 on the second side of the semiconductor wafer 102 .
- the integrated circuit die 140 is attached to the backside of the semiconductor wafer 102 using benzocyclobutene (BCB) as the adhesive material 128 . Additionally, the integrated circuit die 140 may be attached and properly aligned using alignment marks 106 formed in the semiconductor wafer 102 .
- BCB benzocyclobutene
- an integrated circuit die 140 is attached to the second side (e.g., backside) of the semiconductor wafer 102 and the adhesive material 128 .
- the integrated circuit die 140 includes a conductive pad 116 that functions as an electrical interconnection between the integrated circuit die 140 and the semiconductor wafer 102 .
- a cap wafer 104 may be attached to the semiconductor wafer 102 and the adhesive material 128 , where the cap wafer 104 includes a pre-formed cavity 138 configured to house the integrated circuit die 140 .
- the cap wafer 104 may include a wafer (e.g., an unprocessed passive silicon wafer) that is configured to provide protection to the integrated circuit die 140 .
- the cap wafer 104 functions to structurally and environmentally protect the integrated circuit die 102 .
- the cap wafer 104 may be thinned as necessary to reduce weight and/or bulk of the semiconductor device 100 .
- the cap wafer 104 may be background so that the integrated circuit die 140 is at least partially exposed.
- the cavity 138 may be at least partially filled with a mold compound or an encapsulation material to further protect the integrated circuit die 140 .
- a second side (e.g., backside) of the semiconductor wafer 102 is patterned and wet-etched to form a cavity 138 configured to house the integrated circuit die 140 .
- the cavity 138 is configured to house a substantially planar integrated circuit die 140 .
- the second surface of the semiconductor wafer 102 to which the integrated circuit die 140 is attached and the adhesive material 128 must also be substantially planar to form a solid attachment.
- the cavity 138 may subsequently be filled with a mold or encapsulation material to further protect the integrated circuit die 102 .
- the semiconductor device 100 also includes a via 130 (e.g., a through-substrate via (TSV)) that extends through the semiconductor wafer 102 and the adhesive material 128 to at least one conductive layer 116 of the integrated circuit die 140 .
- the via 130 includes a conductive material 132 that furnishes an electrical interconnection between a first conductive layer 116 of semiconductor wafer 102 and a second conductive layer 116 of the integrated circuit die 140 .
- the conductive material 132 may include a metal material (e.g., copper, aluminum, etc.).
- the via 130 may provide an electrical interconnection between a first integrated circuit formed in the semiconductor wafer 102 and a second integrated circuit formed in the integrated circuit die 140 .
- the via 130 also includes an insulating liner 134 to electrically isolate the conductive material 132 disposed in the via 130 from the semiconductor wafer 102 .
- the insulating liner 134 is deposited in the via 130 such that the insulating liner 134 extends through the via 130 at least substantially the thickness of the semiconductor wafer 104 (e.g., the first surface to the second surface), as well as at least substantially the thickness of the adhesive material 128 to the conductive pad 116 of the integrated circuit die 140 .
- the insulating liner 134 may be configured in a variety of ways.
- the insulating liner 134 may be an insulating material (e.g., an oxide material, a nitride material, etc.).
- the insulating liner 134 is formed by depositing the insulating material in the via 130 and then etching the insulating material to form the insulating liner 134 along the sides of the via 130 .
- the insulating material may be deposited via plasma-enhanced chemical vapor deposition (PECVD) techniques and then anisotropically etching the insulating material down to the contact pad 116 of the integrated circuit die 140 to form the insulating liner 134 .
- the insulating material may include a silicon dioxide (SiO 2 ) material or the like.
- FIGS. 1A and 1B While a wafer and an attached integrated circuit die (e.g., semiconductor wafer 102 , integrated circuit die 140 ) are shown in FIGS. 1A and 1B , it is contemplated that the semiconductor device 100 may employ additional wafers and/or die stacked and bonded together. For example, a third die may be positioned over the first or second surface of the semiconductor wafer 102 and one or more vias formed therein. It is contemplated that many through-silicon via configurations may be utilized depending on the characteristics of semiconductor device 100 (e.g., design requirements, structural requirements, etc.).
- a semiconductor device 100 includes a semiconductor wafer 102 with an integrated circuit die 140 bonded together via an adhesive material 128 .
- the adhesive material 128 may be selectively patterned before the integrated circuit die 140 is positioned over and attached to the second surface (e.g., the backside) of the semiconductor wafer 102 and in contact with the adhesive material 128 . If the adhesive material 128 is patterned, the selective patterning may allow the adhesive material 128 to reflow laterally during the bonding procedure.
- a via 130 is formed that extends through the semiconductor wafer 102 and the adhesive material 128 to a conductive layer 116 in the integrated circuit die 140 .
- the conductive layer 116 of the integrated circuit die 140 is configured to provide an electrical interconnection with one or more integrated circuits formed in the semiconductor wafer 102 .
- the via 130 includes a conductive material 132 that further provides an interconnection between the conductive layer 116 of the semiconductor wafer 102 to a conductive layer 116 of the integrated circuit die 140 so that the integrated circuit of the semiconductor wafer 102 is electrically connected to an integrated circuit formed in the integrated circuit die 140 .
- the segmented semiconductor devices may comprise wafer chip-scale package devices, which may further be attached to another device (e.g., a printed circuit board) to create an electronic device.
- another device e.g., a printed circuit board
- FIG. 2 illustrates an example process 200 that employs wafer-level packaging techniques to fabricate three-dimensional semiconductor devices, such as the semiconductor device 100 shown in FIGS. 1A and 1B .
- FIGS. 3A through 3G illustrate sections of example wafers that may be utilized to fabricate semiconductor devices 300 (such as semiconductor device 100 ) shown in FIGS. 1A and 1B .
- a semiconductor wafer 302 as shown in FIG. 3A , includes a first surface (e.g., the top or frontside) and a second surface (e.g., the bottom or backside).
- the semiconductor wafer 302 includes one or more integrated circuits (not shown) formed proximate to the first surface.
- the integrated circuits are connected to one or more contact pads 316 (e.g., a metal pad, etc.) that are configured to provide electrical contacts through which the integrated circuits are interconnected to other components (e.g., other integrated circuits, printed circuit boards, etc.) associated with semiconductor device 300 .
- the semiconductor wafer 302 may further include one or more interconnect layer(s) 332 , 316 formed of various conducting and insulating materials, such as silicon dioxide (SiO 2 ), aluminum, copper, tungsten, and so forth between the contact pads 316 and the first surface of the semiconductor wafer 102 .
- the passivation layer 336 covers the interconnect layer(s) 332 , 316 and other components of the semiconductor wafer 302 to provide protection and insulation to the integrated circuits.
- the passivation layer 336 can be either planarized or non-planar and may include patterned holes to provide access to the contact pads 316 .
- a semiconductor wafer is bonded to a carrier wafer (Block 202 ).
- the semiconductor wafer 302 is bonded to a carrier wafer 342 via a temporary adhesive material 344 .
- the temporary adhesive material 344 may be a soluble bonding agent or wax.
- the carrier wafer 342 is configured to provide structural support to the semiconductor wafer 302 during one or more backgrinding processes. Once the carrier wafer 342 is bonded to the semiconductor wafer 302 , a backgrinding process is applied to the second surface (e.g., backside) of the semiconductor wafer 302 to allow for stacking and high density packaging of the semiconductor device (Block 204 ).
- the semiconductor device 300 includes a semiconductor wafer 302 having a first surface and a second surface.
- the first surface includes one or more integrated circuits formed therein.
- the integrated circuits are connected to one or more contact pads 316 to provide electrical interconnection between the integrated circuits and other components associated with the semiconductor device 300 (e.g., other integrated circuits, printed circuit boards, etc.)
- a passivation layer e.g., SiO 2 ) at least partially covers the first surface to provide protection to the integrated circuits from later fabrication steps.
- the second side (e.g., backside) of the semiconductor wafer is patterned and etched (Block 206 ).
- the second side of the semiconductor wafer 302 is patterned (e.g., using photolithography) and wet-etched to form a cavity 338 that is suitable to house the integrated circuit die 340 .
- Wet-etching may include exposing the semiconductor wafer 302 in an etchant (e.g., potassium hydroxide (KOH), buffered hydrofluoric acid, etc.) to remove an exposed portion of the backside of the semiconductor wafer 302 .
- the first side of the semiconductor wafer 302 may be cushioned and protected with a gas while the second side of the semiconductor wafer 302 is etched to form the cavity 338 .
- a second surface of a semiconductor wafer is coated with an adhesive material (Block 208 ).
- the adhesive material 328 may be configured as an adhesive dielectric (e.g., benzocyclobutene (BCB), etc.).
- placing the integrated circuit die 340 includes placing the integrated circuit die 340 on the adhesive material 328 on the second side of the semiconductor wafer 302 . If the semiconductor wafer 302 has been etched, the integrated circuit die 340 is placed in the cavity 338 formed by the etching process. It is contemplated that once the integrated circuit die 340 is attached to the second side of the semiconductor wafer 302 , a curing process may be utilized to further harden the adhesive material 328 .
- a cap wafer is placed on the backside of the semiconductor wafer and over the integrated circuit die (Block 212 ).
- placing a cap wafer 304 includes placing the cap wafer 304 having a pre-formed cavity 338 on the second side (the second side of the semiconductor wafer 302 is illustrated at the top of FIG. 3D ) of the semiconductor wafer 302 , where the previously attached integrated circuit die 340 is housed in the pre-formed cavity 338 .
- the cap wafer 304 is attached to the adhesive material 328 , which may subsequently be cured.
- placing the cap wafer 304 may include grinding the cap wafer 304 such that a portion of the integrated circuit chip 340 is exposed.
- the cavity 338 between the cap wafer 304 and the integrated circuit die 340 may be filled with a mold material or an encapsulation material for further support and/or environmental protection.
- aligning procedures may be employed to align the integrated circuit die 340 , the semiconductor wafer 302 , the carrier wafer 342 , and/or the cap wafer 304 .
- alignment marking techniques may be utilized to align each component.
- the semiconductor wafer 302 may include one or more alignment marks 306 to properly align the semiconductor wafer 302 with the integrated circuit die 340 , the carrier wafer 342 , and/or the cap wafer 304 during placement and/or bonding.
- visible light/infrared light alignment techniques may be utilized to align each component.
- a top visible light source (not shown) positioned above the semiconductor wafer 302 provides visible light to properly align the semiconductor wafer 302 .
- a top infrared light detector (not shown) positioned above the semiconductor wafer 302 , in combination with a bottom infrared source positioned below the semiconductor wafer 302 , allow for positioning of the integrated circuit die 340 , the carrier wafer 342 , and/or the cap wafer 304 .
- the infrared optics may be configured to provide an infrared light such that an operator, with proper magnification and visualization equipment, can see through the wafers and/or components to allow for proper alignment with the already properly aligned semiconductor wafer 302 .
- the carrier wafer is then removed from the semiconductor wafer (Block 214 ) by heating the temporary adhesive material (e.g., temporary adhesive material 344 ) sufficiently to allow for removal of the carrier wafer (e.g., carrier wafer 342 ) (see FIG. 3E ).
- a via is then formed through the semiconductor wafer and the adhesive material (Block 216 ) down (the second side of the semiconductor wafer is illustrated at the bottom in FIG. 3E ) to a conductive layer disposed as a portion of the integrated circuit die.
- the via 330 is formed by etching an aperture through the semiconductor wafer 302 and the adhesive material 328 . As illustrated in FIGS.
- a via 330 is formed through the semiconductor wafer 302 and the adhesive material 328 utilizing one or more photolithography and etching techniques. For instance, once the semiconductor wafer 302 is patterned, an etch to remove the various insulation layers (e.g., passivation layers), silicon layers, adhesive material, and so forth, is performed. The etching step is configured to form the via 330 and to stop on the conductive pad (e.g., conductive pad 316 of the integrated circuit die 340 ). It is contemplated that various etching techniques (e.g., dry etch, wet etch, etc.) may be utilized depending on the requirements of the semiconductor device 300 , the via 330 , and so forth.
- various insulation layers e.g., passivation layers
- silicon layers e.g., silicon layers, adhesive material, and so forth
- An insulating liner is formed in the via (Block 218 ) to electrically isolate the semiconductor wafer from the via.
- an insulating material is first deposited via plasma enhanced chemical vapor deposition (PECVD) techniques and then anisotropically etched down to the conductive layer 316 to form the insulating liner 334 as shown in FIGS. 3F and 3G .
- PECVD plasma enhanced chemical vapor deposition
- a diffusion barrier metal e.g., Ti, etc.
- a seed metal may be deposited over the first surface of the semiconductor wafer 302 as a part of the electrical interconnection layers (e.g., redistribution layer 124 , conductive material 332 , conductive pad 316 , etc.).
- the barrier metal and the seed metal may be patterned (e.g., via photolithography) to further provide electrical interconnections between the semiconductor wafer 302 and the integrated circuit die 340 at later fabrication stages.
- a conductive material is then deposited in the via (Block 220 ) to provide an electrical interconnection between the semiconductor wafer and the integrated circuit die.
- a conductive material 332 e.g., copper, or the like
- the via 330 is deposited in the via 330 to form an electrical interconnection between the conductive layer 316 of the semiconductor wafer 302 and the conductive layer 316 of the integrated circuit die 340 .
- the conductive material 332 is selectively plated-up via electroplating to form the electrical interconnections.
- the conductive material 332 deposited in the via 330 may also serve as the conductive material utilized for a redistribution structure, such as the redistribution structure 324 shown in FIGS. 3F and 3G .
- the deposition of the conductive material 332 in the via 330 may also result in the formation of a redistribution structure.
- further semiconductor fabrication techniques may be utilized to finalize the semiconductor device 300 fabrication process. For instance, further stripping of photoresist, etching of the seed and barrier metals to electrically isolate plated-up lines, and depositing of passivation layers may be incorporated. For example, seed and barrier metal in unplated areas may be removed to form the electrical interconnections.
- suitable wafer-level packaging processes may be employed to segment and package the individual semiconductor devices (Block 222 ).
- the segmented semiconductor devices may comprise wafer chip-scale package devices.
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Abstract
Description
- The present application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application Ser. No. 61/783,486, filed Mar. 14, 2013, and titled “SEMICONDUCTOR DEVICE HAVING A DIE AND THROUGH-SUBSTRATE VIA.” U.S. Provisional Application Ser. No. 61/783,486 is herein incorporated by reference in its entirety.
- Consumer electronic devices, in particular, mobile electronic devices such as smart phones, tablet computers, and so forth, increasingly employ smaller, more compact components to furnish their users with desired features. Such devices often employ three dimensional integrated circuit devices (3D IC). Three-dimensional integrated circuit devices are semiconductor devices that employ two or more layers of active electronic components. Through-substrate vias (TSV) interconnect electronic components on the different layers (e.g., different substrates) of the device allowing the devices to be integrated vertically as well as horizontally. Consequently, three-dimensional integrated circuit devices can provide increased functionality within a smaller, more compact footprint than do conventional two-dimensional integrated circuit devices.
- Semiconductor devices are described that include a semiconductor wafer and an integrated circuit die bonded together. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the semiconductor wafer and the integrated circuit die. In implementations, the semiconductor devices are fabricated by bonding a semiconductor wafer and an integrated circuit die together using an adhesive material, such as a dielectric. The adhesive material allows for lateral expansion when the integrated circuit die is attached to the semiconductor wafer and during the bonding process. For example, an integrated circuit die may be bonded to a semiconductor wafer by applying adhesive material to a second (e.g., backside or bottom) surface of the semiconductor wafer. The adhesive material may then be used to bond the integrated circuit die to the second (e.g., backside or bottom) surface of the semiconductor wafer. Vias may then be formed through the semiconductor wafer and the patterned adhesive material to furnish electrical interconnection between the semiconductor wafer and the integrated circuit die. The semiconductor wafer may then be segmented into individual semiconductor devices.
- This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
- The detailed description is described with reference to the accompanying figures. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items.
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FIG. 1A is a diagrammatic partial cross-sectional view illustrating a semiconductor device at wafer level (e.g., prior to singulation of the device) in accordance with an example implementation of the present disclosure. -
FIG. 1B is a diagrammatic partial cross-sectional view illustrating a semiconductor device at wafer level (e.g., prior to singulation of the device) in accordance with an example implementation of the present disclosure. -
FIG. 2 is a flow diagram illustrating a process in an example implementation for fabricating semiconductor devices, such as the device shown inFIG. 1 . -
FIGS. 3A through 3G are diagrammatic partial cross-sectional views illustrating the fabrication of wafer-level packaged semiconductor devices, such as the semiconductor device shown inFIGS. 1A and 1B according to the process shown inFIG. 2 , in an example implementation. - Three-dimensional integrated circuit devices are commonly manufactured using die-on-wafer techniques wherein electronic components (e.g., circuits) are first fabricated on two or more semiconductor wafers. The individual die are aligned on and attached to semiconductor wafers and segmented to provide individual devices. Through-substrate vias (TSV) are either built into wafers before they are attached, or else created in the wafer stack after attachment. However, the fabrication of three-dimensional integrated circuit devices requires additional manufacturing steps to join the die and wafers together. This increases the cost of the devices. Moreover, each extra manufacturing step adds a risk for inducing defects, possibly reducing device yield.
- Accordingly, techniques are described to fabricate semiconductor devices having multiple, stacked die on a substrate (e.g., a semiconductor wafer) in a reliable, production-worthy way. In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include a die bonded to the backside of a semiconductor wafer with an adhesive material. The die and semiconductor wafer include one or more integrated circuits formed therein. Through-substrate vias (TSV) are formed through the semiconductor wafer and the adhesive material is disposed between the die and the semiconductor wafer. The through-substrate vias in the semiconductor wafer include a conductive material, such as copper, that furnishes electrical interconnection between the integrated circuits in the semiconductor wafer and the die. It is contemplated that more than one die may be provided for attaching to the semiconductor wafer.
- In implementations, a wafer-level package device that employs example techniques in accordance with the present disclosure includes bonding a carrier wafer to a processed semiconductor wafer, using an adhesive material to attach an integrated circuit die to a second side of the processed semiconductor wafer, removing the carrier wafer, and forming a through-silicon via in the processed semiconductor wafer, where the through-silicon via furnishes an electrical connection between the processed semiconductor wafer and the integrated circuit die. Additionally, the integrated circuit die may be placed in a cavity on the second side (e.g., the backside) of the semiconductor wafer or may be covered by a cap wafer placed over the integrated circuit die and on the second side of the processed semiconductor wafer. The processed semiconductor wafer may then be segmented into individual semiconductor devices.
- Example Implementations
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FIG. 1 illustrates asemiconductor semiconductor device 100 in accordance with example implementations of the present disclosure. As shown, thesemiconductor semiconductor device 100 is illustrated at wafer level prior to singulation of thesemiconductor semiconductor device 100. Thesemiconductor semiconductor device 100 includes asemiconductor wafer 102. Thesemiconductor wafer 102 includes one or more integrated circuits (not shown), which are formed within thesemiconductor wafer 102. As illustrated inFIG. 1 , thesemiconductor wafer 102 further includes one ormore alignment marks 106. Thealignment marks 106 may be utilized to align thesemiconductor wafer 102 with a carrier wafer (described herein below). Additionally, thealignment marks 106 may be utilized to indicate a location for forming a through-silicon via 130, further described below. Thesemiconductor wafer 102 includes a first (e.g., top or front) surface and a second (e.g., bottom or backside) surface. The integrated circuits are formed (e.g., fabricated) proximate to the first surface of thesemiconductor wafer 102. It is contemplated that the first and/or the second surface of thesemiconductor wafer 102 may be planarized or unplanarized. - The
semiconductor wafer 102 include a base material utilized to form one or more integrated circuit devices through various fabrication techniques such as photolithography, ion implantation, deposition, etching, and so forth. Thesemiconductor wafer 102 may be configured in a variety of ways. For example, thesemiconductor wafer 102 may comprise an n-type silicon wafer or a p-type silicon wafer. In an implementation, thesemiconductor wafer 102 may comprise group V elements (e.g., phosphorus, arsenic, antimony, etc.) configured to furnish n-type charge carrier elements. In another implementation, thesemiconductor wafer 102 may comprise group IIIA elements (e.g., boron, etc.) configured to furnish p-type charge carrier elements. Further, the integrated circuits may be configured in a variety of ways. For example, the integrated circuits may include digital integrated circuits, analog integrated circuits, mixed-signal circuits, and so forth. In one or more implementations, the integrated circuits may include digital logic devices, analog devices (e.g., amplifiers, etc.), combinations thereof, and so forth. As described above, the integrated circuits may be fabricated utilizing various fabrication techniques. For example, the integrated circuits may be fabricated via complimentary metal-oxide-semiconductor (CMOS) techniques, bi-polar semiconductor techniques, and so on. - As shown in
FIG. 1 , thesemiconductor semiconductor device 100 also includes one or more area arrays ofconductive layers 116 of thesemiconductor wafer 102. In an implementation, theconductive layers 116 may comprise one or more conductive (e.g., contact) pads, redistribution structures, or the like. In a further implementation, theconductive layers 116 may include seed metal and/or barrier metal layers to allow for plated-line formation. The number and configuration ofconductive layers 116 may vary depending on the complexity and configuration of the integrated circuits, and so forth. Theconductive layers 116 provide electrical contacts through which the integrated circuits are interconnected to other components, such as printed circuit boards (not shown), when thesemiconductor devices 100 are configured as wafer-level packaging (WLP) devices or other integrated circuits disposed within thesemiconductor semiconductor device 100. In one or more implementations, theconductive layers 116 may comprise an electrically conductive material, such as a metal material (e.g., aluminum, copper, etc.), or the like. - The
conductive layers 116 may furnish electrical interconnection between various electrical components associated with thesemiconductor semiconductor device 100. For instance, a firstconductive layer 116 deployed over thesemiconductor wafer 102 may furnish an electrical interconnection to a secondconductive layer 116 deployed over another device (e.g., an integrated circuit die 140). In another instance, aconductive layer 116 deployed over thesemiconductor wafer 102 may provide electrical interconnection with one or more solder bumps 118. Solder bumps 118 are provided to furnish mechanical and/or electrical interconnection between theconductive layers 116 and corresponding pads (not shown) formed on the surface of a printed circuit board (not shown) or another semiconductor device. In one or more implementations, the solder bumps 118 may be fabricated of a lead-free solder such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on. However, it is contemplated that Tin-Lead (PbSn) solders may be used. - Bump interfaces 120 may be applied to the
conductive layers 116 to provide a reliable interconnect boundary between theconductive layers 116 and the solder bumps 118. For instance, in thesemiconductor semiconductor device 100 shown inFIG. 1 , thebump interface 120 comprises under-bump metallization (UBM) 122 applied to theconductive layers 116 of theintegrated circuit chip 102. TheUBM 122 may have a variety of compositions. For example, theUBM 122 include multiple layers of different metals (e.g., Aluminum (Al), Nickel (Ni), Copper (Cu), etc.) that function as an adhesion layer, a diffusion barrier layer, a solderable layer, an oxidation barrier layer, and so forth. However, other UBM structures are possible. - In one or more implementations, the
semiconductor semiconductor device 100 may employ a Redistribution Layer (“RDL”) configuration. The RDL configuration employs aredistribution structure 124 comprised of a thin-film metal (e.g., aluminum, copper, etc.) rerouting and interconnection system that redistributes theconductive layers 116 to an area array of bump interfaces 120 (e.g., UBM pads) that may be more evenly deployed over the surface of thesemiconductor semiconductor device 100. The solder bumps 118 are subsequently placed over thesebump interfaces 120 to formbump assemblies 126. - As illustrated in
FIG. 1 , theredistribution layer 124 may includewings semiconductor semiconductor device 100, which may prevent the cracking of thesemiconductor semiconductor device 100 during various testing phases (e.g., temperature cycling, drop testing, etc.). In one or more implementations, thewings redistribution layer 124 extension that may extend to approximately the width (W) of thesolder bump 118. However, it is contemplated that thewings wings semiconductor semiconductor device 100, such as the structural requirements of thesemiconductor semiconductor device 100, the power requirements of thesemiconductor semiconductor device 100, and so forth. - While
FIG. 1 illustrates asemiconductor semiconductor device 100 that employs a Redistribution Layer (“RDL”) configuration, it is contemplated that thesemiconductor semiconductor device 100 illustrated and described herein may also employ a Bump-On-Pad (“BOP”) configuration. The BOP configuration may employ aconductive layer 116 disposed under the bump interface 120 (e.g., UBM pads). - Viewed together, the solder bumps 118 and associated bump interfaces 120 (e.g., UBM 122) comprise
bump assemblies 126 that are configured to provide mechanical and/or electrical interconnection of the integrated circuits formed in thesemiconductor wafer 102 to the printed circuit board (not shown). - The
semiconductor semiconductor device 100 further includes anadhesive material 128 disposed on a second side (e.g., the backside or side opposite the formed integrated circuits) of thesemiconductor wafer 102. Theadhesive material 128 is configured to bond thesemiconductor wafer 102 and the integrated circuit die 140 once the integrated circuit die 140 is placed on thesemiconductor wafer 102. Theadhesive material 128 may be configured in a variety of ways. For example, theadhesive material 128 may be an adhesive dielectric material such as benzocyclobutene (BCB), or the like. In one implementation, theadhesive material 128 is configured to be patterned (e.g., not continuous) to allow for lateral expansion when theadhesive material 128 is pressed vertically (e.g., the integrated circuit die 140 is brought into contact with the adhesive material 128) for bonding purposes. In this implementation, the patternedadhesive material 128 is coated at least partially over the second surface of thesemiconductor wafer 102 and then patterned to allow theadhesive material 128 to reflow laterally during the bonding procedure. Moreover, theadhesive material 128 may function to planarize the second surface of the semiconductor wafer 102 (e.g., when thesemiconductor wafer 102 is non-planarized) during reflow of theadhesive material 128. - The
semiconductor device 100 includes an integrated circuit die 140 that is attached to the second side (e.g., backside) of thesemiconductor wafer 102. In embodiments, the integrated circuit die 140 includes a conductive pad 116 (e.g., a bond pad) that functions as an electrical connection between the integrated circuit die 140 and the electrical interconnections of thesemiconductor wafer 102. Theconductive pad 116 may be exposed or may be covered by a passivation layer. In implementations, the integrated circuit die 140 is attached to theadhesive material 128 on the second side of thesemiconductor wafer 102. In one implementation, the integrated circuit die 140 is attached to the backside of thesemiconductor wafer 102 using benzocyclobutene (BCB) as theadhesive material 128. Additionally, the integrated circuit die 140 may be attached and properly aligned using alignment marks 106 formed in thesemiconductor wafer 102. - In one embodiment and as shown in
FIG. 1A , an integrated circuit die 140 is attached to the second side (e.g., backside) of thesemiconductor wafer 102 and theadhesive material 128. In this embodiment, the integrated circuit die 140 includes aconductive pad 116 that functions as an electrical interconnection between the integrated circuit die 140 and thesemiconductor wafer 102. Additionally, acap wafer 104 may be attached to thesemiconductor wafer 102 and theadhesive material 128, where thecap wafer 104 includes apre-formed cavity 138 configured to house the integrated circuit die 140. Thecap wafer 104 may include a wafer (e.g., an unprocessed passive silicon wafer) that is configured to provide protection to the integrated circuit die 140. Thecap wafer 104 functions to structurally and environmentally protect the integrated circuit die 102. Thecap wafer 104 may be thinned as necessary to reduce weight and/or bulk of thesemiconductor device 100. In some implementations, thecap wafer 104 may be background so that the integrated circuit die 140 is at least partially exposed. In these implementations, thecavity 138 may be at least partially filled with a mold compound or an encapsulation material to further protect the integrated circuit die 140. - In another embodiment and as shown in
FIG. 1B , a second side (e.g., backside) of thesemiconductor wafer 102 is patterned and wet-etched to form acavity 138 configured to house the integrated circuit die 140. Thecavity 138 is configured to house a substantially planar integrated circuit die 140. The second surface of thesemiconductor wafer 102 to which the integrated circuit die 140 is attached and theadhesive material 128 must also be substantially planar to form a solid attachment. In some implementations, thecavity 138 may subsequently be filled with a mold or encapsulation material to further protect the integrated circuit die 102. - The
semiconductor device 100 also includes a via 130 (e.g., a through-substrate via (TSV)) that extends through thesemiconductor wafer 102 and theadhesive material 128 to at least oneconductive layer 116 of the integrated circuit die 140. As illustrated inFIGS. 1A and 1B , the via 130 includes aconductive material 132 that furnishes an electrical interconnection between a firstconductive layer 116 ofsemiconductor wafer 102 and a secondconductive layer 116 of the integrated circuit die 140. In one or more implementations, theconductive material 132 may include a metal material (e.g., copper, aluminum, etc.). For instance, the via 130 may provide an electrical interconnection between a first integrated circuit formed in thesemiconductor wafer 102 and a second integrated circuit formed in the integrated circuit die 140. - The via 130 also includes an insulating
liner 134 to electrically isolate theconductive material 132 disposed in the via 130 from thesemiconductor wafer 102. As illustrated inFIGS. 1A and 1B , the insulatingliner 134 is deposited in the via 130 such that the insulatingliner 134 extends through the via 130 at least substantially the thickness of the semiconductor wafer 104 (e.g., the first surface to the second surface), as well as at least substantially the thickness of theadhesive material 128 to theconductive pad 116 of the integrated circuit die 140. The insulatingliner 134 may be configured in a variety of ways. For example, the insulatingliner 134 may be an insulating material (e.g., an oxide material, a nitride material, etc.). The insulatingliner 134 is formed by depositing the insulating material in the via 130 and then etching the insulating material to form the insulatingliner 134 along the sides of thevia 130. In one or more implementations, the insulating material may be deposited via plasma-enhanced chemical vapor deposition (PECVD) techniques and then anisotropically etching the insulating material down to thecontact pad 116 of the integrated circuit die 140 to form the insulatingliner 134. In one or more implementations, the insulating material may include a silicon dioxide (SiO2) material or the like. - While a wafer and an attached integrated circuit die (e.g.,
semiconductor wafer 102, integrated circuit die 140) are shown inFIGS. 1A and 1B , it is contemplated that thesemiconductor device 100 may employ additional wafers and/or die stacked and bonded together. For example, a third die may be positioned over the first or second surface of thesemiconductor wafer 102 and one or more vias formed therein. It is contemplated that many through-silicon via configurations may be utilized depending on the characteristics of semiconductor device 100 (e.g., design requirements, structural requirements, etc.). - In accordance with the present disclosure, a
semiconductor device 100 includes asemiconductor wafer 102 with an integrated circuit die 140 bonded together via anadhesive material 128. In some embodiments, theadhesive material 128 may be selectively patterned before the integrated circuit die 140 is positioned over and attached to the second surface (e.g., the backside) of thesemiconductor wafer 102 and in contact with theadhesive material 128. If theadhesive material 128 is patterned, the selective patterning may allow theadhesive material 128 to reflow laterally during the bonding procedure. Once the bonding procedure is complete (e.g., after curing of theadhesive material 128, etc.), a via 130 is formed that extends through thesemiconductor wafer 102 and theadhesive material 128 to aconductive layer 116 in the integrated circuit die 140. Theconductive layer 116 of the integrated circuit die 140 is configured to provide an electrical interconnection with one or more integrated circuits formed in thesemiconductor wafer 102. The via 130 includes aconductive material 132 that further provides an interconnection between theconductive layer 116 of thesemiconductor wafer 102 to aconductive layer 116 of the integrated circuit die 140 so that the integrated circuit of thesemiconductor wafer 102 is electrically connected to an integrated circuit formed in the integrated circuit die 140. Once the fabrication is complete, suitable wafer-level packaging processes may be employed to segment and package the individualsemiconductor semiconductor device 100. In one or more implementations, the segmented semiconductor devices may comprise wafer chip-scale package devices, which may further be attached to another device (e.g., a printed circuit board) to create an electronic device. - Example Fabrication Processes
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FIG. 2 illustrates anexample process 200 that employs wafer-level packaging techniques to fabricate three-dimensional semiconductor devices, such as thesemiconductor device 100 shown inFIGS. 1A and 1B .FIGS. 3A through 3G illustrate sections of example wafers that may be utilized to fabricate semiconductor devices 300 (such as semiconductor device 100) shown inFIGS. 1A and 1B . Asemiconductor wafer 302, as shown inFIG. 3A , includes a first surface (e.g., the top or frontside) and a second surface (e.g., the bottom or backside). Thesemiconductor wafer 302 includes one or more integrated circuits (not shown) formed proximate to the first surface. The integrated circuits are connected to one or more contact pads 316 (e.g., a metal pad, etc.) that are configured to provide electrical contacts through which the integrated circuits are interconnected to other components (e.g., other integrated circuits, printed circuit boards, etc.) associated withsemiconductor device 300. Thesemiconductor wafer 302 may further include one or more interconnect layer(s) 332, 316 formed of various conducting and insulating materials, such as silicon dioxide (SiO2), aluminum, copper, tungsten, and so forth between thecontact pads 316 and the first surface of thesemiconductor wafer 102. Thepassivation layer 336 covers the interconnect layer(s) 332, 316 and other components of thesemiconductor wafer 302 to provide protection and insulation to the integrated circuits. Thepassivation layer 336 can be either planarized or non-planar and may include patterned holes to provide access to thecontact pads 316. - As illustrated in
FIG. 2 , a semiconductor wafer is bonded to a carrier wafer (Block 202). For example, as shown inFIG. 3B , thesemiconductor wafer 302 is bonded to acarrier wafer 342 via a temporaryadhesive material 344. In one or more implementations, the temporaryadhesive material 344 may be a soluble bonding agent or wax. Thecarrier wafer 342 is configured to provide structural support to thesemiconductor wafer 302 during one or more backgrinding processes. Once thecarrier wafer 342 is bonded to thesemiconductor wafer 302, a backgrinding process is applied to the second surface (e.g., backside) of thesemiconductor wafer 302 to allow for stacking and high density packaging of the semiconductor device (Block 204). - As illustrated in
FIG. 3 , thesemiconductor device 300 includes asemiconductor wafer 302 having a first surface and a second surface. The first surface includes one or more integrated circuits formed therein. The integrated circuits are connected to one ormore contact pads 316 to provide electrical interconnection between the integrated circuits and other components associated with the semiconductor device 300 (e.g., other integrated circuits, printed circuit boards, etc.) A passivation layer (e.g., SiO2) at least partially covers the first surface to provide protection to the integrated circuits from later fabrication steps. - In some embodiments, the second side (e.g., backside) of the semiconductor wafer is patterned and etched (Block 206). In these embodiments and as shown in
FIG. 3G , the second side of thesemiconductor wafer 302 is patterned (e.g., using photolithography) and wet-etched to form acavity 338 that is suitable to house the integrated circuit die 340. Wet-etching may include exposing thesemiconductor wafer 302 in an etchant (e.g., potassium hydroxide (KOH), buffered hydrofluoric acid, etc.) to remove an exposed portion of the backside of thesemiconductor wafer 302. In some embodiments, the first side of thesemiconductor wafer 302 may be cushioned and protected with a gas while the second side of thesemiconductor wafer 302 is etched to form thecavity 338. - As illustrated in
FIG. 2 , a second surface of a semiconductor wafer is coated with an adhesive material (Block 208). In implementations where thesemiconductor wafer 302 is patterned and etched to form acavity 338, the second side of thesemiconductor wafer 302 as well as thecavity 338 is coated with theadhesive material 328. Theadhesive material 328 may be configured as an adhesive dielectric (e.g., benzocyclobutene (BCB), etc.). Once theadhesive material 328 is applied to thesemiconductor wafer 302, theadhesive material 328 may be patterned to allow for lateral expansion of the patternedadhesive material 328 when the integrated circuit die 340 is pressed into contact with the patternedadhesive material 328. - Next, the integrated circuit die is placed on the adhesive material and the semiconductor wafer (Block 210). As illustrated in
FIG. 3C , placing the integrated circuit die 340 includes placing the integrated circuit die 340 on theadhesive material 328 on the second side of thesemiconductor wafer 302. If thesemiconductor wafer 302 has been etched, the integrated circuit die 340 is placed in thecavity 338 formed by the etching process. It is contemplated that once the integrated circuit die 340 is attached to the second side of thesemiconductor wafer 302, a curing process may be utilized to further harden theadhesive material 328. - In embodiments where the semiconductor wafer is not etched to form a cavity, a cap wafer is placed on the backside of the semiconductor wafer and over the integrated circuit die (Block 212). As shown in
FIG. 3D , placing acap wafer 304 includes placing thecap wafer 304 having apre-formed cavity 338 on the second side (the second side of thesemiconductor wafer 302 is illustrated at the top ofFIG. 3D ) of thesemiconductor wafer 302, where the previously attached integrated circuit die 340 is housed in thepre-formed cavity 338. In implementations, thecap wafer 304 is attached to theadhesive material 328, which may subsequently be cured. In some embodiments, placing thecap wafer 304 may include grinding thecap wafer 304 such that a portion of theintegrated circuit chip 340 is exposed. In these specific embodiments, thecavity 338 between thecap wafer 304 and the integrated circuit die 340 may be filled with a mold material or an encapsulation material for further support and/or environmental protection. - It is contemplated that various aligning procedures may be employed to align the integrated circuit die 340, the
semiconductor wafer 302, thecarrier wafer 342, and/or thecap wafer 304. In an implementation, alignment marking techniques may be utilized to align each component. For instance, thesemiconductor wafer 302 may include one or more alignment marks 306 to properly align thesemiconductor wafer 302 with the integrated circuit die 340, thecarrier wafer 342, and/or thecap wafer 304 during placement and/or bonding. In implementations, visible light/infrared light alignment techniques may be utilized to align each component. In an implementation, a top visible light source (not shown) positioned above thesemiconductor wafer 302 provides visible light to properly align thesemiconductor wafer 302. Then, a top infrared light detector (not shown) positioned above thesemiconductor wafer 302, in combination with a bottom infrared source positioned below thesemiconductor wafer 302, allow for positioning of the integrated circuit die 340, thecarrier wafer 342, and/or thecap wafer 304. The infrared optics may be configured to provide an infrared light such that an operator, with proper magnification and visualization equipment, can see through the wafers and/or components to allow for proper alignment with the already properly alignedsemiconductor wafer 302. - The carrier wafer is then removed from the semiconductor wafer (Block 214) by heating the temporary adhesive material (e.g., temporary adhesive material 344) sufficiently to allow for removal of the carrier wafer (e.g., carrier wafer 342) (see
FIG. 3E ). A via is then formed through the semiconductor wafer and the adhesive material (Block 216) down (the second side of the semiconductor wafer is illustrated at the bottom inFIG. 3E ) to a conductive layer disposed as a portion of the integrated circuit die. The via 330 is formed by etching an aperture through thesemiconductor wafer 302 and theadhesive material 328. As illustrated inFIGS. 3F and 3G , a via 330 is formed through thesemiconductor wafer 302 and theadhesive material 328 utilizing one or more photolithography and etching techniques. For instance, once thesemiconductor wafer 302 is patterned, an etch to remove the various insulation layers (e.g., passivation layers), silicon layers, adhesive material, and so forth, is performed. The etching step is configured to form the via 330 and to stop on the conductive pad (e.g.,conductive pad 316 of the integrated circuit die 340). It is contemplated that various etching techniques (e.g., dry etch, wet etch, etc.) may be utilized depending on the requirements of thesemiconductor device 300, the via 330, and so forth. - An insulating liner is formed in the via (Block 218) to electrically isolate the semiconductor wafer from the via. In an implementation, an insulating material is first deposited via plasma enhanced chemical vapor deposition (PECVD) techniques and then anisotropically etched down to the
conductive layer 316 to form the insulatingliner 334 as shown inFIGS. 3F and 3G . Moreover, a diffusion barrier metal (e.g., Ti, etc.) and a seed metal may be deposited over the first surface of thesemiconductor wafer 302 as a part of the electrical interconnection layers (e.g.,redistribution layer 124,conductive material 332,conductive pad 316, etc.). The barrier metal and the seed metal may be patterned (e.g., via photolithography) to further provide electrical interconnections between thesemiconductor wafer 302 and the integrated circuit die 340 at later fabrication stages. - A conductive material is then deposited in the via (Block 220) to provide an electrical interconnection between the semiconductor wafer and the integrated circuit die. For instance, as illustrated in
FIGS. 3F and 3G , a conductive material 332 (e.g., copper, or the like) is deposited in the via 330 to form an electrical interconnection between theconductive layer 316 of thesemiconductor wafer 302 and theconductive layer 316 of the integrated circuit die 340. In one or more implementations, theconductive material 332 is selectively plated-up via electroplating to form the electrical interconnections. Moreover, in one or more implementations, theconductive material 332 deposited in the via 330 may also serve as the conductive material utilized for a redistribution structure, such as theredistribution structure 324 shown inFIGS. 3F and 3G . Thus, the deposition of theconductive material 332 in the via 330 may also result in the formation of a redistribution structure. It is contemplated that further semiconductor fabrication techniques may be utilized to finalize thesemiconductor device 300 fabrication process. For instance, further stripping of photoresist, etching of the seed and barrier metals to electrically isolate plated-up lines, and depositing of passivation layers may be incorporated. For example, seed and barrier metal in unplated areas may be removed to form the electrical interconnections. - Once the wafer fabrication process is complete, suitable wafer-level packaging processes may be employed to segment and package the individual semiconductor devices (Block 222). In one or more implementations, the segmented semiconductor devices may comprise wafer chip-scale package devices.
- Although the subject matter has been described in language specific to structural features and/or process operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/930,417 US9196587B2 (en) | 2013-03-14 | 2013-06-28 | Semiconductor device having a die and through substrate-via |
CN201410255113.6A CN104183597B (en) | 2013-03-14 | 2014-03-14 | Semiconductor device with die and through-substrate via |
US14/948,664 US9659900B2 (en) | 2013-03-14 | 2015-11-23 | Semiconductor device having a die and through-substrate via |
Applications Claiming Priority (2)
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US201361783486P | 2013-03-14 | 2013-03-14 | |
US13/930,417 US9196587B2 (en) | 2013-03-14 | 2013-06-28 | Semiconductor device having a die and through substrate-via |
Related Child Applications (1)
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US14/948,664 Division US9659900B2 (en) | 2013-03-14 | 2015-11-23 | Semiconductor device having a die and through-substrate via |
Publications (2)
Publication Number | Publication Date |
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US20140264844A1 true US20140264844A1 (en) | 2014-09-18 |
US9196587B2 US9196587B2 (en) | 2015-11-24 |
Family
ID=51523888
Family Applications (2)
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US13/930,417 Active 2033-10-31 US9196587B2 (en) | 2013-03-14 | 2013-06-28 | Semiconductor device having a die and through substrate-via |
US14/948,664 Active US9659900B2 (en) | 2013-03-14 | 2015-11-23 | Semiconductor device having a die and through-substrate via |
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CN (1) | CN104183597B (en) |
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US20160079197A1 (en) | 2016-03-17 |
US9659900B2 (en) | 2017-05-23 |
US9196587B2 (en) | 2015-11-24 |
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CN104183597B (en) | 2020-12-08 |
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