US20140231817A1 - Iii-n material grown on alo/aln buffer on si substrate - Google Patents
Iii-n material grown on alo/aln buffer on si substrate Download PDFInfo
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- US20140231817A1 US20140231817A1 US13/772,126 US201313772126A US2014231817A1 US 20140231817 A1 US20140231817 A1 US 20140231817A1 US 201313772126 A US201313772126 A US 201313772126A US 2014231817 A1 US2014231817 A1 US 2014231817A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000000463 material Substances 0.000 title claims abstract description 57
- 239000010410 layer Substances 0.000 claims abstract description 111
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 239000010703 silicon Substances 0.000 claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 64
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 48
- 239000013078 crystal Substances 0.000 claims abstract description 36
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 34
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910002601 GaN Inorganic materials 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 41
- 238000000151 deposition Methods 0.000 claims description 30
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 27
- AXTADRUCVAUCRS-UHFFFAOYSA-N 1-(2-hydroxyethyl)pyrrole-2,5-dione Chemical group OCCN1C(=O)C=CC1=O AXTADRUCVAUCRS-UHFFFAOYSA-N 0.000 claims description 3
- 229910002704 AlGaN Inorganic materials 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 3
- 238000010924 continuous production Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910016909 AlxOy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910001404 rare earth metal oxide Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Definitions
- This invention relates in general to the growth of III-N material on a silicon substrate and more specifically to the formation of an AlO/AlN buffer between the silicon substrate and GaN with thin AlN interlayers.
- the method includes a single crystal buffer positioned on a silicon substrate.
- the buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface.
- a first layer of III-N material is positioned on the upper surface of the buffer.
- An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer.
- the inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
- the desired objects and aspects of the instant invention are further achieved in accordance with a preferred method of growing III-N material on a silicon substrate including a step of growing or depositing a single crystal buffer on a silicon substrate.
- the buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface.
- the method further includes the steps of growing or depositing a first layer of III-N material on the surface of the rare earth oxide layer; growing or depositing an inter-layer of aluminum nitride (AlN) on the first layer of III-N material; and growing or depositing an additional layer of III-N material on the surface of the layer of aluminum nitride.
- the step of growing or depositing the inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
- FIG. 1 is a simplified layer diagram illustrating a method of growing III-N material on a silicon substrate, in accordance with the present invention
- FIG. 2 is a simplified layer diagram of the III-N material on the silicon substrate of FIG. 1 with an LED structure formed thereon;
- FIG. 3 is a simplified layer diagram of the GaN on the silicon substrate of FIG. 1 with an HEMT structure formed thereon.
- FIG. 1 a simplified layer diagram is illustrated representing several steps in a process of growing III-N material and in this preferred example GaN on a silicon substrate 10 , in accordance with the present invention.
- substrate 10 is or may be a standard well known single crystal wafer or portion thereof generally known and used in the semiconductor industry.
- Single crystal substrates are not limited to any specific crystal orientation but could include (111) silicon, (110) silicon, (100) silicon or any other orientation or variation known and used in the art.
- the Si (100) and (111) substrates could also include various miscuts with nominal value between 0 and 10° in any direction.
- substrate 10 is illustrated with a preferred (111) orientation because of the simplification of further operations.
- a layer 11 of aluminum oxynitride (Al x O y N) is epitaxially grown on silicon substrate 10 .
- Aluminum oxynitride has a crystal lattice spacing that can be substantially matched to silicon with very little strain. Further, the crystal lattice spacing of layer 11 can be varied by varying the composition of the aluminum oxynitride (e.g. varying y between 0 and 0.5), which allows for strain engineering of the silicon wafers. Generally, the aluminum oxynitride material closest to or adjacent silicon substrate 10 will have a larger y component which adjusts the crystal spacing closest to the crystal spacing of silicon while aluminum oxynitride material adjacent the opposite side of layer 11 will have a smaller y component. Also, aluminum oxynitride layer 11 can be formed with a single continuous composition or it can be graded, in linear, stepwise or any similar schemes.
- aluminum oxide is impervious to MBE process gasses, i.e. N 2 plasma, NH 3 and metallic Ga, which is the preferred growth process in this invention.
- MOCVD process gasses NH 3 , H 2 , TMGa, etc.
- Reaction of silicon with process gasses usually results in etching of silicon (H 2 ), formation of nitrides (NH 3 ), or severe reaction and blistering (Ga precursors).
- silicon substrate 10 is protected from damage caused by generally all growth process gasses by aluminum oxynitride layer 11 .
- a layer 12 of aluminum nitride (AlN) is epitaxially grown on aluminum oxynitride layer 11 . Since the material of layer 11 adjacent the upper surface has or may have a smaller y component, the crystal spacing is closer to the crystal spacing of the AlN grown on the surface. In some applications it may be convenient for layers 11 and 12 to be formed as a single layer in which the oxygen (y component) varies from a maximum content adjacent silicon substrate 10 to zero adjacent the upper surface. Also, layers 11 and 12 can be formed as two single continuous compositions (generally as illustrated) or one or both can be graded, in linear, stepwise or any similar schemes.
- Aluminum oxynitride layer 11 and aluminum nitride layer 12 form a buffer 15 for the further epitaxial growth of III-N materials.
- the aluminum nitride in buffer 15 is closer to matching the crystal formation and lattice spacing of III-N materials, such as GaN, so that III-N materials can be epitaxially grown directly on buffer 15 .
- GaN layer 16 is epitaxially grown on aluminum nitride layer 11 of buffer 15 preferably by an MBE process.
- GaN layer 16 will be in a range of 50 nm to 100 nm thick, although thicker or thinner layers can be grown. Because there will still be some strain in GaN layer 16 , i.e. the crystal lattice junction with buffer 15 still produces some strain, a thinner layer 16 of GaN is preferred.
- a thin inter-layer of aluminum nitride (AlN) 18 is epitaxially grown on GaN layer 16 to further reduce the strain.
- AlN inter-layer 18 is in a range of approximately 1 nm to approximately 10 nm thick but for certain applications thicker or thinner films can be grown.
- AlN inter-layer 18 can be grown using either a low or a high temperature process.
- a second layer 19 of GaN is epitaxially grown on AlN inter-layer 18 .
- a second inter-layer of AlN is grown on second GaN layer 19 and this process is repeated n times or until the strain in the upper GaN layer has been reduced to an acceptable level.
- the strain formed during the growth of the GaN is controlled by insertion of the thin inter-layers of AlN, each of which allows the following layer of GaN to be under compressive stress due to the pseudomorphic growth at the interface. Repeating the process (i.e. the alternating growth of layers 18 and 19 ) n times can be used to further reduce or engineer strain in the final GaN or III-N layer. Also, it should be noted that since each additional layer of GaN grown on the next inter-layer of AlN has less strain, each additional layer can be grown thicker if desired.
- buffer 15 GaN layer 16 /AlN inter-layer 18 /GaN layer 19 (repeated n times) is illustrated with a III-N LED structure 20 formed thereon.
- Structure 20 is illustrated as a single layer for convenience but it should be understood that III-N LED structure 20 includes the growth of one or more typical layers, including for example, i-GaN, n-GaN, active layers such as InGaN/GaN, electron blocking layers, p-GaN, and other inter-layers used in the formation and performance of LED (especially photonic LED) devices.
- buffer 15 GaN layer 16 /AlN inter-layer 18 /GaN layer 19 (repeated n times) is illustrated with a HEMT structure 30 formed thereon.
- Structure 30 is illustrated as a single layer for convenience but it should be understood that HEMT structure 30 includes the growth of one or more typical layers, including for example, i-GaN, AlN, AlGaN, GaN, and other inter-layers used in the formation and performance of HEMT devices.
- new and improved methods for the growth of III-N material and devices on a silicon substrate are disclosed.
- the new and improved methods for the III-N material include the growth of a substantially crystal lattice matching buffer on the silicon substrate and n repetitions of the growth of thin AlN inter-layers in the III-N material to further reduce or engineer the strain.
- the buffer eliminates or greatly reduces the problem of possibly damaging the silicon substrate with process gasses.
- New and improved LED and/or HEMI structures can be substantially lattice matched and thermally matched by the new process on a silicon substrate.
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Abstract
Description
- This invention relates in general to the growth of III-N material on a silicon substrate and more specifically to the formation of an AlO/AlN buffer between the silicon substrate and GaN with thin AlN interlayers.
- In the semiconductor industry, it is known that growing a III-N material, such as GaN, on a silicon substrate is difficult due in large part to the large crystal lattice mismatch (−16.9%) and the thermal mismatch (53%) between silicon and GaN. Thus, some type of buffer layer or layers is generally formed on the silicon substrate and the III-N material is grown on the buffer layer. Generally, the prior art buffer layers are either complicated and expensive to form or do no adequately reduce the strain in the GaN due to crystal lattice mismatch.
- It is also known that during much of the growth process there must ideally be no exposed silicon surface due to detrimental reaction between silicon and the various MBE process gasses, i.e. N2 plasma, NH3 and metallic Ga. Also in the case where other growth processes are used, such as MOCVD process gasses (NH3, H2, TMGa, etc.). Reaction of silicon with process gasses usually results in etching of silicon (H2), formation of nitrides (NH3), or severe reaction and blistering (Ga precursors). Many of the prior art buffer schemes do not adequately protect the silicon substrate.
- It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
- Accordingly, it is an object of the present invention to provide new and improved methods for the growth of III-N material on a silicon substrate.
- It is another object of the present invention to provide new and improved methods for the growth of III-N material on a silicon substrate that includes eliminating or greatly reducing the problem of possible damage to the silicon substrate with process gasses.
- It is another object of the present invention to provide new and improved III-N layers grown on a silicon substrate.
- It is another object of the present invention to provide new and improved LED and/or HEMI structures formed on III-N layers on a silicon substrate.
- Briefly, the desired objects and aspects of the instant invention are realized in accordance with a method of growing a III-N material on a silicon substrate. The method includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
- The desired objects and aspects of the instant invention are further achieved in accordance with a preferred method of growing III-N material on a silicon substrate including a step of growing or depositing a single crystal buffer on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. The method further includes the steps of growing or depositing a first layer of III-N material on the surface of the rare earth oxide layer; growing or depositing an inter-layer of aluminum nitride (AlN) on the first layer of III-N material; and growing or depositing an additional layer of III-N material on the surface of the layer of aluminum nitride. The step of growing or depositing the inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
- The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the drawings, in which:
-
FIG. 1 is a simplified layer diagram illustrating a method of growing III-N material on a silicon substrate, in accordance with the present invention; -
FIG. 2 is a simplified layer diagram of the III-N material on the silicon substrate ofFIG. 1 with an LED structure formed thereon; and -
FIG. 3 is a simplified layer diagram of the GaN on the silicon substrate ofFIG. 1 with an HEMT structure formed thereon. - Turning to
FIG. 1 , a simplified layer diagram is illustrated representing several steps in a process of growing III-N material and in this preferred example GaN on a silicon substrate 10, in accordance with the present invention. It will be understood that substrate 10 is or may be a standard well known single crystal wafer or portion thereof generally known and used in the semiconductor industry. Single crystal substrates, it will be understood, are not limited to any specific crystal orientation but could include (111) silicon, (110) silicon, (100) silicon or any other orientation or variation known and used in the art. The Si (100) and (111) substrates could also include various miscuts with nominal value between 0 and 10° in any direction. However, throughout this disclosure substrate 10 is illustrated with a preferred (111) orientation because of the simplification of further operations. - A layer 11 of aluminum oxynitride (AlxOyN) is epitaxially grown on silicon substrate 10. Aluminum oxynitride has a crystal lattice spacing that can be substantially matched to silicon with very little strain. Further, the crystal lattice spacing of layer 11 can be varied by varying the composition of the aluminum oxynitride (e.g. varying y between 0 and 0.5), which allows for strain engineering of the silicon wafers. Generally, the aluminum oxynitride material closest to or adjacent silicon substrate 10 will have a larger y component which adjusts the crystal spacing closest to the crystal spacing of silicon while aluminum oxynitride material adjacent the opposite side of layer 11 will have a smaller y component. Also, aluminum oxynitride layer 11 can be formed with a single continuous composition or it can be graded, in linear, stepwise or any similar schemes.
- It should be noted that aluminum oxide is impervious to MBE process gasses, i.e. N2 plasma, NH3 and metallic Ga, which is the preferred growth process in this invention. Also, in the event that other growth processes are used, such as the MOCVD process, the aluminum oxide is also impervious to MOCVD process gasses (NH3, H2, TMGa, etc.). Reaction of silicon with process gasses usually results in etching of silicon (H2), formation of nitrides (NH3), or severe reaction and blistering (Ga precursors). Thus silicon substrate 10 is protected from damage caused by generally all growth process gasses by aluminum oxynitride layer 11.
- A layer 12 of aluminum nitride (AlN) is epitaxially grown on aluminum oxynitride layer 11. Since the material of layer 11 adjacent the upper surface has or may have a smaller y component, the crystal spacing is closer to the crystal spacing of the AlN grown on the surface. In some applications it may be convenient for layers 11 and 12 to be formed as a single layer in which the oxygen (y component) varies from a maximum content adjacent silicon substrate 10 to zero adjacent the upper surface. Also, layers 11 and 12 can be formed as two single continuous compositions (generally as illustrated) or one or both can be graded, in linear, stepwise or any similar schemes. Aluminum oxynitride layer 11 and aluminum nitride layer 12 form a buffer 15 for the further epitaxial growth of III-N materials. The aluminum nitride in buffer 15 is closer to matching the crystal formation and lattice spacing of III-N materials, such as GaN, so that III-N materials can be epitaxially grown directly on buffer 15.
- A III-N material, in this specific example gallium nitride (GaN) layer 16, is epitaxially grown on aluminum nitride layer 11 of buffer 15 preferably by an MBE process. Generally, GaN layer 16 will be in a range of 50 nm to 100 nm thick, although thicker or thinner layers can be grown. Because there will still be some strain in GaN layer 16, i.e. the crystal lattice junction with buffer 15 still produces some strain, a thinner layer 16 of GaN is preferred.
- A thin inter-layer of aluminum nitride (AlN) 18 is epitaxially grown on GaN layer 16 to further reduce the strain. Preferably, AlN inter-layer 18 is in a range of approximately 1 nm to approximately 10 nm thick but for certain applications thicker or thinner films can be grown. Also, AlN inter-layer 18 can be grown using either a low or a high temperature process. A second layer 19 of GaN is epitaxially grown on AlN inter-layer 18. A second inter-layer of AlN is grown on second GaN layer 19 and this process is repeated n times or until the strain in the upper GaN layer has been reduced to an acceptable level. Basically, the strain formed during the growth of the GaN is controlled by insertion of the thin inter-layers of AlN, each of which allows the following layer of GaN to be under compressive stress due to the pseudomorphic growth at the interface. Repeating the process (i.e. the alternating growth of layers 18 and 19) n times can be used to further reduce or engineer strain in the final GaN or III-N layer. Also, it should be noted that since each additional layer of GaN grown on the next inter-layer of AlN has less strain, each additional layer can be grown thicker if desired.
- Turning to
FIG. 2 , buffer 15 GaN layer 16/AlN inter-layer 18/GaN layer 19 (repeated n times) is illustrated with a III-N LED structure 20 formed thereon.Structure 20 is illustrated as a single layer for convenience but it should be understood that III-N LED structure 20 includes the growth of one or more typical layers, including for example, i-GaN, n-GaN, active layers such as InGaN/GaN, electron blocking layers, p-GaN, and other inter-layers used in the formation and performance of LED (especially photonic LED) devices. - Turning to
FIG. 3 , buffer 15, GaN layer 16/AlN inter-layer 18/GaN layer 19 (repeated n times) is illustrated with a HEMT structure 30 formed thereon. Structure 30 is illustrated as a single layer for convenience but it should be understood that HEMT structure 30 includes the growth of one or more typical layers, including for example, i-GaN, AlN, AlGaN, GaN, and other inter-layers used in the formation and performance of HEMT devices. - Thus, new and improved methods for the growth of III-N material and devices on a silicon substrate are disclosed. The new and improved methods for the III-N material include the growth of a substantially crystal lattice matching buffer on the silicon substrate and n repetitions of the growth of thin AlN inter-layers in the III-N material to further reduce or engineer the strain. Also, the buffer eliminates or greatly reduces the problem of possibly damaging the silicon substrate with process gasses. New and improved LED and/or HEMI structures can be substantially lattice matched and thermally matched by the new process on a silicon substrate.
- Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
- Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:
Claims (18)
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