US20140210430A1 - Maintaining the Resistor Divider Ratio During Start-up - Google Patents

Maintaining the Resistor Divider Ratio During Start-up Download PDF

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Publication number
US20140210430A1
US20140210430A1 US13/756,568 US201313756568A US2014210430A1 US 20140210430 A1 US20140210430 A1 US 20140210430A1 US 201313756568 A US201313756568 A US 201313756568A US 2014210430 A1 US2014210430 A1 US 2014210430A1
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Prior art keywords
voltage
circuit
access point
feed
voltage divider
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US13/756,568
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Ambreesh Bhattad
Ludmil Nikolov
Marinus Wilhelmus Kruiskamp
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Dialog Semiconductor GmbH
Dialog Semiconductor BV
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Dialog Semiconductor GmbH
Dialog Semiconductor BV
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Assigned to DIALOG SEMICONDUCTOR GMBH reassignment DIALOG SEMICONDUCTOR GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BHATTAD, AMBREESH, NIKOLOV, LUDMIL
Assigned to DIALOG SEMICONDUCTOR B.V. reassignment DIALOG SEMICONDUCTOR B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KRUISKAMP, MARINUS WILHELMUS
Publication of US20140210430A1 publication Critical patent/US20140210430A1/en
Priority to US14/794,135 priority Critical patent/US9372491B2/en
Abandoned legal-status Critical Current

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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H03G1/0094Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated using switched capacitors

Definitions

  • the present document relates to start-up processes of electronic circuits.
  • the present document relates to a method and system for maintaining a resistor voltage divider ratio during start-up using a dynamic circuit.
  • a principal object of the present disclosure is to achieve a correct determination of the output voltage of a circuit by a start-up comparator.
  • a further object of the disclosure is to avoid an output voltage drop (brown out) condition of the circuit as e.g. an LDO.
  • a further object of the disclosure is to avoid any violation of a start-up specification.
  • a further object of the disclosure is to achieve a clean start-up process.
  • a further object of the disclosure is to maintain a constant voltage divider ratio during start-up.
  • a further object of the disclosure is to use a dynamic circuit to manage the start-up process only during start-up.
  • the method disclosed comprises the following steps: (1) providing an electronic circuit comprising a feed-forward capacitor across a first feedback resistor of a resistive voltage divider and a start-up circuit, (2) avoiding modification of resistive voltage divider ratio caused by feed-forward capacitor during start-up phase, (3) monitoring output voltage and finish start-up-phase when desired output voltage of the electronic circuit is reached, and (4) processing normal operation after start-up phase is finished wherein feed-forward capacitor is connected across the feedback resistor of the resistive voltage divider after end of start-up phase.
  • a circuit to maintain a resistive voltage divider ratio during start-up of a LDO comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit
  • the circuit disclosed comprises, the feed-forward capacitor, wherein a first plate of the feed-forward capacitor is connected to an output port of the LDO voltage, said resistive voltage divider, being connected between the output port of the LDO and ground, comprising the feedback resistor having a resistance R 2 connected between the output port of the LDO and the voltage access point in-between the voltage divider having a fraction of the output voltage and further comprising a second resistor having a resistance R 1 , and a means to maintain a voltage level of the voltage access point across the feed-forward capacitor during start-up of the LDO.
  • the circuit disclosed firstly comprises: the feed-forward capacitor, wherein a first plate of the feed-forward capacitor is connected to an output port of the circuit and a second plate is connected to a voltage access point of the resistive voltage divider after the start-up phase of the electronic circuit is finished and said resistive voltage divider, being connected between an output port of the circuit and ground, comprising the feedback resistor having a resistance R 2 connected between the output port of the circuit and the voltage access point in-between the voltage divider having a fraction of the output voltage and further comprising a second resistor having a resistance R 1 .
  • the circuit comprises: a start-up comparator detecting if the start-up phase is finished by comparing a voltage representing the output voltage of the electronic circuit with a reference voltage and a means to maintain a voltage level of the voltage access point across the feed-forward capacitor during start-up of the circuit, wherein the means to maintain a voltage level of the voltage access point comprises switching means to connect or disconnect components of the circuit at beginning and end of the start-up process, wherein the switching means are activated by the start-up comparator.
  • FIG. 1 shows the basic elements of a second embodiment of a start-up circuit of the present disclosure applied to a LDO.
  • FIG. 2 illustrates a third embodiment of a start-up circuit of the present disclosure applied to a LDO.
  • FIG. 3 illustrates a flowchart of a method to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit.
  • FIG. 4 shows basic elements of an embodiment of a start-up circuit of the present disclosure applied for example to a LDO.
  • FIG. 4 shows basic elements of an embodiment of a start-up circuit of the present disclosure applied for example to a LDO.
  • the circuit comprises a port for output voltage 1 , a resistor voltage divider comprising a first resistor R 1 and a second controllable resistor R 2 , a start-up comparator 2 , a differential amplifier 3 , having as inputs a reference input voltage V ref and the voltage of a voltage access point divider-in 6 of the voltage divider R 1 /R 2 , representing the output voltage V out of the circuit as input, and a pass transistor 4 .
  • a current source I START provides an extra bias current to the differential amplifier 3 .
  • a switch 5 opens and hence deactivates the extra bias current I START when the start-up phase is finished.
  • the output of the start-up comparator 2 indicates that the circuit as e.g. a LDO is now ready for loading, i.e. the output of the comparator 2 triggers interrupting the extra bias current via switch 5 .
  • the feed-forward capacitor CFF modifies the resistor divider R 1 /R 2 ratio
  • the circuit of FIG. 4 may have the following disadvantages:
  • FIG. 1 shows a second embodiment of a start-up circuit of the present disclosure overcoming the disadvantages cited above.
  • the start-up circuit of FIG. 1 can also be applied for example to a LDO or to other circuits as amplifiers, etc. . . . .
  • the circuit disclosed comprises a port for output voltage 1 , a resistor voltage divider comprising in a preferred embodiment a first resistor R 1 and a second controllable resistor R 2 , a start-up comparator 2 , a differential amplifier 3 , having a reference input voltage V ref and the voltage of a voltage access point divider-in 6 of the voltage divider R 1 /R 2 , representing the output voltage V out of the circuit as input, a start-up buffer 5 , and a pass transistor 4 .
  • Each of the resistors R 1 and R 2 could be implemented by more than one resistor in series. Furthermore other resistive means than resistors could be implemented for the voltage divider as well, e.g. transistors (BJT or MOS) or diodes or FETS or MOS transistors connected as diodes.
  • resistors BJT or MOS
  • diodes FETS or MOS transistors connected as diodes.
  • the output of the start-up comparator 2 comparing voltage V ref with the voltage of the voltage access point divider-in 6 of the voltage divider R 1 /R 2 , indicates that the circuit, as e.g. a LDO, that a start-up phase is completed and is now ready for loading.
  • the comparator 2 controls the duration of a biasing current I buf for the start-up buffer 5 via switch S 3 .
  • Switch S 3 opens after start-up is completed, i.e. comparator 2 detects that voltage V ref is equal to divider-in 6 voltage, switch S 3 opens, biasing current I buf is interrupted and start-up time specification are met.
  • the circuit comprises a capacitor C ext , at the output which may be deployed externally or internally to the circuit, and a feed-forward capacitor C FF , which is connected only after start-up phase is completed in parallel to the controllable resistor R 2 .
  • Capacitor C FF is connected in parallel to the controllable resistor R 2 via switch S 2 , which is closed after the start-up phase is completed.
  • the comparator 2 detects when the start-up phase is completed and activates the closing of switch S 2 .
  • an optional current source I start providing an optional bias current to the differential amplifier 3 during start-up
  • the optional current source I start may be activated by a switch S 1 , which is used only if the optional extra bias current is to be provided during the startup.
  • Switch S 1 is also optional, it is not required if no extra bias current to the amplifier 3 is required during start-up of the circuit.
  • Switch S 2 connects, after it is closed when the start-up phase is finished, a voltage access point of the voltage divider R 1 /R 2 to a lower plate of the feed-forward capacitor C FF .
  • voltages VDD 1 and VDD 2 can be the same or different.
  • switch S 3 is closed and switch S 2 is open.
  • the open switch S 2 disconnects the feed-forward capacitor C FF from the resistor divider R 1 /R 2 but the start-up buffer 5 maintains the lower plate of feed-forward capacitor C FF to a same potential as the voltage access point divider_in 6 of the voltage divider R 1 /R 2 .
  • switch S 2 is closed and switch S 3 is opened. The start-up buffer is then shut down.
  • the start-up buffer 5 is a means to maintain the voltage level of the voltage access point divider_in 6 of the resistive voltage divider R 1 /R 2 on the feed-forward capacitor without impacting the voltage divider ratio. Other means could be used for this purpose as well. It has to be noted that the startup buffer 5 consumes power only during the start-up phase of the circuit. It does not add to the quiescent current consumption of the circuit.
  • FIG. 2 illustrates a third embodiment of a start-up circuit of the present disclosure applied to a LDO.
  • the circuit of FIG. 2 comprises also a differential amplifier 3 , a start-up comparator 2 , a pass transistor 4 , and a voltage divider R 1 /R 2 with a the voltage access point divider_in 6 .
  • the differential amplifier 3 may have a fixed or variable reference voltage as first input and the voltage of the voltage access point divider_in 6 as second input.
  • the start-up comparator 2 detects when the start-up phase is completed.
  • the resistors R 1 /R 2 may have a fixed resistance, or both a controllable resistance, or a combination thereof.
  • This implementation is characterized by having a start-up capacitor C FF2 connected during the start-up phase in series with the feed-forward capacitor C FF and in parallel to resistor R 1 , i.e. the resistive voltage divider R 1 /R 2 and the capacitor string C FF /C FF2 are in parallel, while a mid-point of the capacitor string is connected to the voltage access point divider_in 6 of the resistive divider R 1 /R 2 .
  • a key point of the circuit of FIG. 2 is that the start-up capacitor C FF2 is disconnected by switch S 4 at the end of the start-up phase, which is triggered by the start-up comparator 2 .
  • the start-up capacitor C EFF2 has a capacitance of C FF ⁇ R 2 /R 1 , i.e. the capacitive string has capacitances according to the resistances of the resistive voltage divider R 1 /R 2 .
  • C FF2 prevents any modification of the resistive voltage divider ratio by the feed-forward capacitor C FF during start-up.
  • a start-up comparator 2 monitors if the output voltage has reached a desired level and if the start-up phase is finished and the desired output level has been reached the start-up comparator activates that switch S 4 is opened and hence the additional capacitor C EFF2 is disconnected.
  • an optional current source I start providing an optional extra bias current to the differential amplifier 3 during start-up
  • the optional current source I start may be activated by a switch S 5 , which is used only if the optional extra bias current is to be provided during the startup to the differential amplifier 3 .
  • Switch S 5 is also optional, it is not required if no extra bias current to the amplifier 3 is required during start-up of the circuit.
  • FIG. 2 does not require, compared to the circuit of FIG. 1 , a start-up buffer amplifier 5 and switches S 2 and S 3 as shown in FIG. 1 , but it requires switch S 4 and the additional capacitor C EFF2 , which will be disconnected by switch S 4 after start-up is completed.
  • the circuit of FIG. 2 may comprise a capacitor C ext , at the output which may be deployed externally or internally to the circuit.
  • the reference input voltage V ref may be replaced by a variable voltage Vin or both resistors R 1 and R 2 are controllable.
  • resistors R 1 and R 2 are controllable.
  • FIG. 3 illustrates a flowchart of a method to maintain a resistive voltage divider ratio during start-up of an electronic circuit such as a LDO, amplifier, or buffer comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit.
  • an electronic circuit such as a LDO, amplifier, or buffer comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit.
  • the circuit and the method disclosed are applicable to any circuit using a resistive voltage divider and a feed-forward capacitor.
  • Step 30 of the method of FIG. 3 illustrates the provision of e.g. a LDO or any other suitable circuit as e.g. an amplifier comprising a feed-forward capacitor across a first feedback resistor R 2 of a resistive voltage divider and a start-up circuit.
  • Step 31 depicts avoiding modification of resistive voltage divider ratio caused by feed-forward capacitor during start-up phase.
  • Step 32 illustrates monitoring output voltage and finish start-up-phase when desired output voltage of the electronic circuit is reached.
  • Step 33 shows processing normal operation after start-up phase is finished wherein feed-forward capacitor is connected across the feedback resistor of the resistive voltage after end of start-up phase.

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Abstract

Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. Embodiments of the disclosure presented comprise using a start-up buffer or a start-up capacitor during the start-up phase.

Description

    BACKGROUND
  • (1) Technical Field
  • The present document relates to start-up processes of electronic circuits. In particular, the present document relates to a method and system for maintaining a resistor voltage divider ratio during start-up using a dynamic circuit.
  • (2) Background
  • Prior art implementations of circuits as e.g. a low-dropout (LDO) voltage regulator using a feed-forward capacitor in parallel to a feedback resistor of a resistor voltage divider have the disadvantage that a voltage divider ratio is impacted by the feed-forward capacitor during start-up phase and clean start-up specification may not always being met.
  • It is a challenge for engineers to design start-up processes of circuits as e.g. an LDO without the disadvantage cited above.
  • SUMMARY
  • A principal object of the present disclosure is to achieve a correct determination of the output voltage of a circuit by a start-up comparator.
  • A further object of the disclosure is to avoid an output voltage drop (brown out) condition of the circuit as e.g. an LDO.
  • A further object of the disclosure is to avoid any violation of a start-up specification.
  • A further object of the disclosure is to achieve a clean start-up process.
  • A further object of the disclosure is to maintain a constant voltage divider ratio during start-up.
  • A further object of the disclosure is to use a dynamic circuit to manage the start-up process only during start-up.
  • In accordance with the objects of this disclosure a method to maintain a resistive voltage divider ratio during start-up of any electronic circuit comprising a feed-forward capacitor across a feedback resistor of a resistive voltage divider using a dynamic start-up circuit has been disclosed. The method disclosed comprises the following steps: (1) providing an electronic circuit comprising a feed-forward capacitor across a first feedback resistor of a resistive voltage divider and a start-up circuit, (2) avoiding modification of resistive voltage divider ratio caused by feed-forward capacitor during start-up phase, (3) monitoring output voltage and finish start-up-phase when desired output voltage of the electronic circuit is reached, and (4) processing normal operation after start-up phase is finished wherein feed-forward capacitor is connected across the feedback resistor of the resistive voltage divider after end of start-up phase.
  • In accordance with the objects of this disclosure a circuit to maintain a resistive voltage divider ratio during start-up of a LDO comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit has been achieved. The circuit disclosed comprises, the feed-forward capacitor, wherein a first plate of the feed-forward capacitor is connected to an output port of the LDO voltage, said resistive voltage divider, being connected between the output port of the LDO and ground, comprising the feedback resistor having a resistance R2 connected between the output port of the LDO and the voltage access point in-between the voltage divider having a fraction of the output voltage and further comprising a second resistor having a resistance R1, and a means to maintain a voltage level of the voltage access point across the feed-forward capacitor during start-up of the LDO.
  • In accordance with the objects of this disclosure a circuit to maintain a resistive voltage divider ratio during start-up of any electronic circuit comprising a feed-forward capacitor across a feedback resistor and a resistive voltage divider using a dynamic start-up circuit, has been disclosed. The circuit disclosed firstly comprises: the feed-forward capacitor, wherein a first plate of the feed-forward capacitor is connected to an output port of the circuit and a second plate is connected to a voltage access point of the resistive voltage divider after the start-up phase of the electronic circuit is finished and said resistive voltage divider, being connected between an output port of the circuit and ground, comprising the feedback resistor having a resistance R2 connected between the output port of the circuit and the voltage access point in-between the voltage divider having a fraction of the output voltage and further comprising a second resistor having a resistance R1. Furthermore the circuit comprises: a start-up comparator detecting if the start-up phase is finished by comparing a voltage representing the output voltage of the electronic circuit with a reference voltage and a means to maintain a voltage level of the voltage access point across the feed-forward capacitor during start-up of the circuit, wherein the means to maintain a voltage level of the voltage access point comprises switching means to connect or disconnect components of the circuit at beginning and end of the start-up process, wherein the switching means are activated by the start-up comparator.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the accompanying drawings forming a material part of this description, there is shown:
  • FIG. 1 shows the basic elements of a second embodiment of a start-up circuit of the present disclosure applied to a LDO.
  • FIG. 2 illustrates a third embodiment of a start-up circuit of the present disclosure applied to a LDO.
  • FIG. 3 illustrates a flowchart of a method to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit.
  • FIG. 4 shows basic elements of an embodiment of a start-up circuit of the present disclosure applied for example to a LDO.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Methods and circuits to achieve fast and clean start-up process of an electronic circuit as e.g. a LDO or an amplifier using a feed-forward capacitor and a resistive voltage divider or another means to represent an output voltage of the electronic circuit are disclosed. It has to be noted that the methods and circuits disclosed can be applied to any other circuits using a feed-forward capacitor and a resistive voltage divider.
  • FIG. 4 shows basic elements of an embodiment of a start-up circuit of the present disclosure applied for example to a LDO. The circuit comprises a port for output voltage 1, a resistor voltage divider comprising a first resistor R1 and a second controllable resistor R2, a start-up comparator 2, a differential amplifier 3, having as inputs a reference input voltage Vref and the voltage of a voltage access point divider-in 6 of the voltage divider R1/R2, representing the output voltage Vout of the circuit as input, and a pass transistor 4. During the start-up phase a current source ISTART provides an extra bias current to the differential amplifier 3. A switch 5 opens and hence deactivates the extra bias current ISTART when the start-up phase is finished.
  • The output of the start-up comparator 2 indicates that the circuit as e.g. a LDO is now ready for loading, i.e. the output of the comparator 2 triggers interrupting the extra bias current via switch 5. The feed-forward capacitor CFF modifies the resistor divider R1/R2 ratio
  • The circuit of FIG. 4 may have the following disadvantages:
      • 1. Longer startup time
      • 2. Startup specifications may not being met
      • 3. Incorrect decision by startup comparator about the output voltage which may impact system functionality if this output is used to load the output of the circuit
      • 4. Drop in voltage of the LDO (brown out).
  • FIG. 1 shows a second embodiment of a start-up circuit of the present disclosure overcoming the disadvantages cited above. The start-up circuit of FIG. 1 can also be applied for example to a LDO or to other circuits as amplifiers, etc. . . . .
  • The circuit disclosed comprises a port for output voltage 1, a resistor voltage divider comprising in a preferred embodiment a first resistor R1 and a second controllable resistor R2, a start-up comparator 2, a differential amplifier 3, having a reference input voltage Vref and the voltage of a voltage access point divider-in 6 of the voltage divider R1/R2, representing the output voltage Vout of the circuit as input, a start-up buffer 5, and a pass transistor 4.
  • Each of the resistors R1 and R2 could be implemented by more than one resistor in series. Furthermore other resistive means than resistors could be implemented for the voltage divider as well, e.g. transistors (BJT or MOS) or diodes or FETS or MOS transistors connected as diodes.
  • The output of the start-up comparator 2, comparing voltage Vref with the voltage of the voltage access point divider-in 6 of the voltage divider R1/R2, indicates that the circuit, as e.g. a LDO, that a start-up phase is completed and is now ready for loading. The comparator 2 controls the duration of a biasing current Ibuf for the start-up buffer 5 via switch S3. Switch S3 opens after start-up is completed, i.e. comparator 2 detects that voltage Vref is equal to divider-in 6 voltage, switch S3 opens, biasing current Ibuf is interrupted and start-up time specification are met.
  • Furthermore the circuit comprises a capacitor Cext, at the output which may be deployed externally or internally to the circuit, and a feed-forward capacitor CFF, which is connected only after start-up phase is completed in parallel to the controllable resistor R2. Capacitor CFF is connected in parallel to the controllable resistor R2 via switch S2, which is closed after the start-up phase is completed. The comparator 2 detects when the start-up phase is completed and activates the closing of switch S2.
  • Furthermore there may be an optional current source Istart providing an optional bias current to the differential amplifier 3 during start-up, wherein the optional current source Istart may be activated by a switch S1, which is used only if the optional extra bias current is to be provided during the startup. Switch S1 is also optional, it is not required if no extra bias current to the amplifier 3 is required during start-up of the circuit. Switch S2 connects, after it is closed when the start-up phase is finished, a voltage access point of the voltage divider R1/R2 to a lower plate of the feed-forward capacitor CFF.
  • Furthermore it should be noted that voltages VDD1 and VDD2 can be the same or different.
  • During startup the switch S3 is closed and switch S2 is open. The open switch S2 disconnects the feed-forward capacitor CFF from the resistor divider R1/R2 but the start-up buffer 5 maintains the lower plate of feed-forward capacitor CFF to a same potential as the voltage access point divider_in 6 of the voltage divider R1/R2. Once the output voltage Vout reaches the desired voltage, switch S2 is closed and switch S3 is opened. The start-up buffer is then shut down.
  • The start-up buffer 5 is a means to maintain the voltage level of the voltage access point divider_in 6 of the resistive voltage divider R1/R2 on the feed-forward capacitor without impacting the voltage divider ratio. Other means could be used for this purpose as well. It has to be noted that the startup buffer 5 consumes power only during the start-up phase of the circuit. It does not add to the quiescent current consumption of the circuit.
  • FIG. 2 illustrates a third embodiment of a start-up circuit of the present disclosure applied to a LDO. Similarly to the circuit shown in FIG. 1 the circuit of FIG. 2 comprises also a differential amplifier 3, a start-up comparator 2, a pass transistor 4, and a voltage divider R1/R2 with a the voltage access point divider_in 6. The differential amplifier 3 may have a fixed or variable reference voltage as first input and the voltage of the voltage access point divider_in 6 as second input. As shown in FIG. 1 the start-up comparator 2 detects when the start-up phase is completed. The resistors R1/R2 may have a fixed resistance, or both a controllable resistance, or a combination thereof.
  • This implementation is characterized by having a start-up capacitor CFF2 connected during the start-up phase in series with the feed-forward capacitor CFF and in parallel to resistor R1, i.e. the resistive voltage divider R1/R2 and the capacitor string CFF/CFF2 are in parallel, while a mid-point of the capacitor string is connected to the voltage access point divider_in 6 of the resistive divider R1/R2.
  • A key point of the circuit of FIG. 2 is that the start-up capacitor CFF2 is disconnected by switch S4 at the end of the start-up phase, which is triggered by the start-up comparator 2.
  • The start-up capacitor CEFF2 has a capacitance of CFF×R2/R1, i.e. the capacitive string has capacitances according to the resistances of the resistive voltage divider R1/R2. Thus CFF2 prevents any modification of the resistive voltage divider ratio by the feed-forward capacitor CFF during start-up.
  • Similarly to the circuit shown in FIG. 1 a start-up comparator 2 monitors if the output voltage has reached a desired level and if the start-up phase is finished and the desired output level has been reached the start-up comparator activates that switch S4 is opened and hence the additional capacitor CEFF2 is disconnected.
  • Furthermore there may be an optional current source Istart providing an optional extra bias current to the differential amplifier 3 during start-up, wherein the optional current source Istart may be activated by a switch S5, which is used only if the optional extra bias current is to be provided during the startup to the differential amplifier 3. Switch S5 is also optional, it is not required if no extra bias current to the amplifier 3 is required during start-up of the circuit.
  • The embodiment of FIG. 2 does not require, compared to the circuit of FIG. 1, a start-up buffer amplifier 5 and switches S2 and S3 as shown in FIG. 1, but it requires switch S4 and the additional capacitor CEFF2, which will be disconnected by switch S4 after start-up is completed.
  • Similarly to the circuit of FIG. 1 the circuit of FIG. 2 may comprise a capacitor Cext, at the output which may be deployed externally or internally to the circuit.
  • In alternative embodiments of the circuits of FIG. 1 or FIG. 2 the reference input voltage Vref, as shown in FIG. 1 and FIG. 2, may be replaced by a variable voltage Vin or both resistors R1 and R2 are controllable. Alternatively it would be possible to have a fixed resistance for R2 and a controllable resistance for R1.
  • FIG. 3 illustrates a flowchart of a method to maintain a resistive voltage divider ratio during start-up of an electronic circuit such as a LDO, amplifier, or buffer comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit. As already mentioned above, the circuit and the method disclosed are applicable to any circuit using a resistive voltage divider and a feed-forward capacitor. Step 30 of the method of FIG. 3 illustrates the provision of e.g. a LDO or any other suitable circuit as e.g. an amplifier comprising a feed-forward capacitor across a first feedback resistor R2 of a resistive voltage divider and a start-up circuit. Step 31 depicts avoiding modification of resistive voltage divider ratio caused by feed-forward capacitor during start-up phase. Step 32 illustrates monitoring output voltage and finish start-up-phase when desired output voltage of the electronic circuit is reached. Step 33 shows processing normal operation after start-up phase is finished wherein feed-forward capacitor is connected across the feedback resistor of the resistive voltage after end of start-up phase.
  • While the disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.

Claims (24)

What is claimed is:
1. A method to maintain a resistive voltage divider ratio during start-up of any electronic circuit comprising a feed-forward capacitor across a feedback resistor of a resistive voltage divider using a dynamic start-up circuit, comprising the following steps:
(1) providing an electronic circuit comprising a feed-forward capacitor across a first feedback resistor of a resistive voltage divider and a start-up circuit;
(2) avoiding modification of resistive voltage divider ratio caused by feed-forward capacitor during start-up phase;
(3) monitoring output voltage and finish start-up-phase when desired output voltage of the electronic circuit is reached; and
(4) processing normal operation after start-up phase is finished wherein feed-forward capacitor is connected across the feedback resistor of the resistive voltage divider after end of start-up phase.
2. The method of claim 1 wherein said electronic circuit is a LDO.
3. The method of claim 1 wherein said electronic circuit is an amplifier.
4. The method of claim 1 wherein a start-up comparator detects if a desired output voltage is reached and hence the start-up phase is finished.
5. The method of claim 4 wherein the start-up comparator detects if the start-up phase is finished by comparing a voltage representing the output voltage of the electronic circuit with a reference voltage.
6. The method of claim 5 wherein the reference voltage is a variable voltage.
7. The method of claim 1 wherein said modification of resistive voltage divider ratio is avoided by disconnecting the feed-forward capacitor from a voltage access point of the resistive voltage divider during start-up phase only, wherein the voltage of the voltage access point of the resistive voltage divider represents the output voltage of the electronic circuit.
8. The method of claim 1 wherein a voltage level of the voltage access point of the resistive voltage divider is maintained on the feed-forward capacitor by a start-up buffer during start-up phase, wherein the voltage of the voltage access point of the resistive voltage divider represents the output voltage of the electronic circuit and wherein a bias current of the buffer amplifier is disconnected at the end of the start-up phase, wherein an input of the start-up buffer is connected to the voltage access point of the voltage divider.
9. The method of claim 8 wherein a start-up comparator detects if a desired output voltage of the electronic circuit is reached and, in this case, initiates disconnecting the bias current of the start-up buffer and connecting the feed-forward capacitor directly to the voltage access point of the resistive voltage divider.
10. The method of claim 1 wherein said modification of resistive voltage divider ratio is prevented by connecting a start-up capacitor across a second resistor of the resistive voltage divider during the start-up phase only, wherein the start-up capacitor has a capacitance of CFF×R2/R1, wherein CFF is a capacitance of the feed-forward capacitor, R1 is a resistance of the part of the voltage divider between access point and ground and R2 is a resistance of the part of the voltage diver between output voltage and access point.
11. The method of claim 10 wherein a start-up comparator detects if a desired output voltage is reached and, in this case, disconnects the start-up capacitor from the voltage access point of the voltage divider.
12. The method of claim 10 wherein the start-up capacitor has a capacitance of CFF×R2/R1, wherein CFF is a capacitance of the feed-forward capacitor, R1 is a resistance of a part of the voltage divider between a voltage access point of the resistive voltage divider and ground and R2 is a resistance of the part of the voltage divider between output voltage and access point.
13. The method of claim 1 wherein said first feedback resistor is a part of the resistive voltage divider.
14. A circuit to maintain a resistive voltage divider ratio during start-up of any electronic circuit comprising a feed-forward capacitor across a feedback resistor and a resistive voltage divider using a dynamic start-up circuit, comprising:
the feed-forward capacitor, wherein a first plate of the feed-forward capacitor is connected to an output port of the circuit and a second plate is connected to a voltage access point of the resistive voltage divider after the start-up phase of the electronic circuit is finished;
said resistive voltage divider, being connected between an output port of the circuit and ground, comprising the feedback resistor having a resistance R2 connected between the output port of the circuit and the voltage access point in-between the voltage divider having a fraction of the output voltage and further comprising a second resistor having a resistance R1;
a start-up comparator detecting if the start-up phase is finished by comparing a voltage representing the output voltage of the electronic circuit with a reference voltage;
a means to maintain a voltage level of the voltage access point across the feed-forward capacitor during start-up of the circuit, wherein the means to maintain a voltage level of the voltage access point comprises switching means to connect or disconnect components of the circuit at beginning and end of the start-up process, wherein the switching means are activated by the start-up comparator.
15. The circuit of claim 14 wherein said circuit is an LDO.
16. The circuit of claim 14 wherein said circuit is an amplifier.
17. The circuit of claim 14 wherein the end of the start-up phase is reached when the voltage of the voltage access point equals a reference voltage.
18. The circuit of claim 17 wherein the reference voltage is a fixed voltage.
19. The circuit of claim 17 wherein the reference voltage is a variable voltage.
20. The circuit of claim 14 wherein said means to maintain the voltage level further comprises a buffer amplifier wherein the start-up comparator initiates both connecting a second plate of the feed-forward capacitor to the voltage access point and disconnecting a bias current of the buffer amplifier at the end of the start-up phase using said switching means, wherein an input of the start-up buffer is connected to the voltage access point of the voltage divider.
21. The circuit of claim 20 wherein said switching means comprises a first switching means connecting the second plate of the feed-forward capacitor to the voltage access point at the end of the start-up phase and a second switching means disconnecting the bias current of the buffer amplifier.
22. The circuit of claim 21 wherein said switching means further comprises a third switching means providing an extra bias current to a differential amplifier of the circuit during start-up only.
23. The circuit of claim 14 wherein said means to maintain the voltage level comprises a second capacitor connected between the voltage access point and ground.
24. The circuit of claim 23 wherein the second capacitor has a capacitance C=CFF×R2/R1, wherein CFF is the capacitance of the feed-forward capacitor and wherein the start-up comparator initiates disconnecting the second capacitor from the voltage access point via a switching means at the end of the start-up phase.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150061622A1 (en) * 2013-09-05 2015-03-05 Dialog Semiconductor Gmbh Method and Apparatus for Limiting Startup Inrush Current for Low Dropout Regulator
JP2016143341A (en) * 2015-02-04 2016-08-08 エスアイアイ・セミコンダクタ株式会社 Voltage regulator
US20160239038A1 (en) * 2015-02-16 2016-08-18 Freescale Semiconductor, Inc. Supply-side voltage regulator
US20180259987A1 (en) * 2017-03-09 2018-09-13 Macronix International Co., Ltd. Low dropout regulating device and operating method thereof
US10331152B2 (en) * 2017-04-07 2019-06-25 Dialog Semiconductor (Uk) Limited Quiescent current control in voltage regulators
DE102019202853B3 (en) * 2019-03-01 2020-06-18 Dialog Semiconductor (Uk) Limited Linear voltage regulator and method for voltage regulation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019047173A (en) 2017-08-30 2019-03-22 ルネサスエレクトロニクス株式会社 Semiconductor device, signal processing system, and signal processing method
US11296596B1 (en) * 2021-02-18 2022-04-05 Nxp B.V. Noise reduction circuit for voltage regulator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110254521A1 (en) * 2010-04-14 2011-10-20 Iacob Radu H Floating-gate programmable low-dropout regulator and methods therefor
US20130002220A1 (en) * 2011-06-29 2013-01-03 Mitsumi Electric Co., Ltd. Semiconductor integrated circuit for regulator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208124B1 (en) * 1999-06-04 2001-03-27 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US7872454B2 (en) 2003-08-21 2011-01-18 Marvell World Trade Ltd. Digital low dropout regulator
US7122996B1 (en) * 2004-06-01 2006-10-17 National Semiconductor Corporation Voltage regulator circuit
FR2872305B1 (en) 2004-06-24 2006-09-22 St Microelectronics Sa METHOD FOR CONTROLLING THE OPERATION OF A LOW VOLTAGE DROP REGULATOR AND CORRESPONDING INTEGRATED CIRCUIT
US7531996B2 (en) 2006-11-21 2009-05-12 System General Corp. Low dropout regulator with wide input voltage range
US8222881B2 (en) * 2010-01-22 2012-07-17 Texas Instruments Incorporated Low-power feedback and method for DC-DC converters and voltage regulators for energy harvesters
US8188719B2 (en) * 2010-05-28 2012-05-29 Seiko Instruments Inc. Voltage regulator
US8710811B2 (en) * 2012-01-03 2014-04-29 Nan Ya Technology Corporation Voltage regulator with improved voltage regulator response and reduced voltage drop

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110254521A1 (en) * 2010-04-14 2011-10-20 Iacob Radu H Floating-gate programmable low-dropout regulator and methods therefor
US20130002220A1 (en) * 2011-06-29 2013-01-03 Mitsumi Electric Co., Ltd. Semiconductor integrated circuit for regulator

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150061622A1 (en) * 2013-09-05 2015-03-05 Dialog Semiconductor Gmbh Method and Apparatus for Limiting Startup Inrush Current for Low Dropout Regulator
US9454164B2 (en) * 2013-09-05 2016-09-27 Dialog Semiconductor Gmbh Method and apparatus for limiting startup inrush current for low dropout regulator
JP2016143341A (en) * 2015-02-04 2016-08-08 エスアイアイ・セミコンダクタ株式会社 Voltage regulator
US20160239038A1 (en) * 2015-02-16 2016-08-18 Freescale Semiconductor, Inc. Supply-side voltage regulator
US9588540B2 (en) * 2015-09-10 2017-03-07 Freescale Semiconductor, Inc. Supply-side voltage regulator
US20180259987A1 (en) * 2017-03-09 2018-09-13 Macronix International Co., Ltd. Low dropout regulating device and operating method thereof
US10768646B2 (en) * 2017-03-09 2020-09-08 Macronix International Co., Ltd. Low dropout regulating device and operating method thereof
US10331152B2 (en) * 2017-04-07 2019-06-25 Dialog Semiconductor (Uk) Limited Quiescent current control in voltage regulators
DE102019202853B3 (en) * 2019-03-01 2020-06-18 Dialog Semiconductor (Uk) Limited Linear voltage regulator and method for voltage regulation
US11625055B2 (en) 2019-03-01 2023-04-11 Dialog Semiconductor (Uk) Limited Programmable two-way fast DVC control circuit

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