US20140210029A1 - Backside Illumination Image Sensor Chips and Methods for Forming the Same - Google Patents
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- US20140210029A1 US20140210029A1 US13/754,612 US201313754612A US2014210029A1 US 20140210029 A1 US20140210029 A1 US 20140210029A1 US 201313754612 A US201313754612 A US 201313754612A US 2014210029 A1 US2014210029 A1 US 2014210029A1
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Definitions
- Backside Illumination (BSI) image sensor chips are replacing front side illumination sensor chips for their higher efficiency in capturing photons.
- image sensors such as photo diodes, and logic circuits are formed on a silicon substrate of a wafer, followed by the formation of an interconnect structure on a front side of the silicon chip.
- the image sensors in the BSI image sensor chips generate electrical signals in response to the stimulation of photons.
- FIGS. 1A through 3D illustrate top views and a cross-sectional views of intermediate stages in the formation of a Backside Illumination (BSI) image sensor wafer in accordance with some exemplary embodiments; and
- BSI Backside Illumination
- FIG. 4 illustrates a top view of a BSI image sensor chip sawed from the BSI image sensor wafer in accordance with some embodiments.
- a Backside Illumination (BSI) image sensor chip and the method of forming the same are provided in accordance with various exemplary embodiments.
- the intermediate stages of forming the image sensor chip are illustrated.
- the variations of the image sensor wafer and the image sensor chip are discussed.
- like reference numbers are used to designate like elements.
- image sensors and logic circuits may be formed on a silicon substrate of a wafer (not shown), followed by the formation of an interconnect structure on a front side of the silicon chip.
- the interconnect structure includes a plurality of metal layers including bottom metal layer M 1 through top metal layer Mtop.
- the wafer may then be flipped over.
- a backside grinding may then be performed on the silicon substrate from the backside of the silicon substrate.
- a buffer oxide layer may be formed over the back surface of the remaining silicon substrate, and the silicon substrate in the wafer is etched. In the etching of the silicon substrate, the portions of the silicon substrate in the scribe lines are removed. The remaining silicon substrate in each of the image sensor chip is thus isolated from the portions of the silicon substrate in other image sensor chips.
- trenches are formed in the silicon substrate. Openings are then formed inside the trench, wherein some portions of the STI pad and the underlying portions of interlayer dielectric (ILD) are etched, so that metal pads in the bottom metal layer M 1 are exposed. Metal pads are then formed in the openings to electrically couple to the metal pads in metal layer M 1 .
- the metal pad may be used for bonding to the BSI chip.
- the trench in the silicon substrate forms a grid, and the remaining portions of the silicon substrate are fully isolated from each other. This generates a stress in the remaining portions of the silicon substrate, which stress may be un-balanced, and adversely affects the devices in the silicon substrate.
- Such problems may be addressed by the exemplary embodiments shown in FIGS. 1 through 4 .
- FIG. 1 illustrates a top view of wafer 100 in accordance with some exemplary embodiments.
- Wafer 100 includes chips 10 and the adjoining scribe lines 12 .
- seal ring 14 is formed, wherein the outer boundaries of the seal rings 14 define the outer boundaries of chips 10 .
- the illustrated seal rings 14 are the outmost seal rings among the plurality of seal rings in each of chips 10 .
- Scribe lines 12 are portions of the wafer 100 that are between seal rings 14 of neighboring chips 10 . Accordingly, each of the scribe lines 12 is between and adjoining two rows (or two columns) of chips 10 , and may be between and adjoining two rows (or two columns) of seal rings 14 .
- Within-Scribe-Line (WSL) features 16 may be formed in scribe lines 12 .
- WSL features 16 are schematically illustrated, and may include, for example, test devices that are used for monitoring the manufacturing process of wafer 100 , Scribe-line Primary Mark (SPM), overlay marks, or the like.
- SPM Scribe-line Primary Mark
- FIG. 1B illustrates a cross-sectional view of a portion of wafer 100 shown in FIG. 1A , wherein the cross-sectional view is obtained from the plane crossing line 1 B- 1 B in FIG. 1A .
- wafer 100 is attached to carrier 104 (which may be a glass carrier), for example, through adhesive 102 .
- Wafer 100 includes substrate 20 , which expands throughout the entirety of wafer 100 and extends into chips 10 and scribe lines 12 .
- Substrate 20 is a semiconductor substrate comprising a semiconductor material such as silicon, silicon carbon, a III-V compound semiconductor, germanium, or the like.
- Interconnect structure 22 is formed on a side (referred to as a front side hereinafter) of semiconductor substrate 20 .
- Interconnect structure 22 includes metal lines 30 and vias 32 formed in dielectric layers 24 .
- Dielectric layers 24 may have low dielectric constants (k values), which may be lower than about 3.5, or lower than about 3.0, for example.
- Passivation layer(s) 26 are also included in chips 10 , wherein passivation layers 26 may have non-low-k dielectric constants greater than 3.9.
- chips 10 are image sensor chips, which may be Backside Illumination (BSI) image sensor chips.
- Image sensor array 34 is formed in each of chips 10 , and includes image sensors 36 allocated as a plurality of rows and columns. Image sensors 36 may be photo diodes, photo transistors, or the like, which are capable of converting photons into electrical signals.
- Each of chips 10 may include logic circuits 38 , which are used to process electrical signals, for example, the signals generated by image sensor array 34 .
- seal rings 14 may extend throughout all of low-k dielectric layers 24 , and may, or may not, extend into passivation layer(s) 26 . Seal rings 14 may also include portions (not shown) contacting substrate 20 . Seal rings 14 form solid metal rings adjacent to the peripheral region of the respective chips 10 , so that after wafer 100 is sawed into dies, moisture and detrimental chemicals may not penetrate into chips 10 and reach the devices and interconnect structure located within seal rings 14 .
- WSL feature 16 is schematically illustrated, and may be formed to extend into one or more (in any combination) of substrate 20 and interconnect structure 22 . Furthermore, WSL features 16 may include portions on a side (the backside) of substrate 20 opposite to the front side in which interconnect structure 22 is located. The backside portions of WSL features 16 are illustrated as being a portion over substrate 20 .
- Substrate 20 is thinned, for example, to a thickness of several microns.
- BARC Bottom Anti-Reflective Coating
- BARC 42 comprises silicon oxynitride (SiON), although other materials may be used.
- Buffer oxide layer 44 is formed over BARC 42 .
- Buffer oxide layer 44 may be formed of silicon oxide, for example, although other dielectric materials may be used.
- Buffer oxide layer 44 may be formed using Plasma Enhance Chemical Vapor Deposition (PECVD), and hence is sometimes referred to as a Plasma enhanced (PE) oxide, although other formation methods may be used.
- PECVD Plasma Enhance Chemical Vapor Deposition
- metal grid 46 and metal shield 48 are formed over oxide layer 44 in accordance with some embodiments.
- Metal grid 46 may have a top-view shape of a grid, with the openings in the grid aligned to image sensors 36 .
- Metal shield 48 overlaps logic circuit 38 to prevent the devices (such as transistors, diodes, etc.) in logic circuit 38 from being adversely affected by light.
- Metal grid 46 and metal shield 48 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, aluminum copper, alloys thereof, and/or multi-layers thereof.
- Metal grid 46 and metal shield 48 may be formed simultaneously, and hence include same materials.
- FIGS. 2A and 2B are a top view and a cross-sectional view, respectively.
- the cross-sectional view in FIG. 2B is obtained from the plane crossing line 2 B- 2 B in FIG. 2A .
- the etching is performed using Shallow Trench Isolation (STI) region 50 as an etch stop layer. Accordingly, after the etching, STI region 50 is exposed. Trench 52 is formed in substrate 20 as a result of the etching.
- STI Shallow Trench Isolation
- the etching results in substrate 20 to be patterned into a plurality of in-chip substrate portions 20 A (also referred to as bulk portions), wherein each of in-chip substrate portions 20 A is located within the boundaries of the respective chips 10 . Furthermore, some outer portions of substrate 20 that are within chips 10 and close to the boundaries of chips 10 may also be removed by the etching step, so that edges 21 of in-chip substrate portions 20 A are not aligned to the outer boundaries (defined by seal rings 14 ) of chips 10 . Edges 21 are also inside the respective chips 10 in the top view. In some exemplary embodiments, distance D 1 between the edges 21 and the respective edges of chip 10 is greater than about 100 ⁇ m.
- the remaining portions of substrate 20 also include substrate portions 20 B, which are the portions at which WSL features 16 are formed.
- substrate portions 20 also include substrate portions 20 C, wherein each of substrate portions 20 C interconnects two substrate portions 20 A.
- Substrate portions 20 C have lengths significantly greater than their widths, and hence are also referred to as substrate strips 20 C hereinafter.
- Each of substrate portions 20 C may cross an entirety of a scribe line 12 , and may extend into two neighboring chips 10 .
- Through substrate portions 20 C all substrate portions 20 A in wafer 100 may be interconnected, although substrate portions 20 A themselves are disconnected from each other.
- each edge 21 of portion 20 A is connected to one, two, three, or more substrate strips 20 C. In the illustrated embodiments, there are two substrate strips 20 C connected to the opposite edges of the same edge 21 , with a portion 20 B in between.
- Width W 1 of substrate strips 20 C may be between about 20 ⁇ m and about 80 ⁇ m. In some embodiments, width W 1 is between about 0.5 percent and about 2.0 percent of length L 1 of the respective side of the corresponding substrate portion 20 A. Substrate strips 20 C may have longitudinal directions perpendicular to the respective edge 21 it connects to. Since each portion 20 A may include four sides, substrate strips 20 C are formed to connect to four sides of portion 20 A. In some embodiments, substrate portion 20 B is disconnected from substrate portions 20 A and substrate strips 20 C.
- Substrate portions 20 A may have adverse stress after the substrate etching step, which adverse stress affects the performance of the devices in chip 10 .
- substrate strips 20 C interconnecting neighboring substrate portions 20 A of neighboring chips 10 With substrate strips 20 C interconnecting neighboring substrate portions 20 A of neighboring chips 10 , a force is provided to push or pull neighboring substrate portions 20 A, so that the adverse stress is at least reduced, or substantially eliminated.
- FIGS. 3A through 3D the remaining features of wafer 100 are formed.
- FIGS. 3B , 3 C, and 3 D illustrate the cross-sectional views obtained from the planes crossing lines 3 B- 3 B, 3 C- 3 C, and 3 D- 3 D, respectively, in FIG. 3A .
- FIGS. 3A and 3B illustrate bond pads 54 formed in chips 10 . Bond pads 54 penetrate through STI region 50 , and are electrically connected to the metal layers on the front side of substrate 20 .
- the formation process includes forming openings 56 in STI region 50 , wherein openings 56 are further formed in trenches 52 that are formed due to the removal of substrate 20 .
- Dielectric layer 53 is formed to cover sidewalls of trenches 52 and openings 56 . Some horizontal portions of dielectric layer 53 are removed to expose one of metal pads 30 , which may be in a metal layer such as the bottom metal layer (M 1 ) or another metal layer. A conductive layer (not shown) is then formed to extend into openings 56 , and is then patterned. The remaining portions of the conductive layer form bond pads 54 , which extend into openings 56 . Bond pads 54 are electrically coupled to interconnect structure 22 , and may be electrically coupled to image sensor array 34 and/or logic circuit 38 .
- the remaining components of BSI chip 10 including dielectric layer 60 , color filters 62 , micro-lenses 64 , and the like, are formed.
- Dielectric layer 60 may fill the gaps between metal grid 46 and metal shield 48 , so that a flat top surface may be formed for the subsequent formation of color filters 62 and micro-lenses 64 .
- Each of color filters 62 and micro-lenses 64 may be aligned to one of image sensors 36 .
- the cross-sectional view in FIG. 3B is obtained from the plane crossing bond pads 54 and portion 20 B of substrate 20 , and hence bond pads 54 and portion 20 B are illustrated.
- FIG. 3C is obtained from the plane in which substrate strip 20 C is located, and hence substrate portions 20 A and 20 C are both illustrated in the same view.
- the cross-sectional view in FIG. 3D is obtained from the plane in which no bond pads 54 and substrate portion 20 C exist, and hence trench 52 is shown as extending throughout scribe line 12 , and extending into neighboring chips 10 .
- FIG. 4 illustrates a top view of one of dies 200 , which includes chip 10 therein.
- the illustrated die 200 besides the portion of chip 10 shown in FIG. 3A , may also include residue portions of scribe lines 12 shown in FIG. 3A .
- each of substrate strips 20 C is sawed, and each of substrate strips 12 has a portion remaining in die 200 .
- Substrate portion 20 A may include four edges 21 , which are substantially parallel to the respective edges 200 A of die 200 .
- the remaining portions of substrate strips 20 C have edges 20 C′, which are generated due to the sawing.
- Edges 20 C′ are aligned to the respective edges 200 A of die 200 . There may be two or more substrate strips 20 C connected to a same edge 21 in order to maximize the benefit of reducing stress, although in other embodiments, there is a single substrate strip 20 C connected to one edge 21 .
- substrate portions 20 B FIG. 3A
- substrate portions 20 B may have some residues left. Accordingly, substrate portions 20 B are illustrated using dashed lines to indicate that they may, or may not exist.
- each of substrate portions 20 B is located between two substrate strips 20 C that are connected to the same edge 21 .
- substrate portions 20 B have portions remaining in die 200
- an edge 20 B′ of each of substrate portions 20 B is aligned to one of edges 200 A due to the step of sawing.
- Substrate strips 20 C cross over seal ring 14 . Accordingly, some portions of substrate strips 20 C are outside of seal ring 14 , and some other portions of substrate strips 20 C are inside seal ring 14 .
- the substrate strips may interconnect the substrate portions in the image sensor chips as an integrated unit.
- the substrate strips may push or pull the neighboring substrate portions, so that the adverse stress caused by the partial removal of substrate is at least reduced, or substantially eliminated.
- the formation of the substrate strips does not require additional manufacturing cost since the substrate strips are formed simultaneously with the step of etching the substrate. After the dicing of the wafer, the remaining portions of the substrate strips may be observable in the resulting dies.
- a die includes a first plurality of edges, and a semiconductor substrate in the die.
- the semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges.
- the semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die.
- the second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.
- a BSI image sensor die includes a first plurality of edges, and a seal ring including a plurality of sides, with each of the plurality of sides adjacent to, and parallel to, one of the first plurality of edges.
- a semiconductor substrate is in the BSI image sensor die.
- the semiconductor substrate includes a bulk portion within the seal ring, wherein the first portion has a second plurality of edges, each adjacent to, and parallel to, one of the first plurality of edges.
- the semiconductor substrate further includes a plurality of strips, with each of the plurality of strips connected to one of the second plurality of edges. Each of the plurality of strips extends from inside the seal ring to outside the seal ring.
- a method includes forming a plurality of integrated circuit devices in each of a plurality of chips of a wafer, and etching a semiconductor substrate of the wafer into a plurality of portions.
- the plurality of portions of the semiconductor substrate includes a plurality of bulk portions, each in one of the plurality of chips, and a plurality of strip portions, each interconnecting two of the plurality of bulk portions that are located in two neighboring chips.
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Abstract
Description
- Backside Illumination (BSI) image sensor chips are replacing front side illumination sensor chips for their higher efficiency in capturing photons. In the formation of the BSI image sensor chips, image sensors, such as photo diodes, and logic circuits are formed on a silicon substrate of a wafer, followed by the formation of an interconnect structure on a front side of the silicon chip. The image sensors in the BSI image sensor chips generate electrical signals in response to the stimulation of photons.
- For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1A through 3D illustrate top views and a cross-sectional views of intermediate stages in the formation of a Backside Illumination (BSI) image sensor wafer in accordance with some exemplary embodiments; and -
FIG. 4 illustrates a top view of a BSI image sensor chip sawed from the BSI image sensor wafer in accordance with some embodiments. - The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
- A Backside Illumination (BSI) image sensor chip and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the image sensor chip are illustrated. The variations of the image sensor wafer and the image sensor chip are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
- In the formation of the BSI image sensor chips, image sensors and logic circuits (not shown) may be formed on a silicon substrate of a wafer (not shown), followed by the formation of an interconnect structure on a front side of the silicon chip. The interconnect structure includes a plurality of metal layers including bottom metal layer M1 through top metal layer Mtop.
- The wafer may then be flipped over. A backside grinding may then be performed on the silicon substrate from the backside of the silicon substrate. A buffer oxide layer may be formed over the back surface of the remaining silicon substrate, and the silicon substrate in the wafer is etched. In the etching of the silicon substrate, the portions of the silicon substrate in the scribe lines are removed. The remaining silicon substrate in each of the image sensor chip is thus isolated from the portions of the silicon substrate in other image sensor chips.
- Due to the etching of the silicon substrate, trenches are formed in the silicon substrate. Openings are then formed inside the trench, wherein some portions of the STI pad and the underlying portions of interlayer dielectric (ILD) are etched, so that metal pads in the bottom metal layer M1 are exposed. Metal pads are then formed in the openings to electrically couple to the metal pads in metal layer M1. The metal pad may be used for bonding to the BSI chip.
- In the above-described processes, the trench in the silicon substrate forms a grid, and the remaining portions of the silicon substrate are fully isolated from each other. This generates a stress in the remaining portions of the silicon substrate, which stress may be un-balanced, and adversely affects the devices in the silicon substrate. Such problems may be addressed by the exemplary embodiments shown in
FIGS. 1 through 4 . -
FIG. 1 illustrates a top view ofwafer 100 in accordance with some exemplary embodiments. Wafer 100 includeschips 10 and theadjoining scribe lines 12. In each ofchips 10,seal ring 14 is formed, wherein the outer boundaries of theseal rings 14 define the outer boundaries ofchips 10. In some embodiments, there may be more than one seal ring (although one is shown), wherein outer seal rings encircle inner seal rings. In these embodiments, the illustratedseal rings 14 are the outmost seal rings among the plurality of seal rings in each ofchips 10. Scribelines 12 are portions of thewafer 100 that are betweenseal rings 14 of neighboringchips 10. Accordingly, each of thescribe lines 12 is between and adjoining two rows (or two columns) ofchips 10, and may be between and adjoining two rows (or two columns) ofseal rings 14. - In some embodiments, Within-Scribe-Line (WSL)
features 16 may be formed inscribe lines 12. WSLfeatures 16 are schematically illustrated, and may include, for example, test devices that are used for monitoring the manufacturing process ofwafer 100, Scribe-line Primary Mark (SPM), overlay marks, or the like. -
FIG. 1B illustrates a cross-sectional view of a portion ofwafer 100 shown inFIG. 1A , wherein the cross-sectional view is obtained from theplane crossing line 1B-1B inFIG. 1A . As shown inFIG. 2 ,wafer 100 is attached to carrier 104 (which may be a glass carrier), for example, through adhesive 102. Wafer 100 includessubstrate 20, which expands throughout the entirety ofwafer 100 and extends intochips 10 and scribelines 12.Substrate 20 is a semiconductor substrate comprising a semiconductor material such as silicon, silicon carbon, a III-V compound semiconductor, germanium, or the like.Interconnect structure 22 is formed on a side (referred to as a front side hereinafter) ofsemiconductor substrate 20.Interconnect structure 22 includesmetal lines 30 andvias 32 formed indielectric layers 24.Dielectric layers 24 may have low dielectric constants (k values), which may be lower than about 3.5, or lower than about 3.0, for example. Passivation layer(s) 26 are also included inchips 10, whereinpassivation layers 26 may have non-low-k dielectric constants greater than 3.9. - In some embodiments,
chips 10 are image sensor chips, which may be Backside Illumination (BSI) image sensor chips.Image sensor array 34 is formed in each ofchips 10, and includesimage sensors 36 allocated as a plurality of rows and columns.Image sensors 36 may be photo diodes, photo transistors, or the like, which are capable of converting photons into electrical signals. Each ofchips 10 may includelogic circuits 38, which are used to process electrical signals, for example, the signals generated byimage sensor array 34. - Each of
seal rings 14 may extend throughout all of low-kdielectric layers 24, and may, or may not, extend into passivation layer(s) 26.Seal rings 14 may also include portions (not shown) contactingsubstrate 20.Seal rings 14 form solid metal rings adjacent to the peripheral region of therespective chips 10, so that afterwafer 100 is sawed into dies, moisture and detrimental chemicals may not penetrate intochips 10 and reach the devices and interconnect structure located withinseal rings 14. - The boundaries of
chips 10 and scribeline 12 are marked inFIG. 1B . WSLfeature 16 is schematically illustrated, and may be formed to extend into one or more (in any combination) ofsubstrate 20 andinterconnect structure 22. Furthermore, WSLfeatures 16 may include portions on a side (the backside) ofsubstrate 20 opposite to the front side in whichinterconnect structure 22 is located. The backside portions of WSLfeatures 16 are illustrated as being a portion oversubstrate 20. -
Substrate 20 is thinned, for example, to a thickness of several microns. In some embodiments, oversubstrate 20 resides Bottom Anti-Reflective Coating (BARC) 42, which is formed onback surface 20B ofsemiconductor substrate 20. In some embodiments,BARC 42 comprises silicon oxynitride (SiON), although other materials may be used.Buffer oxide layer 44 is formed overBARC 42.Buffer oxide layer 44 may be formed of silicon oxide, for example, although other dielectric materials may be used.Buffer oxide layer 44 may be formed using Plasma Enhance Chemical Vapor Deposition (PECVD), and hence is sometimes referred to as a Plasma enhanced (PE) oxide, although other formation methods may be used. - In each of chips 18,
metal grid 46 andmetal shield 48 are formed overoxide layer 44 in accordance with some embodiments.Metal grid 46 may have a top-view shape of a grid, with the openings in the grid aligned to imagesensors 36.Metal shield 48 overlapslogic circuit 38 to prevent the devices (such as transistors, diodes, etc.) inlogic circuit 38 from being adversely affected by light.Metal grid 46 andmetal shield 48 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, aluminum copper, alloys thereof, and/or multi-layers thereof.Metal grid 46 andmetal shield 48 may be formed simultaneously, and hence include same materials. -
Substrate 20 and the layers over substrate 20 (includingBARC 42 andoxide layer 44, for example) are then etched. The resulting structure is shown inFIGS. 2A and 2B , which are a top view and a cross-sectional view, respectively. The cross-sectional view inFIG. 2B is obtained from the plane crossing line 2B-2B inFIG. 2A . As shown inFIG. 2B , the etching is performed using Shallow Trench Isolation (STI)region 50 as an etch stop layer. Accordingly, after the etching,STI region 50 is exposed.Trench 52 is formed insubstrate 20 as a result of the etching. - Referring to
FIG. 2A , the etching results insubstrate 20 to be patterned into a plurality of in-chip substrate portions 20A (also referred to as bulk portions), wherein each of in-chip substrate portions 20A is located within the boundaries of therespective chips 10. Furthermore, some outer portions ofsubstrate 20 that are withinchips 10 and close to the boundaries ofchips 10 may also be removed by the etching step, so that edges 21 of in-chip substrate portions 20A are not aligned to the outer boundaries (defined by seal rings 14) ofchips 10.Edges 21 are also inside therespective chips 10 in the top view. In some exemplary embodiments, distance D1 between theedges 21 and the respective edges ofchip 10 is greater than about 100 μm. The remaining portions ofsubstrate 20 also includesubstrate portions 20B, which are the portions at which WSL features 16 are formed. - In addition, the remaining portions of
substrate 20 also includesubstrate portions 20C, wherein each ofsubstrate portions 20C interconnects twosubstrate portions 20A.Substrate portions 20C have lengths significantly greater than their widths, and hence are also referred to as substrate strips 20C hereinafter. Each ofsubstrate portions 20C may cross an entirety of ascribe line 12, and may extend into two neighboringchips 10. Throughsubstrate portions 20C, allsubstrate portions 20A inwafer 100 may be interconnected, althoughsubstrate portions 20A themselves are disconnected from each other. In some embodiments, eachedge 21 ofportion 20A is connected to one, two, three, or more substrate strips 20C. In the illustrated embodiments, there are twosubstrate strips 20C connected to the opposite edges of thesame edge 21, with aportion 20B in between. Width W1 ofsubstrate strips 20C may be between about 20 μm and about 80 μm. In some embodiments, width W1 is between about 0.5 percent and about 2.0 percent of length L1 of the respective side of the correspondingsubstrate portion 20A. Substrate strips 20C may have longitudinal directions perpendicular to therespective edge 21 it connects to. Since eachportion 20A may include four sides, substrate strips 20C are formed to connect to four sides ofportion 20A. In some embodiments,substrate portion 20B is disconnected fromsubstrate portions 20A andsubstrate strips 20C. -
Substrate portions 20A may have adverse stress after the substrate etching step, which adverse stress affects the performance of the devices inchip 10. Withsubstrate strips 20C interconnecting neighboringsubstrate portions 20A of neighboringchips 10, a force is provided to push or pull neighboringsubstrate portions 20A, so that the adverse stress is at least reduced, or substantially eliminated. - Referring to
FIGS. 3A through 3D , the remaining features ofwafer 100 are formed.FIGS. 3B , 3C, and 3D illustrate the cross-sectional views obtained from theplanes crossing lines 3B-3B, 3C-3C, and 3D-3D, respectively, inFIG. 3A .FIGS. 3A and 3B illustratebond pads 54 formed inchips 10.Bond pads 54 penetrate throughSTI region 50, and are electrically connected to the metal layers on the front side ofsubstrate 20. In some embodiments, the formation process includes forming openings 56 inSTI region 50, wherein openings 56 are further formed intrenches 52 that are formed due to the removal ofsubstrate 20.Dielectric layer 53 is formed to cover sidewalls oftrenches 52 and openings 56. Some horizontal portions ofdielectric layer 53 are removed to expose one ofmetal pads 30, which may be in a metal layer such as the bottom metal layer (M1) or another metal layer. A conductive layer (not shown) is then formed to extend into openings 56, and is then patterned. The remaining portions of the conductive layerform bond pads 54, which extend into openings 56.Bond pads 54 are electrically coupled to interconnectstructure 22, and may be electrically coupled toimage sensor array 34 and/orlogic circuit 38. - Furthermore, as shown in
FIGS. 3B , 3C, and 3D, the remaining components ofBSI chip 10, includingdielectric layer 60,color filters 62, micro-lenses 64, and the like, are formed.Dielectric layer 60 may fill the gaps betweenmetal grid 46 andmetal shield 48, so that a flat top surface may be formed for the subsequent formation ofcolor filters 62 andmicro-lenses 64. Each ofcolor filters 62 andmicro-lenses 64 may be aligned to one ofimage sensors 36. The cross-sectional view inFIG. 3B is obtained from the plane crossingbond pads 54 andportion 20B ofsubstrate 20, and hencebond pads 54 andportion 20B are illustrated. The cross-sectional view inFIG. 3C is obtained from the plane in whichsubstrate strip 20C is located, and hencesubstrate portions FIG. 3D is obtained from the plane in which nobond pads 54 andsubstrate portion 20C exist, and hence trench 52 is shown as extending throughoutscribe line 12, and extending into neighboringchips 10. - Next, after
wafer 100 inFIGS. 3A-3D is formed,wafer 100 is diced alongscribe lines 12, so that a plurality of identical dies are formed.FIG. 4 illustrates a top view of one of dies 200, which includeschip 10 therein. The illustrateddie 200, besides the portion ofchip 10 shown inFIG. 3A , may also include residue portions ofscribe lines 12 shown inFIG. 3A . Further, each ofsubstrate strips 20C is sawed, and each of substrate strips 12 has a portion remaining indie 200.Substrate portion 20A may include fouredges 21, which are substantially parallel to therespective edges 200A ofdie 200. The remaining portions ofsubstrate strips 20C haveedges 20C′, which are generated due to the sawing.Edges 20C′ are aligned to therespective edges 200A ofdie 200. There may be two ormore substrate strips 20C connected to asame edge 21 in order to maximize the benefit of reducing stress, although in other embodiments, there is asingle substrate strip 20C connected to oneedge 21. In some embodiments,substrate portions 20B (FIG. 3A ) are fully sawed, and hencesubstrate portions 20B are not indie 200. In alternative embodiments,substrate portions 20B may have some residues left. Accordingly,substrate portions 20B are illustrated using dashed lines to indicate that they may, or may not exist. In accordance with the illustrated embodiments, each ofsubstrate portions 20B is located between twosubstrate strips 20C that are connected to thesame edge 21. In thecase substrate portions 20B have portions remaining indie 200, anedge 20B′ of each ofsubstrate portions 20B is aligned to one ofedges 200A due to the step of sawing. Substrate strips 20C cross overseal ring 14. Accordingly, some portions ofsubstrate strips 20C are outside ofseal ring 14, and some other portions ofsubstrate strips 20C areinside seal ring 14. - In the embodiments of the present disclosure, by leaving substrate strips un-etched when the respective substrate is etched, the substrate strips may interconnect the substrate portions in the image sensor chips as an integrated unit. When the substrate portions in the image sensor chips have and/or suffer from stresses, the substrate strips may push or pull the neighboring substrate portions, so that the adverse stress caused by the partial removal of substrate is at least reduced, or substantially eliminated. The formation of the substrate strips does not require additional manufacturing cost since the substrate strips are formed simultaneously with the step of etching the substrate. After the dicing of the wafer, the remaining portions of the substrate strips may be observable in the resulting dies.
- In accordance with some embodiments, a die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.
- In accordance with other embodiments, a BSI image sensor die includes a first plurality of edges, and a seal ring including a plurality of sides, with each of the plurality of sides adjacent to, and parallel to, one of the first plurality of edges. A semiconductor substrate is in the BSI image sensor die. The semiconductor substrate includes a bulk portion within the seal ring, wherein the first portion has a second plurality of edges, each adjacent to, and parallel to, one of the first plurality of edges. The semiconductor substrate further includes a plurality of strips, with each of the plurality of strips connected to one of the second plurality of edges. Each of the plurality of strips extends from inside the seal ring to outside the seal ring.
- In accordance with yet other embodiments, a method includes forming a plurality of integrated circuit devices in each of a plurality of chips of a wafer, and etching a semiconductor substrate of the wafer into a plurality of portions. The plurality of portions of the semiconductor substrate includes a plurality of bulk portions, each in one of the plurality of chips, and a plurality of strip portions, each interconnecting two of the plurality of bulk portions that are located in two neighboring chips.
- Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims (21)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170257554A1 (en) * | 2016-03-04 | 2017-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit device |
US20220271071A1 (en) * | 2013-11-06 | 2022-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming backside illuminated image sensor device with shielding layer |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8884390B2 (en) * | 2013-01-30 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside illumination image sensor chips and methods for forming the same |
US9905466B2 (en) * | 2016-06-28 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer partitioning method and device formed |
TWI668813B (en) * | 2016-11-02 | 2019-08-11 | 以色列商馬維爾以色列股份有限公司 | On-die seal rings |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8338917B2 (en) * | 2010-08-13 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple seal ring structure |
US20130119556A1 (en) * | 2011-11-15 | 2013-05-16 | Xintec Inc. | Chip package |
US20130122637A1 (en) * | 2011-01-06 | 2013-05-16 | Omnivision Technologies, Inc. | Seal ring support for backside illuminated image sensor |
US20140077320A1 (en) * | 2012-09-14 | 2014-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scribe Lines in Wafers |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7973380B2 (en) | 2005-11-23 | 2011-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for providing metal extension in backside illuminated sensor for wafer level testing |
US7588993B2 (en) * | 2007-12-06 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment for backside illumination sensor |
TWI450389B (en) | 2011-06-21 | 2014-08-21 | Himax Imaging Inc | Back-side illumination image sensor and method for fabricating back-side illumination image sensor |
US8435824B2 (en) * | 2011-07-07 | 2013-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside illumination sensor having a bonding pad structure and method of making the same |
US9356059B2 (en) * | 2011-12-15 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | BSI image sensor chips and methods for forming the same |
US8766387B2 (en) * | 2012-05-18 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertically integrated image sensor chips and methods for forming the same |
US8884390B2 (en) * | 2013-01-30 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside illumination image sensor chips and methods for forming the same |
-
2013
- 2013-01-30 US US13/754,612 patent/US8884390B2/en active Active
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-
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- 2014-10-28 US US14/525,491 patent/US9142588B2/en active Active
-
2015
- 2015-08-31 US US14/840,143 patent/US9450014B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8338917B2 (en) * | 2010-08-13 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple seal ring structure |
US20130122637A1 (en) * | 2011-01-06 | 2013-05-16 | Omnivision Technologies, Inc. | Seal ring support for backside illuminated image sensor |
US20130119556A1 (en) * | 2011-11-15 | 2013-05-16 | Xintec Inc. | Chip package |
US20140077320A1 (en) * | 2012-09-14 | 2014-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scribe Lines in Wafers |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220271071A1 (en) * | 2013-11-06 | 2022-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming backside illuminated image sensor device with shielding layer |
US11810939B2 (en) * | 2013-11-06 | 2023-11-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming backside illuminated image sensor device with shielding layer |
US20170257554A1 (en) * | 2016-03-04 | 2017-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit device |
US10484590B2 (en) * | 2016-03-04 | 2019-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit device |
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US20150044810A1 (en) | 2015-02-12 |
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US20150372045A1 (en) | 2015-12-24 |
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TW201431052A (en) | 2014-08-01 |
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