US20140198653A1 - Scheduling and Traffic Management with Offload Processors - Google Patents

Scheduling and Traffic Management with Offload Processors Download PDF

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US20140198653A1
US20140198653A1 US13/924,558 US201313924558A US2014198653A1 US 20140198653 A1 US20140198653 A1 US 20140198653A1 US 201313924558 A US201313924558 A US 201313924558A US 2014198653 A1 US2014198653 A1 US 2014198653A1
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memory
offload
network packets
processor
session
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Parin Bhadrik Dalal
Stephen Paul Belair
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XOCKETS Inc
Xockets IP LLC
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Xockets IP LLC
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Definitions

  • Described embodiments relate to scheduling and traffic management services for computer systems that can be provided by a memory bus connected module with offload processors.
  • Network packet flow can be highly variable, depending on hardware configurations, process flows and data flows, with data processing needs varying over several orders of magnitude on time scales that can range from seconds to hours.
  • Substantial improvements in network service are made possible by systems that can flexibly process a data flow, recognize or characterize patterns in the data flow, and improve routing and processing decisions for the data flow. This is of particular importance for networked computer environment using packet switching communication. For example, delays in data flow are often created due to network security required packet inspection.
  • Such packet inspection may be directed at either a header of the packet or a payload of the packet, and can include processor content matching, behavioral anomaly detection, “black” or “white” listing comparisons, or the like.
  • High packet processing applications can include encryption/decryption, quality of service controlled packet reassembly, streaming sensor data, or video or audio processing. Without an efficient mechanism for scheduling packet processing arriving as part of a complex data flow system, users may encounter unacceptable delays in network system response.
  • Commonly available traffic management circuits supporting a packet switch fabric capable of handling complex data flow streams often include depth-limited output queues, the access to which is arbitrated by a scheduling circuit.
  • the input queues are managed using a scheduling discipline to provide traffic management for incoming data flows.
  • Schedulers may allocate or identify a data flow priorities and provide output port to each of these data flows. If multiple data flows compete for the same output port, time multiplexed access to each of the output ports can be provided, or alternatively multiple data flows contending for an output port may be arbitrated by an arbitration circuit before being sent out over an output port.
  • a traffic management circuit typically has limited or no access to information relating to handling and management of data by downstream memory or processing elements.
  • TM packet processing prioritization
  • the scheduling discipline chosen for such packet processing prioritization or traffic management (TM) can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), or delay jitter (temporally shifting cells of a flow by different amounts).
  • the system includes a classification circuit connected to a memory bus and configurable to classify network packets.
  • the classification circuit can place the classified network packets into first multiple input/output queues.
  • a scheduling circuit can reorder the network packets received from the classification circuit through the first multiple input/output queues and place the reordered network packets into second multiple input/output queues.
  • An arbitration circuit directs network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports. Multiple offload processors, each connected to one of the multiple output ports, are respectively configured to modify network packets.
  • the memory bus supports direct memory access, and multiple offload processors can direct modified packets back to the memory bus.
  • the classification circuit can classify network packets based on session metadata.
  • the scheduling circuit can direct network packets based on availability of respective multiple offload processors; reorder network packets according to session priority; initiates a context switch for the multiple offload processors; transfer network packets into a defined traffic management queue; check with each of the multiple offload processors to determine if respective network packet processing is complete; or operate in preemption mode to control session execution.
  • Another embodiment is a method for scheduling packet processing, including the step of classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with packets transported to a classification circuit using a memory bus having a defined memory transport protocol.
  • Reordered network packets received from the first multiple input/output queues using a scheduling circuit can be placed into a second multiple input/output queues, where an arbitration circuit directs network packets received from the scheduling circuit through the second multiple input/output queues into multiple output ports.
  • These network packets can be modified using multiple offload processors, each offload processor respectively connected to one of the multiple output ports, with the respective offload processers able to direct modified packets back to the memory bus.
  • the module includes a memory bus connection and a scheduling circuit for reordering the network packets received from the memory bus connection and placing the reordered network packets into multiple input/output queues.
  • Multiple offload processors are connected to the memory bus connection, with each offload processor capable of modifying network packets placed into multiple input/output queues.
  • the memory bus connection can be compatible with a memory bus socket, and in certain embodiments be formed to fit into a dual in-line memory module (DIMM) socket.
  • DIMM dual in-line memory module
  • FIG. 1-0 shows a traffic management and scheduler system according to an embodiment.
  • FIG. 1-1 shows a scheduling process according to an embodiment.
  • FIG. 1-2 shows a module supporting multiple scheduling circuits and an arbitration circuit according to an embodiment.
  • FIGS. 2-0 to 2 - 3 show processor modules according to various embodiments.
  • FIG. 2-4 shows a conventional dual-in-line memory module.
  • FIG. 2-5 shows a system according to another embodiment.
  • FIGS. 3 shows one particular implementation of a memory bus connected offload processor that can be included in embodiments.
  • FIG. 4 shows an exemplary flow chart for a scheduling process according to an embodiment.
  • processing systems and methods for scheduling packet flow in a packet processing systems can be performed by, or with the use of, offload modules connect to a memory bus of a system.
  • offload processors can be in addition to any host processors connected to the system memory bus, and, in some embodiments, process packets transferred over the system memory bus independent of any host processors.
  • processing modules can populate physical slots for connecting in-line memory modules (e.g., DIMMs) to a system memory bus.
  • FIG. 1-0 is a diagram of a system 100 for providing scheduling and traffic management services.
  • a system 100 can include a switch 106 , host processor section 108 / 110 , memory controller 112 , and offload processing section 116 / 116 / 118 .
  • host processor section can include a switch 106 , a switching fabric 108 , host processor(s) 110 , and a bus interconnect 109 connected to memory controller 112 .
  • offload processing section can be in communication with memory controller 112 , and can include a switch 114 , scheduler 116 and offload processor(s) 118 .
  • a switch 106 can receive and/or transmit data packets 104 from data source 102 .
  • a data source 102 can be any suitable source of packet data, including the Internet, a network cloud, inter- or intra-data center networks, cluster computers, rack systems, multiple or individual servers or personal computers, or the like.
  • Data can be packet or switch based, although in particular embodiments non-packet data is generally converted or encapsulated into packets for ease of handling.
  • the data packets typically have certain characteristics, including transport protocol number, source and destination port numbers, or source and destination (Internet Protocol) IP addresses.
  • the data packets can further have associated metadata that helps in packet classification and management.
  • a switch 106 can be a virtual switch (an I/O device).
  • a switch 106 can include, but is not limited to, devices compatible with peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with host motherboard via PCI or PCIe bus 107 .
  • the switch 106 can include a network interface controller (NIC), a host bus adapter, a converged network adapter, or a switched or an asynchronous transfer mode (ATM) network interface.
  • NIC network interface controller
  • a host bus adapter a host bus adapter, a converged network adapter, or a switched or an asynchronous transfer mode (ATM) network interface.
  • ATM asynchronous transfer mode
  • a switch 106 can employ IO virtualization schemes such as a single root I/O virtualization (SR-IOV) interface to make a single network I/O device appear as multiple devices.
  • SR-IOV single root I/O virtualization
  • SR-IOV permits separate access to resources among various PCIe hardware functions by providing both physical control and virtual functions.
  • the switch 106 can support OpenFlow or similar software defined networking to abstract out of the control plane.
  • the control plane of the first virtual switch performs functions such as route determination, target node identification etc.
  • a switch 106 can be capable of examining network packets, and using its control plane to create appropriate output ports for network packets. Based on route calculation for the network packets or data flows associated with the network packets, the forwarding plane of the switch 106 can transfer the packets to an output interface.
  • An output interface of the switch may be connected with an IO bus, and in certain embodiments the switch 106 may have the capability to directly (or indirectly, via an I/O fabric 108 ) transfer the network packets to a memory bus interconnect 109 for a memory read or write operation (direct memory access operation).
  • the network packets can be assigned for transport to specific memory locations based on control plane functionality.
  • Switch 106 connected to an IO fabric 108 and memory bus interconnect 109 , can also be connected to host processor(s) 110 .
  • Host processor(s) 110 can include one or more host processors which can provide computational services including a provisioning agent 111 .
  • the provisioning agent 111 can be part of an operating system or user code running on the host processor(s) 110 .
  • the provisioning agent 111 typically initializes and interacts with virtual function drivers provided by system 100 .
  • the virtual function driver can be responsible for providing the virtual address of the memory space where a direct memory addressing (DMA) is needed.
  • DMA direct memory addressing
  • Each device driver can be allocated virtual addresses that map to the physical addresses.
  • a device model can be used to create an emulation of a physical device for the host processor 110 to recognize each of the multiple virtual functions (VF) that can be created.
  • the device model can be replicated multiple times to give the impression to VF drivers (a driver that interacts with a virtual IO device) that they are interacting with a physical device.
  • VF drivers a driver that interacts with a virtual IO device
  • a certain device model may be used to emulate a network adapter that the VF driver can act to connect.
  • the device model and the VF driver can be run in either privileged or non-privileged mode. There can be no restriction with regard to which device hosts/runs the code corresponding to the device model and the VF driver.
  • the code can have the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created.
  • the operating system can also create a defined physical address space for applications supported by VF drivers.
  • the host operating system can allocate a virtual memory address space to the application or provisioning agent.
  • the provisioning agent 111 can broker with the host operating system to create a mapping between virtual addresses and a subset of the available physical address space.
  • the provisioning agent 111 can be responsible for creating each VF driver and allocating it a defined virtual address space.
  • data e.g., packet data
  • a second switch 114 can also be connected to the memory controller 112 by memory bus 109 .
  • a second switch 114 can be a virtual switch, and can receive and switch traffic originating from the memory bus 109 both to and from offload processor(s) 118 . Traffic may include, but is not limited to, data flows to virtual devices created and assigned by the provisioning agent 111 , with processing supported by offload processors 118 .
  • the forwarding plane of the second switch 114 can transports packets from a memory bus 109 to offload processors 118 or from the offload processors 118 back onto the memory bus 109 .
  • the described system architecture can allow relatively direct communication of network packets to the offload processors 118 with minimal or no interruptions to a host processor(s) 110 .
  • the second switch 114 can be capable of receiving packets and classifying them prior to distribution to different hardware schedulers based on a defined arbitration and scheduling scheme.
  • the hardware scheduler 116 receives packets that can be assigned to flow sessions that are scheduled for processing in one or more separate sessions run by offload processor(s) 118 .
  • scheduler 116 can be employed to implement traffic management of incoming packets.
  • Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata.
  • Session metadata often serve as the criterion by which packets are prioritized and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows.
  • Packets of a session that are reordered based on session metadata can be sent over to specific traffic managed queues that are arbitrated out to output ports using an arbitration circuit (not shown). The arbitration circuit can feed these packet flows to a downstream packet processing/terminating resource directly.
  • Certain embodiments provide for integration of thread and queue management so as to enhance the throughput of downstream resources handling termination of network data through above said threads.
  • bus architecture can also be based on relevant JEDEC standards, on DIMM data transfer protocols, on Hypertransport, or any other suitable high speed, low latency interconnection system.
  • Offload processor(s) 118 may include double data rate (DDR) dynamic random access memory (DRAM), reduced latency DRAM (RLDRAM), embedded DRAM, next generation stacked memory such as Hybrid Memory Cube (HMC), flash, or other suitable memory, separate logic or bus management chips, programmable units such as field programmable gate arrays (FPGAs), custom designed application specific integrated circuits (ASICs) and an energy efficient, general purpose processor such as those based on ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC architectures.
  • Host processor(s) 110 can include general purpose processor(s), including those based on Intel or AMD x86 architecture, Intel Itanium architecture, MIPS architecture, SPARC architecture or the like.
  • FIG. 1-1 illustrates one embodiment of a hardware scheduled data flow method 140 suitable for operation in conjunction with an embodiment like that of FIG. 1-0 .
  • a hardware scheduler can manage traffic by segregating packets based on sessions ( 141 ). In some embodiments, sessions are identified by metadata of the packets. Sessions can be prioritized and queued ( 142 ) and a general purpose operating system (OS) running on one or more offload processors can be used control execution of a current session ( 143 ).
  • a hardware scheduler can use the current state of the OS, including numbers of session, state of the session, feedback from the OS relating to processing resources or future scheduling requirements, etc., to make scheduling decisions or arbitration between competing processes for memory resources ( 144 ). If certain conditions are met, the hardware scheduler can initiate a context switch in which a current session has its state stored in memory, and a new session is begun or returned to ( 145 ).
  • FIG. 1-2 illustrates one embodiment of a hardware scheduler 150 (i.e., a scheduling circuit).
  • the hardware scheduler 150 can include input ports 152 / 152 ′, classification circuit 154 , input queues (one shown as 156 ), scheduling circuits 158 / 158 ′, output queues (one shown as 160 ), arbitration circuit 162 , and output ports 164 / 164 ′.
  • Connected to the hardware scheduler can be common packet status registers 166 / 166 ′, packet buffers 168 / 168 ′, one or more cache memory ports 170 (which can be an accelerator coherency port ACP, in one particular embodiment), and a low latency memory 172 .
  • FIG. 1-2 shows an architecture with two input ports and two output ports, alternate embodiments can include one input and output port, or more than two such ports.
  • the hardware scheduler 150 can receive packets from an arbiter circuit (not shown) that is connected to several such hardware schedulers.
  • the hardware scheduler 150 can receive such data at one or more input ports 152 / 152 ′.
  • the hardware scheduler 150 can employ a classification circuit 154 , which can examine incoming packets, and based on metadata present in the packets, classifies packets into different incoming queues.
  • the classification circuit 154 can examine different packet headers, and can use an interval matching circuit to carry out segregation of incoming packets.
  • One suitable interval matching circuit is described in U.S. Pat. No. 7,760,715 issued to Dalal on Aug. 4, 2007 (hereinafter the '715 patent). However, any other suitable classification scheme may be employed to execute the classification circuit.
  • the hardware scheduler 150 can be connected with packet status registers 166 / 166 ′ for communicating with offload processors (not shown). Registers 166 / 166 ′ can be operated upon by both the hardware scheduler 150 and an OS running on an offload processor.
  • the hardware scheduler can also be connected with a packet buffer 168 / 168 ′ to store outgoing packets of a session or for processing to/by an offload processor OS.
  • the hardware scheduler 150 can use port 170 to access data related to a session that is currently running on an offload processor OS in the cache of the offload processor and transfer it out using a bulk transfer during a context switch to a different session.
  • the hardware scheduler 150 can uses the cache transfer to reduce the overhead associated with the session.
  • the hardware scheduler 150 can also use a low latency memory 172 to store the session related information from the cache for its subsequent access.
  • a hardware scheduler 150 can have more than one input port 152 / 152 ′.
  • the data coming into the hardware scheduler may be packet data waiting to be terminated at the offload processors or it could be packet data waiting to be processed, modified or switched out.
  • the hardware scheduler 150 can be responsible for segregating incoming packets into corresponding application sessions based on examination of packet data.
  • the hardware scheduler 150 can be capable of packet inspection and identifying relevant packet characteristics.
  • a hardware scheduler 150 may offload part of the network stack to free offload processors from overhead incurred from such network stack processing.
  • a hardware scheduler 150 may carry out any of TCP/transport offload, encryption/decryption offload, segmentation and reassembly, or the like, thus allowing the offload processor to use the payload of the network packets directly.
  • hardware scheduler 150 can further have the capability to transfer the packets belonging to a session into a particular traffic management queue (e.g., 156 ) for its scheduling ( 158 ) and transfer to an output queues (e.g., 160 ).
  • the hardware scheduler 150 may be used to control the scheduling of each of these persistent sessions into a general purpose OS.
  • the stickiness of sessions across a pipeline of stages, including a general purpose OS, can be accentuated by a scheduler circuit 150 carrying out optimizations at each of the stages in the pipeline (described in more detail below).
  • a hardware scheduler 150 can takes into account of downstream execution resources.
  • the session flows queued in each of these queues can be sent out through an output port to a downstream network element.
  • One particular implementation of such scheduling is shown in the '715 patent, which is incorporated herein by reference, in its entirety.
  • a hardware scheduler 150 may employ an arbitration circuit 162 to arbitrate or otherwise control access of multiple traffic management output queues to available output ports.
  • Each of the output ports may be connected to one of the offload processor cores through a packet buffer 168 / 168 ′.
  • a packet buffer 168 / 168 ′ may further include a header pool and a packet body pool.
  • a header pool can contain only the header of packets to be processed by offload processors. Sometimes, if the size of the packet to be processed is sufficiently small, the header pool may contain the entire packet. Packets can be transferred over to the header pool/packet body pool depending on the nature of operation carried out at the offload processor.
  • the offload processors For packet processing, overlay, analytics, filtering and such other applications it might be appropriate to transfer only the packet header to the offload processors. In this case, depending on the handling of the packet header, the packet body might either be sewn together with a packet header and transferred over an egress interface, or dropped. For applications requiring the termination of packets, the entire body of the packet might be transferred.
  • the offload processor cores may receive the packets and execute suitable application session on them to execute said packet contents.
  • a hardware scheduler 150 can schedule different sessions on a downstream processor, wherein the two are operated in coordination to reduce the overhead during context switches.
  • a hardware scheduler 150 can be understood to arbitrate not just between outgoing queues or session flows at line rate speeds, but between terminated sessions at very high speeds.
  • the hardware scheduler 150 can manage the queuing of sessions on the offload processor.
  • a scheduling circuit 158 / 158 ′ can be responsible for queuing each session flow into the OS as a different OS processing entity. Scheduling circuit 158 / 158 ′ can be responsible for causing the execution of a new application session on the OS. It can indicate to the OS that packets for a new session are available based on traffic management carried out by it.
  • a hardware scheduler 150 can be informed of the state of the execution resources on the offload processors, the current session that is run on the execution resource, the memory space allocated to it, and the location of the session context in the processor cache. It can use the state of the execution resource to carry out traffic management and arbitration decisions.
  • the hardware scheduler 150 can provide for an integration of thread management on the operating system with traffic management of incoming packets. It can induce persistence of session flows across a spectrum of components including traffic management queues and processing entities on the offload processors.
  • An OS running on a downstream (e.g. offload) processor may allocate execution resources such as processor cycles and memory to a particular queue it is currently handling.
  • the OS may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element as a separate entity.
  • the offload OS can be modified to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the hardware scheduler to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.
  • a hardware scheduler can be employed to implement traffic management of incoming packets.
  • Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and can be classified using session metadata.
  • Session metadata often serve as the criterion by which packets are prioritized and as such, incoming packets are reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows.
  • Packets of a session that are reordered based on session metadata can be sent over to specific traffic managed queues that are arbitrated out to output ports using an arbitration circuit.
  • An arbitration circuit (e.g. 162 ) can feed these packet flows to a downstream packet processing/terminating resource directly.
  • Certain embodiments provide for integration of thread and queue management so as to enhance the throughput of downstream resources handling termination of network data through above said threads.
  • a hardware scheduler can perform any of the following functions:
  • the hardware scheduler is responsible for carrying out traffic management, arbitration and scheduling of incoming network packets (and flows); b) hardware scheduler is responsible for offloading part of the network stack of the offload OS, so that the offload OS can be kept free of stack level processing and resources are free to carry out execution of application sessions; c) the hardware scheduler is responsible for classification of packets based on packet metadata, and packets classified into different session are queued in output traffic queues are sent over to the offload OS; d) the hardware scheduler is responsible for cooperating with minimal overhead context switching between terminated sessions on the offload OS; the hardware scheduler ensures that multiple sessions on the offload OS can be switched with as minimal overhead as possible (the ability to switch between multiple sessions on the offload sessions makes it possible to terminate multiple sessions at very high speeds, providing packet processing speeds for terminated sessions); d) the hardware scheduler is responsible for queuing each session flow into the OS as a different OS processing entity; e) the hardware scheduler is responsible for causing the execution of a new application session on the OS
  • the hardware scheduler can use the state of the execution resource to carry out traffic management and arbitration decisions.
  • the hardware scheduler can provide for an integration of thread management on the operating system with traffic management of incoming packets. It can induce persistence of session flows across a spectrum of components including traffic management queues and processing entities on the offload processors.
  • processors architectures such as MIPS may include deep instruction pipelines to improve the number of instructions per cycle. Further, the ability to run a multi-threaded programming environment results in enhanced usage of existing processor resources.
  • processor architecture may include multiple processor cores. Multi-core architectures comprising the same type of cores, referred to as homogeneous core architectures, provide higher instruction throughput by parallelizing threads or processes across multiple cores. However, in such homogeneous core architectures, the shared resources, such as memory, are amortized over a small number of processors.
  • multiple offload or host processors can reside on modules connected to individual rack units or blades that in turn reside on racks or individual servers. These can be further grouped into clusters and datacenters, which can be spatially located in the same building, in the same city, or even in different countries. Any grouping level can be connected to each other, and/or connected to public or private cloud internets.
  • Memory and I/O accesses can incur a high amount of processor overhead.
  • context switches in conventional general purpose processing units can be computationally intensive. It is therefore desirable to reduce context switch overhead in a networked computing resource handling a plurality of networked applications in order to increase processor throughput.
  • Conventional server loads can require complex transport, high memory bandwidth, extreme amounts of data bandwidth (randomly accessed, parallelized, and highly available), but often with light touch processing: HTML, video, packet-level services, security, and analytics. Further, idle processors still consume more than 50% of their peak power consumption.
  • complex transport, data bandwidth intensive, frequent random access oriented, ‘light’ touch processing loads can be handled behind a socket abstraction created on multiple offload processor cores.
  • “heavy” touch, computing intensive loads can be handled by a socket abstraction on a host processor core (e.g., x86 processor cores).
  • a host processor core e.g., x86 processor cores.
  • Such software sockets can allow for a natural partitioning of these loads between ARM and x86 processor cores.
  • server loads can be broken up across the offload processing cores and the host processing cores.
  • FIGS. 2-0 to 2 - 5 describe aspects of hardware embodiments and methods for providing scheduling and traffic management services using processing modules.
  • processing modules can include DIMM mountable modules to support offload processing.
  • FIG. 2-0 is a block diagram of a processing module 200 according to one embodiment.
  • a processing module 200 can include a physical connector 202 , a memory interface 204 , arbiter logic 206 , offload processor(s) 208 , local memory 210 , and control logic 212 .
  • a connector 202 can provide a physical connection to system memory bus. This is in contrast to a host processor which can access a system memory bus via a memory controller, or the like.
  • a connector 202 can be compatible with a dual in-line memory module (DIMM) slot of a computing system. Accordingly, a system including multiple DIMM slots can be populated with one or more processing modules 200 , or a mix of processing modules and DIMM modules.
  • DIMM dual in-line memory module
  • a memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200 . Such data transfers can include the receipt of packet data having a particular network identifier.
  • a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module 200 .
  • a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory bus initiated by a DMA master.
  • a DMA master can be a device different from a host processor.
  • processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.
  • a memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200 .
  • a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module.
  • a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory initiated by a DMA master.
  • a DMA master can be a device different from a host processor.
  • processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.
  • Arbiter logic 206 can arbitrate between conflicting accesses of data within processing module 200 .
  • arbiter logic 206 can arbitrate between accesses by offload processor 208 and accesses external to the processor module 200 . It is understood that a processing module 200 can include multiple locations that are operated on at the same time. It is understood that accesses arbitrated by arbiter logic 206 can include accesses to physical system memory space occupied by the processor module 200 , as well as accesses to other resources (e.g., cache memory of offload or host processor). Accordingly, arbitration rules for arbiter logic 206 can vary according to application. In some embodiments, such arbitration rules are fixed for a given processor module 200 . In such cases, different applications can be accommodated by switching out different processing modules. However, in alternate embodiments, such arbitration rules can be configurable.
  • Offload processor 208 can include one or more processors that can operate on data transferred over the system memory bus.
  • offload processors can run a general operating system or server applications such as Apache (as but one very particular example), enabling processor contexts to be saved and retrieved. Computing tasks executed by offload processor 208 can be handled by the hardware scheduler.
  • Offload processors 208 can operate on data buffered in the processor module 200 .
  • offload processors 208 can access data stored elsewhere in a system memory space.
  • offload processors 208 can include a cache memory configured to store context information.
  • An offload processor 208 can include multiple cores or one core.
  • a processor module 200 can be included in a system having a host processor (not shown).
  • offload processors 208 can be a different type of processor as compared to the host processor.
  • offload processors 208 can consume less power and/or have less computing power than a host processor.
  • offload processors 208 can be “wimpy” core processors, while a host processor can be a “brawny” core processor.
  • offload processors 208 can have equivalent computing power to any host processor.
  • a host processor can be an x86 type processor, while an offload processor 208 can include an ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC type processor, as but a few examples.
  • Local memory 210 can be connected to offload processor 208 to enable the storing of context information. Accordingly, an offload processor 208 can store current context information, and then switch to a new computing task, then subsequently retrieve the context information to resume the prior task.
  • local memory 210 can be a low latency memory with respect to other memories in a system.
  • storing of context information can include copying an offload processor 208 cache.
  • a same space within local memory 210 is accessible by multiple offload processors 208 of the same type. In this way, a context stored by one offload processor can be resumed by a different offload processor.
  • Control logic 212 can control processing tasks executed by offload processor(s).
  • control logic 212 can be considered a hardware scheduler that can be conceptualized as including a data evaluator 214 , scheduler 216 and a switch controller 218 .
  • a data evaluator 214 can extract “metadata” from write data transferred over a system memory bus.
  • “Metadata”, as used herein, can be any information embedded at one or more predetermined locations of a block of write data that indicates processing to be performed on all or a portion of the block of write data and/or indicate a particular task/process to which the data belongs (e.g., classification data).
  • metadata can be data that indicates a higher level organization for the block of write data.
  • metadata can be header information of one or more network packets (which may or may not be encapsulated within a higher layer packet structure).
  • a scheduler 216 can order computing tasks for offload processor(s) 208 .
  • scheduler 216 can generate a schedule that is continually updated as write data for processing is received.
  • a scheduler 216 can generate such a schedule based on the ability to switch contexts of offload processor(s) 208 . In this way, on-module computing priorities can be adjusted on the fly.
  • a scheduler 216 can assign a portion of physical address space (e.g., memory locations within local memory 210 ) to an offload processor 208 , according to computing tasks. The offload processor 208 can then switch between such different spaces, saving context information prior to each switch, and subsequently restoring context information when returning to the memory space.
  • Switch controller 218 can control computing operations of offload processor(s) 208 .
  • switch controller 218 can order offload processor(s) 208 to switch contexts.
  • a context switch operation can be an “atomic” operation, executed in response to a single command from switch controller 218 .
  • a switch controller 218 can issue an instruction set that stores current context information, recalls context information, etc.
  • processor module 200 can include a buffer memory (not shown).
  • a buffer memory can store received write data on board the processor module.
  • a buffer memory can be implemented on an entirely different set of memory devices, or can be a memory embedded with logic and/or the offload processor. In the latter case, arbiter logic 206 can arbitrate access to the buffer memory.
  • a buffer memory can correspond to a portion of a system physical memory space. The remaining portion of the system memory space can correspond to other like processor modules and/or memory modules connected to the same system memory bus.
  • buffer memory can be different than local memory 210 .
  • buffer memory can have a slower access time than local memory 210 .
  • buffer memory and local memory can be implemented with like memory devices.
  • write data for processing can have an expected maximum flow rate.
  • a processor module 200 can be configured to operate on such data at, or faster than, such a flow rate. In this way, a master device (not shown) can write data to a processor module without danger of overwriting data “in process”.
  • the various computing elements of a processor module 200 can be implemented as one or more integrated circuit devices (ICs). It is understood that the various components shown in FIG. 2-0 can be formed in the same or different ICs.
  • control logic 212 , memory interface 214 , and/or arbiter logic 206 can be implemented on one or more logic ICs, while offload processor(s) 208 and local memory 210 are separate ICs.
  • Logic ICs can be fixed logic (e.g., application specific ICs), programmable logic (e.g., field programmable gate arrays, FPGAs), or combinations thereof.
  • the foregoing hardware and systems can provide improved computational performance as compared to traditional computing systems.
  • Conventional systems including those based on x86 processors, are often ill-equipped to handle such high volume applications. Even idling, x86 processors use a significant amount of power, and near continuous operation for high bandwidth packet analysis or other high volume processing tasks makes the processor energy costs one of the dominant price factors.
  • conventional systems can have issues with the high cost of context switching wherein a host processor is required to execute instructions which can include switching from one thread to another. Such a switch can require storing and recalling the context for the thread. If such context data is resident in a host cache memory, such a context switch can occur relatively quickly. However, if such context data is no longer in cache memory (i.e., a cache miss), the data must be recalled from system memory, which can incur a multi-cycle latency. Continuous cache misses during context switching can adversely impact system performance.
  • FIG. 2-1 shows a processor module 200 - 1 according to one very particular embodiment which is capable of reducing issues associated with high volume processing or context switching associated with many conventional server systems.
  • a processor module 200 - 1 can include ICs 220 - 0 / 1 mounted to a printed circuit board (PCB) type substrate 222 .
  • PCB type substrate 222 can include in-line module connector 202 , which in one very particular embodiment, can be a DIMM compatible connector.
  • IC 220 - 0 can be a system-on-chip (SoC) type device, integrating multiple functions.
  • SoC system-on-chip
  • an IC 220 - 0 can include embedded processor(s), logic and memory.
  • Such embedded processor(s) can be offload processor(s) 208 as described herein, or equivalents.
  • Such logic can be any of controller logic 212 , memory interface 204 and/or arbiter logic 206 , as described herein, or equivalents.
  • Such memory can be any of local memory 210 , cache memory for offload processor(s) 208 , or buffer memory, as described herein, or equivalents.
  • FIG. 2-2 shows a processor module 200 - 2 according to another very particular embodiment.
  • a processor module 200 - 2 can include ICs 220 - 2 , - 3 , - 4 , - 5 mounted to a PCB type substrate 222 , like that of FIG. 2-1 .
  • processor module functions are distributed among single purpose type ICs.
  • IC 220 - 2 can be a processor IC, which can be an offload processor 208 .
  • IC 220 - 3 can be a memory IC which can include local memory 210 , buffer memory, or combinations thereof.
  • IC 220 - 4 can be a logic IC which can include control logic 212 , and in one very particular embodiment, can be an FPGA.
  • IC 220 - 5 can be another logic IC which can include memory interface 204 and arbiter logic 206 , and in one very particular embodiment, can also be an FPGA.
  • FIGS. 2 - 1 / 2 represent but two of various implementations.
  • the various functions of a processor module can be distributed over any suitable number of ICs, including a single SoC type IC.
  • FIG. 2-3 shows an opposing side of a processor module 200 - 1 or 200 - 2 according to a very particular embodiment.
  • Processor module 200 - 3 can include a number of memory ICs, one shown as 220 - 6 , mounted to a PCB type substrate 222 , like that of FIG. 2-1 . It is understood that various processing and logic components can be mounted on an opposing side to that shown.
  • a memory IC 220 - 6 can be configured to represent a portion of the physical memory space of a system.
  • Memory ICs 220 - 6 can perform any or all of the following functions: operate independently of other processor module components, providing system memory accessed in a conventional fashion; serve as buffer memory, storing write data that can be processed with other processor module components, or serve as local memory for storing processor context information.
  • FIG. 2-4 shows a conventional DIMM module (i.e., it serves only a memory function) that can populate a memory bus along with processor modules as described herein, or equivalents.
  • FIG. 2-5 shows a system 230 according to one embodiment.
  • a system 230 can include a system memory bus 228 accessible via multiple in-line module slots (one shown as 226 ).
  • any or all of the slots 226 can be occupied by a processor module 200 as described herein, or an equivalent.
  • available slots can be occupied by conventional in-line memory modules 224 .
  • slots 226 can be DIMM slots.
  • a processor module 200 can occupy one slot. However, in other embodiments, a processor module can occupy multiple slots.
  • a system memory bus 228 can be further interfaced with one or more host processors and/or input/output device (not shown).
  • FIG. 3 shows a system 301 according to another embodiment.
  • a system 301 can transport packet data requiring network overlay services to one or more computational units (one shown as 300 ) located on a module, which in particular embodiments, can include a connector compatible with an existing memory module.
  • a computational unit 300 can include a processor module as described in embodiments herein, or an equivalent.
  • a computational unit 300 can be capable of intercepting or otherwise accessing packets sent over a memory bus 316 and carrying out processing on such packets, including but not limited to termination or metadata processing.
  • a system memory bus 316 can be a system memory bus like those described herein, or equivalents (e.g., 228 ).
  • a system 301 can include an I/O device 302 which can receive packet or other I/O data from an external source.
  • I/O device 302 can include physical or virtual functions generated by the physical device to receive a packet or other I/O data from the network or another computer or virtual machine.
  • an I/O device 302 can include a network interface card (NIC) having input buffer 302 a (e.g., DMA ring buffer) and an I/O virtualization function 302 b.
  • NIC network interface card
  • an I/O device 302 can write a descriptor including details of the necessary memory operation for the packet (i.e. read/write, source/destination). Such a descriptor can be assigned a virtual memory location (e.g., by an operating system of the system 301 ). I/O device 302 then communicates with an input output memory management unit (IOMMU) 304 which can translate virtual addresses to corresponding physical addresses with an IOMMU function 304 b . In the particular embodiment shown, a translation look-aside buffer (TLB) 304 a can be used for such translation.
  • IOMMU input output memory management unit
  • TLB translation look-aside buffer
  • Virtual function reads or writes data between I/O device and system memory locations can then be executed with a direct memory transfer (e.g., DMA) via a memory controller 306 b of the system 301 .
  • An I/O device 302 can be connected to IOMMU 304 by a host bus 312 .
  • a host bus 312 can be a peripheral interconnect (PCI) type bus.
  • IOMMU 304 can be connected to a host processing section 306 at a central processing unit I/O (CPUIO) 306 a .
  • such a connection 314 can support a HyperTransport (HT) protocol.
  • HT HyperTransport
  • a host processing section 306 can include the CPUIO 306 a , memory controller 306 b , processing core 306 c and corresponding provisioning agent 306 d.
  • a computational unit 300 can interface with the system bus 316 via standard in-line module connection, which in very particular embodiments can include a DIMM type slot.
  • a memory bus 316 can be a DDR3 type memory bus. Alternate embodiments can include any suitable system memory bus.
  • Packet data can be sent by memory controller 306 b via memory bus 316 to a DMA slave interface 310 a .
  • DMA slave interface 310 a can be adapted to receive encapsulated read/write instructions from a DMA write over the memory bus 316 .
  • a hardware scheduler ( 308 b/c/d /e/h) can perform traffic management on incoming packets by categorizing them according to flow using session metadata. Packets can be queued for output in an onboard memory ( 310 b / 308 a / 308 m ) based on session priority.
  • the hardware scheduler determines that a packet for a particular session is ready to be processed by the offload processor 308 i , the onboard memory is signaled for a context switch to that session. Utilizing this method of prioritization, context switching overhead can be reduced, as compared to conventional approaches. That is, a hardware scheduler can handle context switching decisions and thus optimize the performance of the downstream resource (e.g., offload processor 308 i ).
  • an offload processor 308 i can be a “wimpy core” type processor.
  • a host processor 306 c can be a “brawny core” type processor (e.g., an x86 or any other processor capable of handling “heavy touch” computational operations).
  • an I/O device 302 can be configured to trigger host processor interrupts in response to incoming packets, according to embodiments, such interrupts can be disabled, thereby reducing processing overhead for the host processor 306 c .
  • an offload processor 308 i can include an ARM, ARC, Tensilica, MIPS, Strong/ARM or any other processor capable of handling “light touch” operations.
  • an offload processor can run a general purpose operating system for executing a plurality of sessions, which can be optimized to work in conjunction with the hardware scheduler in order to reduce context switching overhead.
  • a system 301 can receive packets from an external network over a network interface.
  • the packets are destined for either a host processor 306 c or an offload processor 308 i based on the classification logic and schematics employed by I/O device 302 .
  • I/O device 302 can operate as a virtualized NIC, with packets for a particular logical network or to a certain virtual MAC (VMAC) address can be directed into separate queues and sent over to the destination logical entity.
  • VMAC virtual MAC
  • Such an arrangement can transfer packets to different entities.
  • each such entity can have a virtual driver, a virtual device model that it uses to communicate with connected virtual network.
  • multiple devices can be used to redirect traffic to specific memory addresses. So, each of the network devices operates as if it is transferring the packets to the memory location of a logical entity. However, in reality, such packets are transferred to memory addresses where they can be handled by one or more offload processors (e.g., 308 i ). In particular embodiments such transfers are to physical memory addresses, thus logical entities can be removed from the processing, and a host processor can be free from such packet handling.
  • offload processors e.g., 308 i
  • embodiments can be conceptualized as providing a memory “black box” to which specific network data can be fed.
  • a memory black box can handle the data (e.g., process it) and respond back when such data is requested.
  • I/O device 302 can receive data packets from a network or from a computing device.
  • the data packets can have certain characteristics, including transport protocol number, source and destination port numbers, source and destination IP addresses, for example.
  • the data packets can further have metadata that is processed ( 308 d ) that helps in their classification and management.
  • I/O device 302 can include, but is not limited to, peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with a host motherboard via PCI or PCIe bus (e.g., 312 ).
  • PCI peripheral component interconnect
  • PCIe PCI express
  • Examples of I/O devices include a network interface controller (NIC), a host bus adapter, a converged network adapter, an ATM network interface, etc.
  • the I/O device may be virtualized to provide for multiple virtual devices each of which can perform some of the functions of the physical I/O device.
  • the IO virtualization program (e.g., 302 b ) according to an embodiment, can redirect traffic to different memory locations (and thus to different offload processors attached to modules on a memory bus).
  • an I/O device 302 e.g., a network card
  • CF controlling function
  • IOV input/output virtualization
  • VF virtual function
  • Each virtual function interface may be provided with resources during runtime for dedicated usage.
  • Examples of the CF and VF may include the physical function and virtual functions under schemes such as Single Root I/O Virtualization or Multi-Root I/O Virtualization architecture.
  • the CF acts as the physical resources that sets up and manages virtual resources.
  • the CF is also capable of acting as a full-fledged IO device.
  • the VF is responsible for providing an abstraction of a virtual device for communication with multiple logical entities/multiple memory regions.
  • the operating system/the hypervisor/any of the virtual machines/user code running on a host processor 306 c may be loaded with a device model, a VF driver and a driver for a CF.
  • the device model may be used to create an emulation of a physical device for the host processor 306 c to recognize each of the multiple VFs that are created.
  • the device model may be replicated multiple times to give the impression to a VF driver (a driver that interacts with a virtual IO device) that it is interacting with a physical device of a particular type.
  • a certain device module may be used to emulate a network adapter such as the Intel® Ethernet Converged Network Adapter(CNA) X540-T2, so that the I/O device 302 believes it is interacting with such an adapter.
  • each of the virtual functions may have the capability to support the functions of the above said CNA, i.e., each of the Physical Functions should be able to support such functionality.
  • the device model and the VF driver can be run in either privileged or non-privileged mode. In some embodiments, there is no restriction with regard to who hosts/runs the code corresponding to the device model and the VF driver. The code, however, has the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created.
  • An application or provisioning agent 306 d may create a virtual I/O address space for each VF, during runtime and allocate part of the physical address space to it. For example, if an application handling the VF driver instructs it to read or write packets from or to memory addresses 0xaaaa to 0xfff, the device driver may write I/O descriptors into a descriptor queue with a head and tail pointer that are changed dynamically as queue entries are filled.
  • the data structure may be of another type as well, including but not limited to a ring structure 302 a or hash table.
  • the VF can read from or write data to the address location pointed to by the driver. Further, on completing the transfer of data to the address space allocated to the driver, interrupts, which are usually triggered to the host processor to handle said network packets, can be disabled. Allocating a specific I/O space to a device can include allocating said IO space a specific physical memory space occupied.
  • the descriptor may comprise only a write operation, if the descriptor is associated with a specific data structure for handling incoming packets. Further, the descriptor for each of the entries in the incoming data structure may be constant so as to redirect all data write to a specific memory location. In an alternate embodiment, the descriptor for consecutive entries may point to consecutive entries in memory so as to direct incoming packets to consecutive memory locations.
  • said operating system may create a defined physical address space for an application supporting the VF drivers and allocate a virtual memory address space to the application or provisioning agent 306 d , thereby creating a mapping for each virtual function between said virtual address and a physical address space.
  • Said mapping between virtual memory address space and physical memory space may be stored in IOMMU tables (e.g., a TLB 304 a ).
  • the application performing memory reads or writes may supply virtual addresses to say virtual function, and the host processor OS may allocate a specific part of the physical memory location to such an application.
  • VF may be configured to generate requests such as read and write which may be part of a direct memory access (DMA) read or write operation, for example.
  • the virtual addresses is be translated by the IOMMU 304 to their corresponding physical addresses and the physical addresses may be provided to the memory controller for access. That is, the IOMMU 304 may modify the memory requests sourced by the I/O devices to change the virtual address in the request to a physical address, and the memory request may be forwarded to the memory controller for memory access.
  • the memory request may be forwarded over a bus 314 that supports a protocol such as HyperTransport 314 .
  • the VF may in such cases carry out a direct memory access by supplying the virtual memory address to the IOMMU 304 .
  • said application may directly code the physical address into the VF descriptors if the VF allows for it. If the VF cannot support physical addresses of the form used by the host processor 306 c , an aperture with a hardware size supported by the VF device may be coded into the descriptor so that the VF is informed of the target hardware address of the device. Data that is transferred to an aperture may be mapped by a translation table to a defined physical address space in the system memory.
  • the DMA operations may be initiated by software executed by the processors, programming the I/O devices directly or indirectly to perform the DMA operations.
  • computational unit 300 can be implemented with one or more FPGAs.
  • computational unit 300 can include FPGA 310 in which can be formed a DMA slave device module 310 a and arbiter 310 f .
  • a DMA slave module 310 a can be any device suitable for attachment to a memory bus 316 that can respond to DMA read/write requests.
  • a DMA slave module 310 a can be another interface capable of block data transfers over memory bus 316 .
  • the DMA slave module 310 a can be capable of receiving data from a DMA controller (when it performs a read from a ‘memory’ or from a peripheral) or transferring data to a DMA controller (when it performs a write instruction on the DMA slave module 310 a ).
  • the DMA slave module 310 a may be adapted to receive DMA read and write instructions encapsulated over a memory bus, (e.g., in the form of a DDR data transmission, such as a packet or data burst), or any other format that can be sent over the corresponding memory bus.
  • a DMA slave module 310 a can reconstruct the DMA read/write instruction from the memory R/W packet.
  • the DMA slave module 310 a may be adapted to respond to these instructions in the form of data reads/data writes to the DMA master, which could either be housed in a peripheral device, in the case of a PCIe bus, or a system DMA controller in the case of an ISA bus.
  • I/O data that is received by the DMA device 310 a can then queued for arbitration.
  • Arbitration can include the process of scheduling packets of different flows, such that they are provided access to available bandwidth based on a number of parameters.
  • an arbiter 310 f provides resource access to one or more requestors. If multiple requestors request access, an arbiter 310 f can determine which requestor becomes the accessor and then passes data from the accessor to the resource interface, and the downstream resource can begin execution on the data. After the data has been completely transferred to a resource, and the resource has competed execution, the arbiter 310 f can transfer control to a different requestor and this cycle repeats for all available requestors. In the embodiment of FIG. 3 arbiter 310 f can notify other portions of computational unit 300 (e.g., 308 ) of incoming data.
  • a computation unit 300 can utilize an arbitration scheme shown in U.S. Pat. No. 7,813,283, issued to Dalal on Oct. 12, 2010, the contents of which are incorporated herein by reference.
  • Other suitable arbitration schemes known in art could be implemented in embodiments herein.
  • the arbitration scheme of the current invention might be implemented using an OpenFlow switch and an OpenFlow controller.
  • computational unit 300 can further include notify/prefetch circuits 310 c which can prefetch data stored in a buffer memory 310 b in response to DMA slave module 310 a , and as arbitrated by arbiter 310 f . Further, arbiter 310 f can access other portions of the computational unit 300 via a memory mapped I/O ingress path 310 e and egress path 310 g.
  • a hardware scheduler can include a scheduling circuit 308 b/n to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata. Such classification can be performed by classifier 308 e.
  • session metadata 308 d can serve as the criterion by which packets are prioritized and scheduled and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows.
  • the scheduling discipline chosen for this prioritization, or traffic management (TM) can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), delay jitter (temporally shifting cells of a flow by different amounts) and by not admitting a connection (e.g., cannot simultaneously guarantee existing service level agreements (SLAs) with an additional flow's SLA).
  • SLAs service level agreements
  • computational unit 300 can serve as part of a switch fabric, and provide traffic management with depth-limited output queues, the access to which is arbitrated by a scheduling circuit 308 b/n .
  • Such output queues are managed using a scheduling discipline to provide traffic management for incoming flows.
  • the session flows queued in each of these queues can be sent out through an output port to a downstream network element.
  • a scheduler circuit 308 b/n can allocate a priority to each of the output queues and carry out reordering of incoming packets to maintain persistence of session flows in these queues.
  • a scheduler circuit 308 b/n can be used to control the scheduling of each of these persistent sessions into a general purpose operating system (OS) 308 j , executed on an offload processor 308 i .
  • OS operating system
  • Packets of a particular session flow can belong to a particular queue.
  • the scheduler circuit 308 b/n may control the prioritization of these queues such that they are arbitrated for handling by a general purpose (GP) processing resource (e.g., offload processor 308 i ) located downstream.
  • GP general purpose
  • An OS 308 j running on a downstream processor 308 i can allocate execution resources such as processor cycles and memory to a particular queue it is currently handling.
  • the OS 308 j may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element 308 i as a separate entity.
  • Dedicated computing resources e.g., 308 i
  • memory space and session context information for each of the sessions can provide a way of handling, processing and/or terminating each of the session flows at the general purpose processor 308 i .
  • the scheduler circuit 308 b/n can exploit this functionality of the execution resource to queue session flows for scheduling downstream.
  • the scheduler circuit 308 b/n can be informed of the state of the execution resource(s) (e.g., 308 i ), the current session that is run on the execution resource; the memory space allocated to it, the location of the session context in the processor cache.
  • a scheduler circuit 308 b/n can further include switching circuits to change execution resources from one state to another.
  • the scheduler circuit 308 b/n can use such a capability to arbitrate between the queues that are ready to be switched into the downstream execution resource.
  • the downstream execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the scheduler circuit 308 b/n to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.
  • a scheduler circuit 308 b/n can schedule different sessions on a downstream processing resource, wherein the two are operated in coordination to reduce the overhead during context switches.
  • An important factor in decreasing the latency of services and engineering computational availability can be hardware context switching synchronized with network queuing.
  • a pipeline coordinates swapping in of the cache (e.g., L2 cache) of the corresponding resource (e.g., 308 i ) and transfers the reassembled I/O data into the memory space of the executing process.
  • the scheduler circuit ( 308 b/n ) can enable queued data from an I/O device 302 to continue scheduling the thread.
  • a maximum context size can be assumed as data processed.
  • a queue can be provisioned as the greater of computational resource and network bandwidth resource.
  • a computation resource can be an ARM A9 processor running at 800 MHz, while a network bandwidth can be 3 Gbps of bandwidth.
  • embodiments can utilize computation having many parallel sessions (such that the hardware's prefetching of session-specific data offloads a large portion of the host processor load) and having minimal general purpose processing of data.
  • a scheduler circuit 308 b/n can be conceptualized as arbitrating, not between outgoing queues at line rate speeds, but arbitrating between terminated sessions at very high speeds.
  • the stickiness of sessions across a pipeline of stages, including a general purpose OS, can be a scheduler circuit optimizing any or all such stages of such a pipeline.
  • a scheduling scheme can be used as shown in U.S. Pat. No. 7,760,715 issued to Dalal on Jul. 20, 2010, incorporated herein by reference. This scheme can be useful when it is desirable to rate limit the flows for preventing the downstream congestion of another resource specific to the over-selected flow, or for enforcing service contracts for particular flows.
  • Embodiments can include arbitration scheme that allows for service contracts of downstream resources, such as general purpose OS that can be enforced seamlessly.
  • a hardware scheduler can provide for the classification of incoming packet data into session flows based on session metadata. It can further provide for traffic management of these flows before they are arbitrated and queued as distinct processing entities on the offload processors.
  • offload processors can be general purpose processing units capable of handling packets of different application or transport sessions. Such offload processors can be low power processors capable of executing general purpose instructions.
  • the offload processors could be any suitable processor, including but not limited to: ARM, ARC, Tensilica, MIPS, StrongARM or any other processor that serves the functions described herein.
  • Such offload processors have a general purpose OS running on them, wherein the general purpose OS is optimized to reduce the penalty associated with context switching between different threads or group of threads.
  • context switches on host processors can be computationally intensive processes that require the register save area, process context in the cache and TLB entries to be restored if they are invalidated or overwritten.
  • Instruction Cache misses in host processing systems can lead to pipeline stalls and data cache misses lead to operation stall and such cache misses reduce processor efficiency and increase processor overhead.
  • an OS 308 j running on the offload processors 308 i in association with a scheduler circuit 308 b/n can operate together to reduce the context switch overhead incurred between different processing entities running on it.
  • Embodiments can include a cooperative mechanism between a scheduler circuit and the OS on the offload processor 308 i , wherein the OS sets up session context to be physically contiguous (physically colored allocator for session heap and stack) in the cache; then communicates the session color, size, and starting physical address to the scheduler circuit upon session initialization.
  • a scheduler circuit can identify the session context in the cache by using these parameters and initiate a bulk transfer of these contents to an external low latency memory (e.g., 308 g ).
  • a local memory 308 g can be low latency memory, such as a reduced latency dynamic random access memory (RLDRAM), as but one very particular embodiment.
  • RLDRAM reduced latency dynamic random access memory
  • session context can be identified distinctly in the cache.
  • context size can be limited to ensure fast switching speeds.
  • embodiments can include a bulk transfer mechanism to transfer out session context to a local memory 308 g .
  • the cache contents stored therein can then be retrieved and prefetched during context switch back to a previous session.
  • Different context session data can be tagged and/or identified within the local memory 308 g for fast retrieval.
  • context stored by one offload processor may be recalled by a different offload processor.
  • multiple offload processing cores can be integrated into a computation FPGA 308 .
  • Multiple computational FPGAs can be arbitrated by arbitrator circuits in another FPGA 310 .
  • the combination of computational FPGAs (e.g., 308 ) and arbiter FPGAs (e.g., 310 ) are referred to as “XIMM” modules or “Xockets DIMM modules” (e.g., computation unit 300 ).
  • these XIMM modules can provide integrated traffic and thread management circuits that broker execution of multiple sessions on the offload processors.
  • FIG. 3 also shows an offload processor tunnel connection 308 k , as well as a memory interface 308 m and port 3081 (which can be an accelerator coherency port (ACP)).
  • Memory interface 308 m can access buffer memory 308 a.
  • FIG. 4 illustrates an example embodiment of a scheduling process 400 for access to offload processing resources according to a very particular embodiment.
  • a scheduler e.g., hardware scheduler
  • the scheduler can be responsible for controlling the execution of a session on the OS.
  • the scheduler can decide when to remove a current session from execution and cause another session to be executed.
  • a session may comprise of a thread or a group of threads on an offload processor.
  • the hardware scheduler may make a context switching decision.
  • the scheduler may decide to context switch if the packet is for a different session.
  • a method 400 can wait for packets or other data ( 402 ). Incoming packets can be received by a monitor buffer, queue or file. Once a packet or service level specification (SLS) has been received, there may be a check to ensure other conditions are met ( 406 ). If the packet/data has arrived (and optionally, other conditions met, such as those noted above) (Yes from 406 ), a packet session status is determined ( 408 ). If the packet is part of a current session (Yes from 408 ), it can be queued for the current session ( 412 ) and processed as part of the current session ( 410 ). In some embodiments, this can include hardware scheduler queuing the packet and sending it to an offload processor for processing.
  • SLS packet or service level specification
  • a packet is not part of a current session (No from 408 ), it can be determined if the packet is for a previous session ( 414 ). If the packet is not from a previous session (No from 414 ), it can be determined if there is enough memory for a new session ( 416 ). If there is enough memory (Yes from 416 ), when the offload processor(s) is ready ( 428 ), the transfer of context data can be made to the cache memory of the processor(s) ( 430 ). Once such a transfer is complete, the session can run ( 410 ).
  • the packet is from a previous session (Yes from 414 ) or there is not enough memory for a new session (No from 416 ), it can be determined if the previous session or new session is of the same color ( 418 ). If this is not the case, a switch can be made to the previous session or new session ( 420 ). A least recently uses (LRU) cache entity can be flushed, and the previous session context can be retrieved, or the new session context created. The packets of this retrieved/new session can be assigned a new color which can be retained. In some embodiments, this can include reading context data stored in a low latency memory to the cache of an offload processor.
  • LRU least recently uses
  • a previous/new session is of the same color (Yes from 418 )
  • a check can be made to see if the color pressure can be exceeded ( 422 ). If this is not possible, but another color is available (“No, other color available” from 422 ), a switch to the previous or new session can be made (i.e., 420 ). If the color pressure can be excluded, or it cannot, but no other color is available (“Yes/No, other color unavail.”), an LRU cache entity of the same color can be flushed, and the previous session context can be retrieved, or the new session context created ( 424 ). These packets will retain their assigned color. Again, in some embodiments, this can include reading context data stored in a low latency memory to the cache of an offload processor.
  • the new session can be initialized ( 426 ).
  • the offload processor(s) are ready ( 428 )
  • the transfer of context data can be made to the cache memory of the processor(s) ( 430 ). Once such a transfer is complete, the session can run ( 410 ).
  • the offload processor While the offload processor is processing a packet ( 410 ), there is a periodic check to see if the packet has finished processing ( 432 ) and return if processing is not done (No, dequeue packets from 432 ). If the packet is done (Yes from 432 ), a hardware scheduler can looks to its output queue for more packets ( 434 ). If there are more packets (Yes from 434 ) and the offload processor is ready to receive them (Yes from 436 ), the packets can transferred to the offload processor. In some embodiments, packets can be queued into the offload processor as soon as a “ready for processing” message is triggered by the offload processor. After the offload processor is done processing the packets, the entire cycle can repeat beginning with the hardware scheduler checking to which session the packet belongs, etc.
  • the hardware scheduler can check to see if there are other packets available. If there are no more packets in the queue, the hardware scheduler can goes into a wait mode, waiting for rate limit until more packets arrive. Thus, the hardware scheduler works quickly and efficiently to manage and supply packets going to the downstream resource.
  • a session can be preempted by the arrival of a packet from a different session, resulting in the new packet being processed as noted above ( 406 ).

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Abstract

A method for scheduling packet processing is disclosed. The method can include classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with network packets transported to a classification circuit using a memory bus having a defined memory transport protocol, reordering network packets received from the first multiple input/output queues using a scheduling circuit and placing the reordered network packets into a second multiple input/output queues, directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports using an arbitration circuit, and modifying network packets using multiple offload processors, each offload processor coupled to at least one of the multiple output ports, the offload processors configured to direct modified network packets back to the memory bus.

Description

    PRIORITY CLAIMS
  • This application claims the benefit of U.S. Provisional Patent Applications 61/753,892 filed on Jan. 17, 2013, 61/753,895 filed on Jan. 17, 2013, 61/753,899 filed on Jan. 17, 2013, 61/753,901 filed on Jan. 17, 2013, 61/753,903 filed on Jan. 17, 2013, 61/753,904 filed on Jan. 17, 2013, 61/753,906 filed on Jan. 17, 2013, 61/753,907 filed on Jan. 17, 2013, and 61/753,910 filed on Jan. 17, 2013, the contents all of which are incorporated by reference herein.
  • TECHNICAL FIELD
  • Described embodiments relate to scheduling and traffic management services for computer systems that can be provided by a memory bus connected module with offload processors.
  • BACKGROUND
  • Efficient managing of network packet flow and processing is critical for high performance networked computing systems. Network packet flow can be highly variable, depending on hardware configurations, process flows and data flows, with data processing needs varying over several orders of magnitude on time scales that can range from seconds to hours. Substantial improvements in network service are made possible by systems that can flexibly process a data flow, recognize or characterize patterns in the data flow, and improve routing and processing decisions for the data flow. This is of particular importance for networked computer environment using packet switching communication. For example, delays in data flow are often created due to network security required packet inspection. Such packet inspection may be directed at either a header of the packet or a payload of the packet, and can include processor content matching, behavioral anomaly detection, “black” or “white” listing comparisons, or the like. Other high packet processing applications can include encryption/decryption, quality of service controlled packet reassembly, streaming sensor data, or video or audio processing. Without an efficient mechanism for scheduling packet processing arriving as part of a complex data flow system, users may encounter unacceptable delays in network system response.
  • Commonly available traffic management circuits supporting a packet switch fabric capable of handling complex data flow streams often include depth-limited output queues, the access to which is arbitrated by a scheduling circuit. The input queues are managed using a scheduling discipline to provide traffic management for incoming data flows. Schedulers may allocate or identify a data flow priorities and provide output port to each of these data flows. If multiple data flows compete for the same output port, time multiplexed access to each of the output ports can be provided, or alternatively multiple data flows contending for an output port may be arbitrated by an arbitration circuit before being sent out over an output port. However, a traffic management circuit typically has limited or no access to information relating to handling and management of data by downstream memory or processing elements. For example, based on an allocation of priority, data flow performance can be improved if incoming packets can be dynamically reordered in a buffer to help maintain persistence of session flows in these queues. The scheduling discipline chosen for such packet processing prioritization or traffic management (TM), can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), or delay jitter (temporally shifting cells of a flow by different amounts).
  • SUMMARY
  • This disclosure describes embodiments of systems, hardware and methods suitable to act as a scheduling system for a packet processing system. The system includes a classification circuit connected to a memory bus and configurable to classify network packets. The classification circuit can place the classified network packets into first multiple input/output queues. A scheduling circuit can reorder the network packets received from the classification circuit through the first multiple input/output queues and place the reordered network packets into second multiple input/output queues. An arbitration circuit directs network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports. Multiple offload processors, each connected to one of the multiple output ports, are respectively configured to modify network packets.
  • In certain embodiments the memory bus supports direct memory access, and multiple offload processors can direct modified packets back to the memory bus. In addition, the classification circuit can classify network packets based on session metadata. In still other embodiments, the scheduling circuit can direct network packets based on availability of respective multiple offload processors; reorder network packets according to session priority; initiates a context switch for the multiple offload processors; transfer network packets into a defined traffic management queue; check with each of the multiple offload processors to determine if respective network packet processing is complete; or operate in preemption mode to control session execution.
  • Another embodiment is a method for scheduling packet processing, including the step of classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with packets transported to a classification circuit using a memory bus having a defined memory transport protocol. Reordered network packets received from the first multiple input/output queues using a scheduling circuit can be placed into a second multiple input/output queues, where an arbitration circuit directs network packets received from the scheduling circuit through the second multiple input/output queues into multiple output ports. These network packets can be modified using multiple offload processors, each offload processor respectively connected to one of the multiple output ports, with the respective offload processers able to direct modified packets back to the memory bus.
  • Another embodiment described includes a memory bus connected module for scheduling services for network packet processing. The module includes a memory bus connection and a scheduling circuit for reordering the network packets received from the memory bus connection and placing the reordered network packets into multiple input/output queues. Multiple offload processors are connected to the memory bus connection, with each offload processor capable of modifying network packets placed into multiple input/output queues. The memory bus connection can be compatible with a memory bus socket, and in certain embodiments be formed to fit into a dual in-line memory module (DIMM) socket.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1-0 shows a traffic management and scheduler system according to an embodiment.
  • FIG. 1-1 shows a scheduling process according to an embodiment.
  • FIG. 1-2 shows a module supporting multiple scheduling circuits and an arbitration circuit according to an embodiment.
  • FIGS. 2-0 to 2-3 show processor modules according to various embodiments.
  • FIG. 2-4 shows a conventional dual-in-line memory module.
  • FIG. 2-5 shows a system according to another embodiment.
  • FIGS. 3 shows one particular implementation of a memory bus connected offload processor that can be included in embodiments.
  • FIG. 4 shows an exemplary flow chart for a scheduling process according to an embodiment.
  • DETAILED DESCRIPTION
  • Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show processing systems and methods for scheduling packet flow in a packet processing systems. Such scheduling can be performed by, or with the use of, offload modules connect to a memory bus of a system. Such offload processors can be in addition to any host processors connected to the system memory bus, and, in some embodiments, process packets transferred over the system memory bus independent of any host processors. In very particular embodiments, processing modules can populate physical slots for connecting in-line memory modules (e.g., DIMMs) to a system memory bus.
  • FIG. 1-0 is a diagram of a system 100 for providing scheduling and traffic management services. A system 100 can include a switch 106, host processor section 108/110, memory controller 112, and offload processing section 116/116/118. In the particular embodiment shown, host processor section can include a switch 106, a switching fabric 108, host processor(s) 110, and a bus interconnect 109 connected to memory controller 112. Further, offload processing section can be in communication with memory controller 112, and can include a switch 114, scheduler 116 and offload processor(s) 118.
  • In operation, a switch 106 can receive and/or transmit data packets 104 from data source 102. A data source 102 can be any suitable source of packet data, including the Internet, a network cloud, inter- or intra-data center networks, cluster computers, rack systems, multiple or individual servers or personal computers, or the like. Data can be packet or switch based, although in particular embodiments non-packet data is generally converted or encapsulated into packets for ease of handling. The data packets typically have certain characteristics, including transport protocol number, source and destination port numbers, or source and destination (Internet Protocol) IP addresses. The data packets can further have associated metadata that helps in packet classification and management.
  • A switch 106 can be a virtual switch (an I/O device). A switch 106 can include, but is not limited to, devices compatible with peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with host motherboard via PCI or PCIe bus 107. The switch 106 can include a network interface controller (NIC), a host bus adapter, a converged network adapter, or a switched or an asynchronous transfer mode (ATM) network interface. In some embodiments, a switch 106 can employ IO virtualization schemes such as a single root I/O virtualization (SR-IOV) interface to make a single network I/O device appear as multiple devices. SR-IOV permits separate access to resources among various PCIe hardware functions by providing both physical control and virtual functions. In certain embodiments, the switch 106 can support OpenFlow or similar software defined networking to abstract out of the control plane. The control plane of the first virtual switch performs functions such as route determination, target node identification etc.
  • A switch 106 can be capable of examining network packets, and using its control plane to create appropriate output ports for network packets. Based on route calculation for the network packets or data flows associated with the network packets, the forwarding plane of the switch 106 can transfer the packets to an output interface. An output interface of the switch may be connected with an IO bus, and in certain embodiments the switch 106 may have the capability to directly (or indirectly, via an I/O fabric 108) transfer the network packets to a memory bus interconnect 109 for a memory read or write operation (direct memory access operation). Functionally, for certain applications the network packets can be assigned for transport to specific memory locations based on control plane functionality.
  • Switch 106, connected to an IO fabric 108 and memory bus interconnect 109, can also be connected to host processor(s) 110. Host processor(s) 110 can include one or more host processors which can provide computational services including a provisioning agent 111. The provisioning agent 111 can be part of an operating system or user code running on the host processor(s) 110. The provisioning agent 111 typically initializes and interacts with virtual function drivers provided by system 100. The virtual function driver can be responsible for providing the virtual address of the memory space where a direct memory addressing (DMA) is needed. Each device driver can be allocated virtual addresses that map to the physical addresses. A device model can be used to create an emulation of a physical device for the host processor 110 to recognize each of the multiple virtual functions (VF) that can be created. The device model can be replicated multiple times to give the impression to VF drivers (a driver that interacts with a virtual IO device) that they are interacting with a physical device. For example, a certain device model may be used to emulate a network adapter that the VF driver can act to connect. The device model and the VF driver can be run in either privileged or non-privileged mode. There can be no restriction with regard to which device hosts/runs the code corresponding to the device model and the VF driver. The code, however, can have the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created. In certain embodiments the operating system can also create a defined physical address space for applications supported by VF drivers. Further, the host operating system can allocate a virtual memory address space to the application or provisioning agent. The provisioning agent 111 can broker with the host operating system to create a mapping between virtual addresses and a subset of the available physical address space. The provisioning agent 111 can be responsible for creating each VF driver and allocating it a defined virtual address space.
  • By operation of such memory mapping, data (e.g., packet data) can be transmitted from switch 106 offload processor section 114/116/118. A second switch 114 can also be connected to the memory controller 112 by memory bus 109. A second switch 114 can be a virtual switch, and can receive and switch traffic originating from the memory bus 109 both to and from offload processor(s) 118. Traffic may include, but is not limited to, data flows to virtual devices created and assigned by the provisioning agent 111, with processing supported by offload processors 118. The forwarding plane of the second switch 114 can transports packets from a memory bus 109 to offload processors 118 or from the offload processors 118 back onto the memory bus 109. For certain applications, the described system architecture can allow relatively direct communication of network packets to the offload processors 118 with minimal or no interruptions to a host processor(s) 110. The second switch 114 can be capable of receiving packets and classifying them prior to distribution to different hardware schedulers based on a defined arbitration and scheduling scheme. The hardware scheduler 116 receives packets that can be assigned to flow sessions that are scheduled for processing in one or more separate sessions run by offload processor(s) 118.
  • In particular embodiments, scheduler 116 can be employed to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata. Session metadata often serve as the criterion by which packets are prioritized and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. Packets of a session that are reordered based on session metadata can be sent over to specific traffic managed queues that are arbitrated out to output ports using an arbitration circuit (not shown). The arbitration circuit can feed these packet flows to a downstream packet processing/terminating resource directly. Certain embodiments provide for integration of thread and queue management so as to enhance the throughput of downstream resources handling termination of network data through above said threads.
  • As will be understand, multiple types of conventional input/output busses such as PCI, Fibre Channel can be used in system embodiments described herein. The bus architecture can also be based on relevant JEDEC standards, on DIMM data transfer protocols, on Hypertransport, or any other suitable high speed, low latency interconnection system. Offload processor(s) 118 may include double data rate (DDR) dynamic random access memory (DRAM), reduced latency DRAM (RLDRAM), embedded DRAM, next generation stacked memory such as Hybrid Memory Cube (HMC), flash, or other suitable memory, separate logic or bus management chips, programmable units such as field programmable gate arrays (FPGAs), custom designed application specific integrated circuits (ASICs) and an energy efficient, general purpose processor such as those based on ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC architectures. Host processor(s) 110 can include general purpose processor(s), including those based on Intel or AMD x86 architecture, Intel Itanium architecture, MIPS architecture, SPARC architecture or the like.
  • FIG. 1-1 illustrates one embodiment of a hardware scheduled data flow method 140 suitable for operation in conjunction with an embodiment like that of FIG. 1-0. As seen in flowchart 140, a hardware scheduler can manage traffic by segregating packets based on sessions (141). In some embodiments, sessions are identified by metadata of the packets. Sessions can be prioritized and queued (142) and a general purpose operating system (OS) running on one or more offload processors can be used control execution of a current session (143). A hardware scheduler can use the current state of the OS, including numbers of session, state of the session, feedback from the OS relating to processing resources or future scheduling requirements, etc., to make scheduling decisions or arbitration between competing processes for memory resources (144). If certain conditions are met, the hardware scheduler can initiate a context switch in which a current session has its state stored in memory, and a new session is begun or returned to (145).
  • FIG. 1-2 illustrates one embodiment of a hardware scheduler 150 (i.e., a scheduling circuit). The hardware scheduler 150 can include input ports 152/152′, classification circuit 154, input queues (one shown as 156), scheduling circuits 158/158′, output queues (one shown as 160), arbitration circuit 162, and output ports 164/164′. Connected to the hardware scheduler can be common packet status registers 166/166′, packet buffers 168/168′, one or more cache memory ports 170 (which can be an accelerator coherency port ACP, in one particular embodiment), and a low latency memory 172. It is understood that while FIG. 1-2 shows an architecture with two input ports and two output ports, alternate embodiments can include one input and output port, or more than two such ports.
  • The hardware scheduler 150 can receive packets from an arbiter circuit (not shown) that is connected to several such hardware schedulers. The hardware scheduler 150 can receive such data at one or more input ports 152/152′. The hardware scheduler 150 can employ a classification circuit 154, which can examine incoming packets, and based on metadata present in the packets, classifies packets into different incoming queues. The classification circuit 154 can examine different packet headers, and can use an interval matching circuit to carry out segregation of incoming packets. One suitable interval matching circuit is described in U.S. Pat. No. 7,760,715 issued to Dalal on Aug. 4, 2007 (hereinafter the '715 patent). However, any other suitable classification scheme may be employed to execute the classification circuit.
  • The hardware scheduler 150 can be connected with packet status registers 166/166′ for communicating with offload processors (not shown). Registers 166/166′ can be operated upon by both the hardware scheduler 150 and an OS running on an offload processor. The hardware scheduler can also be connected with a packet buffer 168/168′ to store outgoing packets of a session or for processing to/by an offload processor OS. A detailed explanation of packet status registers and packet buffers that can be included in embodiments is given below.
  • The hardware scheduler 150 can use port 170 to access data related to a session that is currently running on an offload processor OS in the cache of the offload processor and transfer it out using a bulk transfer during a context switch to a different session. The hardware scheduler 150 can uses the cache transfer to reduce the overhead associated with the session. The hardware scheduler 150 can also use a low latency memory 172 to store the session related information from the cache for its subsequent access.
  • As noted above, a hardware scheduler 150 can have more than one input port 152/152′. The data coming into the hardware scheduler may be packet data waiting to be terminated at the offload processors or it could be packet data waiting to be processed, modified or switched out. The hardware scheduler 150 can be responsible for segregating incoming packets into corresponding application sessions based on examination of packet data. The hardware scheduler 150 can be capable of packet inspection and identifying relevant packet characteristics.
  • A hardware scheduler 150 may offload part of the network stack to free offload processors from overhead incurred from such network stack processing. A hardware scheduler 150 may carry out any of TCP/transport offload, encryption/decryption offload, segmentation and reassembly, or the like, thus allowing the offload processor to use the payload of the network packets directly.
  • In some embodiments, hardware scheduler 150 can further have the capability to transfer the packets belonging to a session into a particular traffic management queue (e.g., 156) for its scheduling (158) and transfer to an output queues (e.g., 160). The hardware scheduler 150 may be used to control the scheduling of each of these persistent sessions into a general purpose OS. The stickiness of sessions across a pipeline of stages, including a general purpose OS, can be accentuated by a scheduler circuit 150 carrying out optimizations at each of the stages in the pipeline (described in more detail below). For example, a hardware scheduler 150 can takes into account of downstream execution resources. The session flows queued in each of these queues can be sent out through an output port to a downstream network element. One particular implementation of such scheduling is shown in the '715 patent, which is incorporated herein by reference, in its entirety.
  • Referring still to FIG. 1-2, a hardware scheduler 150 may employ an arbitration circuit 162 to arbitrate or otherwise control access of multiple traffic management output queues to available output ports. Each of the output ports may be connected to one of the offload processor cores through a packet buffer 168/168′. A packet buffer 168/168′ may further include a header pool and a packet body pool. A header pool can contain only the header of packets to be processed by offload processors. Sometimes, if the size of the packet to be processed is sufficiently small, the header pool may contain the entire packet. Packets can be transferred over to the header pool/packet body pool depending on the nature of operation carried out at the offload processor. For packet processing, overlay, analytics, filtering and such other applications it might be appropriate to transfer only the packet header to the offload processors. In this case, depending on the handling of the packet header, the packet body might either be sewn together with a packet header and transferred over an egress interface, or dropped. For applications requiring the termination of packets, the entire body of the packet might be transferred. The offload processor cores may receive the packets and execute suitable application session on them to execute said packet contents.
  • A hardware scheduler 150 can schedule different sessions on a downstream processor, wherein the two are operated in coordination to reduce the overhead during context switches. A hardware scheduler 150 can be understood to arbitrate not just between outgoing queues or session flows at line rate speeds, but between terminated sessions at very high speeds. The hardware scheduler 150 can manage the queuing of sessions on the offload processor. A scheduling circuit 158/158′ can be responsible for queuing each session flow into the OS as a different OS processing entity. Scheduling circuit 158/158′ can be responsible for causing the execution of a new application session on the OS. It can indicate to the OS that packets for a new session are available based on traffic management carried out by it.
  • A hardware scheduler 150 can be informed of the state of the execution resources on the offload processors, the current session that is run on the execution resource, the memory space allocated to it, and the location of the session context in the processor cache. It can use the state of the execution resource to carry out traffic management and arbitration decisions. The hardware scheduler 150 can provide for an integration of thread management on the operating system with traffic management of incoming packets. It can induce persistence of session flows across a spectrum of components including traffic management queues and processing entities on the offload processors. An OS running on a downstream (e.g. offload) processor may allocate execution resources such as processor cycles and memory to a particular queue it is currently handling. The OS may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element as a separate entity. The fact that there are multiple sessions running on a general purpose (GP) processing resource, each handling data from a particular session flow resident in a queue on the hardware scheduler, can tightly integrate the hardware scheduler and the downstream resource. This can bring an element of persistence within session information across the traffic management and scheduling circuit and the general purpose processing resource. Further, the offload OS can be modified to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the hardware scheduler to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.
  • In effect, in some embodiments a hardware scheduler can be employed to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and can be classified using session metadata. Session metadata often serve as the criterion by which packets are prioritized and as such, incoming packets are reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. Packets of a session that are reordered based on session metadata can be sent over to specific traffic managed queues that are arbitrated out to output ports using an arbitration circuit. An arbitration circuit (e.g. 162) can feed these packet flows to a downstream packet processing/terminating resource directly. Certain embodiments provide for integration of thread and queue management so as to enhance the throughput of downstream resources handling termination of network data through above said threads.
  • Accordingly, a hardware scheduler can perform any of the following functions:
  • a) the hardware scheduler is responsible for carrying out traffic management, arbitration and scheduling of incoming network packets (and flows);
    b) hardware scheduler is responsible for offloading part of the network stack of the offload OS, so that the offload OS can be kept free of stack level processing and resources are free to carry out execution of application sessions;
    c) the hardware scheduler is responsible for classification of packets based on packet metadata, and packets classified into different session are queued in output traffic queues are sent over to the offload OS;
    d) the hardware scheduler is responsible for cooperating with minimal overhead context switching between terminated sessions on the offload OS; the hardware scheduler ensures that multiple sessions on the offload OS can be switched with as minimal overhead as possible (the ability to switch between multiple sessions on the offload sessions makes it possible to terminate multiple sessions at very high speeds, providing packet processing speeds for terminated sessions);
    d) the hardware scheduler is responsible for queuing each session flow into the OS as a different OS processing entity;
    e) the hardware scheduler is responsible for causing the execution of a new application session on the OS, it can indicate to the OS that packets for a new session are available based on traffic management carried out by it;
    f) the hardware scheduler is informed of the state of the execution resources on the offload processors, the current session that is run on the execution resource and the memory space allocated to it, the location of the session context in the processor cache. The hardware scheduler can use the state of the execution resource to carry out traffic management and arbitration decisions. The hardware scheduler can provide for an integration of thread management on the operating system with traffic management of incoming packets. It can induce persistence of session flows across a spectrum of components including traffic management queues and processing entities on the offload processors.
  • As will be understood, many of the foregoing processing tasks can be implemented on multiple threads running on multiple processing cores. Such parallelization of tasks into multiple thread contexts can provide for increased throughput. Processors architectures such as MIPS may include deep instruction pipelines to improve the number of instructions per cycle. Further, the ability to run a multi-threaded programming environment results in enhanced usage of existing processor resources. To further increase parallel execution on the hardware, processor architecture may include multiple processor cores. Multi-core architectures comprising the same type of cores, referred to as homogeneous core architectures, provide higher instruction throughput by parallelizing threads or processes across multiple cores. However, in such homogeneous core architectures, the shared resources, such as memory, are amortized over a small number of processors. In still other embodiments, multiple offload or host processors can reside on modules connected to individual rack units or blades that in turn reside on racks or individual servers. These can be further grouped into clusters and datacenters, which can be spatially located in the same building, in the same city, or even in different countries. Any grouping level can be connected to each other, and/or connected to public or private cloud internets.
  • Memory and I/O accesses can incur a high amount of processor overhead. Further, context switches in conventional general purpose processing units can be computationally intensive. It is therefore desirable to reduce context switch overhead in a networked computing resource handling a plurality of networked applications in order to increase processor throughput. Conventional server loads can require complex transport, high memory bandwidth, extreme amounts of data bandwidth (randomly accessed, parallelized, and highly available), but often with light touch processing: HTML, video, packet-level services, security, and analytics. Further, idle processors still consume more than 50% of their peak power consumption.
  • In contrast, according to embodiments herein, complex transport, data bandwidth intensive, frequent random access oriented, ‘light’ touch processing loads can be handled behind a socket abstraction created on multiple offload processor cores. At the same time, “heavy” touch, computing intensive loads can be handled by a socket abstraction on a host processor core (e.g., x86 processor cores). Such software sockets can allow for a natural partitioning of these loads between ARM and x86 processor cores. By usage of new application level sockets, according to embodiments, server loads can be broken up across the offload processing cores and the host processing cores.
  • FIGS. 2-0 to 2-5 describe aspects of hardware embodiments and methods for providing scheduling and traffic management services using processing modules. In particular embodiments, such processing modules can include DIMM mountable modules to support offload processing.
  • FIG. 2-0 is a block diagram of a processing module 200 according to one embodiment. A processing module 200 can include a physical connector 202, a memory interface 204, arbiter logic 206, offload processor(s) 208, local memory 210, and control logic 212. A connector 202 can provide a physical connection to system memory bus. This is in contrast to a host processor which can access a system memory bus via a memory controller, or the like. In very particular embodiments, a connector 202 can be compatible with a dual in-line memory module (DIMM) slot of a computing system. Accordingly, a system including multiple DIMM slots can be populated with one or more processing modules 200, or a mix of processing modules and DIMM modules.
  • A memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200. Such data transfers can include the receipt of packet data having a particular network identifier. In some embodiments, a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module 200. In very particular embodiments, a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory bus initiated by a DMA master. In some embodiments, a DMA master can be a device different from a host processor. In such configurations, processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.
  • A memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200. In some embodiments, a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module. In very particular embodiments, a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory initiated by a DMA master. In some embodiments, a DMA master can be a device different from a host processor. In such configurations, processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.
  • Arbiter logic 206 can arbitrate between conflicting accesses of data within processing module 200. In some embodiments, arbiter logic 206 can arbitrate between accesses by offload processor 208 and accesses external to the processor module 200. It is understood that a processing module 200 can include multiple locations that are operated on at the same time. It is understood that accesses arbitrated by arbiter logic 206 can include accesses to physical system memory space occupied by the processor module 200, as well as accesses to other resources (e.g., cache memory of offload or host processor). Accordingly, arbitration rules for arbiter logic 206 can vary according to application. In some embodiments, such arbitration rules are fixed for a given processor module 200. In such cases, different applications can be accommodated by switching out different processing modules. However, in alternate embodiments, such arbitration rules can be configurable.
  • Offload processor 208 can include one or more processors that can operate on data transferred over the system memory bus. In some embodiments, offload processors can run a general operating system or server applications such as Apache (as but one very particular example), enabling processor contexts to be saved and retrieved. Computing tasks executed by offload processor 208 can be handled by the hardware scheduler. Offload processors 208 can operate on data buffered in the processor module 200. In addition or alternatively, offload processors 208 can access data stored elsewhere in a system memory space. In some embodiments, offload processors 208 can include a cache memory configured to store context information. An offload processor 208 can include multiple cores or one core.
  • A processor module 200 can be included in a system having a host processor (not shown). In some embodiments, offload processors 208 can be a different type of processor as compared to the host processor. In particular embodiments, offload processors 208 can consume less power and/or have less computing power than a host processor. In very particular embodiments, offload processors 208 can be “wimpy” core processors, while a host processor can be a “brawny” core processor. However, in alternate embodiments, offload processors 208 can have equivalent computing power to any host processor. In very particular embodiments, a host processor can be an x86 type processor, while an offload processor 208 can include an ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC type processor, as but a few examples.
  • Local memory 210 can be connected to offload processor 208 to enable the storing of context information. Accordingly, an offload processor 208 can store current context information, and then switch to a new computing task, then subsequently retrieve the context information to resume the prior task. In very particular embodiments, local memory 210 can be a low latency memory with respect to other memories in a system. In some embodiments, storing of context information can include copying an offload processor 208 cache.
  • In some embodiments, a same space within local memory 210 is accessible by multiple offload processors 208 of the same type. In this way, a context stored by one offload processor can be resumed by a different offload processor.
  • Control logic 212 can control processing tasks executed by offload processor(s). In some embodiments, control logic 212 can be considered a hardware scheduler that can be conceptualized as including a data evaluator 214, scheduler 216 and a switch controller 218. A data evaluator 214 can extract “metadata” from write data transferred over a system memory bus. “Metadata”, as used herein, can be any information embedded at one or more predetermined locations of a block of write data that indicates processing to be performed on all or a portion of the block of write data and/or indicate a particular task/process to which the data belongs (e.g., classification data). In some embodiments, metadata can be data that indicates a higher level organization for the block of write data. As but one very particular embodiment, metadata can be header information of one or more network packets (which may or may not be encapsulated within a higher layer packet structure).
  • A scheduler 216 (e.g., a hardware scheduler) can order computing tasks for offload processor(s) 208. In some embodiments, scheduler 216 can generate a schedule that is continually updated as write data for processing is received. In very particular embodiments, a scheduler 216 can generate such a schedule based on the ability to switch contexts of offload processor(s) 208. In this way, on-module computing priorities can be adjusted on the fly. In very particular embodiments, a scheduler 216 can assign a portion of physical address space (e.g., memory locations within local memory 210) to an offload processor 208, according to computing tasks. The offload processor 208 can then switch between such different spaces, saving context information prior to each switch, and subsequently restoring context information when returning to the memory space.
  • Switch controller 218 can control computing operations of offload processor(s) 208. In particular embodiments, according to scheduler 216, switch controller 218 can order offload processor(s) 208 to switch contexts. It is understood that a context switch operation can be an “atomic” operation, executed in response to a single command from switch controller 218. In addition or alternatively, a switch controller 218 can issue an instruction set that stores current context information, recalls context information, etc.
  • In some embodiments, processor module 200 can include a buffer memory (not shown). A buffer memory can store received write data on board the processor module. A buffer memory can be implemented on an entirely different set of memory devices, or can be a memory embedded with logic and/or the offload processor. In the latter case, arbiter logic 206 can arbitrate access to the buffer memory. In some embodiments, a buffer memory can correspond to a portion of a system physical memory space. The remaining portion of the system memory space can correspond to other like processor modules and/or memory modules connected to the same system memory bus. In some embodiments buffer memory can be different than local memory 210. For example, buffer memory can have a slower access time than local memory 210. However, in other embodiments, buffer memory and local memory can be implemented with like memory devices.
  • In very particular embodiments, write data for processing can have an expected maximum flow rate. A processor module 200 can be configured to operate on such data at, or faster than, such a flow rate. In this way, a master device (not shown) can write data to a processor module without danger of overwriting data “in process”.
  • The various computing elements of a processor module 200 can be implemented as one or more integrated circuit devices (ICs). It is understood that the various components shown in FIG. 2-0 can be formed in the same or different ICs. For example, control logic 212, memory interface 214, and/or arbiter logic 206 can be implemented on one or more logic ICs, while offload processor(s) 208 and local memory 210 are separate ICs. Logic ICs can be fixed logic (e.g., application specific ICs), programmable logic (e.g., field programmable gate arrays, FPGAs), or combinations thereof.
  • Advantageously, the foregoing hardware and systems can provide improved computational performance as compared to traditional computing systems. Conventional systems, including those based on x86 processors, are often ill-equipped to handle such high volume applications. Even idling, x86 processors use a significant amount of power, and near continuous operation for high bandwidth packet analysis or other high volume processing tasks makes the processor energy costs one of the dominant price factors.
  • In addition, conventional systems can have issues with the high cost of context switching wherein a host processor is required to execute instructions which can include switching from one thread to another. Such a switch can require storing and recalling the context for the thread. If such context data is resident in a host cache memory, such a context switch can occur relatively quickly. However, if such context data is no longer in cache memory (i.e., a cache miss), the data must be recalled from system memory, which can incur a multi-cycle latency. Continuous cache misses during context switching can adversely impact system performance.
  • FIG. 2-1 shows a processor module 200-1 according to one very particular embodiment which is capable of reducing issues associated with high volume processing or context switching associated with many conventional server systems. A processor module 200-1 can include ICs 220-0/1 mounted to a printed circuit board (PCB) type substrate 222. PCB type substrate 222 can include in-line module connector 202, which in one very particular embodiment, can be a DIMM compatible connector. IC 220-0 can be a system-on-chip (SoC) type device, integrating multiple functions. In the very particular embodiment shown, an IC 220-0 can include embedded processor(s), logic and memory. Such embedded processor(s) can be offload processor(s) 208 as described herein, or equivalents. Such logic can be any of controller logic 212, memory interface 204 and/or arbiter logic 206, as described herein, or equivalents. Such memory can be any of local memory 210, cache memory for offload processor(s) 208, or buffer memory, as described herein, or equivalents. Logic
  • IC 220-1 can provide logic functions not included IC 220-0. FIG. 2-2 shows a processor module 200-2 according to another very particular embodiment. A processor module 200-2 can include ICs 220-2, -3, -4, -5 mounted to a PCB type substrate 222, like that of FIG. 2-1. However, unlike FIG. 2-1, processor module functions are distributed among single purpose type ICs. IC 220-2 can be a processor IC, which can be an offload processor 208. IC 220-3 can be a memory IC which can include local memory 210, buffer memory, or combinations thereof. IC 220-4 can be a logic IC which can include control logic 212, and in one very particular embodiment, can be an FPGA. IC 220-5 can be another logic IC which can include memory interface 204 and arbiter logic 206, and in one very particular embodiment, can also be an FPGA.
  • It is understood that FIGS. 2-1/2 represent but two of various implementations. The various functions of a processor module can be distributed over any suitable number of ICs, including a single SoC type IC.
  • FIG. 2-3 shows an opposing side of a processor module 200-1 or 200-2 according to a very particular embodiment. Processor module 200-3 can include a number of memory ICs, one shown as 220-6, mounted to a PCB type substrate 222, like that of FIG. 2-1. It is understood that various processing and logic components can be mounted on an opposing side to that shown. A memory IC 220-6 can be configured to represent a portion of the physical memory space of a system. Memory ICs 220-6 can perform any or all of the following functions: operate independently of other processor module components, providing system memory accessed in a conventional fashion; serve as buffer memory, storing write data that can be processed with other processor module components, or serve as local memory for storing processor context information.
  • FIG. 2-4 shows a conventional DIMM module (i.e., it serves only a memory function) that can populate a memory bus along with processor modules as described herein, or equivalents.
  • FIG. 2-5 shows a system 230 according to one embodiment. A system 230 can include a system memory bus 228 accessible via multiple in-line module slots (one shown as 226). According to embodiments, any or all of the slots 226 can be occupied by a processor module 200 as described herein, or an equivalent. In the event all slots 226 are not occupied by a processor module 200, available slots can be occupied by conventional in-line memory modules 224. In a very particular embodiment, slots 226 can be DIMM slots.
  • In some embodiments, a processor module 200 can occupy one slot. However, in other embodiments, a processor module can occupy multiple slots.
  • In some embodiments, a system memory bus 228 can be further interfaced with one or more host processors and/or input/output device (not shown).
  • Having described processor modules according to various embodiments, operations of an offload processor module capable of interfacing with server or similar system via a memory bus and according to a particular embodiment will now be described.
  • FIG. 3 shows a system 301 according to another embodiment. A system 301 can transport packet data requiring network overlay services to one or more computational units (one shown as 300) located on a module, which in particular embodiments, can include a connector compatible with an existing memory module. In some embodiments, a computational unit 300 can include a processor module as described in embodiments herein, or an equivalent. A computational unit 300 can be capable of intercepting or otherwise accessing packets sent over a memory bus 316 and carrying out processing on such packets, including but not limited to termination or metadata processing. A system memory bus 316 can be a system memory bus like those described herein, or equivalents (e.g., 228).
  • Referring still to FIG. 3, a system 301 can include an I/O device 302 which can receive packet or other I/O data from an external source. In some embodiments I/O device 302 can include physical or virtual functions generated by the physical device to receive a packet or other I/O data from the network or another computer or virtual machine. In the very particular embodiment shown, an I/O device 302 can include a network interface card (NIC) having input buffer 302 a (e.g., DMA ring buffer) and an I/O virtualization function 302 b.
  • According to embodiments, an I/O device 302 can write a descriptor including details of the necessary memory operation for the packet (i.e. read/write, source/destination). Such a descriptor can be assigned a virtual memory location (e.g., by an operating system of the system 301). I/O device 302 then communicates with an input output memory management unit (IOMMU) 304 which can translate virtual addresses to corresponding physical addresses with an IOMMU function 304 b. In the particular embodiment shown, a translation look-aside buffer (TLB) 304 a can be used for such translation. Virtual function reads or writes data between I/O device and system memory locations can then be executed with a direct memory transfer (e.g., DMA) via a memory controller 306 b of the system 301. An I/O device 302 can be connected to IOMMU 304 by a host bus 312. In one very particular embodiment, a host bus 312 can be a peripheral interconnect (PCI) type bus. IOMMU 304 can be connected to a host processing section 306 at a central processing unit I/O (CPUIO) 306 a. In the embodiment shown, such a connection 314 can support a HyperTransport (HT) protocol.
  • In the embodiment shown, a host processing section 306 can include the CPUIO 306 a, memory controller 306 b, processing core 306 c and corresponding provisioning agent 306 d.
  • In particular embodiments, a computational unit 300 can interface with the system bus 316 via standard in-line module connection, which in very particular embodiments can include a DIMM type slot. In the embodiment shown, a memory bus 316 can be a DDR3 type memory bus. Alternate embodiments can include any suitable system memory bus. Packet data can be sent by memory controller 306 b via memory bus 316 to a DMA slave interface 310 a. DMA slave interface 310 a can be adapted to receive encapsulated read/write instructions from a DMA write over the memory bus 316.
  • A hardware scheduler (308 b/c/d/e/h) can perform traffic management on incoming packets by categorizing them according to flow using session metadata. Packets can be queued for output in an onboard memory (310 b/308 a/308 m) based on session priority. When the hardware scheduler determines that a packet for a particular session is ready to be processed by the offload processor 308 i, the onboard memory is signaled for a context switch to that session. Utilizing this method of prioritization, context switching overhead can be reduced, as compared to conventional approaches. That is, a hardware scheduler can handle context switching decisions and thus optimize the performance of the downstream resource (e.g., offload processor 308 i).
  • As noted above, in very particular embodiments, an offload processor 308 i can be a “wimpy core” type processor. According to some embodiments, a host processor 306 c can be a “brawny core” type processor (e.g., an x86 or any other processor capable of handling “heavy touch” computational operations). While an I/O device 302 can be configured to trigger host processor interrupts in response to incoming packets, according to embodiments, such interrupts can be disabled, thereby reducing processing overhead for the host processor 306 c. In some very particular embodiments, an offload processor 308 i can include an ARM, ARC, Tensilica, MIPS, Strong/ARM or any other processor capable of handling “light touch” operations. Preferably, an offload processor can run a general purpose operating system for executing a plurality of sessions, which can be optimized to work in conjunction with the hardware scheduler in order to reduce context switching overhead.
  • Referring still to FIG. 3, in operation, a system 301 can receive packets from an external network over a network interface. The packets are destined for either a host processor 306 c or an offload processor 308 i based on the classification logic and schematics employed by I/O device 302. In particular embodiments, I/O device 302 can operate as a virtualized NIC, with packets for a particular logical network or to a certain virtual MAC (VMAC) address can be directed into separate queues and sent over to the destination logical entity. Such an arrangement can transfer packets to different entities. In some embodiments, each such entity can have a virtual driver, a virtual device model that it uses to communicate with connected virtual network.
  • According to embodiments, multiple devices can be used to redirect traffic to specific memory addresses. So, each of the network devices operates as if it is transferring the packets to the memory location of a logical entity. However, in reality, such packets are transferred to memory addresses where they can be handled by one or more offload processors (e.g., 308 i). In particular embodiments such transfers are to physical memory addresses, thus logical entities can be removed from the processing, and a host processor can be free from such packet handling.
  • Accordingly, embodiments can be conceptualized as providing a memory “black box” to which specific network data can be fed. Such a memory black box can handle the data (e.g., process it) and respond back when such data is requested.
  • Referring still to FIG. 3, according to some embodiments, I/O device 302 can receive data packets from a network or from a computing device. The data packets can have certain characteristics, including transport protocol number, source and destination port numbers, source and destination IP addresses, for example. The data packets can further have metadata that is processed (308 d) that helps in their classification and management.
  • I/O device 302 can include, but is not limited to, peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with a host motherboard via PCI or PCIe bus (e.g., 312). Examples of I/O devices include a network interface controller (NIC), a host bus adapter, a converged network adapter, an ATM network interface, etc.
  • In order to provide for an abstraction scheme that allows multiple logical entities to access the same I/O device 302, the I/O device may be virtualized to provide for multiple virtual devices each of which can perform some of the functions of the physical I/O device. The IO virtualization program (e.g., 302 b) according to an embodiment, can redirect traffic to different memory locations (and thus to different offload processors attached to modules on a memory bus). To achieve this, an I/O device 302 (e.g., a network card) may be partitioned into several function parts; including controlling function (CF) supporting input/output virtualization (IOV) architecture (e.g., single-root IOV) and multiple virtual function (VF) interfaces. Each virtual function interface may be provided with resources during runtime for dedicated usage. Examples of the CF and VF may include the physical function and virtual functions under schemes such as Single Root I/O Virtualization or Multi-Root I/O Virtualization architecture. The CF acts as the physical resources that sets up and manages virtual resources. The CF is also capable of acting as a full-fledged IO device. The VF is responsible for providing an abstraction of a virtual device for communication with multiple logical entities/multiple memory regions.
  • The operating system/the hypervisor/any of the virtual machines/user code running on a host processor 306 c may be loaded with a device model, a VF driver and a driver for a CF. The device model may be used to create an emulation of a physical device for the host processor 306 c to recognize each of the multiple VFs that are created. The device model may be replicated multiple times to give the impression to a VF driver (a driver that interacts with a virtual IO device) that it is interacting with a physical device of a particular type.
  • For example, a certain device module may be used to emulate a network adapter such as the Intel® Ethernet Converged Network Adapter(CNA) X540-T2, so that the I/O device 302 believes it is interacting with such an adapter. In such a case, each of the virtual functions may have the capability to support the functions of the above said CNA, i.e., each of the Physical Functions should be able to support such functionality. The device model and the VF driver can be run in either privileged or non-privileged mode. In some embodiments, there is no restriction with regard to who hosts/runs the code corresponding to the device model and the VF driver. The code, however, has the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created.
  • An application or provisioning agent 306 d, as part of an application/user level code running in a kernel, may create a virtual I/O address space for each VF, during runtime and allocate part of the physical address space to it. For example, if an application handling the VF driver instructs it to read or write packets from or to memory addresses 0xaaaa to 0xffff, the device driver may write I/O descriptors into a descriptor queue with a head and tail pointer that are changed dynamically as queue entries are filled. The data structure may be of another type as well, including but not limited to a ring structure 302 a or hash table.
  • The VF can read from or write data to the address location pointed to by the driver. Further, on completing the transfer of data to the address space allocated to the driver, interrupts, which are usually triggered to the host processor to handle said network packets, can be disabled. Allocating a specific I/O space to a device can include allocating said IO space a specific physical memory space occupied.
  • In another embodiment, the descriptor may comprise only a write operation, if the descriptor is associated with a specific data structure for handling incoming packets. Further, the descriptor for each of the entries in the incoming data structure may be constant so as to redirect all data write to a specific memory location. In an alternate embodiment, the descriptor for consecutive entries may point to consecutive entries in memory so as to direct incoming packets to consecutive memory locations.
  • Alternatively, said operating system may create a defined physical address space for an application supporting the VF drivers and allocate a virtual memory address space to the application or provisioning agent 306 d, thereby creating a mapping for each virtual function between said virtual address and a physical address space. Said mapping between virtual memory address space and physical memory space may be stored in IOMMU tables (e.g., a TLB 304 a). The application performing memory reads or writes may supply virtual addresses to say virtual function, and the host processor OS may allocate a specific part of the physical memory location to such an application.
  • Alternatively, VF may be configured to generate requests such as read and write which may be part of a direct memory access (DMA) read or write operation, for example. The virtual addresses is be translated by the IOMMU 304 to their corresponding physical addresses and the physical addresses may be provided to the memory controller for access. That is, the IOMMU 304 may modify the memory requests sourced by the I/O devices to change the virtual address in the request to a physical address, and the memory request may be forwarded to the memory controller for memory access. The memory request may be forwarded over a bus 314 that supports a protocol such as HyperTransport 314. The VF may in such cases carry out a direct memory access by supplying the virtual memory address to the IOMMU 304.
  • Alternatively, said application may directly code the physical address into the VF descriptors if the VF allows for it. If the VF cannot support physical addresses of the form used by the host processor 306 c, an aperture with a hardware size supported by the VF device may be coded into the descriptor so that the VF is informed of the target hardware address of the device. Data that is transferred to an aperture may be mapped by a translation table to a defined physical address space in the system memory. The DMA operations may be initiated by software executed by the processors, programming the I/O devices directly or indirectly to perform the DMA operations.
  • Referring still to FIG. 3, in particular embodiments, parts of computational unit 300 can be implemented with one or more FPGAs. In the system of FIG. 3, computational unit 300 can include FPGA 310 in which can be formed a DMA slave device module 310 a and arbiter 310 f. A DMA slave module 310 a can be any device suitable for attachment to a memory bus 316 that can respond to DMA read/write requests. In alternate embodiments, a DMA slave module 310 a can be another interface capable of block data transfers over memory bus 316. The DMA slave module 310 a can be capable of receiving data from a DMA controller (when it performs a read from a ‘memory’ or from a peripheral) or transferring data to a DMA controller (when it performs a write instruction on the DMA slave module 310 a). The DMA slave module 310 a may be adapted to receive DMA read and write instructions encapsulated over a memory bus, (e.g., in the form of a DDR data transmission, such as a packet or data burst), or any other format that can be sent over the corresponding memory bus.
  • A DMA slave module 310 a can reconstruct the DMA read/write instruction from the memory R/W packet. The DMA slave module 310 a may be adapted to respond to these instructions in the form of data reads/data writes to the DMA master, which could either be housed in a peripheral device, in the case of a PCIe bus, or a system DMA controller in the case of an ISA bus.
  • I/O data that is received by the DMA device 310 a can then queued for arbitration. Arbitration can include the process of scheduling packets of different flows, such that they are provided access to available bandwidth based on a number of parameters. In general, an arbiter 310 f provides resource access to one or more requestors. If multiple requestors request access, an arbiter 310 f can determine which requestor becomes the accessor and then passes data from the accessor to the resource interface, and the downstream resource can begin execution on the data. After the data has been completely transferred to a resource, and the resource has competed execution, the arbiter 310 f can transfer control to a different requestor and this cycle repeats for all available requestors. In the embodiment of FIG. 3 arbiter 310 f can notify other portions of computational unit 300 (e.g., 308) of incoming data.
  • Alternatively, a computation unit 300 can utilize an arbitration scheme shown in U.S. Pat. No. 7,813,283, issued to Dalal on Oct. 12, 2010, the contents of which are incorporated herein by reference. Other suitable arbitration schemes known in art could be implemented in embodiments herein. Alternatively, the arbitration scheme of the current invention might be implemented using an OpenFlow switch and an OpenFlow controller.
  • In the very particular embodiment of FIG. 3, computational unit 300 can further include notify/prefetch circuits 310 c which can prefetch data stored in a buffer memory 310 b in response to DMA slave module 310 a, and as arbitrated by arbiter 310 f. Further, arbiter 310 f can access other portions of the computational unit 300 via a memory mapped I/O ingress path 310 e and egress path 310 g.
  • Referring to FIG. 3, a hardware scheduler can include a scheduling circuit 308 b/n to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata. Such classification can be performed by classifier 308 e.
  • In some embodiments, session metadata 308 d can serve as the criterion by which packets are prioritized and scheduled and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. The scheduling discipline chosen for this prioritization, or traffic management (TM), can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), delay jitter (temporally shifting cells of a flow by different amounts) and by not admitting a connection (e.g., cannot simultaneously guarantee existing service level agreements (SLAs) with an additional flow's SLA).
  • According to embodiments, computational unit 300 can serve as part of a switch fabric, and provide traffic management with depth-limited output queues, the access to which is arbitrated by a scheduling circuit 308 b/n. Such output queues are managed using a scheduling discipline to provide traffic management for incoming flows. The session flows queued in each of these queues can be sent out through an output port to a downstream network element.
  • It is noted that conventional traffic management do not take into account the handling and management of data by downstream elements except for meeting the SLA agreements it already has with said downstream elements.
  • In contrast, according to embodiments a scheduler circuit 308 b/n can allocate a priority to each of the output queues and carry out reordering of incoming packets to maintain persistence of session flows in these queues. A scheduler circuit 308 b/n can be used to control the scheduling of each of these persistent sessions into a general purpose operating system (OS) 308 j, executed on an offload processor 308 i. Packets of a particular session flow, as defined above, can belong to a particular queue. The scheduler circuit 308 b/n may control the prioritization of these queues such that they are arbitrated for handling by a general purpose (GP) processing resource (e.g., offload processor 308 i) located downstream. An OS 308 j running on a downstream processor 308 i can allocate execution resources such as processor cycles and memory to a particular queue it is currently handling. The OS 308 j may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element 308 i as a separate entity. The fact that there can be multiple sessions running on a GP processing resource, each handling data from a particular session flow resident in a queue established by the scheduler circuit, tightly integrates the scheduler and the downstream resource (e.g., 308 i). This can bring about persistence of session information across the traffic management and scheduling circuit and the general purpose processing resource 308 i.
  • Dedicated computing resources (e.g., 308 i), memory space and session context information for each of the sessions can provide a way of handling, processing and/or terminating each of the session flows at the general purpose processor 308 i. The scheduler circuit 308 b/n can exploit this functionality of the execution resource to queue session flows for scheduling downstream. The scheduler circuit 308 b/n can be informed of the state of the execution resource(s) (e.g., 308 i), the current session that is run on the execution resource; the memory space allocated to it, the location of the session context in the processor cache.
  • According to embodiments, a scheduler circuit 308 b/n can further include switching circuits to change execution resources from one state to another. The scheduler circuit 308 b/n can use such a capability to arbitrate between the queues that are ready to be switched into the downstream execution resource. Further, the downstream execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the scheduler circuit 308 b/n to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.
  • According to embodiments, a scheduler circuit 308 b/n can schedule different sessions on a downstream processing resource, wherein the two are operated in coordination to reduce the overhead during context switches. An important factor in decreasing the latency of services and engineering computational availability can be hardware context switching synchronized with network queuing. In embodiments, when a queue is selected by a traffic manager, a pipeline coordinates swapping in of the cache (e.g., L2 cache) of the corresponding resource (e.g., 308 i) and transfers the reassembled I/O data into the memory space of the executing process. In certain cases, no packets are pending in the queue, but computation is still pending to service previous packets. Once this process makes a memory reference outside of the data swapped, the scheduler circuit (308 b/n) can enable queued data from an I/O device 302 to continue scheduling the thread.
  • In some embodiments, to provide fair queuing to a process not having data, a maximum context size can be assumed as data processed. In this way, a queue can be provisioned as the greater of computational resource and network bandwidth resource. As but one very particular example, a computation resource can be an ARM A9 processor running at 800 MHz, while a network bandwidth can be 3 Gbps of bandwidth. Given the lopsided nature of this ratio, embodiments can utilize computation having many parallel sessions (such that the hardware's prefetching of session-specific data offloads a large portion of the host processor load) and having minimal general purpose processing of data.
  • Accordingly, in some embodiments, a scheduler circuit 308 b/n can be conceptualized as arbitrating, not between outgoing queues at line rate speeds, but arbitrating between terminated sessions at very high speeds. The stickiness of sessions across a pipeline of stages, including a general purpose OS, can be a scheduler circuit optimizing any or all such stages of such a pipeline.
  • Alternatively, a scheduling scheme can be used as shown in U.S. Pat. No. 7,760,715 issued to Dalal on Jul. 20, 2010, incorporated herein by reference. This scheme can be useful when it is desirable to rate limit the flows for preventing the downstream congestion of another resource specific to the over-selected flow, or for enforcing service contracts for particular flows. Embodiments can include arbitration scheme that allows for service contracts of downstream resources, such as general purpose OS that can be enforced seamlessly.
  • Referring still to FIG. 3, a hardware scheduler according to embodiments herein, or equivalents, can provide for the classification of incoming packet data into session flows based on session metadata. It can further provide for traffic management of these flows before they are arbitrated and queued as distinct processing entities on the offload processors.
  • In some embodiments, offload processors (e.g., 308 i) can be general purpose processing units capable of handling packets of different application or transport sessions. Such offload processors can be low power processors capable of executing general purpose instructions. The offload processors could be any suitable processor, including but not limited to: ARM, ARC, Tensilica, MIPS, StrongARM or any other processor that serves the functions described herein. Such offload processors have a general purpose OS running on them, wherein the general purpose OS is optimized to reduce the penalty associated with context switching between different threads or group of threads.
  • In contrast, context switches on host processors can be computationally intensive processes that require the register save area, process context in the cache and TLB entries to be restored if they are invalidated or overwritten. Instruction Cache misses in host processing systems can lead to pipeline stalls and data cache misses lead to operation stall and such cache misses reduce processor efficiency and increase processor overhead.
  • In contrast, an OS 308 j running on the offload processors 308 i in association with a scheduler circuit 308 b/n, can operate together to reduce the context switch overhead incurred between different processing entities running on it. Embodiments can include a cooperative mechanism between a scheduler circuit and the OS on the offload processor 308 i, wherein the OS sets up session context to be physically contiguous (physically colored allocator for session heap and stack) in the cache; then communicates the session color, size, and starting physical address to the scheduler circuit upon session initialization. During an actual context switch, a scheduler circuit can identify the session context in the cache by using these parameters and initiate a bulk transfer of these contents to an external low latency memory (e.g., 308 g). In addition, the scheduler circuit can manage the prefetch of the old session if its context was saved to a local memory 308 g. In particular embodiments, a local memory 308 g can be low latency memory, such as a reduced latency dynamic random access memory (RLDRAM), as but one very particular embodiment. Thus, in embodiments, session context can be identified distinctly in the cache.
  • In some embodiments, context size can be limited to ensure fast switching speeds. In addition or alternatively, embodiments can include a bulk transfer mechanism to transfer out session context to a local memory 308 g. The cache contents stored therein can then be retrieved and prefetched during context switch back to a previous session. Different context session data can be tagged and/or identified within the local memory 308 g for fast retrieval. As noted above, context stored by one offload processor may be recalled by a different offload processor.
  • In the very particular embodiment of FIG. 3, multiple offload processing cores can be integrated into a computation FPGA 308. Multiple computational FPGAs can be arbitrated by arbitrator circuits in another FPGA 310. The combination of computational FPGAs (e.g., 308) and arbiter FPGAs (e.g., 310) are referred to as “XIMM” modules or “Xockets DIMM modules” (e.g., computation unit 300). In particular applications, these XIMM modules can provide integrated traffic and thread management circuits that broker execution of multiple sessions on the offload processors.
  • FIG. 3 also shows an offload processor tunnel connection 308 k, as well as a memory interface 308 m and port 3081 (which can be an accelerator coherency port (ACP)). Memory interface 308 m can access buffer memory 308 a.
  • Having described various embodiments suitable for hardware scheduling and traffic management operations, an example illustrating particular aspects will now be described.
  • FIG. 4 illustrates an example embodiment of a scheduling process 400 for access to offload processing resources according to a very particular embodiment. In some embodiments, a scheduler (e.g., hardware scheduler) can implement a scheduling process as a traffic management scheme in order to meet the requirements of offload processors, and may be operated in a preemption mode. In a preemption mode, the scheduler can be responsible for controlling the execution of a session on the OS. The scheduler can decide when to remove a current session from execution and cause another session to be executed. A session may comprise of a thread or a group of threads on an offload processor. Depending on a number of parameters, including such factors as the characteristics of the current session—whether it is stalled or running or waiting for a packet, the amount of execution resources allocated to the session, and factors such as time allocated to the current session, the hardware scheduler may make a context switching decision. When a packet arrives at the hardware scheduler, and based on meeting any of the above said criteria, the scheduler may decide to context switch if the packet is for a different session.
  • As seen in FIG. 4, a method 400 can wait for packets or other data (402). Incoming packets can be received by a monitor buffer, queue or file. Once a packet or service level specification (SLS) has been received, there may be a check to ensure other conditions are met (406). If the packet/data has arrived (and optionally, other conditions met, such as those noted above) (Yes from 406), a packet session status is determined (408). If the packet is part of a current session (Yes from 408), it can be queued for the current session (412) and processed as part of the current session (410). In some embodiments, this can include hardware scheduler queuing the packet and sending it to an offload processor for processing.
  • If a packet is not part of a current session (No from 408), it can be determined if the packet is for a previous session (414). If the packet is not from a previous session (No from 414), it can be determined if there is enough memory for a new session (416). If there is enough memory (Yes from 416), when the offload processor(s) is ready (428), the transfer of context data can be made to the cache memory of the processor(s) (430). Once such a transfer is complete, the session can run (410).
  • If the packet is from a previous session (Yes from 414) or there is not enough memory for a new session (No from 416), it can be determined if the previous session or new session is of the same color (418). If this is not the case, a switch can be made to the previous session or new session (420). A least recently uses (LRU) cache entity can be flushed, and the previous session context can be retrieved, or the new session context created. The packets of this retrieved/new session can be assigned a new color which can be retained. In some embodiments, this can include reading context data stored in a low latency memory to the cache of an offload processor. If a previous/new session is of the same color (Yes from 418), a check can be made to see if the color pressure can be exceeded (422). If this is not possible, but another color is available (“No, other color available” from 422), a switch to the previous or new session can be made (i.e., 420). If the color pressure can be excluded, or it cannot, but no other color is available (“Yes/No, other color unavail.”), an LRU cache entity of the same color can be flushed, and the previous session context can be retrieved, or the new session context created (424). These packets will retain their assigned color. Again, in some embodiments, this can include reading context data stored in a low latency memory to the cache of an offload processor.
  • In the event of a context switch (420/424), the new session can be initialized (426). When the offload processor(s) are ready (428), the transfer of context data can be made to the cache memory of the processor(s) (430). Once such a transfer is complete, the session can run (410).
  • Referring still to FIG. 4, While the offload processor is processing a packet (410), there is a periodic check to see if the packet has finished processing (432) and return if processing is not done (No, dequeue packets from 432). If the packet is done (Yes from 432), a hardware scheduler can looks to its output queue for more packets (434). If there are more packets (Yes from 434) and the offload processor is ready to receive them (Yes from 436), the packets can transferred to the offload processor. In some embodiments, packets can be queued into the offload processor as soon as a “ready for processing” message is triggered by the offload processor. After the offload processor is done processing the packets, the entire cycle can repeat beginning with the hardware scheduler checking to which session the packet belongs, etc.
  • If an offload processor is not ready for a packet (No from 436) and it is waiting for rate limit (438), the hardware scheduler can check to see if there are other packets available. If there are no more packets in the queue, the hardware scheduler can goes into a wait mode, waiting for rate limit until more packets arrive. Thus, the hardware scheduler works quickly and efficiently to manage and supply packets going to the downstream resource.
  • As shown, a session can be preempted by the arrival of a packet from a different session, resulting in the new packet being processed as noted above (406).
  • It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
  • It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.
  • Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.

Claims (7)

What is claimed is:
1. A method for scheduling packet processing, comprising the steps of:
classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with network packets transported to a classification circuit using a memory bus having a defined memory transport protocol,
reordering network packets received from the first multiple input/output queues using a scheduling circuit and placing the reordered network packets into a second multiple input/output queues,
directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports using an arbitration circuit, and
modifying network packets using multiple offload processors, each offload processor coupled to at least one of the multiple output ports, the offload processors configured to direct modified network packets back to the memory bus.
2. The method of claim 1 wherein the directing of network packets is based on availability of the multiple offload processors.
3. The method of claim 1 wherein the reordering of network packets is according to session priorities of the network packets.
4. The method of claim 1 further including initiating a context switch for at least one of the multiple offload processors by operation of the scheduling circuit.
5. The method of claim 1 further including transferring network packets into a defined traffic management queue by operation of the scheduling circuit.
6. The method of claim 1 further including determining when packet processing for each of the multiple offload processors is complete by operation of the scheduling circuit.
7. The method of claim 1 further including preempting a current network packet processing session by operation of the scheduling circuit.
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US13/931,913 Active - Reinstated 2034-07-09 US9460031B1 (en) 2013-01-17 2013-06-29 Full bandwidth packet handling with server systems including offload processors
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US15/396,323 Active - Reinstated 2033-10-11 US10649924B2 (en) 2013-01-17 2016-12-30 Network overlay systems and methods using offload processors

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017112143A1 (en) * 2015-12-22 2017-06-29 Intel Corporation Methods and apparatus for multi-stage vm virtual network function and virtual service function chain acceleration for nfv and needs-based hardware acceleration
US20170286332A1 (en) * 2016-03-29 2017-10-05 Karunakara Kotary Technologies for processor core soft-offlining
US10148576B2 (en) * 2016-07-28 2018-12-04 Fortinet, Inc. Network processing unit (NPU) integrated layer 2 network device for layer 3 offloading
WO2019108310A1 (en) * 2017-12-03 2019-06-06 Intel Corporation Mechanisms for fpga chaining and unified fpga views to composed system hosts
US20210105221A1 (en) * 2016-12-06 2021-04-08 Microsoft Technology Licensing, Llc Network processing resource management in computing systems

Families Citing this family (140)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005089241A2 (en) 2004-03-13 2005-09-29 Cluster Resources, Inc. System and method for providing object triggers
US20070266388A1 (en) 2004-06-18 2007-11-15 Cluster Resources, Inc. System and method for providing advanced reservations in a compute environment
US8271980B2 (en) 2004-11-08 2012-09-18 Adaptive Computing Enterprises, Inc. System and method of providing system jobs within a compute environment
US8631130B2 (en) 2005-03-16 2014-01-14 Adaptive Computing Enterprises, Inc. Reserving resources in an on-demand compute environment from a local compute environment
US9231886B2 (en) 2005-03-16 2016-01-05 Adaptive Computing Enterprises, Inc. Simple integration of an on-demand compute environment
CA2603577A1 (en) 2005-04-07 2006-10-12 Cluster Resources, Inc. On-demand access to compute resources
US11720290B2 (en) 2009-10-30 2023-08-08 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9432298B1 (en) * 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
CN103377161A (en) * 2012-04-24 2013-10-30 鸿富锦精密工业(深圳)有限公司 Main board and data processing method applied to same
US9495308B2 (en) 2012-05-22 2016-11-15 Xockets, Inc. Offloading of computation for rack level servers and corresponding methods and systems
US9558351B2 (en) 2012-05-22 2017-01-31 Xockets, Inc. Processing structured and unstructured data using offload processors
US10311014B2 (en) * 2012-12-28 2019-06-04 Iii Holdings 2, Llc System, method and computer readable medium for offloaded computation of distributed application protocols within a cluster of data processing nodes
US9250954B2 (en) 2013-01-17 2016-02-02 Xockets, Inc. Offload processor modules for connection to system memory, and corresponding methods and systems
US9569223B2 (en) * 2013-02-13 2017-02-14 Red Hat Israel, Ltd. Mixed shared/non-shared memory transport for virtual machines
US9288163B2 (en) * 2013-03-15 2016-03-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Low-latency packet receive method for networking devices
US10084718B1 (en) * 2013-03-15 2018-09-25 Google Llc Bi-Connected hierarchical data center network based on multi-ported network interface controllers (NICs)
US9317444B2 (en) * 2013-03-15 2016-04-19 Vmware, Inc. Latency reduction for direct memory access operations involving address translation
US9462088B2 (en) * 2013-04-02 2016-10-04 Cisco Technology, Inc. Offload operations for overlay networks
US9606842B2 (en) * 2013-05-08 2017-03-28 National Science Foundation Resource and core scaling for improving performance of power-constrained multi-core processors
US9143403B2 (en) * 2013-06-19 2015-09-22 Hewlett-Packard Development Company, L.P. Autonomous metric tracking and adjustment
US9331868B2 (en) * 2013-10-15 2016-05-03 At&T Intellectual Property I, L.P. Method of bus virtualization in computing machine intercommunications
WO2015061965A1 (en) * 2013-10-29 2015-05-07 Hua Zhong University Of Science Technology Mixed cache management
US9454394B2 (en) * 2013-11-22 2016-09-27 Red Hat Israel, Ltd. Hypervisor dynamically assigned input/output resources for virtual devices
US10254987B2 (en) * 2013-12-12 2019-04-09 Samsung Electronics Co., Ltd. Disaggregated memory appliance having a management processor that accepts request from a plurality of hosts for management, configuration and provisioning of memory
KR101572689B1 (en) * 2014-01-06 2015-11-27 (주)구름네트웍스 Apparatus for Virtualizing a Network Interface and Method thereof
US9705798B1 (en) * 2014-01-07 2017-07-11 Google Inc. Systems and methods for routing data through data centers using an indirect generalized hypercube network
JP2015143945A (en) * 2014-01-31 2015-08-06 富士通株式会社 Storage control device, storage device and control program
CN103905337B (en) * 2014-03-31 2018-01-23 华为技术有限公司 A kind of processing unit of Internet resources, method and system
US9467389B2 (en) 2014-04-28 2016-10-11 International Business Machines Corporation Handling large frames in a virtualized fibre channel over ethernet (FCoE) data forwarder
US9491031B2 (en) * 2014-05-06 2016-11-08 At&T Intellectual Property I, L.P. Devices, methods, and computer readable storage devices for collecting information and sharing information associated with session flows between communication devices and servers
US9742881B2 (en) * 2014-06-30 2017-08-22 Nicira, Inc. Network virtualization using just-in-time distributed capability for classification encoding
US9213903B1 (en) 2014-07-07 2015-12-15 Google Inc. Method and system for cluster-based video monitoring and event categorization
US10127783B2 (en) 2014-07-07 2018-11-13 Google Llc Method and device for processing motion events
US9170707B1 (en) 2014-09-30 2015-10-27 Google Inc. Method and system for generating a smart time-lapse video clip
US10140827B2 (en) 2014-07-07 2018-11-27 Google Llc Method and system for processing motion event notifications
US9501915B1 (en) 2014-07-07 2016-11-22 Google Inc. Systems and methods for analyzing a video stream
US9449229B1 (en) 2014-07-07 2016-09-20 Google Inc. Systems and methods for categorizing motion event candidates
US9892079B2 (en) * 2014-07-25 2018-02-13 Rajiv Ganth Unified converged network, storage and compute system
WO2016013024A1 (en) * 2014-07-25 2016-01-28 StorNetware Systems Pvt. Ltd. Unified converged network, storage and computer system
US10261817B2 (en) * 2014-07-29 2019-04-16 Nxp Usa, Inc. System on a chip and method for a controller supported virtual machine monitor
WO2016030757A1 (en) * 2014-08-25 2016-03-03 Marvell World Trade Ltd. Packet buffer with dynamic bypass
US10313683B2 (en) * 2014-08-30 2019-06-04 Apple Inc. Video encoder with context switching
US9703951B2 (en) 2014-09-30 2017-07-11 Amazon Technologies, Inc. Allocation of shared system resources
USD782495S1 (en) 2014-10-07 2017-03-28 Google Inc. Display screen or portion thereof with graphical user interface
US9754103B1 (en) 2014-10-08 2017-09-05 Amazon Technologies, Inc. Micro-architecturally delayed timer
US9378363B1 (en) 2014-10-08 2016-06-28 Amazon Technologies, Inc. Noise injected virtual timer
DE102014221726A1 (en) * 2014-10-24 2016-04-28 Continental Teves Ag & Co. Ohg A method of handling a received vehicle-to-X message in a vehicle, vehicle-to-X communication module and storage medium
US9491112B1 (en) 2014-12-10 2016-11-08 Amazon Technologies, Inc. Allocating processor resources based on a task identifier
US9864636B1 (en) * 2014-12-10 2018-01-09 Amazon Technologies, Inc. Allocating processor resources based on a service-level agreement
US20160188529A1 (en) * 2014-12-25 2016-06-30 Intel Corporation Guaranteed quality of service in system-on-a-chip uncore fabric
US20160197834A1 (en) * 2015-01-02 2016-07-07 Siegfried Luft Architecture and method for traffic engineering between diverse cloud providers
US9952979B1 (en) * 2015-01-14 2018-04-24 Cavium, Inc. Methods and systems for direct memory access operations
CN106326140B (en) * 2015-06-30 2020-06-02 华为技术有限公司 Data copying method, direct memory access controller and computer system
US10310998B2 (en) 2015-06-30 2019-06-04 Microsoft Technology Licensing, Llc Direct memory access with filtering
KR102402672B1 (en) * 2015-09-01 2022-05-26 삼성전자주식회사 Computing system and method for processing operations thereof
US9491765B1 (en) * 2015-09-21 2016-11-08 Dell Products L.P. Beam forming communication system
US20170142234A1 (en) * 2015-11-13 2017-05-18 Microsoft Technology Licensing, Llc Scalable addressing mechanism for virtual machines
US10853303B2 (en) 2015-11-18 2020-12-01 Oracle International Corporation Separation of control and data plane functions in SoC virtualized I/O device
US10817456B2 (en) 2015-11-18 2020-10-27 Oracle International Corporation Separation of control and data plane functions in SoC virtualized I/O device
US10031801B2 (en) 2015-12-01 2018-07-24 Microsoft Technology Licensing, Llc Configurable reliability for memory devices
US10445271B2 (en) 2016-01-04 2019-10-15 Intel Corporation Multi-core communication acceleration using hardware queue device
US9985890B2 (en) 2016-03-14 2018-05-29 International Business Machines Corporation Identifying a local congestion control algorithm of a virtual machine
EP3438823B1 (en) * 2016-03-31 2022-08-03 Nec Corporation Control method and control apparatus for network system, and server
US10045252B2 (en) * 2016-06-02 2018-08-07 International Business Machines Corporation Virtual switch-based congestion control for multiple TCP flows
US11671382B2 (en) 2016-06-17 2023-06-06 Intel Corporation Technologies for coordinating access to data packets in a memory
KR102548599B1 (en) 2016-06-17 2023-06-29 삼성전자주식회사 Memory device including buffer-memory and memory module including the same
US10341264B2 (en) 2016-06-30 2019-07-02 Intel Corporation Technologies for scalable packet reception and transmission
US10034407B2 (en) * 2016-07-22 2018-07-24 Intel Corporation Storage sled for a data center
US10277636B2 (en) 2016-09-08 2019-04-30 Macnica Americas, Inc. FPGA offload module and processes for seamless frame-level switching of media streams in real-time
US10552212B2 (en) * 2016-11-28 2020-02-04 Arm Limited Data processing
US20180150256A1 (en) 2016-11-29 2018-05-31 Intel Corporation Technologies for data deduplication in disaggregated architectures
US10554554B2 (en) * 2016-12-06 2020-02-04 Microsoft Technology Licensing, Llc Hybrid network processing load distribution in computing systems
US10715424B2 (en) 2016-12-06 2020-07-14 Microsoft Technology Licensing, Llc Network traffic management with queues affinitized to one or more cores
CN106656711B (en) * 2016-12-26 2019-06-18 中核控制系统工程有限公司 A kind of predefined method of token bus time slot
US11853244B2 (en) * 2017-01-26 2023-12-26 Wisconsin Alumni Research Foundation Reconfigurable computer accelerator providing stream processor and dataflow processor
US10949427B2 (en) 2017-01-31 2021-03-16 Microsoft Technology Licensing, Llc Stream data processing on multiple application timelines
JP6859755B2 (en) * 2017-03-02 2021-04-14 富士通株式会社 Information processing device, control method of information processing device, and control program of information processing device
US10686729B2 (en) 2017-03-29 2020-06-16 Fungible, Inc. Non-blocking any-to-any data center network with packet spraying over multiple alternate data paths
US10257033B2 (en) * 2017-04-12 2019-04-09 Cisco Technology, Inc. Virtualized network functions and service chaining in serverless computing infrastructure
US20180330288A1 (en) * 2017-05-15 2018-11-15 Alteryx, Inc. Method of data aggregation for cache optimization and efficient processing
US10331445B2 (en) * 2017-05-24 2019-06-25 Microsoft Technology Licensing, Llc Multifunction vector processor circuits
US20180341494A1 (en) * 2017-05-26 2018-11-29 Intel Corporation Accelerating network security monitoring
US10990291B2 (en) * 2017-06-12 2021-04-27 Dell Products, L.P. Software assist memory module hardware architecture
US10838902B2 (en) 2017-06-23 2020-11-17 Facebook, Inc. Apparatus, system, and method for performing hardware acceleration via expansion cards
CN109213268A (en) * 2017-07-04 2019-01-15 佛山市顺德区顺达电脑厂有限公司 Server cabinet system and its signal transmission frequency method of adjustment
US10659254B2 (en) * 2017-07-10 2020-05-19 Fungible, Inc. Access node integrated circuit for data centers which includes a networking unit, a plurality of host units, processing clusters, a data network fabric, and a control network fabric
EP3625679A1 (en) 2017-07-10 2020-03-25 Fungible, Inc. Data processing unit for stream processing
CN109426556B (en) * 2017-08-31 2021-06-04 大唐移动通信设备有限公司 Process scheduling method and device
CN107741867B (en) * 2017-09-30 2020-03-10 Oppo广东移动通信有限公司 Application program management method and device, storage medium and electronic equipment
US10496437B2 (en) * 2017-11-14 2019-12-03 International Business Machines Corporation Context switch by changing memory pointers
US10592164B2 (en) 2017-11-14 2020-03-17 International Business Machines Corporation Portions of configuration state registers in-memory
US10810064B2 (en) * 2018-04-27 2020-10-20 Nasdaq Technology Ab Publish-subscribe framework for application execution
US10812315B2 (en) 2018-06-07 2020-10-20 Cisco Technology, Inc. Cross-domain network assurance
KR102665410B1 (en) 2018-07-30 2024-05-13 삼성전자주식회사 Performing internal processing operations of memory device
US10862805B1 (en) 2018-07-31 2020-12-08 Juniper Networks, Inc. Intelligent offloading of services for a network device
US10795612B2 (en) * 2018-07-31 2020-10-06 EMC IP Holding Company LLC Offload processing using storage device slots
US10649927B2 (en) * 2018-08-20 2020-05-12 Intel Corporation Dual in-line memory module (DIMM) programmable accelerator card
TWI819072B (en) 2018-08-23 2023-10-21 美商阿爾克斯股份有限公司 System, non-transitory computer readable storage media and computer-implemented method for loop conflict avoidance in a network computing environment
US10979542B2 (en) * 2018-08-28 2021-04-13 Vmware, Inc. Flow cache support for crypto operations and offload
US10705762B2 (en) 2018-08-30 2020-07-07 Micron Technology, Inc. Forward caching application programming interface systems and methods
CN109358953B (en) * 2018-09-20 2020-09-08 中南大学 Multitask application unloading method in micro cloud
US10942824B2 (en) 2018-10-08 2021-03-09 Hewlett Packard Enterprise Development Lp Programming model and framework for providing resilient parallel tasks
US11204819B2 (en) 2018-12-21 2021-12-21 Samsung Electronics Co., Ltd. System and method for offloading application functions to a device
US10606775B1 (en) 2018-12-28 2020-03-31 Micron Technology, Inc. Computing tile
US11003539B2 (en) * 2019-01-15 2021-05-11 EMC IP Holding Company LLC Offload processing using a storage slot
CN109714217A (en) * 2019-02-28 2019-05-03 苏州浪潮智能科技有限公司 A kind of cabinet and rack room communication means
US10929310B2 (en) 2019-03-01 2021-02-23 Cisco Technology, Inc. Adaptive address translation caches
JP2020184690A (en) * 2019-05-08 2020-11-12 富士通株式会社 Packet categorization program, packet categorization method, and information processing unit
US11374880B2 (en) * 2019-06-17 2022-06-28 Cyxtera Data Centers, Inc. Automated deployment of internet connectivity to rack switches in a data center
US11374879B2 (en) * 2019-06-17 2022-06-28 Cyxtera Data Centers, Inc. Network configuration of top-of-rack switches across multiple racks in a data center
CN110181928B (en) * 2019-07-09 2021-09-21 苏州微影激光技术有限公司 Plate making device and plate making method of screen printing plate
CN114303138A (en) * 2019-09-11 2022-04-08 英特尔公司 Hardware queue scheduling for multi-core computing environments
US11275111B2 (en) 2019-09-20 2022-03-15 Micron Technology, Inc. Plurality of edge through-silicon vias and related systems, methods, and devices
EP4052442B1 (en) * 2019-10-30 2024-07-17 Telefonaktiebolaget LM Ericsson (publ) In-band protocol-based in-network computation offload framework
US11232049B2 (en) * 2019-12-13 2022-01-25 Micron Technology, Inc. Memory module with computation capability
US11934330B2 (en) * 2020-05-08 2024-03-19 Intel Corporation Memory allocation for distributed processing devices
US11962518B2 (en) 2020-06-02 2024-04-16 VMware LLC Hardware acceleration techniques using flow selection
FR3113346A1 (en) * 2020-08-10 2022-02-11 Orange Method of processing a data transport service
JP7508962B2 (en) * 2020-09-15 2024-07-02 富士通株式会社 Semiconductor device and transfer method
US11636053B2 (en) 2020-09-28 2023-04-25 Vmware, Inc. Emulating a local storage by accessing an external storage through a shared port of a NIC
US11606310B2 (en) 2020-09-28 2023-03-14 Vmware, Inc. Flow processing offload using virtual port identifiers
US11829793B2 (en) 2020-09-28 2023-11-28 Vmware, Inc. Unified management of virtual machines and bare metal computers
US11593278B2 (en) 2020-09-28 2023-02-28 Vmware, Inc. Using machine executing on a NIC to access a third party storage not supported by a NIC or host
US11824931B2 (en) * 2020-09-28 2023-11-21 Vmware, Inc. Using physical and virtual functions associated with a NIC to access an external storage through network fabric driver
US12021759B2 (en) * 2020-09-28 2024-06-25 VMware LLC Packet processing with hardware offload units
US11418597B2 (en) * 2020-10-08 2022-08-16 Toyota Motor Engineering & Manufacturing North America, Inc. System and method for value-anticipating task offloading
US11301410B1 (en) * 2020-12-13 2022-04-12 Advanced Mciro Devices, Inc. Tags for request packets on a network communication link
WO2022139795A1 (en) * 2020-12-21 2022-06-30 Google Llc Preemption in a machine learning hardware accelerator
US11451493B2 (en) * 2021-01-06 2022-09-20 Mellanox Technologies, Ltd. Connection management in a network adapter
CN115033122A (en) * 2021-03-03 2022-09-09 华为技术有限公司 Screen control method of electronic device, readable medium and electronic device
US11822675B2 (en) * 2021-06-24 2023-11-21 International Business Machines Corporation Securing customer data and internal register data during hardware checkstops in a multi-tenant environment
US12105647B2 (en) * 2021-08-30 2024-10-01 EMC IP Holding Company LLC Asynchronous reservation of storage volumes with persistent storage of reservation data
US11995024B2 (en) 2021-12-22 2024-05-28 VMware LLC State sharing between smart NICs
US11863376B2 (en) 2021-12-22 2024-01-02 Vmware, Inc. Smart NIC leader election
US20230221874A1 (en) * 2022-01-12 2023-07-13 Vmware, Inc. Method of efficiently receiving files over a network with a receive file command
US11928367B2 (en) 2022-06-21 2024-03-12 VMware LLC Logical memory addressing for network devices
US11899594B2 (en) 2022-06-21 2024-02-13 VMware LLC Maintenance of data message classification cache on smart NIC
US11928062B2 (en) 2022-06-21 2024-03-12 VMware LLC Accelerating data message classification with smart NICs
US20220327061A1 (en) * 2022-06-23 2022-10-13 Daniel Christian Biederman Packet processing device to determine memory to store data in a server architecture and computing system including same
US20240248855A1 (en) * 2023-01-19 2024-07-25 SambaNova Systems, Inc. Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179489B1 (en) * 1997-04-04 2001-01-30 Texas Instruments Incorporated Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto
US20040059825A1 (en) * 2002-02-08 2004-03-25 Edwards Paul C. Medium access control in a wireless network
US20040202319A1 (en) * 2003-04-12 2004-10-14 Hussain Muhammad Raghib Apparatus and method for allocating resources within a security processor
US7436845B1 (en) * 2004-06-08 2008-10-14 Sun Microsystems, Inc. Input and output buffering
US8072887B1 (en) * 2005-02-07 2011-12-06 Extreme Networks, Inc. Methods, systems, and computer program products for controlling enqueuing of packets in an aggregated queue including a plurality of virtual queues using backpressure messages from downstream queues

Family Cites Families (241)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214464A (en) * 1986-03-17 1987-09-21 Hitachi Ltd Coprocessor coupling system
JP2514954B2 (en) * 1987-03-13 1996-07-10 三菱電機株式会社 IC card
EP0422310A1 (en) * 1989-10-10 1991-04-17 International Business Machines Corporation Distributed mechanism for the fast scheduling of shared objects
US5237662A (en) 1991-06-27 1993-08-17 Digital Equipment Corporation System and method with a procedure oriented input/output mechanism
US5247675A (en) 1991-08-09 1993-09-21 International Business Machines Corporation Preemptive and non-preemptive scheduling and execution of program threads in a multitasking operating system
US5577213A (en) 1994-06-03 1996-11-19 At&T Global Information Solutions Company Multi-device adapter card for computer
US5913028A (en) * 1995-10-06 1999-06-15 Xpoint Technologies, Inc. Client/server data traffic delivery system and method
US5923887A (en) * 1996-05-20 1999-07-13 Advanced Micro Devices, Inc. Interrupt request that defines resource usage
US6085307A (en) 1996-11-27 2000-07-04 Vlsi Technology, Inc. Multiple native instruction set master/slave processor arrangement and method thereof
US6791947B2 (en) * 1996-12-16 2004-09-14 Juniper Networks In-line packet processing
US5930256A (en) * 1997-03-28 1999-07-27 Xerox Corporation Self-arbitrating crossbar switch
US6374330B1 (en) * 1997-04-14 2002-04-16 International Business Machines Corporation Cache-coherency protocol with upstream undefined state
US5870350A (en) 1997-05-21 1999-02-09 International Business Machines Corporation High performance, high bandwidth memory bus architecture utilizing SDRAMs
US6128642A (en) * 1997-07-22 2000-10-03 At&T Corporation Load balancing based on queue length, in a network of processor stations
US6092146A (en) 1997-07-31 2000-07-18 Ibm Dynamically configurable memory adapter using electronic presence detects
US7565461B2 (en) * 1997-12-17 2009-07-21 Src Computers, Inc. Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
US6157955A (en) 1998-06-15 2000-12-05 Intel Corporation Packet processing system including a policy engine having a classification unit
US20060117274A1 (en) 1998-08-31 2006-06-01 Tseng Ping-Sheng Behavior processor system and method
US6370622B1 (en) * 1998-11-20 2002-04-09 Massachusetts Institute Of Technology Method and apparatus for curious and column caching
US6446163B1 (en) * 1999-01-04 2002-09-03 International Business Machines Corporation Memory card with signal processing element
US20020107990A1 (en) * 2000-03-03 2002-08-08 Surgient Networks, Inc. Network connected computing system including network switch
US6625685B1 (en) 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
US7120155B2 (en) 2000-10-03 2006-10-10 Broadcom Corporation Switch having virtual shared memory
US6665495B1 (en) * 2000-10-27 2003-12-16 Yotta Networks, Inc. Non-blocking, scalable optical router architecture and method for routing optical traffic
US20020107971A1 (en) * 2000-11-07 2002-08-08 Bailey Brian W. Network transport accelerator
US7274706B1 (en) * 2001-04-24 2007-09-25 Syrus Ziai Methods and systems for processing network data
JP2002324363A (en) * 2001-04-25 2002-11-08 Ricoh Co Ltd Information recording/reproducing apparatus
TWI240864B (en) 2001-06-13 2005-10-01 Hitachi Ltd Memory device
WO2003034227A2 (en) * 2001-10-12 2003-04-24 Koninklijke Philips Electronics N.V. Apparatus and method for reading or writing user data
US20030078749A1 (en) * 2001-10-18 2003-04-24 Hans Eberle Memory module with integrated radio transmitter
US6889294B1 (en) * 2001-10-29 2005-05-03 Lsi Logic Corporation Virtual shared volume via proxy data transfer
US6751113B2 (en) 2002-03-07 2004-06-15 Netlist, Inc. Arrangement of integrated circuits in a memory module
US7472205B2 (en) 2002-04-24 2008-12-30 Nec Corporation Communication control apparatus which has descriptor cache controller that builds list of descriptors
US7415723B2 (en) * 2002-06-11 2008-08-19 Pandya Ashish A Distributed network security system and a hardware processor therefor
EP2264628A1 (en) 2002-09-18 2010-12-22 Netezza Corporation Intelligent storage device controller
US7454749B2 (en) 2002-11-12 2008-11-18 Engineered Intelligence Corporation Scalable parallel processing on shared memory computers
US20040133720A1 (en) * 2002-12-31 2004-07-08 Steven Slupsky Embeddable single board computer
JP2004220070A (en) * 2003-01-09 2004-08-05 Japan Science & Technology Agency Context switching method and device, central processing unit, context switching program and computer-readable storage medium storing it
US7089412B2 (en) 2003-01-17 2006-08-08 Wintec Industries, Inc. Adaptive memory module
US7421694B2 (en) * 2003-02-18 2008-09-02 Microsoft Corporation Systems and methods for enhancing performance of a coprocessor
US7673304B2 (en) * 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US7155379B2 (en) 2003-02-25 2006-12-26 Microsoft Corporation Simulation of a PCI device's memory-mapped I/O registers
US7657933B2 (en) * 2003-04-12 2010-02-02 Cavium Networks, Inc. Apparatus and method for allocating resources within a security processing architecture using multiple groups
US6794896B1 (en) * 2003-04-21 2004-09-21 Xilinx, Inc. Method and apparatus for multithreading
WO2004095304A1 (en) * 2003-04-23 2004-11-04 Dot Hill Systems Corporation Network storage appliance with integrated redundant servers and storage controllers
US6982892B2 (en) 2003-05-08 2006-01-03 Micron Technology, Inc. Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
US8560627B2 (en) * 2003-05-23 2013-10-15 Alcatel Lucent Virtual switch for use in fibre channel applications
US20050038946A1 (en) 2003-08-12 2005-02-17 Tadpole Computer, Inc. System and method using a high speed interface in a system having co-processors
US20050114700A1 (en) * 2003-08-13 2005-05-26 Sensory Networks, Inc. Integrated circuit apparatus and method for high throughput signature based network applications
US8776050B2 (en) 2003-08-20 2014-07-08 Oracle International Corporation Distributed virtual machine monitor for managing multiple virtual resources across multiple physical nodes
US20050078708A1 (en) * 2003-10-14 2005-04-14 International Business Machines Corporation Formatting packet headers in a communications adapter
US7787471B2 (en) * 2003-11-10 2010-08-31 Broadcom Corporation Field processor for a network device
US7493621B2 (en) * 2003-12-18 2009-02-17 International Business Machines Corporation Context switch data prefetching in multithreaded computer
US7657706B2 (en) 2003-12-18 2010-02-02 Cisco Technology, Inc. High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory
US7558890B1 (en) * 2003-12-19 2009-07-07 Applied Micro Circuits Corporation Instruction set for programmable queuing
US7213126B1 (en) * 2004-01-12 2007-05-01 Advanced Micro Devices, Inc. Method and processor including logic for storing traces within a trace cache
US20050018495A1 (en) 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7286436B2 (en) 2004-03-05 2007-10-23 Netlist, Inc. High-density memory module utilizing low-density memory components
US7532537B2 (en) 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7668165B2 (en) 2004-03-31 2010-02-23 Intel Corporation Hardware-based multi-threading for packet processing
US7254036B2 (en) 2004-04-09 2007-08-07 Netlist, Inc. High density memory module using stacked printed circuit boards
US7502474B2 (en) * 2004-05-06 2009-03-10 Advanced Micro Devices, Inc. Network interface with security association data prefetch for high speed offloaded security processing
US7480611B2 (en) 2004-05-13 2009-01-20 International Business Machines Corporation Method and apparatus to increase the usable memory capacity of a logic simulation hardware emulator/accelerator
US7945705B1 (en) * 2004-05-25 2011-05-17 Chelsio Communications, Inc. Method for using a protocol language to avoid separate channels for control messages involving encapsulated payload data messages
US20060004965A1 (en) 2004-06-30 2006-01-05 Tu Steven J Direct processor cache access within a system having a coherent multi-processor protocol
US7930422B2 (en) * 2004-07-14 2011-04-19 International Business Machines Corporation Apparatus and method for supporting memory management in an offload of network protocol processing
EP1622009A1 (en) * 2004-07-27 2006-02-01 Texas Instruments Incorporated JSM architecture and systems
US7895431B2 (en) * 2004-09-10 2011-02-22 Cavium Networks, Inc. Packet queuing, scheduling and ordering
US7305574B2 (en) 2004-10-29 2007-12-04 International Business Machines Corporation System, method and storage medium for bus calibration in a memory subsystem
KR100666169B1 (en) 2004-12-17 2007-01-09 삼성전자주식회사 Flash memory data storing device
US8010682B2 (en) * 2004-12-28 2011-08-30 International Business Machines Corporation Early coherency indication for return data in shared memory architecture
US8281031B2 (en) * 2005-01-28 2012-10-02 Standard Microsystems Corporation High speed ethernet MAC and PHY apparatus with a filter based ethernet packet router with priority queuing and single or multiple transport stream interfaces
US20060215649A1 (en) * 2005-03-08 2006-09-28 Chris Morrall Network address converting apparatus using SSW tree
EP2383661A1 (en) 2005-04-21 2011-11-02 Violin Memory, Inc. Interconnection system
JP4322232B2 (en) * 2005-06-14 2009-08-26 株式会社ソニー・コンピュータエンタテインメント Information processing apparatus, process control method, and computer program
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
WO2007006146A1 (en) 2005-07-12 2007-01-18 Advancedio Systems Inc. System and method of offloading protocol functions
US20070016906A1 (en) * 2005-07-18 2007-01-18 Mistletoe Technologies, Inc. Efficient hardware allocation of processes to processors
US7543131B2 (en) * 2005-08-12 2009-06-02 Advanced Micro Devices, Inc. Controlling an I/O MMU
US7500083B2 (en) * 2005-08-15 2009-03-03 Silicon Informatics Accelerated processing with scheduling to configured coprocessor for molecular data type by service and control coprocessor upon analysis of software code
US7442050B1 (en) 2005-08-29 2008-10-28 Netlist, Inc. Circuit card with flexible connection for memory module with heat spreader
US7650557B2 (en) 2005-09-19 2010-01-19 Network Appliance, Inc. Memory scrubbing of expanded memory
US7620746B2 (en) * 2005-09-29 2009-11-17 Apple Inc. Functional DMA performing operation on DMA data and writing result of operation
US8862783B2 (en) * 2005-10-25 2014-10-14 Broadbus Technologies, Inc. Methods and system to offload data processing tasks
US7899864B2 (en) 2005-11-01 2011-03-01 Microsoft Corporation Multi-user terminal services accelerator
US7773630B2 (en) * 2005-11-12 2010-08-10 Liquid Computing Corportation High performance memory based communications interface
US8225297B2 (en) 2005-12-07 2012-07-17 Microsoft Corporation Cache metadata identifiers for isolation and sharing
US7904688B1 (en) 2005-12-21 2011-03-08 Trend Micro Inc Memory management unit for field programmable gate array boards
US20070150671A1 (en) * 2005-12-23 2007-06-28 Boston Circuits, Inc. Supporting macro memory instructions
EP1977635A2 (en) 2006-01-13 2008-10-08 Sun Microsystems, Inc. Modular blade server
US7619893B1 (en) 2006-02-17 2009-11-17 Netlist, Inc. Heat spreader for electronic modules
US20070226745A1 (en) 2006-02-28 2007-09-27 International Business Machines Corporation Method and system for processing a service request
JP2007233903A (en) * 2006-03-03 2007-09-13 Hitachi Ltd Storage controller and data recovery method for storage controller
US7421552B2 (en) 2006-03-17 2008-09-02 Emc Corporation Techniques for managing data within a data storage system utilizing a flash-based memory vault
US7434002B1 (en) 2006-04-24 2008-10-07 Vmware, Inc. Utilizing cache information to manage memory access and cache utilization
JP2007299279A (en) * 2006-05-01 2007-11-15 Toshiba Corp Arithmetic device, processor system, and video processor
US8869147B2 (en) * 2006-05-31 2014-10-21 Qualcomm Incorporated Multi-threaded processor with deferred thread output control
US7716411B2 (en) 2006-06-07 2010-05-11 Microsoft Corporation Hybrid memory device with single interface
US8948166B2 (en) 2006-06-14 2015-02-03 Hewlett-Packard Development Company, Lp. System of implementing switch devices in a server system
WO2007147170A2 (en) 2006-06-16 2007-12-21 Bittorrent, Inc. Classification and verification of static file transfer protocols
US7636800B2 (en) 2006-06-27 2009-12-22 International Business Machines Corporation Method and system for memory address translation and pinning
US8599716B2 (en) * 2006-06-30 2013-12-03 Cisco Technolgy, Inc. Method and system to configure quality of service in a network
US7291032B1 (en) * 2006-07-05 2007-11-06 International Business Machines Corporation Connector for adjacent devices
KR100823734B1 (en) * 2006-07-07 2008-04-21 한국전자통신연구원 Data acceleration apparatus for iSCSI and iSCSI storage system using the same
US7624118B2 (en) 2006-07-26 2009-11-24 Microsoft Corporation Data processing over very large databases
US7760715B1 (en) 2006-08-04 2010-07-20 Parin B. Dalal Circuit and method for rate-limiting a scheduler
US8116320B2 (en) * 2006-08-07 2012-02-14 Adc Telecommunications, Inc. Mapping external port using virtual local area network
US8943245B2 (en) 2006-09-28 2015-01-27 Virident Systems, Inc. Non-volatile type memory modules for main memory
US20080082750A1 (en) 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
US8074022B2 (en) 2006-09-28 2011-12-06 Virident Systems, Inc. Programmable heterogeneous memory controllers for main memory with different memory modules
WO2008051940A2 (en) 2006-10-23 2008-05-02 Virident Systems, Inc. Methods and apparatus of dual inline memory modules for flash memory
US7774556B2 (en) 2006-11-04 2010-08-10 Virident Systems Inc. Asymmetric memory migration in hybrid main memory
US8447957B1 (en) * 2006-11-14 2013-05-21 Xilinx, Inc. Coprocessor interface architecture and methods of operating the same
US8149834B1 (en) * 2007-01-25 2012-04-03 World Wide Packets, Inc. Forwarding a packet to a port from which the packet is received and transmitting modified, duplicated packets on a single port
US20080222351A1 (en) * 2007-03-07 2008-09-11 Aprius Inc. High-speed optical connection between central processing unit and remotely located random access memory
US20080229049A1 (en) 2007-03-16 2008-09-18 Ashwini Kumar Nanda Processor card for blade server and process.
ES2883587T3 (en) 2007-04-12 2021-12-09 Rambus Inc Memory system with peer-to-peer request interconnect
US8935406B1 (en) * 2007-04-16 2015-01-13 Chelsio Communications, Inc. Network adaptor configured for connection establishment offload
US20080271030A1 (en) * 2007-04-30 2008-10-30 Dan Herington Kernel-Based Workload Management
US8301833B1 (en) 2007-06-01 2012-10-30 Netlist, Inc. Non-volatile memory module
US8904098B2 (en) 2007-06-01 2014-12-02 Netlist, Inc. Redundant backup using non-volatile memory
US8874831B2 (en) 2007-06-01 2014-10-28 Netlist, Inc. Flash-DRAM hybrid memory module
US8347005B2 (en) 2007-07-31 2013-01-01 Hewlett-Packard Development Company, L.P. Memory controller with multi-protocol interface
US7743196B2 (en) * 2007-08-15 2010-06-22 Agere Systems Inc. Interface with multiple packet preemption based on start indicators of different types
US7840748B2 (en) 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
JP5059524B2 (en) * 2007-09-05 2012-10-24 ルネサスエレクトロニクス株式会社 MEMORY CONTROL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND NONVOLATILE MEMORY VERIFY METHOD
US8503465B2 (en) * 2007-09-17 2013-08-06 Qualcomm Incorporated Priority scheduling and admission control in a communication network
US7949683B2 (en) 2007-11-27 2011-05-24 Cavium Networks, Inc. Method and apparatus for traversing a compressed deterministic finite automata (DFA) graph
US20090158276A1 (en) * 2007-12-12 2009-06-18 Eric Lawrence Barsness Dynamic distribution of nodes on a multi-node computer system
US8862706B2 (en) * 2007-12-14 2014-10-14 Nant Holdings Ip, Llc Hybrid transport—application network fabric apparatus
US8990799B1 (en) * 2008-01-30 2015-03-24 Emc Corporation Direct memory access through virtual switch in device driver
US8856464B2 (en) * 2008-02-12 2014-10-07 Virident Systems, Inc. Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices
US20090249330A1 (en) * 2008-03-31 2009-10-01 Abercrombie David K Method and apparatus for hypervisor security code
JP5186982B2 (en) 2008-04-02 2013-04-24 富士通株式会社 Data management method and switch device
US20110235260A1 (en) 2008-04-09 2011-09-29 Apacer Technology Inc. Dram module with solid state disk
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8001434B1 (en) 2008-04-14 2011-08-16 Netlist, Inc. Memory board with self-testing capability
US8417870B2 (en) 2009-07-16 2013-04-09 Netlist, Inc. System and method of increasing addressable memory space on a memory board
CA2719841C (en) 2008-05-22 2016-03-22 Nokia Siemens Networks Oy Adaptive scheduler for communication systems apparatus, system and method
TWI469055B (en) * 2008-06-27 2015-01-11 Realtek Semiconductor Corp Network task offload apparatus and method thereof
US8190699B2 (en) 2008-07-28 2012-05-29 Crossfield Technology LLC System and method of multi-path data communications
US20100031235A1 (en) 2008-08-01 2010-02-04 Modular Mining Systems, Inc. Resource Double Lookup Framework
US20100032820A1 (en) * 2008-08-06 2010-02-11 Michael Bruennert Stacked Memory Module
US7886103B2 (en) * 2008-09-08 2011-02-08 Cisco Technology, Inc. Input-output module, processing platform and method for extending a memory interface for input-output operations
US8452934B2 (en) * 2008-12-16 2013-05-28 Sandisk Technologies Inc. Controlled data access to non-volatile memory
US7930519B2 (en) * 2008-12-17 2011-04-19 Advanced Micro Devices, Inc. Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
GB2466289A (en) * 2008-12-18 2010-06-23 Veda Technology Ltd Executing a service application on a cluster by registering a class and storing subscription information of generated objects at an interconnect
US7870309B2 (en) * 2008-12-23 2011-01-11 International Business Machines Corporation Multithreaded programmable direct memory access engine
US8054832B1 (en) 2008-12-30 2011-11-08 Juniper Networks, Inc. Methods and apparatus for routing between virtual resources based on a routing location policy
GB2466984B (en) * 2009-01-16 2011-07-27 Imagination Tech Ltd Multi-threaded data processing system
US8352710B2 (en) * 2009-01-19 2013-01-08 International Business Machines Corporation Off-loading of processing from a processor blade to storage blades
US20100183033A1 (en) 2009-01-20 2010-07-22 Nokia Corporation Method and apparatus for encapsulation of scalable media
US8498349B2 (en) 2009-03-11 2013-07-30 Texas Instruments Incorporated Demodulation and decoding for frequency modulation (FM) receivers with radio data system (RDS) or radio broadcast data system (RBDS)
US8949838B2 (en) * 2009-04-27 2015-02-03 Lsi Corporation Multi-threaded processing with hardware accelerators
US8869150B2 (en) * 2010-05-18 2014-10-21 Lsi Corporation Local messaging in a scheduling hierarchy in a traffic manager of a network processor
US8009682B2 (en) * 2009-05-05 2011-08-30 Citrix Systems, Inc. Systems and methods for packet steering in a multi-core architecture
US8264903B1 (en) 2009-05-05 2012-09-11 Netlist, Inc. Systems and methods for refreshing a memory module
US8489837B1 (en) 2009-06-12 2013-07-16 Netlist, Inc. Systems and methods for handshaking with a memory module
US8892783B2 (en) * 2009-06-22 2014-11-18 Citrix Systems, Inc. Systems and methods for initialization and link management of NICS in a multi-core environment
US8205057B2 (en) * 2009-06-30 2012-06-19 Texas Instruments Incorporated Method and system for integrated pipeline write hazard handling using memory attributes
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US9535849B2 (en) 2009-07-24 2017-01-03 Advanced Micro Devices, Inc. IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect
US8085801B2 (en) * 2009-08-08 2011-12-27 Hewlett-Packard Development Company, L.P. Resource arbitration
US20110035540A1 (en) 2009-08-10 2011-02-10 Adtron, Inc. Flash blade system architecture and method
US8479216B2 (en) * 2009-08-18 2013-07-02 International Business Machines Corporation Method for decentralized load distribution in an event-driven system using localized migration between physically connected nodes and load exchange protocol preventing simultaneous migration of plurality of tasks to or from a same node
US8848513B2 (en) 2009-09-02 2014-09-30 Qualcomm Incorporated Seamless overlay connectivity using multi-homed overlay neighborhoods
US8972627B2 (en) * 2009-09-09 2015-03-03 Fusion-Io, Inc. Apparatus, system, and method for managing operations for data storage media
US9876735B2 (en) * 2009-10-30 2018-01-23 Iii Holdings 2, Llc Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US20110083175A1 (en) * 2009-10-06 2011-04-07 Sonus Networks, Inc. Methods and Apparatuses for Policing and Prioritizing of Data Services
US8442048B2 (en) * 2009-11-04 2013-05-14 Juniper Networks, Inc. Methods and apparatus for configuring a virtual network switch
US9445309B2 (en) * 2009-12-08 2016-09-13 Nec Corporation Bandwidth control device, bandwidth control method, and wireless network system
US9389895B2 (en) 2009-12-17 2016-07-12 Microsoft Technology Licensing, Llc Virtual storage target offload techniques
US8743877B2 (en) * 2009-12-21 2014-06-03 Steven L. Pope Header processing engine
US9390035B2 (en) 2009-12-21 2016-07-12 Sanmina-Sci Corporation Method and apparatus for supporting storage modules in standard memory and/or hybrid memory bus architectures
US8473695B2 (en) * 2011-03-31 2013-06-25 Mosys, Inc. Memory system including variable write command scheduling
US8489789B2 (en) * 2010-02-05 2013-07-16 Advanced Micro Devices, Inc. Interrupt virtualization
US20110208900A1 (en) * 2010-02-23 2011-08-25 Ocz Technology Group, Inc. Methods and systems utilizing nonvolatile memory in a computer system main memory
EP2363812B1 (en) 2010-03-04 2018-02-28 Karlsruher Institut für Technologie Reconfigurable processor architecture
CN102906696A (en) 2010-03-26 2013-01-30 维尔图尔梅特里克斯公司 Fine grain performance resource management of computer systems
CN101794271B (en) * 2010-03-31 2012-05-23 华为技术有限公司 Implementation method and device of consistency of multi-core internal memory
JP5336423B2 (en) * 2010-05-14 2013-11-06 パナソニック株式会社 Computer system
WO2011150346A2 (en) 2010-05-28 2011-12-01 Laurich Lawrence A Accelerator system for use with secure data storage
US8631271B2 (en) 2010-06-24 2014-01-14 International Business Machines Corporation Heterogeneous recovery in a redundant memory system
US10803066B2 (en) 2010-06-29 2020-10-13 Teradata Us, Inc. Methods and systems for hardware acceleration of database operations and queries for a versioned database based on multiple hardware accelerators
US9118591B2 (en) 2010-07-30 2015-08-25 Broadcom Corporation Distributed switch domain of heterogeneous components
JP5636109B2 (en) * 2010-08-23 2014-12-03 エンパイア テクノロジー ディベロップメント エルエルシー Context switch
TW201214082A (en) * 2010-09-17 2012-04-01 Hon Hai Prec Ind Co Ltd Mother board
GB2513551B (en) 2010-09-24 2018-01-10 Ibm High-speed memory system
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US8483046B2 (en) 2010-09-29 2013-07-09 International Business Machines Corporation Virtual switch interconnect for hybrid enterprise servers
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8405668B2 (en) * 2010-11-19 2013-03-26 Apple Inc. Streaming translation in display pipe
US8996644B2 (en) * 2010-12-09 2015-03-31 Solarflare Communications, Inc. Encapsulated accelerator
US8566831B2 (en) * 2011-01-26 2013-10-22 International Business Machines Corporation Execution of work units in a heterogeneous computing environment
US20120239874A1 (en) 2011-03-02 2012-09-20 Netlist, Inc. Method and system for resolving interoperability of multiple types of dual in-line memory modules
US8885334B1 (en) * 2011-03-10 2014-11-11 Xilinx, Inc. Computing system with network attached processors
US8774213B2 (en) 2011-03-30 2014-07-08 Amazon Technologies, Inc. Frameworks and interfaces for offload device-based packet processing
US8825900B1 (en) * 2011-04-05 2014-09-02 Nicira, Inc. Method and apparatus for stateless transport layer tunneling
US8930647B1 (en) 2011-04-06 2015-01-06 P4tents1, LLC Multiple class memory systems
WO2012141694A1 (en) 2011-04-13 2012-10-18 Hewlett-Packard Development Company, L.P. Input/output processing
US8442056B2 (en) 2011-06-28 2013-05-14 Marvell International Ltd. Scheduling packets in a packet-processing pipeline
US8547825B2 (en) * 2011-07-07 2013-10-01 International Business Machines Corporation Switch fabric management
US20130019057A1 (en) 2011-07-15 2013-01-17 Violin Memory, Inc. Flash disk array and controller
RU2014106859A (en) 2011-07-25 2015-08-27 Серверджи, Инк. METHOD AND SYSTEM FOR CONSTRUCTION OF A LOW POWER COMPUTER SYSTEM
KR101989586B1 (en) * 2011-08-10 2019-06-14 마벨 월드 트레이드 리미티드 Intelligent phy with security detection for ethernet networks
US8767463B2 (en) 2011-08-11 2014-07-01 Smart Modular Technologies, Inc. Non-volatile dynamic random access memory system with non-delay-lock-loop mechanism and method of operation thereof
US9021146B2 (en) * 2011-08-30 2015-04-28 Apple Inc. High priority command queue for peripheral component
US9223618B2 (en) * 2011-09-20 2015-12-29 Intel Corporation Multi-threaded queuing system for pattern matching
US9094333B1 (en) * 2011-10-26 2015-07-28 Qlogic, Corporation Systems and methods for sending and receiving information via a network device
US8966457B2 (en) * 2011-11-15 2015-02-24 Global Supercomputing Corporation Method and system for converting a single-threaded software program into an application-specific supercomputer
US9424188B2 (en) 2011-11-23 2016-08-23 Smart Modular Technologies, Inc. Non-volatile memory packaging system with caching and method of operation thereof
US20140325183A1 (en) * 2011-11-28 2014-10-30 Freescale Semiconductor, Inc. Integrated circuit device, asymmetric multi-core processing module, electronic device and method of managing execution of computer program code therefor
US10203881B2 (en) * 2011-12-19 2019-02-12 Apple Inc. Optimized execution of interleaved write operations in solid state drives
US9443279B2 (en) * 2011-12-26 2016-09-13 Intel Corporation Direct link synchronization communication between co-processors
US9170947B2 (en) * 2011-12-29 2015-10-27 Intel Corporation Recovering from data errors using implicit redundancy
US9542437B2 (en) 2012-01-06 2017-01-10 Sap Se Layout-driven data selection and reporting
US8918634B2 (en) 2012-02-21 2014-12-23 International Business Machines Corporation Network node with network-attached stateless security offload device employing out-of-band processing
JP5565425B2 (en) * 2012-02-29 2014-08-06 富士通株式会社 Arithmetic apparatus, information processing apparatus and arithmetic method
WO2013128494A1 (en) 2012-03-02 2013-09-06 Hitachi, Ltd. Storage system and data transfer control method
US20130254457A1 (en) * 2012-03-21 2013-09-26 Lsi Corporation Methods and structure for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory
US9513845B2 (en) 2012-03-30 2016-12-06 Violin Memory Inc. Memory module virtualization
US10019371B2 (en) 2012-04-27 2018-07-10 Hewlett Packard Enterprise Development Lp Data caching using local and remote memory
US9558351B2 (en) 2012-05-22 2017-01-31 Xockets, Inc. Processing structured and unstructured data using offload processors
US9495308B2 (en) 2012-05-22 2016-11-15 Xockets, Inc. Offloading of computation for rack level servers and corresponding methods and systems
US9749413B2 (en) * 2012-05-29 2017-08-29 Intel Corporation Peer-to-peer interrupt signaling between devices coupled via interconnects
US20130347103A1 (en) * 2012-06-21 2013-12-26 Mark Veteikis Packet capture for error tracking
US20140089609A1 (en) * 2012-09-26 2014-03-27 Advanced Micro Devices, Inc. Interposer having embedded memory controller circuitry
US9170968B2 (en) * 2012-09-27 2015-10-27 Intel Corporation Device, system and method of multi-channel processing
US20140101370A1 (en) * 2012-10-08 2014-04-10 HGST Netherlands B.V. Apparatus and method for low power low latency high capacity storage class memory
US9268716B2 (en) * 2012-10-19 2016-02-23 Yahoo! Inc. Writing data from hadoop to off grid storage
US20140157287A1 (en) * 2012-11-30 2014-06-05 Advanced Micro Devices, Inc Optimized Context Switching for Long-Running Processes
US9654406B2 (en) * 2012-12-26 2017-05-16 Realtek Singapore Pte Ltd Communication traffic processing architectures and methods
US9378161B1 (en) 2013-01-17 2016-06-28 Xockets, Inc. Full bandwidth packet handling with server systems including offload processors
US10031820B2 (en) 2013-01-17 2018-07-24 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Mirroring high performance and high availablity applications across server computers
US9250954B2 (en) 2013-01-17 2016-02-02 Xockets, Inc. Offload processor modules for connection to system memory, and corresponding methods and systems
US10372551B2 (en) 2013-03-15 2019-08-06 Netlist, Inc. Hybrid memory system with configurable error thresholds and failure analysis capability
US9792154B2 (en) 2015-04-17 2017-10-17 Microsoft Technology Licensing, Llc Data processing system having a hardware acceleration plane and a software plane

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179489B1 (en) * 1997-04-04 2001-01-30 Texas Instruments Incorporated Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto
US20040059825A1 (en) * 2002-02-08 2004-03-25 Edwards Paul C. Medium access control in a wireless network
US20040202319A1 (en) * 2003-04-12 2004-10-14 Hussain Muhammad Raghib Apparatus and method for allocating resources within a security processor
US7436845B1 (en) * 2004-06-08 2008-10-14 Sun Microsystems, Inc. Input and output buffering
US8072887B1 (en) * 2005-02-07 2011-12-06 Extreme Networks, Inc. Methods, systems, and computer program products for controlling enqueuing of packets in an aggregated queue including a plurality of virtual queues using backpressure messages from downstream queues

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017112143A1 (en) * 2015-12-22 2017-06-29 Intel Corporation Methods and apparatus for multi-stage vm virtual network function and virtual service function chain acceleration for nfv and needs-based hardware acceleration
US10048977B2 (en) 2015-12-22 2018-08-14 Intel Corporation Methods and apparatus for multi-stage VM virtual network function and virtual service function chain acceleration for NFV and needs-based hardware acceleration
US20170286332A1 (en) * 2016-03-29 2017-10-05 Karunakara Kotary Technologies for processor core soft-offlining
US10802998B2 (en) * 2016-03-29 2020-10-13 Intel Corporation Technologies for processor core soft-offlining
US10148576B2 (en) * 2016-07-28 2018-12-04 Fortinet, Inc. Network processing unit (NPU) integrated layer 2 network device for layer 3 offloading
US20210105221A1 (en) * 2016-12-06 2021-04-08 Microsoft Technology Licensing, Llc Network processing resource management in computing systems
US12015563B2 (en) * 2016-12-06 2024-06-18 Microsoft Technology Licensing, Llc Management of resource affinities in computing systems having multiple cores
WO2019108310A1 (en) * 2017-12-03 2019-06-06 Intel Corporation Mechanisms for fpga chaining and unified fpga views to composed system hosts
US11182324B2 (en) 2017-12-03 2021-11-23 Intel Corporation Unified FPGA view to a composed host

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