US20140173180A1 - Tracking read accesses to regions of non-volatile memory - Google Patents
Tracking read accesses to regions of non-volatile memory Download PDFInfo
- Publication number
- US20140173180A1 US20140173180A1 US13/756,946 US201313756946A US2014173180A1 US 20140173180 A1 US20140173180 A1 US 20140173180A1 US 201313756946 A US201313756946 A US 201313756946A US 2014173180 A1 US2014173180 A1 US 2014173180A1
- Authority
- US
- United States
- Prior art keywords
- regions
- counters
- volatile memory
- counter
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
Definitions
- the present disclosure is generally related to tracking accesses to non-volatile memory.
- Non-volatile data storage devices such as universal serial bus (USB) flash memory devices or removable storage cards
- Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell.
- Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more.
- ECC Error correction coding
- data Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g. “parity bits”) that may be stored with the data as an ECC codeword.
- parity bits redundant information
- an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases.
- One source of errors that occur in data stored in a memory device is a result of read accesses to the memory device.
- threshold voltages of neighboring word lines may be disturbed (e.g., slightly increased) due to inter-cell coupling within the memory device.
- Read disturb effects are cumulative and, if not remedied, may result in a number of errors in stored data exceeding an ECC error correction capacity of a data storage device.
- Read accesses to regions of a non-volatile memory of a data storage device are tracked by a set of counters.
- a remedial action such as a data refresh operation or a data move operation, is initiated to data stored in the particular region.
- read disturb effects to data stored in the memory may be corrected via refreshing or moving the data prior to accumulated read disturb effects exceeding a correction capability of the data storage device.
- Logical partitioning of the non-volatile memory into regions for read access tracking may be programmable and may be adaptively determined based on various factors to accommodate varying sensitivity to read disturb effects within the non-volatile memory.
- FIG. 1 is a block diagram of a particular illustrative embodiment of a system including a data storage device configured to track read accesses to multiple regions of memory and to initiate a remedial action;
- FIG. 2 is a block diagram illustrating a particular embodiment of components that may be incorporated in the data storage device of FIG. 1 ;
- FIG. 3 is a general diagram that illustrates logical partitioning of the memory of FIG. 1 and mappings of counters to regions of the memory;
- FIG. 4 is a flow chart of a particular illustrative embodiment of a method of tracking read accesses to regions of a non-volatile memory.
- a particular embodiment of a system 100 includes a data storage device 102 coupled to a host device 130 .
- the data storage device 102 is configured to track read accesses to multiple regions of a non-volatile memory 104 and to initiate a remedial action based on the tracked read accesses.
- the host device 130 may be configured to provide data, such as user data 132 , to be stored at the non-volatile memory 104 or to request data to be read from the memory 104 .
- the host device 130 may include a mobile telephone, a music or video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer, a notebook computer, or a tablet, solid state storage drive, any other electronic device, or any combination thereof.
- PDA personal digital assistant
- the data storage device 102 includes the non-volatile memory 104 coupled to a controller 120 .
- the non-volatile memory 104 may be a flash memory, such as a NAND flash memory.
- the data storage device 102 may be a memory card, such as a Secure Digital SD® card, a microSD® card, a miniSDTM card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCardTM (MMCTM) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.).
- the data storage device 102 may be configured to be coupled to the host device 130 as embedded memory, such as eMMC® (trademark of JEDEC Solid State Technology Association, Arlington, Va.) and eSD, as illustrative examples.
- the non-volatile memory 104 includes multiple groups of storage elements, such as word lines of a multi-level cell (MLC) flash memory that include multiple MLC flash cells.
- the non-volatile memory 104 may also include multiple blocks of storage elements, such as erase blocks of a flash memory that include multiple word lines in each erase block.
- the non-volatile memory 104 is logically partitioned into multiple regions including a first region (region 1 ) 110 and an Nth region (region N) 112 , where N is an integer greater than one.
- Each region 110 - 112 can include one or more word lines, blocks, or other portions of the non-volatile memory 104 .
- each region 110 - 112 may include multiple word lines or blocks within a single array, plane, or die.
- a single region e.g., the first region 110
- the first region 110 may span multiple arrays, planes, or dies, or any combination thereof.
- the first region 110 may include storage elements within a first die and storage elements within a second die.
- the controller 120 is configured to receive data and instructions from and to send data to the host device 130 while the data storage device 102 is operatively coupled to the host device 130 .
- the controller 120 is further configured to send data and commands to the memory 104 and to receive data from the memory 104 .
- the controller 120 is configured to send data and a write command to instruct the non-volatile memory 104 to store the data to a specified address.
- the controller 120 is configured to send a read command to read data from a specified address of the non-volatile memory 104 .
- the controller 120 may include an ECC engine (not shown) that is configured to receive data to be stored to the non-volatile memory 104 and to generate a codeword.
- the ECC engine may include an encoder configured to encode data using an ECC encoding scheme, such as a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, a Turbo Code encoder, an encoder configured to encode data according to one or more other ECC encoding schemes, or any combination thereof.
- the ECC engine may include a decoder configured to decode data read from the non-volatile memory 104 to detect and correct, up to an error correction capability of the ECC scheme, bit errors that may be present in the data.
- the controller 120 includes a set of counters 122 that are configured to track read accesses performed to the regions 110 - 112 of the non-volatile memory 104 .
- the set of counters 122 includes multiple counters, including a first counter (counter 1 ) 140 and an Nth counter (counter N) 142 .
- the first counter 140 has a first counter value (value 1) 160 that is updatable by the controller 120 to track memory accesses to the first region 110 .
- the Nth counter 142 has an Nth value 162 that is also updatable by the controller 120 to track memory accesses to the Nth region 112 .
- the controller 120 includes a memory management engine 124 .
- the memory management engine 124 is configured to receive read requests from the host device 130 and to determine a read address 152 corresponding to the requested data.
- the read address 152 may correspond to a physical address of one or more wordlines in the non-volatile memory 104 .
- the memory management engine 124 may receive a logical address of requested data stored in the non-volatile memory 104 and may perform an address translation to generate a physical read address, such as the read address 152 .
- the memory management engine 124 is configured to generate a read command 150 to read data from the read address 152 of the non-volatile memory 104 .
- the memory management engine 124 is configured to provide the read address 152 to the set of read access counters 122 .
- the controller 120 may select a particular counter of the set of counters 122 corresponding to a region of the non-volatile memory 104 that is tracked by the particular counter. For example, when the read address 152 corresponds to data in the first region 110 , the controller 120 may determine that the first counter 140 maintains a count of read accesses to the first region 110 , and as a result the first value 160 may be updated by the first counter 140 . As another example, when the read address 152 corresponds to an address in the Nth region 112 , which is tracked by the Nth counter 142 , the Nth value 162 of the Nth counter 142 may be updated to indicate the read operation.
- Each of the values 160 - 162 that correspond to counts of read accesses to the particular regions tracked by the corresponding counters 140 - 142 are compared to a threshold 170 .
- a flag 154 may be generated and provided to the memory management engine 124 .
- the memory management engine 124 may receive the flag 154 and may initiate a remedial action 126 to the corresponding region of the non-volatile memory 104 .
- the controller 120 may be configured to initiate the remedial action 126 to the first region 110 .
- the remedial action 126 may include a data move operation that causes data in the corresponding region 110 to be moved to a different memory location of the non-volatile memory 104 .
- the remedial action 126 may include a data refresh operation.
- the data refresh operation may include copying data from each block of the region 110 , erasing the particular block, and re-writing the data to the erased block.
- a shifting of states of storage elements as a result of read disturb effects may be remedied, and the storage elements within the block or groups of blocks may be returned to an originally programmed state.
- Potential corruption of data in the non-volatile memory 104 caused by read disturb effects may be anticipated based on counts of read accesses to each of the regions 110 - 112 and the remedial action 126 may be performed to avoid unrecoverable corruption of data resulting from accumulated read disturb effects resulting from multiple read accesses.
- the counters 140 - 142 may count upward from a reset value (e.g., a 0 value) with each read access to the region tracked by the particular counter 140 - 142 .
- the value 160 - 162 of each counter 140 - 142 may be compared against the threshold 170 (e.g., each time the value 160 - 162 is updated) to determine when a number of read accesses to a corresponding region 110 - 112 of the non-volatile memory 104 meets or exceeds the threshold 170 .
- other configurations of the counters 140 - 142 may be applied.
- the counters 140 - 142 may be initially set to a value corresponding to a read access limit, and the counters 140 - 142 may decrement the corresponding value 160 - 162 with each read access.
- the flag 154 may be provided to the memory management engine 124 .
- the controller 120 may be configured to store counter values 180 to specific or dedicated portions of the non-volatile memory 104 for storage during power off conditions.
- the controller 120 may be configured to store counter values 180 of the set of counters 122 to the non-volatile memory 104 during a session shutdown operation of the data storage device 102 .
- the controller 120 may further be configured to retrieve the stored counter values 180 from the non-volatile memory 104 and to initialize the counters 140 - 142 of the set of counters 122 according to the stored counter values 180 during a session initialization operation of the data storage device 102 .
- the counter values 180 may include a table or other data structure that indicates a number of the regions 110 - 112 (e.g., N regions), and for each region, may include a value of a corresponding counter (e.g., the first value 160 for the first region 110 , an address range corresponding to the particular region (e.g., addresses of a first and last erase block within the first region 110 ), and a value of the threshold 170 corresponding to the particular region.
- a number and arrangement of the regions 110 - 112 may be modified over the life of the data storage device 102 .
- values of the threshold 170 may be modified from an initial value, and different regions 110 - 112 may correspond to different thresholds.
- the host device 130 may request the user data 132 to be read from the non-volatile memory 104 .
- the memory management engine 124 may translate an address of the requested user data 132 and may provide the read address 152 to the set of read access counters 122 .
- the controller 120 may issue the read command 150 to the non-volatile memory 104 , such as concurrently with providing the read address 152 to the set of read counters 122 .
- the controller 120 may determine a particular counter of the set of counters 122 that tracks the region of the non-volatile memory 104 corresponding to the read address 152 .
- the read address 152 may correspond to a wordline in the first region 110 , which may be tracked by the first counter 140 .
- a determination may be made that the read address 152 corresponds to the first counter 140 , and the first counter 140 may update the first value 160 to indicate an additional read access has been or is being performed within the first region 110 .
- requested data may be provided from the non-volatile memory 104 to the controller 120 as read data 156 .
- the controller 120 may process the read data 156 , such as by decoding the read data 156 and correcting one or more read errors that may occur in the read data 156 , and may provide the resulting user data 132 to the host device 130 .
- a corresponding flag 154 may be provided to the memory management engine 124 in response to the first value 160 (upon being updated by the first counter 140 ) equaling or exceeding the threshold 170 .
- the memory management engine 124 may initiate the remedial action 126 , such as by providing memory addresses or block indicators to a move queue or a refresh queue for scheduling a data move operation or a data refresh operation, such as described in further detail with respect to FIG. 2 .
- the set of counters 122 and corresponding logic to map the set of counters 122 to individual regions of the non-volatile memory 104 may be implemented in dedicated circuitry to reduce latency and processing impact on the controller 120 during the read access operation, as described in further detail with respect to FIG. 2 .
- the set of read access counters 122 may be implemented via one or more software processes executed by a processor within the controller 120 , or by a combination of software executed by a processor and dedicated circuitry.
- the non-volatile memory 104 is illustrated as a NAND flash memory that includes multiple erase blocks, including block 0 220 , block 1 222 , block 2 224 , block 3 226 , and additional blocks up to an Mth block (block M) 228 .
- the NAND flash memory 104 is logically partitioned into multiple read tracking regions, illustrated as a first read tracking region 210 , a second read tracking region 212 , and additional regions up to an N ⁇ 1st read tracking region 214 and an Nth read tracking region 216 .
- the controller 120 includes the set of counters 122 including the first counter 140 , a second counter 141 , and one or more other counters including the Nth counter 142 .
- the controller 120 includes address comparison circuitry 240 that is coupled to receive the read address 152 from the flash management engine 124 and to generate an output signal to a counter that tracks a region 210 - 216 of the NAND flash memory 104 corresponding to the read address 152 .
- the controller 120 further includes a count of write/erase cycles 244 , a write/erase threshold 246 , and a move/refresh queue 242 .
- the controller 120 is configured to provide the read address 152 from the flash management engine 124 to the address comparison circuitry 240 .
- the address comparison circuitry 240 may be programmable to route particular read addresses 152 to particular counters of the set of counters 122 . For example, the address comparison circuitry 240 may determine whether the read address 152 is within a first address range corresponding to the first read tracking region 210 , a second address range corresponding to the second read tracking region 212 , etc., and may generate an output signal to a corresponding one of the counters 140 - 142 to cause the counter to update its counter value.
- Each of the counters 140 - 142 may be responsive to a corresponding threshold, illustrated as threshold 1, threshold 2, . . . threshold N.
- each counter 140 - 142 may be configured to perform comparisons of the counter's value to its corresponding threshold and to generate a flag signal in response to the value meeting or exceeding the threshold.
- the first counter 140 updates its counter value to an amount that matches the first threshold (threshold 1)
- the first counter 140 may generate a first flag indication (Flag 1) that may be provided to the flash management engine 124 as the flag 154 .
- Each of the counters 140 - 142 may have a programmable threshold value such that each of the thresholds may have a distinct value, or one or more (or all) of the counters 140 - 142 may use a same threshold value.
- Each of the counters 140 - 142 may provide a distinct flag signal to the flash management engine 124 .
- the flag indicator 154 may be a multi-bit signal, such as an interrupt signal with each bit of the interrupt signal corresponding to a distinct counter of the set of counters 122 .
- the flash management engine 124 may determine a particular read tracking region 210 - 216 that has a count of read accesses matching or exceeding its corresponding threshold.
- the flash management engine 124 may perform the remedial action 126 of FIG. 1 by adding addresses of the blocks of the corresponding region, such as block 0-3 220 - 226 of the first read tracking region 210 , to the move/refresh queue 242 .
- the flash management engine 124 may be configured to perform data move operations to transfer data from addresses indicated in the move/refresh queue 242 to other addresses in the NAND flash memory 104 .
- the flash management engine 124 may be configured to perform refresh operations of blocks indicated in the move/refresh queue 242 .
- the flash management engine 124 may perform data moves or data refreshes as part of housekeeping operations at the controller 120 , such as in a background process.
- the flash management engine 124 may be configured to keep track of a write/erase count 244 of write and erase cycles performed at the NAND flash memory 104 . For example, the flash management engine 124 may determine an “age” of the NAND flash memory 104 based on the write/erase count 244 . Because an ability of the NAND flash memory 104 to maintain distinct states of storage elements may degrade, as the write/erase count 244 increases, the counter thresholds may be reduced as the device 200 ages (e.g., as the write/erase count 244 increases).
- the flash management engine 124 may be configured to compare the write/erase count 244 to the write/erase threshold 246 , and upon determining that the write/erase count 244 meets or exceeds the write/erase threshold 246 , to perform one or more updates of the read tracking mechanism. For example, the flash management engine 124 may be configured to update logical partitioning of the NAND flash memory 104 into a greater number of read tracking regions 210 - 216 , as described in further detail with respect to FIG. 3 . As another example, the flash management engine 124 may decrease the thresholds for each of the counters 140 - 142 so that remedial actions are taken more frequently for older memories than for fresh memories that have a greater capacity to maintain distinct states of memory cells in the NAND flash memory 104 .
- the first logical partitioning 304 may correspond to a partitioning of the non-volatile memory 104 into four regions including a first region 340 , a second region 342 , a third region 344 , and a fourth region 346 .
- the four regions 340 - 346 may span the entire non-volatile memory 104 , from a lowest indexed block (block 0 220 ) to a highest indexed block (block M 228 ).
- the set of counters 122 is illustrated as including a first counter 320 , a second counter 322 , a third counter 324 , a fourth counter 326 , a fifth counter 328 , a sixth counter 330 , a seventh counter 332 , and an eighth counter 334 , and may include one or more additional counters (not shown).
- the first counter 320 is mapped to the first region 340
- the second counter 322 is mapped to the second region 342
- the third counter 324 is mapped to the third region 344
- the fourth counter 326 is mapped to the fourth region 346 .
- the remaining counters 328 - 334 are not mapped to any of the memory regions 344 - 346 and may be unused.
- the first mapping of regions to counters 302 and the first logical partitioning 304 may be applied by the controller 120 of FIGS. 1-2 in response to the write/erase count 244 of FIG. 2 being less than the write/erase threshold 246 .
- the first mapping of regions to counters 302 and the first logical partitioning 304 may be an initial configuration of the memory device 102 of FIG. 1 and may be set according to an initial set of programmable values, such as determined by a manufacturer of the data storage device 102 .
- the write/erase count 244 may eventually equal or surpass the write/erase threshold 246 .
- the controller 120 of FIG. 1 may be configured to modify the logical partitioning of the non-volatile memory 104 from the first logical partitioning 304 including the first set of regions 340 - 346 to the second logical partitioning 384 that includes a second set of regions.
- the second set of regions includes a first region 350 , a second region 352 , a third region 354 , a fourth region 356 , a fifth region 358 , a sixth region 360 , a seventh region 362 , and an eighth region 364 .
- the number of regions in the second set of regions 350 - 364 (e.g., 8) is greater than the first number of regions in the first set of regions 340 - 346 (e.g., 4).
- the controller 120 may also be configured to update a mapping of regions from the first mapping of regions to counters 302 to the second mapping of regions to counters 382 .
- the second mapping of regions to counters 382 enables tracking of each region of the second set of multiple regions 350 - 364 with a respective counter 320 - 334 of the set of counters 122 .
- the second logical partitioning 384 may be formed by subdividing each of the regions of the first logical partitioning 304 into two regions, to increase the number of regions from four (according to the first logical partitioning 304 ) to eight (corresponding to the second logical partitioning 384 ).
- the controller 120 may further be configured to update the second logical partitioning 384 and the second mapping of regions to counters 382 to generate a third or further set of logical partitionings and mappings of regions to counters according to one or more other triggering events or other criteria. For example, when the erase/write count 244 of FIG. 2 exceeds a second erase/write threshold, the logical partitioning 384 may be increased to a larger number of regions, such as sixteen regions, and additional counters of the set of counters 122 may be assigned to accommodate tracking of memory read accesses to the newly established number of regions (e.g., sixteen counters may be mapped to the sixteen regions).
- first and second logical partitionings 304 and 384 illustrate multiple regions having substantially equal size and that are substantially evenly distributed throughout the non-volatile memory 104
- one or more of the memory regions may have a size differing from others of the memory regions. For example, a higher number of reads may be expected in a region that stores data having a high read access rate, such as a boot partition or area of the non-volatile memory 104 that stores other file management information. In this case, a smaller region may be used for portions of the non-volatile memory 104 expected to have higher read access rates, while larger regions may be used for portions of the non-volatile memory 104 expected to have lower read access rates.
- effects of read disturb on stored data in the non-volatile memory 104 may be dependent on one or more other factors, such as a location in a memory array (e.g., at an edge of the array as compared to at an interior of the array), a particular plane of multi-plane memory, a particular die of a multi-die memory, one or more other factors such as a type of data stored, a ratio of ‘0’ values to ‘1’ values in stored data at the non-volatile memory 104 , or other factors.
- factors such as a location in a memory array (e.g., at an edge of the array as compared to at an interior of the array), a particular plane of multi-plane memory, a particular die of a multi-die memory, one or more other factors such as a type of data stored, a ratio of ‘0’ values to ‘1’ values in stored data at the non-volatile memory 104 , or other factors.
- the data storage device 102 may be configured to accommodate various factors and various differences in read access rates and effects of read disturb on various portions of the non-volatile memory 104 .
- the first logical partitioning 304 and the first mapping of regions to counters 302 may be set by a manufacturer of the data storage device 102 of FIG. 1 .
- regions of the memory 104 defined by the first logical partitioning 304 may be set based on results of testing portions of the non-volatile memory 104 for susceptibility to read disturb effects, based on types of data stored to regions of the non-volatile memory 104 , such as file management data or pre-loaded content, based on one or more other criteria, or any combination thereof.
- the memory management engine 124 may be configured to update the first logical partitioning 304 and the first mapping of regions to counters 302 according to one or more criteria, such as according to a history of read accesses to different portions of the non-volatile memory 104 and/or according to the write erase count 244 of FIG. 2 , as non-limiting examples, to generate the second logical partitioning 384 and the second mapping of regions to counters 382 .
- the flash management engine 124 of FIG. 1 may store the counter values 160 , 162 corresponding to regions of the first logical partitioning 304 .
- the flash management engine 124 may update address ranges used by the address comparison circuitry 240 of FIG.
- Counters of the set of counters 122 may be assigned to an updated address range by the address comparison circuitry 240 .
- the assigned counters may be initialized to a counter value that is approximately half of the stored counter value corresponding to the region of the memory. For example, if the first region 110 is tracked by the first counter 140 and has a counter value 160 of two hundred, after partitioning the first region 110 into two regions, the counters assigned to each of the two regions may each be initialized to a value of one hundred.
- the method 400 may be performed in a data storage device that includes a controller and a non-volatile memory, such as a flash memory.
- the method 400 may be performed by the data storage device 102 of FIG. 1 .
- the method includes updating, in a controller of the data storage device, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter, at 402 .
- Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters.
- read accesses to the first region 110 of FIG. 1 may be tracked by the first counter 140 and read accesses to the Nth region 112 of FIG. 1 may be tracked by the Nth counter 142 .
- a remedial action to the particular region of the non-volatile memory is initiated, at 404 .
- the remedial action may be the remedial action 126 initiated by the memory management engine 124 of FIG. 1 and may include a data move operation or a data refresh operation.
- the value of the particular counter may be reset.
- the method 400 may also include, during a session shut-down operation of the data storage device, storing values of the set of counters to the non-volatile memory.
- stored counter values may be retrieved from the non-volatile memory and counters of the set of counters may be initialized according to the stored counter values.
- the controller 120 may store the counter values 180 of FIG. 1 to the non-volatile memory 104 upon powering down and may retrieve the counter values 180 from the non-volatile memory 104 during an initialization/powering up event.
- the non-volatile memory may be logically partitioned into a first set of multiple regions and a count of read accesses to each of the multiple regions may be tracked by a respective counter of the set of counters, such as the first logical partitioning 304 of FIG. 3 that partitions the memory 104 into four regions 340 - 346 that are tracked by four counters 320 - 326 .
- a first number of regions included in the first set of multiple regions may be programmable.
- the method 400 may include modifying the logical partitioning of the non-volatile memory to form a second set of multiple regions (e.g., the set of eight regions 350 - 364 according to the second logical partitioning 384 of FIG. 3 ).
- the triggering event may correspond to a count of erase cycles (e.g., the W/E count 244 of FIG. 2 ) equaling or exceeding an erase threshold (e.g., the W/E threshold 246 of FIG. 2 ).
- a second number of regions in the second set of regions may be greater than the first number of regions in the first set of regions, and a mapping of regions to counters may be updated to track each region of the second set of multiple regions with a respective counter of the set of counters.
- the first mapping of regions to counters 302 of FIG. 3 may be updated by the memory management engine 124 of FIG. 1 by assigning a counter of the set of counters 122 to each of the regions of the second logical partitioning 384 to generate the second mapping of regions to counters 382 .
- controller 120 may include one or more microprocessors, state machines, or other circuits configured to enable the controller 120 of FIG. 1 to initiate the remedial action based on comparisons of the counter values 160 - 162 to one or more threshold(s) 170 .
- the controller 120 may represent physical components, such as hardware controllers, state machines, logic circuits, or other structures, to enable the controller 120 of FIG. 1 to track read accesses to individual regions 110 - 112 and to initiate a data move operation or a data refresh operation to individual regions 110 - 112 .
- the controller 120 may be implemented using a microprocessor or microcontroller programmed to update counters in response to read accesses to corresponding regions of the memory 104 , and upon determining that a counter value indicates that a number of read accesses to a particular region matches or exceeds a threshold amount, to initiate a remedial action, such as by adding blocks of the region to a refresh queue or a move queue.
- the controller 120 includes a processor executing instructions that are stored at the non-volatile memory 104 .
- executable instructions that are executed by the processor may be stored at a separate memory location that is not part of the non-volatile memory 104 , such as at a read-only memory (ROM).
- the data storage device 102 may be implemented in a portable device configured to be selectively coupled to one or more external devices.
- the data storage device 102 may be attached or embedded within one or more host devices, such as within a housing of a host communication device.
- the data storage device 102 may be within a packaged apparatus such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, or other device that uses internal non-volatile memory.
- PDA personal digital assistant
- the data storage device 102 may be coupled to a non-volatile memory, such as a three-dimensional (3D) memory, a flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), a Divided bit-line NOR (DINOR) memory, an AND memory, a high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory.
- a non-volatile memory such as a three-dimensional (3D) memory, a flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), a Divided bit-line NOR (DINOR) memory, an AND memory, a high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
Description
- The present application claims priority to U.S. Provisional Application No. 61/737,668, filed Dec. 14, 2012, which application is hereby incorporated by reference in its entirety.
- The present disclosure is generally related to tracking accesses to non-volatile memory.
- Non-volatile data storage devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
- Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g. “parity bits”) that may be stored with the data as an ECC codeword. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases.
- One source of errors that occur in data stored in a memory device is a result of read accesses to the memory device. When voltages are applied to a word line and to bit lines of a flash memory device to enable reading of stored data at the word line, threshold voltages of neighboring word lines may be disturbed (e.g., slightly increased) due to inter-cell coupling within the memory device. Read disturb effects are cumulative and, if not remedied, may result in a number of errors in stored data exceeding an ECC error correction capacity of a data storage device.
- Read accesses to regions of a non-volatile memory of a data storage device are tracked by a set of counters. When a counter value indicates that a number of read accesses to a particular region tracked by the counter exceeds a threshold amount, a remedial action, such as a data refresh operation or a data move operation, is initiated to data stored in the particular region. As a result, read disturb effects to data stored in the memory may be corrected via refreshing or moving the data prior to accumulated read disturb effects exceeding a correction capability of the data storage device. Logical partitioning of the non-volatile memory into regions for read access tracking may be programmable and may be adaptively determined based on various factors to accommodate varying sensitivity to read disturb effects within the non-volatile memory.
-
FIG. 1 is a block diagram of a particular illustrative embodiment of a system including a data storage device configured to track read accesses to multiple regions of memory and to initiate a remedial action; -
FIG. 2 is a block diagram illustrating a particular embodiment of components that may be incorporated in the data storage device ofFIG. 1 ; -
FIG. 3 is a general diagram that illustrates logical partitioning of the memory ofFIG. 1 and mappings of counters to regions of the memory; and -
FIG. 4 is a flow chart of a particular illustrative embodiment of a method of tracking read accesses to regions of a non-volatile memory. - Referring to
FIG. 1 , a particular embodiment of asystem 100 includes adata storage device 102 coupled to ahost device 130. Thedata storage device 102 is configured to track read accesses to multiple regions of anon-volatile memory 104 and to initiate a remedial action based on the tracked read accesses. - The
host device 130 may be configured to provide data, such asuser data 132, to be stored at thenon-volatile memory 104 or to request data to be read from thememory 104. For example, thehost device 130 may include a mobile telephone, a music or video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer, a notebook computer, or a tablet, solid state storage drive, any other electronic device, or any combination thereof. - The
data storage device 102 includes thenon-volatile memory 104 coupled to acontroller 120. Thenon-volatile memory 104 may be a flash memory, such as a NAND flash memory. For example, thedata storage device 102 may be a memory card, such as a Secure Digital SD® card, a microSD® card, a miniSD™ card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). As another example, thedata storage device 102 may be configured to be coupled to thehost device 130 as embedded memory, such as eMMC® (trademark of JEDEC Solid State Technology Association, Arlington, Va.) and eSD, as illustrative examples. - The
non-volatile memory 104 includes multiple groups of storage elements, such as word lines of a multi-level cell (MLC) flash memory that include multiple MLC flash cells. Thenon-volatile memory 104 may also include multiple blocks of storage elements, such as erase blocks of a flash memory that include multiple word lines in each erase block. Thenon-volatile memory 104 is logically partitioned into multiple regions including a first region (region 1) 110 and an Nth region (region N) 112, where N is an integer greater than one. Each region 110-112 can include one or more word lines, blocks, or other portions of thenon-volatile memory 104. To illustrate, in an implementation where thenon-volatile memory 104 includes multiple arrays, multiple planes, multiple dies, or any combination thereof, each region 110-112 may include multiple word lines or blocks within a single array, plane, or die. As another example, a single region (e.g., the first region 110) may span multiple arrays, planes, or dies, or any combination thereof. To illustrate, thefirst region 110 may include storage elements within a first die and storage elements within a second die. - The
controller 120 is configured to receive data and instructions from and to send data to thehost device 130 while thedata storage device 102 is operatively coupled to thehost device 130. Thecontroller 120 is further configured to send data and commands to thememory 104 and to receive data from thememory 104. For example, thecontroller 120 is configured to send data and a write command to instruct thenon-volatile memory 104 to store the data to a specified address. As another example, thecontroller 120 is configured to send a read command to read data from a specified address of thenon-volatile memory 104. - The
controller 120 may include an ECC engine (not shown) that is configured to receive data to be stored to thenon-volatile memory 104 and to generate a codeword. For example, the ECC engine may include an encoder configured to encode data using an ECC encoding scheme, such as a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, a Turbo Code encoder, an encoder configured to encode data according to one or more other ECC encoding schemes, or any combination thereof. The ECC engine may include a decoder configured to decode data read from thenon-volatile memory 104 to detect and correct, up to an error correction capability of the ECC scheme, bit errors that may be present in the data. - The
controller 120 includes a set ofcounters 122 that are configured to track read accesses performed to the regions 110-112 of thenon-volatile memory 104. The set ofcounters 122 includes multiple counters, including a first counter (counter 1) 140 and an Nth counter (counter N) 142. Thefirst counter 140 has a first counter value (value 1) 160 that is updatable by thecontroller 120 to track memory accesses to thefirst region 110. TheNth counter 142 has anNth value 162 that is also updatable by thecontroller 120 to track memory accesses to theNth region 112. - The
controller 120 includes amemory management engine 124. Thememory management engine 124 is configured to receive read requests from thehost device 130 and to determine aread address 152 corresponding to the requested data. For example, theread address 152 may correspond to a physical address of one or more wordlines in thenon-volatile memory 104. To illustrate, thememory management engine 124 may receive a logical address of requested data stored in thenon-volatile memory 104 and may perform an address translation to generate a physical read address, such as theread address 152. Thememory management engine 124 is configured to generate aread command 150 to read data from theread address 152 of thenon-volatile memory 104. In addition, thememory management engine 124 is configured to provide theread address 152 to the set ofread access counters 122. - In response to determining the
read address 152 corresponding to a physical address of data to be read from thenon-volatile memory 104, thecontroller 120 may select a particular counter of the set ofcounters 122 corresponding to a region of thenon-volatile memory 104 that is tracked by the particular counter. For example, when theread address 152 corresponds to data in thefirst region 110, thecontroller 120 may determine that thefirst counter 140 maintains a count of read accesses to thefirst region 110, and as a result thefirst value 160 may be updated by thefirst counter 140. As another example, when theread address 152 corresponds to an address in theNth region 112, which is tracked by theNth counter 142, theNth value 162 of theNth counter 142 may be updated to indicate the read operation. - Each of the values 160-162 that correspond to counts of read accesses to the particular regions tracked by the corresponding counters 140-142 are compared to a
threshold 170. In response to determining that one or more of the values 160-162 equals or exceeds thethreshold 170, aflag 154 may be generated and provided to thememory management engine 124. Thememory management engine 124 may receive theflag 154 and may initiate aremedial action 126 to the corresponding region of thenon-volatile memory 104. - For example, when the
first value 160 indicates that a count of read accesses to thefirst region 110 equals or exceeds thethreshold 170, thecontroller 120 may be configured to initiate theremedial action 126 to thefirst region 110. Theremedial action 126 may include a data move operation that causes data in thecorresponding region 110 to be moved to a different memory location of thenon-volatile memory 104. As another example, theremedial action 126 may include a data refresh operation. The data refresh operation may include copying data from each block of theregion 110, erasing the particular block, and re-writing the data to the erased block. By moving data to another block, or by refreshing the data in a block, a shifting of states of storage elements as a result of read disturb effects may be remedied, and the storage elements within the block or groups of blocks may be returned to an originally programmed state. Potential corruption of data in thenon-volatile memory 104 caused by read disturb effects may be anticipated based on counts of read accesses to each of the regions 110-112 and theremedial action 126 may be performed to avoid unrecoverable corruption of data resulting from accumulated read disturb effects resulting from multiple read accesses. - In some implementations, the counters 140-142 may count upward from a reset value (e.g., a 0 value) with each read access to the region tracked by the particular counter 140-142. The value 160-162 of each counter 140-142 may be compared against the threshold 170 (e.g., each time the value 160-162 is updated) to determine when a number of read accesses to a corresponding region 110-112 of the
non-volatile memory 104 meets or exceeds thethreshold 170. However, in other implementations, other configurations of the counters 140-142 may be applied. For example, the counters 140-142 may be initially set to a value corresponding to a read access limit, and the counters 140-142 may decrement the corresponding value 160-162 with each read access. When one of the values 160-162 reaches a zero value, theflag 154 may be provided to thememory management engine 124. - The
controller 120 may be configured to store counter values 180 to specific or dedicated portions of thenon-volatile memory 104 for storage during power off conditions. For example, thecontroller 120 may be configured to store counter values 180 of the set ofcounters 122 to thenon-volatile memory 104 during a session shutdown operation of thedata storage device 102. Thecontroller 120 may further be configured to retrieve the storedcounter values 180 from thenon-volatile memory 104 and to initialize the counters 140-142 of the set ofcounters 122 according to the storedcounter values 180 during a session initialization operation of thedata storage device 102. To illustrate, the counter values 180 may include a table or other data structure that indicates a number of the regions 110-112 (e.g., N regions), and for each region, may include a value of a corresponding counter (e.g., thefirst value 160 for thefirst region 110, an address range corresponding to the particular region (e.g., addresses of a first and last erase block within the first region 110), and a value of thethreshold 170 corresponding to the particular region. For example, as described in further detail with respect toFIG. 3 , a number and arrangement of the regions 110-112 may be modified over the life of thedata storage device 102. In addition, as thedata storage device 102 ages, values of thethreshold 170 may be modified from an initial value, and different regions 110-112 may correspond to different thresholds. - During operation, the
host device 130 may request theuser data 132 to be read from thenon-volatile memory 104. Thememory management engine 124 may translate an address of the requesteduser data 132 and may provide the readaddress 152 to the set of read access counters 122. In addition, thecontroller 120 may issue theread command 150 to thenon-volatile memory 104, such as concurrently with providing theread address 152 to the set of read counters 122. - The
controller 120 may determine a particular counter of the set ofcounters 122 that tracks the region of thenon-volatile memory 104 corresponding to theread address 152. For example, theread address 152 may correspond to a wordline in thefirst region 110, which may be tracked by thefirst counter 140. In response to receiving theread address 152, a determination may be made that theread address 152 corresponds to thefirst counter 140, and thefirst counter 140 may update thefirst value 160 to indicate an additional read access has been or is being performed within thefirst region 110. - In response to the read
command 150 being sent to thenon-volatile memory 104, requested data may be provided from thenon-volatile memory 104 to thecontroller 120 as readdata 156. Thecontroller 120 may process the readdata 156, such as by decoding theread data 156 and correcting one or more read errors that may occur in theread data 156, and may provide the resultinguser data 132 to thehost device 130. - In addition, in response to the first value 160 (upon being updated by the first counter 140) equaling or exceeding the
threshold 170, acorresponding flag 154 may be provided to thememory management engine 124. In response to receiving theflag 154, thememory management engine 124 may initiate theremedial action 126, such as by providing memory addresses or block indicators to a move queue or a refresh queue for scheduling a data move operation or a data refresh operation, such as described in further detail with respect toFIG. 2 . - By tracking counts of read accesses to different regions of the
non-volatile memory 104, and by initiating theremedial action 126 in response to a count of read accesses to a particular region 110-112 meeting or exceeding thethreshold 170, cumulative effects of read disturbs occurring in the particular region 110-112 may be remedied. As a result, a number of errors occurring in theread data 156 due to read disturbs may be maintained at a reduced level as compared to systems that do not track and remedy accumulated read disturb effects. The set ofcounters 122 and corresponding logic to map the set ofcounters 122 to individual regions of thenon-volatile memory 104 may be implemented in dedicated circuitry to reduce latency and processing impact on thecontroller 120 during the read access operation, as described in further detail with respect toFIG. 2 . Alternatively, the set of read access counters 122 may be implemented via one or more software processes executed by a processor within thecontroller 120, or by a combination of software executed by a processor and dedicated circuitry. - Referring to
FIG. 2 , a particular embodiment of thedata storage device 102 ofFIG. 1 is illustrated and generally designated 200. Thenon-volatile memory 104 is illustrated as a NAND flash memory that includes multiple erase blocks, includingblock 0 220, block 1 222, block 2 224, block 3 226, and additional blocks up to an Mth block (block M) 228. TheNAND flash memory 104 is logically partitioned into multiple read tracking regions, illustrated as a firstread tracking region 210, a secondread tracking region 212, and additional regions up to an N−1st read trackingregion 214 and an Nth read trackingregion 216. Thecontroller 120 includes the set ofcounters 122 including thefirst counter 140, asecond counter 141, and one or more other counters including theNth counter 142. Thecontroller 120 includesaddress comparison circuitry 240 that is coupled to receive theread address 152 from theflash management engine 124 and to generate an output signal to a counter that tracks a region 210-216 of theNAND flash memory 104 corresponding to theread address 152. Thecontroller 120 further includes a count of write/erasecycles 244, a write/erasethreshold 246, and a move/refresh queue 242. - The
controller 120 is configured to provide the readaddress 152 from theflash management engine 124 to theaddress comparison circuitry 240. Theaddress comparison circuitry 240 may be programmable to route particular read addresses 152 to particular counters of the set ofcounters 122. For example, theaddress comparison circuitry 240 may determine whether the readaddress 152 is within a first address range corresponding to the firstread tracking region 210, a second address range corresponding to the secondread tracking region 212, etc., and may generate an output signal to a corresponding one of the counters 140-142 to cause the counter to update its counter value. - Each of the counters 140-142 may be responsive to a corresponding threshold, illustrated as
threshold 1,threshold 2, . . . threshold N. For example, each counter 140-142 may be configured to perform comparisons of the counter's value to its corresponding threshold and to generate a flag signal in response to the value meeting or exceeding the threshold. To illustrate, when thefirst counter 140 updates its counter value to an amount that matches the first threshold (threshold 1), thefirst counter 140 may generate a first flag indication (Flag 1) that may be provided to theflash management engine 124 as theflag 154. Each of the counters 140-142 may have a programmable threshold value such that each of the thresholds may have a distinct value, or one or more (or all) of the counters 140-142 may use a same threshold value. - Each of the counters 140-142 may provide a distinct flag signal to the
flash management engine 124. For example, theflag indicator 154 may be a multi-bit signal, such as an interrupt signal with each bit of the interrupt signal corresponding to a distinct counter of the set ofcounters 122. In this manner, theflash management engine 124 may determine a particular read tracking region 210-216 that has a count of read accesses matching or exceeding its corresponding threshold. In response, theflash management engine 124 may perform theremedial action 126 ofFIG. 1 by adding addresses of the blocks of the corresponding region, such as block 0-3 220-226 of the firstread tracking region 210, to the move/refresh queue 242. - The
flash management engine 124 may be configured to perform data move operations to transfer data from addresses indicated in the move/refresh queue 242 to other addresses in theNAND flash memory 104. Alternatively, theflash management engine 124 may be configured to perform refresh operations of blocks indicated in the move/refresh queue 242. For example, theflash management engine 124 may perform data moves or data refreshes as part of housekeeping operations at thecontroller 120, such as in a background process. - The
flash management engine 124 may be configured to keep track of a write/erasecount 244 of write and erase cycles performed at theNAND flash memory 104. For example, theflash management engine 124 may determine an “age” of theNAND flash memory 104 based on the write/erasecount 244. Because an ability of theNAND flash memory 104 to maintain distinct states of storage elements may degrade, as the write/erasecount 244 increases, the counter thresholds may be reduced as thedevice 200 ages (e.g., as the write/erasecount 244 increases). - The
flash management engine 124 may be configured to compare the write/erasecount 244 to the write/erasethreshold 246, and upon determining that the write/erasecount 244 meets or exceeds the write/erasethreshold 246, to perform one or more updates of the read tracking mechanism. For example, theflash management engine 124 may be configured to update logical partitioning of theNAND flash memory 104 into a greater number of read tracking regions 210-216, as described in further detail with respect toFIG. 3 . As another example, theflash management engine 124 may decrease the thresholds for each of the counters 140-142 so that remedial actions are taken more frequently for older memories than for fresh memories that have a greater capacity to maintain distinct states of memory cells in theNAND flash memory 104. - Referring to
FIG. 3 , a firstlogical partitioning 304 and a first mapping of regions tocounters 302 and a secondlogical partitioning 384 and a second mapping of regions tocounters 382 are illustrated. The firstlogical partitioning 304 may correspond to a partitioning of thenon-volatile memory 104 into four regions including afirst region 340, asecond region 342, athird region 344, and afourth region 346. The four regions 340-346 may span the entirenon-volatile memory 104, from a lowest indexed block (block 0 220) to a highest indexed block (block M 228). - The set of
counters 122 is illustrated as including afirst counter 320, asecond counter 322, athird counter 324, afourth counter 326, afifth counter 328, asixth counter 330, aseventh counter 332, and aneighth counter 334, and may include one or more additional counters (not shown). According to the first mapping of regions tocounters 302, thefirst counter 320 is mapped to thefirst region 340, thesecond counter 322 is mapped to thesecond region 342, thethird counter 324 is mapped to thethird region 344, and thefourth counter 326 is mapped to thefourth region 346. The remaining counters 328-334 are not mapped to any of the memory regions 344-346 and may be unused. - The first mapping of regions to
counters 302 and the firstlogical partitioning 304 may be applied by thecontroller 120 ofFIGS. 1-2 in response to the write/erasecount 244 ofFIG. 2 being less than the write/erasethreshold 246. For example, the first mapping of regions tocounters 302 and the firstlogical partitioning 304 may be an initial configuration of thememory device 102 ofFIG. 1 and may be set according to an initial set of programmable values, such as determined by a manufacturer of thedata storage device 102. - With operation of the
data storage device 102, the write/erasecount 244 may eventually equal or surpass the write/erasethreshold 246. In response to the write/erasecount 244 equaling or exceeding the write/erasethreshold 246, or in response to some other triggering event, thecontroller 120 ofFIG. 1 may be configured to modify the logical partitioning of thenon-volatile memory 104 from the firstlogical partitioning 304 including the first set of regions 340-346 to the secondlogical partitioning 384 that includes a second set of regions. The second set of regions includes afirst region 350, asecond region 352, athird region 354, afourth region 356, afifth region 358, asixth region 360, aseventh region 362, and aneighth region 364. The number of regions in the second set of regions 350-364 (e.g., 8) is greater than the first number of regions in the first set of regions 340-346 (e.g., 4). - The
controller 120 may also be configured to update a mapping of regions from the first mapping of regions tocounters 302 to the second mapping of regions tocounters 382. The second mapping of regions tocounters 382 enables tracking of each region of the second set of multiple regions 350-364 with a respective counter 320-334 of the set ofcounters 122. As illustrated, the secondlogical partitioning 384 may be formed by subdividing each of the regions of the firstlogical partitioning 304 into two regions, to increase the number of regions from four (according to the first logical partitioning 304) to eight (corresponding to the second logical partitioning 384). - The
controller 120 may further be configured to update the secondlogical partitioning 384 and the second mapping of regions tocounters 382 to generate a third or further set of logical partitionings and mappings of regions to counters according to one or more other triggering events or other criteria. For example, when the erase/write count 244 ofFIG. 2 exceeds a second erase/write threshold, thelogical partitioning 384 may be increased to a larger number of regions, such as sixteen regions, and additional counters of the set ofcounters 122 may be assigned to accommodate tracking of memory read accesses to the newly established number of regions (e.g., sixteen counters may be mapped to the sixteen regions). - Although the first and second
logical partitionings non-volatile memory 104, it should be understood that in other implementations one or more of the memory regions may have a size differing from others of the memory regions. For example, a higher number of reads may be expected in a region that stores data having a high read access rate, such as a boot partition or area of thenon-volatile memory 104 that stores other file management information. In this case, a smaller region may be used for portions of thenon-volatile memory 104 expected to have higher read access rates, while larger regions may be used for portions of thenon-volatile memory 104 expected to have lower read access rates. As another example, effects of read disturb on stored data in thenon-volatile memory 104 may be dependent on one or more other factors, such as a location in a memory array (e.g., at an edge of the array as compared to at an interior of the array), a particular plane of multi-plane memory, a particular die of a multi-die memory, one or more other factors such as a type of data stored, a ratio of ‘0’ values to ‘1’ values in stored data at thenon-volatile memory 104, or other factors. - Because partitioning of the
non-volatile memory 104 into multiple regions and the mapping of regions to counters may be programmable, thedata storage device 102 may be configured to accommodate various factors and various differences in read access rates and effects of read disturb on various portions of thenon-volatile memory 104. For example, the firstlogical partitioning 304 and the first mapping of regions tocounters 302 may be set by a manufacturer of thedata storage device 102 ofFIG. 1 . To illustrate, regions of thememory 104 defined by the firstlogical partitioning 304 may be set based on results of testing portions of thenon-volatile memory 104 for susceptibility to read disturb effects, based on types of data stored to regions of thenon-volatile memory 104, such as file management data or pre-loaded content, based on one or more other criteria, or any combination thereof. - The
memory management engine 124 may be configured to update the firstlogical partitioning 304 and the first mapping of regions tocounters 302 according to one or more criteria, such as according to a history of read accesses to different portions of thenon-volatile memory 104 and/or according to the write erasecount 244 ofFIG. 2 , as non-limiting examples, to generate the secondlogical partitioning 384 and the second mapping of regions tocounters 382. For example, theflash management engine 124 ofFIG. 1 may store the counter values 160, 162 corresponding to regions of the firstlogical partitioning 304. Theflash management engine 124 may update address ranges used by theaddress comparison circuitry 240 ofFIG. 2 so that twice as many address ranges are used, with each of the updated address ranges including approximately half as many addresses as the prior address ranges. Counters of the set ofcounters 122 may be assigned to an updated address range by theaddress comparison circuitry 240. The assigned counters may be initialized to a counter value that is approximately half of the stored counter value corresponding to the region of the memory. For example, if thefirst region 110 is tracked by thefirst counter 140 and has acounter value 160 of two hundred, after partitioning thefirst region 110 into two regions, the counters assigned to each of the two regions may each be initialized to a value of one hundred. - Referring to
FIG. 4 , a particular embodiment of amethod 400 is depicted. Themethod 400 may be performed in a data storage device that includes a controller and a non-volatile memory, such as a flash memory. For example, themethod 400 may be performed by thedata storage device 102 ofFIG. 1 . - The method includes updating, in a controller of the data storage device, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter, at 402. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. For example, read accesses to the
first region 110 ofFIG. 1 may be tracked by thefirst counter 140 and read accesses to theNth region 112 ofFIG. 1 may be tracked by theNth counter 142. - In response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, a remedial action to the particular region of the non-volatile memory is initiated, at 404. For example, the remedial action may be the
remedial action 126 initiated by thememory management engine 124 ofFIG. 1 and may include a data move operation or a data refresh operation. In response to completion of the remedial action to the particular region, the value of the particular counter may be reset. - The
method 400 may also include, during a session shut-down operation of the data storage device, storing values of the set of counters to the non-volatile memory. During a session initialization operation of the data storage device, stored counter values may be retrieved from the non-volatile memory and counters of the set of counters may be initialized according to the stored counter values. For example, thecontroller 120 may store the counter values 180 ofFIG. 1 to thenon-volatile memory 104 upon powering down and may retrieve the counter values 180 from thenon-volatile memory 104 during an initialization/powering up event. - The non-volatile memory may be logically partitioned into a first set of multiple regions and a count of read accesses to each of the multiple regions may be tracked by a respective counter of the set of counters, such as the first
logical partitioning 304 ofFIG. 3 that partitions thememory 104 into four regions 340-346 that are tracked by four counters 320-326. A first number of regions included in the first set of multiple regions may be programmable. For example, in response to a triggering event, themethod 400 may include modifying the logical partitioning of the non-volatile memory to form a second set of multiple regions (e.g., the set of eight regions 350-364 according to the secondlogical partitioning 384 ofFIG. 3 ). The triggering event may correspond to a count of erase cycles (e.g., the W/E count 244 ofFIG. 2 ) equaling or exceeding an erase threshold (e.g., the W/E threshold 246 ofFIG. 2 ). A second number of regions in the second set of regions may be greater than the first number of regions in the first set of regions, and a mapping of regions to counters may be updated to track each region of the second set of multiple regions with a respective counter of the set of counters. For example, the first mapping of regions tocounters 302 ofFIG. 3 may be updated by thememory management engine 124 ofFIG. 1 by assigning a counter of the set ofcounters 122 to each of the regions of the secondlogical partitioning 384 to generate the second mapping of regions tocounters 382. - Although various components depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable the
controller 120 ofFIG. 1 to initiate the remedial action based on comparisons of the counter values 160-162 to one or more threshold(s) 170. For example, thecontroller 120 may represent physical components, such as hardware controllers, state machines, logic circuits, or other structures, to enable thecontroller 120 ofFIG. 1 to track read accesses to individual regions 110-112 and to initiate a data move operation or a data refresh operation to individual regions 110-112. - The
controller 120 may be implemented using a microprocessor or microcontroller programmed to update counters in response to read accesses to corresponding regions of thememory 104, and upon determining that a counter value indicates that a number of read accesses to a particular region matches or exceeds a threshold amount, to initiate a remedial action, such as by adding blocks of the region to a refresh queue or a move queue. In a particular embodiment, thecontroller 120 includes a processor executing instructions that are stored at thenon-volatile memory 104. Alternatively, or in addition, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of thenon-volatile memory 104, such as at a read-only memory (ROM). - In a particular embodiment, the
data storage device 102 may be implemented in a portable device configured to be selectively coupled to one or more external devices. However, in other embodiments, thedata storage device 102 may be attached or embedded within one or more host devices, such as within a housing of a host communication device. For example, thedata storage device 102 may be within a packaged apparatus such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, or other device that uses internal non-volatile memory. In a particular embodiment, thedata storage device 102 may be coupled to a non-volatile memory, such as a three-dimensional (3D) memory, a flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), a Divided bit-line NOR (DINOR) memory, an AND memory, a high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory. - The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments.
- The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Claims (22)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/756,946 US9141534B2 (en) | 2012-12-14 | 2013-02-01 | Tracking read accesses to regions of non-volatile memory |
PCT/US2013/071280 WO2014092967A1 (en) | 2012-12-14 | 2013-11-21 | Tracking read accesses to regions of non-volatile memory |
KR1020157011763A KR20150096646A (en) | 2012-12-14 | 2013-11-21 | Tracking read accesses to regions of non-volatile memory |
CN201380059648.XA CN104813408B (en) | 2012-12-14 | 2013-11-21 | Track the read access to the region of nonvolatile memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261737668P | 2012-12-14 | 2012-12-14 | |
US13/756,946 US9141534B2 (en) | 2012-12-14 | 2013-02-01 | Tracking read accesses to regions of non-volatile memory |
Publications (2)
Publication Number | Publication Date |
---|---|
US20140173180A1 true US20140173180A1 (en) | 2014-06-19 |
US9141534B2 US9141534B2 (en) | 2015-09-22 |
Family
ID=50932347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/756,946 Active 2033-12-16 US9141534B2 (en) | 2012-12-14 | 2013-02-01 | Tracking read accesses to regions of non-volatile memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US9141534B2 (en) |
KR (1) | KR20150096646A (en) |
CN (1) | CN104813408B (en) |
WO (1) | WO2014092967A1 (en) |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140372691A1 (en) * | 2013-06-13 | 2014-12-18 | Hewlett-Packard Development Company, L. P. | Counter policy implementation |
US20150325291A1 (en) * | 2014-05-08 | 2015-11-12 | Robert Bosch Gmbh | Refresh of a memory area of a non-volatile memory unit |
US20160098201A1 (en) * | 2014-10-07 | 2016-04-07 | SK Hynix Inc. | Data storage device and operating method thereof |
KR20160107381A (en) * | 2015-03-03 | 2016-09-19 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
WO2017016502A1 (en) * | 2015-07-28 | 2017-02-02 | Huawei Technologies Co., Ltd. | Dynamic coding algorithm for intelligent coded memory system |
US9760432B2 (en) | 2015-07-28 | 2017-09-12 | Futurewei Technologies, Inc. | Intelligent code apparatus, method, and computer program for memory |
US9947384B1 (en) | 2016-09-28 | 2018-04-17 | SK Hynix Inc. | Semiconductor device relating to generate target address to execute a refresh operation |
EP3210121A4 (en) * | 2014-10-22 | 2018-05-30 | Netapp, Inc. | Cache optimization technique for large working data sets |
US10140042B1 (en) | 2017-09-13 | 2018-11-27 | Toshiba Memory Corporation | Deterministic read disturb counter-based data checking for NAND flash |
US20190221273A1 (en) * | 2017-04-04 | 2019-07-18 | Sandisk Technologies Llc | Data rewrite during refresh window |
WO2019126416A3 (en) * | 2017-12-22 | 2019-07-25 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US20190287632A1 (en) * | 2018-03-19 | 2019-09-19 | Toshiba Memory Corporation | Memory system and memory control method |
US10566052B2 (en) | 2017-12-22 | 2020-02-18 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10831395B2 (en) | 2018-03-23 | 2020-11-10 | Toshiba Memory Corporation | Memory system, control method, and control device |
CN112309479A (en) * | 2019-08-02 | 2021-02-02 | 美光科技公司 | Read count scaling factor for data integrity scanning |
US10908832B2 (en) * | 2017-10-31 | 2021-02-02 | Micron Technology, Inc. | Common pool management |
WO2021216130A1 (en) * | 2020-04-24 | 2021-10-28 | Western Digital Technologies, Inc. | Weighted read commands and open block timer for storage devices |
US11256613B2 (en) * | 2014-02-19 | 2022-02-22 | Rambus Inc. | Memory system with activate-leveling method |
US11288201B2 (en) | 2017-02-23 | 2022-03-29 | Western Digital Technologies, Inc. | Techniques for performing a non-blocking control sync operation |
US11392292B2 (en) * | 2019-07-15 | 2022-07-19 | Micron Technology, Inc. | Maintenance operations for memory devices |
US11392449B2 (en) | 2018-10-31 | 2022-07-19 | Em Microelectronic-Marin S.A. | Anti-tearing protection system for non-volatile memories |
US11816349B2 (en) | 2021-11-03 | 2023-11-14 | Western Digital Technologies, Inc. | Reduce command latency using block pre-erase |
US11861167B2 (en) | 2019-07-15 | 2024-01-02 | Micron Technology, Inc. | Maintenance operations for memory devices |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9305651B1 (en) * | 2014-09-22 | 2016-04-05 | Sandisk Technologies Inc. | Efficient wide range bit counter |
KR20180014975A (en) * | 2016-08-02 | 2018-02-12 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
KR20180059208A (en) | 2016-11-25 | 2018-06-04 | 삼성전자주식회사 | Memory controller with reclaim controller |
KR20180061557A (en) * | 2016-11-29 | 2018-06-08 | 삼성전자주식회사 | Controller and storage device including controller and nonvolatile memory devices |
US10359955B2 (en) * | 2017-02-23 | 2019-07-23 | Western Digital Technologies, Inc. | Data storage device configured to perform a non-blocking control update operation |
KR20190001417A (en) * | 2017-06-27 | 2019-01-04 | 에스케이하이닉스 주식회사 | Controller and operating method thereof |
US10795828B2 (en) | 2018-08-10 | 2020-10-06 | Micron Technology, Inc. | Data validity tracking in a non-volatile memory |
CN114746848B (en) * | 2019-12-03 | 2023-08-04 | 美光科技公司 | Cache architecture for storage devices |
KR20220059266A (en) | 2020-11-02 | 2022-05-10 | 에스케이하이닉스 주식회사 | Storage system |
CN114817130A (en) * | 2021-01-21 | 2022-07-29 | 伊姆西Ip控股有限责任公司 | Method, apparatus and computer program product for managing a file system |
US20240192891A1 (en) * | 2022-12-08 | 2024-06-13 | Micron Technology, Inc. | Memory device active command tracking |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7653778B2 (en) * | 2006-05-08 | 2010-01-26 | Siliconsystems, Inc. | Systems and methods for measuring the useful life of solid-state storage devices |
US20130138871A1 (en) * | 2011-11-30 | 2013-05-30 | Silicon Motion, Inc. | Flash Memory Device and Data Access Method for Same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4113423B2 (en) * | 2002-12-04 | 2008-07-09 | シャープ株式会社 | Semiconductor memory device and reference cell correction method |
JP2008181380A (en) | 2007-01-25 | 2008-08-07 | Toshiba Corp | Memory system, and method for controlling the same |
JP5661227B2 (en) | 2007-02-07 | 2015-01-28 | 株式会社メガチップス | Memory controller |
JP2009087509A (en) | 2007-10-03 | 2009-04-23 | Toshiba Corp | Semiconductor storage device |
JP2009187159A (en) | 2008-02-05 | 2009-08-20 | Toshiba Corp | Memory system |
US8189379B2 (en) | 2009-08-12 | 2012-05-29 | Texas Memory Systems, Inc. | Reduction of read disturb errors in NAND FLASH memory |
TWI490869B (en) | 2010-08-13 | 2015-07-01 | Mstar Semiconductor Inc | Method and associated controller for flash memory |
CN103392208A (en) | 2011-04-28 | 2013-11-13 | 株式会社日立制作所 | Semiconductor storage apparatus and method for controlling semiconductor storage apparatus |
-
2013
- 2013-02-01 US US13/756,946 patent/US9141534B2/en active Active
- 2013-11-21 CN CN201380059648.XA patent/CN104813408B/en active Active
- 2013-11-21 KR KR1020157011763A patent/KR20150096646A/en active IP Right Grant
- 2013-11-21 WO PCT/US2013/071280 patent/WO2014092967A1/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7653778B2 (en) * | 2006-05-08 | 2010-01-26 | Siliconsystems, Inc. | Systems and methods for measuring the useful life of solid-state storage devices |
US20130138871A1 (en) * | 2011-11-30 | 2013-05-30 | Silicon Motion, Inc. | Flash Memory Device and Data Access Method for Same |
Cited By (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140372691A1 (en) * | 2013-06-13 | 2014-12-18 | Hewlett-Packard Development Company, L. P. | Counter policy implementation |
US11256613B2 (en) * | 2014-02-19 | 2022-02-22 | Rambus Inc. | Memory system with activate-leveling method |
US11899571B2 (en) | 2014-02-19 | 2024-02-13 | Rambus Inc. | Memory system with activate-leveling method |
US10013343B2 (en) * | 2014-05-08 | 2018-07-03 | Robert Bosch Gmbh | Apparatus and method of refreshing a memory area of a non-volatile memory unit used in an embedded system |
US20150325291A1 (en) * | 2014-05-08 | 2015-11-12 | Robert Bosch Gmbh | Refresh of a memory area of a non-volatile memory unit |
US20160098201A1 (en) * | 2014-10-07 | 2016-04-07 | SK Hynix Inc. | Data storage device and operating method thereof |
US9678827B2 (en) * | 2014-10-07 | 2017-06-13 | SK Hynix Inc. | Access counts for performing data inspection operations in data storage device |
EP3210121A4 (en) * | 2014-10-22 | 2018-05-30 | Netapp, Inc. | Cache optimization technique for large working data sets |
KR102527288B1 (en) * | 2015-03-03 | 2023-05-03 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
KR20160107381A (en) * | 2015-03-03 | 2016-09-19 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
US9760432B2 (en) | 2015-07-28 | 2017-09-12 | Futurewei Technologies, Inc. | Intelligent code apparatus, method, and computer program for memory |
US9921754B2 (en) | 2015-07-28 | 2018-03-20 | Futurewei Technologies, Inc. | Dynamic coding algorithm for intelligent coded memory system |
CN107851063A (en) * | 2015-07-28 | 2018-03-27 | 华为技术有限公司 | The dynamic coding algorithm of intelligently encoding accumulator system |
WO2017016502A1 (en) * | 2015-07-28 | 2017-02-02 | Huawei Technologies Co., Ltd. | Dynamic coding algorithm for intelligent coded memory system |
US9947384B1 (en) | 2016-09-28 | 2018-04-17 | SK Hynix Inc. | Semiconductor device relating to generate target address to execute a refresh operation |
US11288201B2 (en) | 2017-02-23 | 2022-03-29 | Western Digital Technologies, Inc. | Techniques for performing a non-blocking control sync operation |
US20190221273A1 (en) * | 2017-04-04 | 2019-07-18 | Sandisk Technologies Llc | Data rewrite during refresh window |
US10885991B2 (en) * | 2017-04-04 | 2021-01-05 | Sandisk Technologies Llc | Data rewrite during refresh window |
US10140042B1 (en) | 2017-09-13 | 2018-11-27 | Toshiba Memory Corporation | Deterministic read disturb counter-based data checking for NAND flash |
US10599346B2 (en) | 2017-09-13 | 2020-03-24 | Toshiba Memory Corporation | Deterministic read disturb counter-based data checking for NAND flash |
US10996870B2 (en) | 2017-09-13 | 2021-05-04 | Toshiba Memory Corporation | Deterministic read disturb counter-based data checking for NAND flash |
US10908832B2 (en) * | 2017-10-31 | 2021-02-02 | Micron Technology, Inc. | Common pool management |
US11282574B2 (en) | 2017-12-22 | 2022-03-22 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US11282571B2 (en) | 2017-12-22 | 2022-03-22 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US12009028B2 (en) | 2017-12-22 | 2024-06-11 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10741243B2 (en) | 2017-12-22 | 2020-08-11 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10896727B2 (en) | 2017-12-22 | 2021-01-19 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
WO2019126416A3 (en) * | 2017-12-22 | 2019-07-25 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
KR20200089762A (en) * | 2017-12-22 | 2020-07-27 | 마이크론 테크놀로지, 인크 | Self-referencing memory cell reading technology |
US10937491B2 (en) | 2017-12-22 | 2021-03-02 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10600480B2 (en) | 2017-12-22 | 2020-03-24 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
KR102386641B1 (en) | 2017-12-22 | 2022-04-14 | 마이크론 테크놀로지, 인크 | Auto-referencing memory cell reading technology |
US10431301B2 (en) | 2017-12-22 | 2019-10-01 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10566052B2 (en) | 2017-12-22 | 2020-02-18 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US11727998B2 (en) | 2018-03-19 | 2023-08-15 | Kioxia Corporation | Memory system and memory control method |
US20190287632A1 (en) * | 2018-03-19 | 2019-09-19 | Toshiba Memory Corporation | Memory system and memory control method |
US11189353B2 (en) * | 2018-03-19 | 2021-11-30 | Toshiba Memory Corporation | Memory system and memory control method |
JP2019164859A (en) * | 2018-03-19 | 2019-09-26 | 東芝メモリ株式会社 | Memory system, and, memory control method |
US10854302B2 (en) * | 2018-03-19 | 2020-12-01 | Toshiba Memory Corporation | Memory system and memory control method |
JP7074519B2 (en) | 2018-03-19 | 2022-05-24 | キオクシア株式会社 | Memory system and memory control method |
US10831395B2 (en) | 2018-03-23 | 2020-11-10 | Toshiba Memory Corporation | Memory system, control method, and control device |
US11392449B2 (en) | 2018-10-31 | 2022-07-19 | Em Microelectronic-Marin S.A. | Anti-tearing protection system for non-volatile memories |
US11392292B2 (en) * | 2019-07-15 | 2022-07-19 | Micron Technology, Inc. | Maintenance operations for memory devices |
US11861167B2 (en) | 2019-07-15 | 2024-01-02 | Micron Technology, Inc. | Maintenance operations for memory devices |
CN112309479A (en) * | 2019-08-02 | 2021-02-02 | 美光科技公司 | Read count scaling factor for data integrity scanning |
US11226761B2 (en) | 2020-04-24 | 2022-01-18 | Western Digital Technologies, Inc. | Weighted read commands and open block timer for storage devices |
WO2021216130A1 (en) * | 2020-04-24 | 2021-10-28 | Western Digital Technologies, Inc. | Weighted read commands and open block timer for storage devices |
US11816349B2 (en) | 2021-11-03 | 2023-11-14 | Western Digital Technologies, Inc. | Reduce command latency using block pre-erase |
Also Published As
Publication number | Publication date |
---|---|
KR20150096646A (en) | 2015-08-25 |
US9141534B2 (en) | 2015-09-22 |
CN104813408B (en) | 2017-11-10 |
CN104813408A (en) | 2015-07-29 |
WO2014092967A1 (en) | 2014-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9141534B2 (en) | Tracking read accesses to regions of non-volatile memory | |
US9153331B2 (en) | Tracking cell erase counts of non-volatile memory | |
US8838883B2 (en) | System and method of adjusting a programming step size for a block of a memory | |
US9362003B2 (en) | System and method to decode data subject to a disturb condition | |
US9070479B2 (en) | Systems and methods of updating read voltages | |
US9129689B2 (en) | Tracking erase pulses for non-volatile memory | |
US9240235B2 (en) | Mitigating disturb effects for non-volatile memory | |
US9710329B2 (en) | Error correction based on historical bit error data | |
US9817749B2 (en) | Apparatus and method of offloading processing from a data storage device to a host device | |
CN106155585B (en) | Adaptive read disturb reclaim strategy | |
US8683297B2 (en) | Systems and methods of generating a replacement default read threshold | |
US8787079B2 (en) | Reading data from multi-level cell memory | |
US9135105B2 (en) | Probability-based remedial action for read disturb effects | |
US20140173172A1 (en) | System and method to update read voltages in a non-volatile memory in response to tracking data | |
US20170076807A1 (en) | Memory system and method of controlling nonvolatile memory | |
US9063879B2 (en) | Inspection of non-volatile memory for disturb effects | |
US9798475B2 (en) | Memory system and method of controlling nonvolatile memory | |
US9117533B2 (en) | Tracking erase operations to regions of non-volatile memory | |
US20130223151A1 (en) | System and method of determining a programming step size for a word line of a memory | |
CN107544925B (en) | Memory system and method for accelerating boot time | |
US11087846B1 (en) | Memory system with single decoder, multiple memory sets and method for decoding multiple codewords from memory sets using the single decoder | |
CN112783435A (en) | Storage device and method of operating storage device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:D'ABREU, MANUEL ANTONIO;SKALA, STEPHEN;REEL/FRAME:029739/0932 Effective date: 20121213 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES LLC, TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038807/0898 Effective date: 20160516 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FEPP | Fee payment procedure |
Free format text: 7.5 YR SURCHARGE - LATE PMT W/IN 6 MO, LARGE ENTITY (ORIGINAL EVENT CODE: M1555); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |