US20140152341A1 - External component-less pvt compensation scheme for io buffers - Google Patents
External component-less pvt compensation scheme for io buffers Download PDFInfo
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- US20140152341A1 US20140152341A1 US13/706,110 US201213706110A US2014152341A1 US 20140152341 A1 US20140152341 A1 US 20140152341A1 US 201213706110 A US201213706110 A US 201213706110A US 2014152341 A1 US2014152341 A1 US 2014152341A1
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- pvt
- controlled oscillator
- osc
- current controlled
- voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
Definitions
- Input/Output for electronics and computing is typically described as the communication between some type of a processing system and the world outside of the subject processing system.
- the input of the IO refers to data/commands sent to the processing system from the outside world and the output of the IO refers to data/commands sent from the processing system to the outside world.
- the outside world simply refers to any entity not contained within the conceptual boundaries of the subject processing system.
- a processing system may be as small as a portion of a single chip or as large as networked group of computers, where the designation of the “processing system” is relative to what system is being designed.
- a computer integration specialist may look at each computer on a system as the “processing system,” while an integrated circuit chip designer may look to an individual integrated circuit chip, or even individual subsystems within a particular integrated circuit as the “processing system” such that the chip or chip subsystem operates as its own “processing system” with IO to the outside world being IO to entities outside of the chip or even other subsystems contained on the same chip if the “processing system” is an individual subsystem of a particular chip.
- An IO interface is necessary for the processor system to interact with the outside world.
- the IO interface provides the necessary logic to interpret addresses/commands issued by and/or sent to the processing system.
- a typical IO interface will implement some form of “handshaking” with the device/entity of the world outside of the processing system using commands such as busy, ready, and/or wait. Once “handshaking” to establish a connection is complete, a typical IO interface permits communication between the processing system and the world outside of the processing system. If different data formats are being exchanged, the IO interface typically performs the necessary conversion between the data formats to permit communication.
- a typical integrated circuit chip is made up of individual electrical elements and typically includes active elements such as one or more transistor devices. Typical operation of a transistor requires connection of the transistors either directly or through other electrical devices to a high and a low output of a voltage supply. Typically, the high output of the voltage supply is identified as the high voltage supply and the low output of the voltage supply is identified as the low voltage supply.
- MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
- VSS is also referred to and defined as the electrical ground for a circuit.
- Typical operation of a MOSFET device involves the application of high (VDD) and or low (VSS) supply voltages to the gate, source, and/or drain either directly or through other electrical circuit devices.
- MOSFET devices are typically divided into two major subdivisions, PMOS devices and NMOS devices which have related, but different operational characteristics. While initially tied to MOSFET based circuits, the use of VDD and VSS to represent the high and low voltage outputs, respectively, has become common usage even for non-MOSFET based circuits.
- An embodiment of the present invention may comprise a method to provide Process-Voltage-Temperature (PVT) compensation for an Input/Output (IO) interface, the IO interface having a bandgap reference voltage (V BGR ) and a reference frequency (F REF ), the method comprising: connecting the V BGR to a voltage reduction system; reducing the V BGR by substantially half at the voltage reduction system to produce V BGR /2; connecting the V BGR /2 to a current mirror system; connecting the current mirror system to a high supply voltage (V DD ); connecting a driver bit cell to a low supply voltage (V SS ); connecting the current mirror system to the driver bit cell such that a process-variable-temperature current (I PVT ) flows through the driver bit cell; connecting the current mirror system to a compensated current controlled oscillator; mirroring the I PVT at the current mirror system such that the compensated current controlled oscillator receives a control current (I CNTL ) that is proportional to the I PVT ; generating
- An embodiment of the present invention may further comprise a Process-Voltage-Temperature (PVT) compensation system for an Input/Output (IO) interface, the IO interface having a bandgap reference voltage (V BGR ) and a reference frequency (F REF ), the PVT compensation system comprising: a voltage reduction subsystem connected to the V BGR that reduces the V BGR by substantially half to produce V BGR /2; a driver bit cell connected to a current mirror subsystem and to a low supply voltage (V SS ); the current mirror subsystem connected to the V BGR /2, to a high supply voltage (V DD ), to the driver bit cell, and to a compensated current controlled oscillator such that a process-variable-temperature current (I PVT ) flows through the driver bit cell and a mirrored control current (I CNTL ) that is proportional to the I PVT is delivered to the compensated current controlled oscillator; a compensated current controlled oscillator connected to the I CNTL that generates an oscil
- FIG. 1 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT) compensation circuit.
- PVT Process-Voltage-Temperature
- FIG. 2 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT) compensation circuit having an op-amp based voltage reduction system and a transistor based current mirror system.
- PVT Process-Voltage-Temperature
- FIG. 3 is a circuit architecture block diagram of the compensated current controlled oscillator for an embodiment showing details of a capacitor calibration embodiment for the compensated current controlled oscillator.
- FIG. 4A is a flow chart of the process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the analog section of the embodiment.
- FIG. 4B is a flow chart of a process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the digital section of the embodiment.
- FIG. 5 is a flow chart of a process of calibrating the capacitance of the compensated current controlled oscillator for an embodiment.
- FIG. 6 is a detailed flow chart of the process of calibrating the capacitance of the compensated current controlled oscillator for an embodiment.
- IO interfaces require a minimum variation of rise and fall times over process, voltage and temperature, often called Process-Voltage-Temperature or PVT.
- Many IO interfaces are integrated circuits that may contain Metal-Oxide-Semiconductor (MOS) devices, some of which may be MOS Field-Effect Transistors (MOSFETs). Typical MOS devices are made up of two classifications of devices, PMOS devices and NMOS devices, which have related, but different operational characteristics.
- MOS Metal-Oxide-Semiconductor
- MOSFETs MOS Field-Effect Transistors
- One method to address the PVT concerns for an IO interface of an Integrated Circuit (IC), particularly an IC containing MOS devices, is to use a precision resistor external to the IO interface IC chip as a reference to calibrate buffer impedance of the IO interface.
- a voltage drop across a compensating device within the IC chip e.g., a PMOS or NMOS device
- a known voltage drop across the external precision resistor is compared to a known voltage drop across the external precision resistor.
- the buffer impedance of the IO interface may be adjusted to correct any variations in voltage caused by PVT effects on the IC operation.
- the external precision resistor method of PVT compensation requires that the IC chip having the IO interface build in an external pin for connecting to the external precision resistor and that any systems incorporating the IC chip also leave space on the Printed Circuit Board (PCB) layout to accommodate the external precision resistor.
- PCB Printed Circuit Board
- FIG. 1 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT) compensation circuit 100 for an IO interface.
- PVT Process-Voltage-Temperature
- an embodiment may eliminate the pin used for connection to the external precision resistor in an IC chip package including an embodiment. Since the external precision resistor is not required, systems need not include space or traces on printed circuit boards to accommodate the now unneeded external precision resistor.
- an embodiment of the PVT compensation circuit may be split into an analog section/portion 138 and a digital section/portion 140 .
- the analog section 138 generally works on analog principles to generate a frequency signal (F OSC ) 114 to deliver to the digital section 140 .
- F OSC frequency signal
- the digital section uses F OSC 114 to determine a PVT control bits value 116 that may be used by the IO interface to set a buffer impedance to mitigate potential PVT issues experienced by the overall IO interface circuitry.
- the overall IO interface circuit may make available a reference voltage (V REF ) 106 , a high voltage supply (V DD ) 124 , a low voltage supply/ground (V SS ) 126 , and a reference frequency (F REF ) 118 .
- the reference voltage (V REF ) 106 may be a Band Gap Reference voltage (V BGR ) of the IO interface circuit.
- the reference voltage will be the bandgap reference voltage (V BGR ).
- various “systems” making up an embodiment may be referenced as a system (e.g., voltage reduction system 142 , current mirror system 134 , etc.) and/or may be referenced as a subsystem of the overall PVT compensation circuit (e.g., voltage reduction subsystem 142 , current mirror subsystem 134 , etc.).
- V BGR 106 is connected to an input of a voltage reduction system 142 .
- the voltage reduction system 142 reduces the voltage to substantially half of V BGR 108 , or V BGR /2 ( 108 ).
- the voltage reduction system may be any type of voltage reduction circuitry including an op-amp loop with an appropriate gain and a standard voltage divider circuit.
- the voltage reduction system 142 makes V BGR /2 ( 108 ) available at an output of the voltage reduction system 142 .
- V BGR /2 ( 108 ) is connected to an input of the current mirror system 134 .
- the current mirror system 134 also connects a high supply voltage connection point to the high supply voltage (V DD ) 124 of the overall IO interface circuit.
- the current mirror system 134 further connects a primary current output to one end of a driver bit cell 136 with the other end of the driver bit cell 136 connected to the low supply voltage/ground (V SS ) 126 . Accordingly, a current 122 flows from VDD 124 to V SS /ground 126 through the driver bit cell 136 .
- the driver bit cell 136 may affect the current 122 in a manner that reflects the overall PVT effects on the IO interface circuit for variations of the current 122 flowing through the driver bit cell 136 .
- the current 122 flowing through the driver bit cell 136 may be referred to as the PVT current (I PVT ) 122 .
- the current mirror system 134 also has a mirrored current output that is connected to the compensated current controlled oscillator (CCO) 102 .
- the mirrored current output provides a mirrored current 120 that is proportional 110 to I PVT 122 .
- the mirrored current 120 may then be used by an embodiment to control the oscillation frequency of the CCO 102 connected to the mirrored current, so the mirrored current 120 may be referred to as the control current (I CNTL ) 120 .
- the current mirror system 134 may be desirable for mirror I PVT 122 to I CNTL 120 on a one-to-one proportional 110 basis.
- the CCO 102 changes frequency with changes in I CNTL 120 to produce oscillations at a frequency (F OSC ) 114 dependent on I CNTL 120 .
- the CCO 102 delivers the F OSC 114 signal to the digital section 140 , and the digital system 104 in particular of the digital section 140 .
- the digital system 104 may also perform calculations to calibrate capacitance of the CCO 102 in order to remove process variation of comb/fringe capacitors that make up the CCO 102 .
- the digital system 104 may deliver the calibration values to the CCO 102 as capacitor calibration bits 112 such that the CCO 102 would be beneficially implemented as a digitally tunable CCO 102 .
- the digital system 104 represents the digital section 140 of the embodiment of the PVT compensation circuit 100 shown in FIG. 1 .
- the digital system 104 need only be a processing circuit element and associated memory capable of performing the operations described herein.
- the processing and memory elements may be implemented as a single logical circuit and/or individual processing and/or memory elements may be implemented in multiple circuits and combined together to provide the necessary processing and memory features to perform the necessary operations for the digital section 140 of an embodiment.
- the digital system 104 has an input that receives F OSC 114 from the CCO 102 and an output that delivers capacitor calibration bits 112 to the CCO 102 .
- the digital system also has an input to receive a reference (i.e., known) frequency (F REF ) 118 that is typically available from the overall IO interface circuit as the output of a crystal oscillator or a PLL (Phase Locked Loop) clock input with a definite jitter specification, which is already a part of the overall product that is adding an embodiment of the external component-less PVT compensation system.
- F REF reference frequency
- the digital system 104 may use F REF 118 to measure a desired count period to accumulate a count of F OSC 114 oscillations in order to determine a frequency of FOSC 114 based on the known frequency of F REF 118 . That is, since F REF 118 is known, a period may be measured by a number of oscillations of F REF 118 , and a count of oscillations of F OSC 114 accumulated by the digital system 104 during the known time period may then be divided by the known period time value to obtain the actual frequency of F OSC 114 .
- the digital system may then compare (in a comparator processor operation) the F OSC 114 generated by the CCO to a range of F OSC 114 values determined by simulation to represent operation of the IO interface from slow to nominal to fast process corners. Further, an embodiment may also advantageously eliminate the calculation of the actual F OSC 114 and simply use the accumulated count value of F OSC 114 measured by the digital system since the actual F OSC 114 and the accumulated count value are linearly dependent on each other and the division calculation is, therefore, unnecessary processing. However, if a system were to add the element of calculating the actual frequency of F OSC 114 , the system would still be an embodiment since the calculation of actual frequency does not provide a meaningful difference from the count value accumulated by the digital system 104 .
- a correlation between F OSC 114 count values and desired buffer impedance to correct for PVT for the IO interface may be established based on a simulation, or even an actual empirical test, of the IO interface circuit from the slow to fast process corners of the IO interface.
- the buffer impedance of the IO interface may be represented as PVT control bits 116 provided to the IO interface by the digital system 104 . Consequently, the correlation between F OSC 114 count values and buffer impedance may be established as a correlation between F OSC 114 and PVT control bit values 116 .
- the correlation between F OSC 114 count values and PVT control bit values 116 may then be put into a look-up table that is stored as a predetermined look-up table in the digital system 104 .
- the digital system 104 may then use the count of F OSC 114 oscillations accumulated during a desired count period as an input to the look-up table to obtain a correlating PVT control bit value 116 to provide to the overall IO interface so the IO interface may adjust the buffer impedance of the IO interface accordingly.
- the process of obtaining the look-up table values may include simulating operation of the CCO 102 and the associated F OSC 114 from a slow process corner to a fast process corner in discrete steps (such as a single change in the accumulated count value of F OSC 114 ) that correlates each count in a range of accumulated counts for a desired count period. Each count in the range of accumulated counts may then be correlated to a desired PVT control bit value 116 and the correlated accumulated count values of F OSC 114 and the associated PVT control bit value 116 for the range of accumulated count values may be stored in the look-up table used by the digital system to determine PVT control bit values 116 based on the current accumulated count measured for F OSC 114 .
- the CCO 102 may be implemented using a current starved approach where all MOS devices in an embodiment of the external component-less PVT compensation system are kept in saturation.
- the CCO 102 capacitances may be comb/fringe capacitors implemented using multi-layer metal structures that have negligible voltage and temperature coefficients.
- a CCO 102 for an embodiment may then be comprised of a “self-calibrating” ring oscillator with a well defined, but digitally tunable ring structure (see the disclosure with respect to FIG. 3 for more information).
- the frequency of oscillation F OSC 114 of the CCO 102 may be given by Eq. 1 below where ⁇ P and ⁇ N represent the channel length modulation parameters for PMOS and NMOS devices, respectively, in the CCO 102 , and C P represents the parasitic capacitance at the output of a unit-delay cell in the oscillator.
- an embodiment may “tune” the CCO 102 to take out the process variation of the comb/fringe capacitors making up the CCO 102 . See the disclosure with respect to FIG. 3 below for a more detailed discussion of the tuning/calibration of the CCO 102 capacitance (C L ) for an embodiment. With the CCO 102 C L tuned to eliminate process variation of the comb/fringe capacitors of the CCO 102 , the frequency of oscillation F OSC 114 of the CCO may be given by Eq. 3 below.
- ⁇ P and ⁇ N may be digitally subtracted out from the accumulated count value by the digital system 104 .
- the CCO 102 output frequency F OSC 114 is substantially linearly dependent on the input I CNTL 120 (and accordingly on I PVT 122 ).
- the digital system 102 accumulates a count of F OSC 114 oscillations in a counter and feeds the accumulated count to the count/PVT bit value look-up table stored on the digital system 104 to obtain a PVT bit value 116 that corresponds to the current F OSC 114 .
- the entries in the look-up table may consist of a count forming a range from 1 to N corresponding to the variations from the slow to fast process corner in discrete steps.
- the step size may be determined by the desired number of PVT control bits 116 needed to achieve acceptable spread in the buffer impedance of the IO interface.
- a Finite State Machine FSM may be used to control the calibration of the CCO 102 at device boot-up/power up, and at subsequent times during operation.
- FIG. 2 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT) compensation circuit 200 having an op-amp 228 based voltage reduction system 242 and a transistor based current mirror system 234 .
- PVT Process-Voltage-Temperature
- an embodiment of the PVT compensation circuit may be split into an analog section/portion 238 and a digital section/portion 240 .
- the analog section 238 generally works on analog principles to generate a frequency signal (F OSC ) 214 to deliver to the digital section 240 .
- F OSC frequency signal
- the digital section uses F OSC 214 to determine a PVT control bits value 216 that may be used by the IO interface to set a buffer impedance to mitigate potential PVT issues experienced by the overall IO interface circuitry.
- the overall IO interface circuit may make available a reference voltage (V REF ) 206 , a high voltage supply (V DD ) 224 , a low voltage supply/ground (V SS ) 226 , and a reference frequency (F REF ) 218 .
- the reference voltage (V REF ) 206 may be a Band Gap Reference voltage (V BGR ) of the IO interface circuit.
- the voltage reduction system is comprised of an op-amp loop made up of an operational amplifier 228 having various connections.
- V BGR 206 is connected to a positive input 230 of the operational amplifier 228 .
- the connection between the current mirror system 234 and the driver bit cell 236 is also connected to loop back to the negative input 232 of the operational amplifier 228 of the voltage reduction system 242 .
- the gain of the operational amplifier 228 may be set to reduce the voltage at the output of the operational amplifier to substantially half of V BGR 108 , or V BGR /2 ( 108 ).
- V BGR /2 ( 108 ) is connected to an input of the current mirror system 134 .
- V BGR /2 ( 108 ) is connected to an input of the current mirror system 134 .
- the current mirror system 234 is comprised of MOSFET devices indicating that the current mirror system 234 is a MOS based current mirror circuit 234 .
- MOSFET devices Other types of current mirror systems may be available, but using MOS in a primarily CMOS based IC is desirable.
- the current mirror system 234 also connects a high supply voltage connection point of the current mirror system 234 to the high supply voltage (V DD ) 224 of the overall IO interface circuit for each shown MOS device.
- the current mirror system 234 further connects a primary current output to one end of a driver bit cell 236 with the other end of the driver bit cell 236 connected to the low supply voltage/ground (V SS ) 226 .
- a current 222 flows from V DD 224 to V SS /ground 226 through the driver bit cell 236 .
- the driver bit cell 236 may affect the current 222 in a manner that reflects the overall PVT effects on the IO interface for the variations of the current 222 flowing through the driver bit cell 236 . Consequently, the current 222 flowing through the driver bit cell 236 may be referred to as the PVT current (I PVT ) 222 .
- the current mirror system 234 also has a mirrored current output that is connected to the compensated current controlled oscillator (CCO) 102 .
- the mirrored current output provides a mirrored current 220 that is proportional 210 to I PVT 222 .
- the mirrored current 220 may then be used by an embodiment to control the oscillation frequency of the CCO 202 connected to the mirrored current, so the mirrored current 220 may be referred to as the control current (I CNTL ) 220 .
- the CCO 202 changes frequency with changes in I CNTL 220 to produce oscillations at a frequency (F OSC ) 214 dependent on I CNTL 220 .
- the CCO 202 delivers the F OSC 214 signal to the digital section 240 , and the digital system 204 in particular of the digital section 240 .
- the digital system 204 may also perform calculations to calibrate capacitance of the CCO 202 in order to remove process variation of comb/fringe capacitors that make up the CCO 202 .
- the digital system 104 may deliver the calibration values to the CCO 202 as capacitor calibration bits 212 such that the CCO 202 would be beneficially implemented as a digitally tunable CCO 202 .
- the digital system 204 represents the digital section 240 of the embodiment of the PVT compensation circuit 200 shown in FIG. 2 .
- the digital system 204 need only be a processing circuit element and associated memory capable of performing the operations described herein.
- the processing and memory elements may be implemented as a single logical circuit and/or individual processing and/or memory elements may be implemented in multiple circuits and combined together to provide the necessary processing and memory features to perform the necessary operations for the digital section 240 of an embodiment.
- the digital system 204 has an input that receives F OSC 214 from the CCO 202 and an output that delivers capacitor calibration bits 212 to the CCO 202 .
- the digital system also has an input to receive a reference (i.e., known) frequency (F REF ) 218 that is typically available from the overall IO interface circuit.
- the digital system 204 may use F REF 218 to measure a desired count period to accumulate a count of F OSC 214 oscillations in order to determine a frequency of F OSC 214 based on the known frequency of F REF 218 .
- a period may be measured by a number of oscillations of F REF 218 , and a count of oscillations of F OSC 214 accumulated by the digital system 204 during the known time period may then be divided by the known period time value to obtain the actual frequency of F OSC 114 .
- the digital system may then compare (in a comparator processor operation) the F OSC 114 generated by the CCO to a range of F OSC 114 values determined by simulation to represent operation of the IO interface from slow to nominal to fast process corners.
- an embodiment may also advantageously eliminate the calculation of the actual F OSC 214 and simply use the accumulated count value of F OSC 124 measured by the digital system since the actual F OSC 214 are linearly dependent on each other and the division calculation is, therefore, unnecessary processing.
- the system would still be an embodiment since the calculation of actual frequency does not provide a meaningful difference from the count value accumulated by the digital system 204 .
- a correlation between F OSC 214 count values and desired buffer impedance to correct for PVT for the IO interface may be established via simulation, or even by empirical test, of the IO interface circuit from the slow to fast process corners of the IO interface.
- the buffer impedance of the IO interface may be represented as PVT control bits 216 provided to the IO interface by the digital system 204 . Consequently, the correlation between F OSC 214 count values and buffer impedance may be established as a correlation between F OSC 214 and PVT control bit values 216 .
- the correlation between F OSC 214 count values and PVT control bit values 216 may then be put into a look-up table that is stored as a predetermined look-up table in the digital system 204 .
- the digital system 204 may then use the count of F OSC 214 oscillations accumulated during a desired count period as an input to the look-up table to obtain a correlating PVT control bit value 216 to provide to the overall IO interface so the IO interface may adjust the buffer impedance of the IO interface accordingly.
- FIG. 3 is a circuit architecture block diagram 300 of the compensated current controlled oscillator 302 for an embodiment showing details of a capacitor calibration embodiment for the compensated current controlled oscillator 302 .
- FIG. 3 shows additional detail of the self-tuning current controlled oscillator 330 as well as the calibration portions of the compensated current controlled oscillator 302 .
- the capacitance loads C L 332 - 336 are connected in a ring structure to create the current controlled oscillator.
- calibration electrical switch 328 is open, an embodiment may operate as previously described.
- the calibration electrical switch 328 may be closed engaging the circuit of the beta-multiplier 324 and capacitor resistor 322 .
- the capacitor resistor is a frequency varying resistor that may vary in value as a function of frequency received at a frequency input for the resistor 322 and the capacitance (C CALIB ) of the self tuning current controlled oscillator 330 during the calibration operation.
- F REF may be connected to the frequency input of the capacitor resistor (R) 322 .
- a first end of capacitor resistor (R) 322 may be connected to V BGR /2 ( 308 ) and a second end may be connected to a beta multiplier system 324 . Accordingly, the value of the capacitor resistor (R) 322 during calibration may, therefore, be found using Eq. 5 below.
- the beta-multiplier 324 may have a gain of one, or unity, such that the calibration current (I CALIB ) 326 may be found using Eq. 6 below.
- the I CALIB 326 current may be used to determine the current value of C L of the loads 332 - 226 of the self tuning current controlled oscillator 330 using Eq. 7 below.
- C CALIB C LNominal + ⁇ ⁇ ⁇ ⁇ F * C LNominal 2 * F OSCNominal Eq . ⁇ 8
- F OSCNominal and C LNominal are simulation determined values at a nominal process corner. Using the difference between F OSCNominal and F OSC 314 along with F OSCNominal and C LNominal , the digital system 304 is able to calculate the current C CALIB of the self tuning current controlled oscillator 330 , and then send appropriate capacitor calibration bits 312 to the self tuning current controlled oscillator 330 to tune process variation out of the capacitor loads C L 332 - 336 .
- the digital system 304 of the embodiment illustrated in FIG. 3 shows three subsystems of the digital system 304 .
- An embodiment may implement a control Finite State Machine (FSM) 338 to handle the state control of the system, such as power-on, calibration, normal operation, etc.
- FSM Finite State Machine
- I CALIB 326 instead of I CNTL 320 (which is proportional to I PVT ).
- the counter/accumulator 340 would determine count values 344 for F OSC 314 and deliver the count values 344 to the control FSM 338 (possibly for use in calibrating the self tuning CCO 330 ) and to the frequency compare plus Look-Up Table (LUT) 342 (possibly for use in looking up desired PVT control bit values 316 during normal operation).
- LUT Look-Up Table
- FIG. 4A is a flow chart 400 of the process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the analog section of the embodiment.
- V BGR is connected to the input of a voltage reduction system.
- the voltage reduction system reduces V BGR by substantially half to produce V BGR /2.
- V BGR /2 at the output of the voltage reduction system is connected to an input of the current mirror system.
- a high voltage supply connection point of the current mirror system is connected to the high supply voltage (V DD ) of the IO interface circuit.
- V DD high supply voltage
- one end of a driver bit cell is connected to ground/low supply voltage (VSS).
- the primary current output of the current mirror system is connected to the other end of the driver bit cell such that a PVT current (I PVT ) flows through the driver bit cell.
- a mirrored current output of the current mirror system is connected to the compensated current controlled oscillator.
- the current mirror system mirrors I PVT on the mirrored current output of the current mirror system such that the compensated current controlled oscillator receives a control current (I CNTL ) that is proportional to I PVT .
- I CNTL control current
- a one-to-one proportion may be chosen for an embodiment, but other linearly dependent proportional relationships may be used if so desired by a system designer.
- the compensated current controlled oscillator generates an oscillation frequency (F OSC ) that is a function of I CNTL (which is substantially linearly proportional to I PVT ).
- the frequency F OSC of the current controlled oscillator may be substantially linearly dependent on the input I CNTL .
- the F OSC signal generated by the compensated current controlled oscillator is connected to a frequency input of the digital system.
- the F REF signal from the IO interface circuit is connected to a reference frequency input of the digital system.
- Off page connector 424 directs the process to FIG. 4B on a separate drawing sheet.
- FIG. 4B is a flow chart 450 of the process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the digital section of the embodiment.
- Off page connector 424 indicates that the flow chart 450 is a continuation from FIG. 4A on a separate drawing sheet.
- a desired count period for accumulating a count of F OSC oscillations is measured by the digital system based on the known F REF .
- an accumulator/counter of the digital system counts the oscillations of F OSC during a desired count period.
- the digital system looks up a PVT control bit value that correlates to the accumulated count of F OSC in a look-up table that contains a predetermined correlation of potential count values of F OSC to desired PVT control bit values.
- the digital system provides the looked up PVT control bit value to the IO interface.
- the IO interface sets the buffer impedance of the IO interface in accord with the looked up PVT control bit value.
- processes 426 - 432 may be performed by the digital system of an embodiment.
- FIG. 5 is a flow chart 500 of the process of calibrating the capacitance of the compensated current controlled oscillator.
- the digital system may calculate capacitor calibration bits to compensate for process variation of the comb/fringe capacitors of the compensated current controlled oscillator.
- the calculated capacitor calibration bits are sent to the compensated current controlled oscillator from a calibration bits output of the digital system to a calibration bits input of the compensated current controlled oscillator.
- the compensated current controlled oscillator should be “digitally” tunable.
- the digitally tunable compensated current controlled oscillator calibrates the capacitance of the comb/fringe capacitors based on the capacitor calibration bits calculated by the digital system.
- FIG. 6 is a detailed flow chart of a process of calibrating a capacitance of the compensated current controlled oscillator for an embodiment.
- one end of the capacitor resistor (R) is connected to V BGR /2.
- the capacitor resistor may be a variable resistor that varies as a function of F REF and the capacitance (C L ) of the compensated current controlled oscillator.
- the other end of the capacitor resistor (R) is connected to the beta-multiplier.
- F REF is connected to a frequency adjustment input to the capacitor resistor.
- the other side of the beta-multiplier is connected to a calibration electrical switch.
- the gain/K value for the beta-multiplier system is preferably one, or unity, for system simplicity, but this is not required.
- the other side of the calibration electrical switch is connected to the compensated current controlled oscillator.
- the calibration electrical switch is closed causing the system to enter a calibration state where a calibration current I CALIB flows through the calibration electrical switch such that I CALIB controls the compensated current controlled oscillator in place of I CNTL , and F OSC at the compensated current controlled oscillator is a function of I CALIB .
- a desired count period for accumulating a count of F OSC oscillations is measured by the digital system based on the known F REF .
- an accumulator/counter of the digital system counts the oscillations of F OSC during a desired count period.
- the digital system calculates capacitor calibration bits as a function of a predetermined nominal F OSC value, a predetermined nominal C L value, and the counted F OSC value for ICALIB. The relationship among the variables is substantially the same as described in Eqs. 5-8 in the disclosure above with respect to FIG. 3 .
- the calculated capacitor calibration bits are sent to the compensated current controlled oscillator from a calibration bits output of the digital system to a calibration bits input of the compensated current controlled oscillator.
- the compensated current controlled oscillator should be “digitally” tunable.
- the digitally tunable compensated current controlled oscillator calibrates the capacitance of the comb/fringe capacitors based on the capacitor calibration bits calculated by the digital system.
- the calibration electrical switch is opened and system operation is returned to normal PVT compensation operation.
- Various embodiments may be implemented using components that have substantially electrically similar characteristics. For instance, in place of one resistor, multiple resistors may be included that together have the same resistance characteristics as the resistors described herein.
Abstract
Description
- Input/Output (IO) for electronics and computing is typically described as the communication between some type of a processing system and the world outside of the subject processing system. The input of the IO refers to data/commands sent to the processing system from the outside world and the output of the IO refers to data/commands sent from the processing system to the outside world. The outside world simply refers to any entity not contained within the conceptual boundaries of the subject processing system. A processing system may be as small as a portion of a single chip or as large as networked group of computers, where the designation of the “processing system” is relative to what system is being designed. For instance, a computer integration specialist may look at each computer on a system as the “processing system,” while an integrated circuit chip designer may look to an individual integrated circuit chip, or even individual subsystems within a particular integrated circuit as the “processing system” such that the chip or chip subsystem operates as its own “processing system” with IO to the outside world being IO to entities outside of the chip or even other subsystems contained on the same chip if the “processing system” is an individual subsystem of a particular chip.
- An IO interface is necessary for the processor system to interact with the outside world. The IO interface provides the necessary logic to interpret addresses/commands issued by and/or sent to the processing system. A typical IO interface will implement some form of “handshaking” with the device/entity of the world outside of the processing system using commands such as busy, ready, and/or wait. Once “handshaking” to establish a connection is complete, a typical IO interface permits communication between the processing system and the world outside of the processing system. If different data formats are being exchanged, the IO interface typically performs the necessary conversion between the data formats to permit communication.
- A typical integrated circuit chip is made up of individual electrical elements and typically includes active elements such as one or more transistor devices. Typical operation of a transistor requires connection of the transistors either directly or through other electrical devices to a high and a low output of a voltage supply. Typically, the high output of the voltage supply is identified as the high voltage supply and the low output of the voltage supply is identified as the low voltage supply. For an integrated circuit based on Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), it is common to refer to the high supply voltage as VDD (or VDDIO when a separate power supply is available for the IO interface) and to refer to the low supply voltage as VSS. Many if not most, times VSS is also referred to and defined as the electrical ground for a circuit. Typical operation of a MOSFET device involves the application of high (VDD) and or low (VSS) supply voltages to the gate, source, and/or drain either directly or through other electrical circuit devices. MOSFET devices are typically divided into two major subdivisions, PMOS devices and NMOS devices which have related, but different operational characteristics. While initially tied to MOSFET based circuits, the use of VDD and VSS to represent the high and low voltage outputs, respectively, has become common usage even for non-MOSFET based circuits.
- An embodiment of the present invention may comprise a method to provide Process-Voltage-Temperature (PVT) compensation for an Input/Output (IO) interface, the IO interface having a bandgap reference voltage (VBGR) and a reference frequency (FREF), the method comprising: connecting the VBGR to a voltage reduction system; reducing the VBGR by substantially half at the voltage reduction system to produce VBGR/2; connecting the VBGR/2 to a current mirror system; connecting the current mirror system to a high supply voltage (VDD); connecting a driver bit cell to a low supply voltage (VSS); connecting the current mirror system to the driver bit cell such that a process-variable-temperature current (IPVT) flows through the driver bit cell; connecting the current mirror system to a compensated current controlled oscillator; mirroring the IPVT at the current mirror system such that the compensated current controlled oscillator receives a control current (ICNTL) that is proportional to the IPVT; generating an oscillation frequency (FOSC) at the compensated current controlled oscillator that is a function of the ICNTL; connecting the FOSC to a digital system; connecting the FREF to the digital system; measuring, by the digital system, a desired count period based on FREF; accumulating, by the digital system, a count of the FOSC at the digital system during the desired count period; looking up, by the digital system, a PVT control bit value that correlates to the accumulated count of the FOSC in a look-up table containing a predetermined correlation of potential count values of the FOSC to desired PVT control bit values; and providing, by the digital system, the looked up PVT control bit value to the IO interface.
- An embodiment of the present invention may further comprise a Process-Voltage-Temperature (PVT) compensation system for an Input/Output (IO) interface, the IO interface having a bandgap reference voltage (VBGR) and a reference frequency (FREF), the PVT compensation system comprising: a voltage reduction subsystem connected to the VBGR that reduces the VBGR by substantially half to produce VBGR/2; a driver bit cell connected to a current mirror subsystem and to a low supply voltage (VSS); the current mirror subsystem connected to the VBGR/2, to a high supply voltage (VDD), to the driver bit cell, and to a compensated current controlled oscillator such that a process-variable-temperature current (IPVT) flows through the driver bit cell and a mirrored control current (ICNTL) that is proportional to the IPVT is delivered to the compensated current controlled oscillator; a compensated current controlled oscillator connected to the ICNTL that generates an oscillation frequency (FOSC) that is a function of the ICNTL; a digital subsystem that is connected to the FOSC and to the FREF, and that measures a desired count period based on FREF, accumulates a count of the FOSC during the desired count period, looks up a PVT control bit value that correlates to the accumulated count of the FOSC in a look-up table containing a predetermined correlation of potential count values of the FOSC to desired PVT control bit values, and provides the looked up PVT control bit value to the IO interface in order for the IO interface to set a buffer impedance of the IO interface in accord with the looked up PVT control bit value.
- In the drawings,
-
FIG. 1 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT) compensation circuit. -
FIG. 2 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT) compensation circuit having an op-amp based voltage reduction system and a transistor based current mirror system. -
FIG. 3 is a circuit architecture block diagram of the compensated current controlled oscillator for an embodiment showing details of a capacitor calibration embodiment for the compensated current controlled oscillator. -
FIG. 4A is a flow chart of the process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the analog section of the embodiment. -
FIG. 4B is a flow chart of a process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the digital section of the embodiment. -
FIG. 5 is a flow chart of a process of calibrating the capacitance of the compensated current controlled oscillator for an embodiment. -
FIG. 6 is a detailed flow chart of the process of calibrating the capacitance of the compensated current controlled oscillator for an embodiment. - As consumers demand more powerful computing in ever smaller packages, the data processing rate and interface speeds for electronic devices are, likewise, increasing to meet consumer expectations. As data processing rates and interface speeds increase, the sensitivity of the Input/Output (IO) interfaces of the electronics has also increased. Accordingly, many IO interfaces require a minimum variation of rise and fall times over process, voltage and temperature, often called Process-Voltage-Temperature or PVT. Many IO interfaces are integrated circuits that may contain Metal-Oxide-Semiconductor (MOS) devices, some of which may be MOS Field-Effect Transistors (MOSFETs). Typical MOS devices are made up of two classifications of devices, PMOS devices and NMOS devices, which have related, but different operational characteristics. One method to address the PVT concerns for an IO interface of an Integrated Circuit (IC), particularly an IC containing MOS devices, is to use a precision resistor external to the IO interface IC chip as a reference to calibrate buffer impedance of the IO interface. In the external precision resistor method for PVT compensation, a voltage drop across a compensating device within the IC chip (e.g., a PMOS or NMOS device) is compared to a known voltage drop across the external precision resistor. Based on the comparison between the known voltage across the external precision resistor and the compensating NMOS/PMOS device contained within the IC chip, the buffer impedance of the IO interface may be adjusted to correct any variations in voltage caused by PVT effects on the IC operation. The external precision resistor method of PVT compensation requires that the IC chip having the IO interface build in an external pin for connecting to the external precision resistor and that any systems incorporating the IC chip also leave space on the Printed Circuit Board (PCB) layout to accommodate the external precision resistor.
-
FIG. 1 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT)compensation circuit 100 for an IO interface. Notably, there is no need for an external precision resistor in thePVT compensation circuit 100 such that an embodiment may eliminate the pin used for connection to the external precision resistor in an IC chip package including an embodiment. Since the external precision resistor is not required, systems need not include space or traces on printed circuit boards to accommodate the now unneeded external precision resistor. Conceptually, an embodiment of the PVT compensation circuit may be split into an analog section/portion 138 and a digital section/portion 140. Theanalog section 138 generally works on analog principles to generate a frequency signal (FOSC) 114 to deliver to thedigital section 140. The digital section usesF OSC 114 to determine a PVTcontrol bits value 116 that may be used by the IO interface to set a buffer impedance to mitigate potential PVT issues experienced by the overall IO interface circuitry. The overall IO interface circuit, as part of the standard aspects of an IO interface circuit, may make available a reference voltage (VREF) 106, a high voltage supply (VDD) 124, a low voltage supply/ground (VSS) 126, and a reference frequency (FREF) 118. The reference voltage (VREF) 106 may be a Band Gap Reference voltage (VBGR) of the IO interface circuit. While anyreference voltage 106 may be used for an embodiment, for the embodiments discussed in this document, the reference voltage will be the bandgap reference voltage (VBGR). Also note that various “systems” making up an embodiment may be referenced as a system (e.g.,voltage reduction system 142,current mirror system 134, etc.) and/or may be referenced as a subsystem of the overall PVT compensation circuit (e.g.,voltage reduction subsystem 142,current mirror subsystem 134, etc.). The choice of describing elements as a system or a subsystem does not affect the disclosed operation of the element, but is intended to permit a discussion in terms of the interaction of the various systems and/or to indicate that a system is a piece (i.e., a subsystem) of the overall PVT compensation system. - For the
embodiment 100 shown inFIG. 1 , in theanalog section 138,V BGR 106 is connected to an input of avoltage reduction system 142. Thevoltage reduction system 142 reduces the voltage to substantially half ofV BGR 108, or VBGR/2 (108). The voltage reduction system may be any type of voltage reduction circuitry including an op-amp loop with an appropriate gain and a standard voltage divider circuit. Thevoltage reduction system 142 makes VBGR/2 (108) available at an output of thevoltage reduction system 142. VBGR/2 (108) is connected to an input of thecurrent mirror system 134. Thecurrent mirror system 134 also connects a high supply voltage connection point to the high supply voltage (VDD) 124 of the overall IO interface circuit. Thecurrent mirror system 134 further connects a primary current output to one end of adriver bit cell 136 with the other end of thedriver bit cell 136 connected to the low supply voltage/ground (VSS) 126. Accordingly, a current 122 flows from VDD 124 to VSS/ground 126 through thedriver bit cell 136. Thedriver bit cell 136 may affect the current 122 in a manner that reflects the overall PVT effects on the IO interface circuit for variations of the current 122 flowing through thedriver bit cell 136. Consequently, the current 122 flowing through thedriver bit cell 136 may be referred to as the PVT current (IPVT) 122. Thecurrent mirror system 134 also has a mirrored current output that is connected to the compensated current controlled oscillator (CCO) 102. The mirrored current output provides a mirrored current 120 that is proportional 110 to IPVT 122. The mirrored current 120 may then be used by an embodiment to control the oscillation frequency of theCCO 102 connected to the mirrored current, so the mirrored current 120 may be referred to as the control current (ICNTL) 120. To ease confusion in creating the system, it may be desirable for thecurrent mirror system 134 to mirror IPVT 122 to ICNTL 120 on a one-to-one proportional 110 basis. TheCCO 102 changes frequency with changes in ICNTL 120 to produce oscillations at a frequency (FOSC) 114 dependent onI CNTL 120. TheCCO 102 delivers theF OSC 114 signal to thedigital section 140, and thedigital system 104 in particular of thedigital section 140. Thedigital system 104 may also perform calculations to calibrate capacitance of theCCO 102 in order to remove process variation of comb/fringe capacitors that make up theCCO 102. Thedigital system 104 may deliver the calibration values to theCCO 102 ascapacitor calibration bits 112 such that theCCO 102 would be beneficially implemented as a digitallytunable CCO 102. - The
digital system 104 represents thedigital section 140 of the embodiment of thePVT compensation circuit 100 shown inFIG. 1 . Thedigital system 104 need only be a processing circuit element and associated memory capable of performing the operations described herein. The processing and memory elements may be implemented as a single logical circuit and/or individual processing and/or memory elements may be implemented in multiple circuits and combined together to provide the necessary processing and memory features to perform the necessary operations for thedigital section 140 of an embodiment. - As also described above, the
digital system 104 has an input that receivesF OSC 114 from theCCO 102 and an output that deliverscapacitor calibration bits 112 to theCCO 102. The digital system also has an input to receive a reference (i.e., known) frequency (FREF) 118 that is typically available from the overall IO interface circuit as the output of a crystal oscillator or a PLL (Phase Locked Loop) clock input with a definite jitter specification, which is already a part of the overall product that is adding an embodiment of the external component-less PVT compensation system. Thedigital system 104 may useF REF 118 to measure a desired count period to accumulate a count ofF OSC 114 oscillations in order to determine a frequency ofFOSC 114 based on the known frequency ofF REF 118. That is, sinceF REF 118 is known, a period may be measured by a number of oscillations ofF REF 118, and a count of oscillations ofF OSC 114 accumulated by thedigital system 104 during the known time period may then be divided by the known period time value to obtain the actual frequency ofF OSC 114. The digital system may then compare (in a comparator processor operation) theF OSC 114 generated by the CCO to a range ofF OSC 114 values determined by simulation to represent operation of the IO interface from slow to nominal to fast process corners. Further, an embodiment may also advantageously eliminate the calculation of theactual F OSC 114 and simply use the accumulated count value ofF OSC 114 measured by the digital system since theactual F OSC 114 and the accumulated count value are linearly dependent on each other and the division calculation is, therefore, unnecessary processing. However, if a system were to add the element of calculating the actual frequency ofF OSC 114, the system would still be an embodiment since the calculation of actual frequency does not provide a meaningful difference from the count value accumulated by thedigital system 104. - A correlation between
F OSC 114 count values and desired buffer impedance to correct for PVT for the IO interface may be established based on a simulation, or even an actual empirical test, of the IO interface circuit from the slow to fast process corners of the IO interface. The buffer impedance of the IO interface may be represented asPVT control bits 116 provided to the IO interface by thedigital system 104. Consequently, the correlation betweenF OSC 114 count values and buffer impedance may be established as a correlation betweenF OSC 114 and PVT control bit values 116. The correlation betweenF OSC 114 count values and PVT control bit values 116 may then be put into a look-up table that is stored as a predetermined look-up table in thedigital system 104. Thedigital system 104 may then use the count ofF OSC 114 oscillations accumulated during a desired count period as an input to the look-up table to obtain a correlating PVTcontrol bit value 116 to provide to the overall IO interface so the IO interface may adjust the buffer impedance of the IO interface accordingly. - The process of obtaining the look-up table values may include simulating operation of the
CCO 102 and the associatedF OSC 114 from a slow process corner to a fast process corner in discrete steps (such as a single change in the accumulated count value of FOSC 114) that correlates each count in a range of accumulated counts for a desired count period. Each count in the range of accumulated counts may then be correlated to a desired PVTcontrol bit value 116 and the correlated accumulated count values ofF OSC 114 and the associated PVTcontrol bit value 116 for the range of accumulated count values may be stored in the look-up table used by the digital system to determine PVT control bit values 116 based on the current accumulated count measured forF OSC 114. - Since it is desirable to implement all aspects of an embodiment on the IC chip needing PVT compensation, it is desirable to implement the
CCO 102 efficiently. Further, it is desirable for the operation of an embodiment to ensure that theCCO 102 is linearly dependent on ICNTL 120 (and hence on IPVT 122 since ICNTL 120 is simply a proportional 110 mirror of IPVT 122). TheCCO 102 may be implemented using a current starved approach where all MOS devices in an embodiment of the external component-less PVT compensation system are kept in saturation. TheCCO 102 capacitances may be comb/fringe capacitors implemented using multi-layer metal structures that have negligible voltage and temperature coefficients. Typical current technology for the comb/fringe capacitors exhibits a process variation of +/−17% across three process corners (nominal, low, and high). ACCO 102 for an embodiment may then be comprised of a “self-calibrating” ring oscillator with a well defined, but digitally tunable ring structure (see the disclosure with respect toFIG. 3 for more information). Under the current starved/saturation condition, the frequency ofoscillation F OSC 114 of theCCO 102 may be given by Eq. 1 below where λP and λN represent the channel length modulation parameters for PMOS and NMOS devices, respectively, in theCCO 102, and CP represents the parasitic capacitance at the output of a unit-delay cell in the oscillator. -
- To achieve the desired PVT compensation for an embodiment it is desirable to make the PVT of the
CCO 102 independent of λP, λN, and CP. To make the PVT of the CCO independent of λP, λN, and λP, an embodiment may “tune” theCCO 102 to take out the process variation of the comb/fringe capacitors making up theCCO 102. See the disclosure with respect toFIG. 3 below for a more detailed discussion of the tuning/calibration of theCCO 102 capacitance (CL) for an embodiment. With the CCO 102 CL tuned to eliminate process variation of the comb/fringe capacitors of theCCO 102, the frequency ofoscillation F OSC 114 of the CCO may be given by Eq. 3 below. -
- The effect of λP and λN may be digitally subtracted out from the accumulated count value by the
digital system 104. With λP and λN removed and theCCO 102 tuned to substantially remove process variation from the comb/fringe capacitors CL of theCCO 102 and with sufficiently granular values of IPVT (such as the discrete steps representing accumulated count values), theCCO 102output frequency F OSC 114 is substantially linearly dependent on the input ICNTL 120 (and accordingly on IPVT 122). Thedigital system 102 accumulates a count ofF OSC 114 oscillations in a counter and feeds the accumulated count to the count/PVT bit value look-up table stored on thedigital system 104 to obtain aPVT bit value 116 that corresponds to thecurrent F OSC 114. The entries in the look-up table may consist of a count forming a range from 1 to N corresponding to the variations from the slow to fast process corner in discrete steps. The step size may be determined by the desired number ofPVT control bits 116 needed to achieve acceptable spread in the buffer impedance of the IO interface. A Finite State Machine (FSM) may be used to control the calibration of theCCO 102 at device boot-up/power up, and at subsequent times during operation. -
FIG. 2 is a circuit architecture block diagram of an external component-less Process-Voltage-Temperature (PVT)compensation circuit 200 having an op-amp 228 basedvoltage reduction system 242 and a transistor basedcurrent mirror system 234. As for the embodiment shown inFIG. 1 , conceptually, an embodiment of the PVT compensation circuit may be split into an analog section/portion 238 and a digital section/portion 240. Again, theanalog section 238 generally works on analog principles to generate a frequency signal (FOSC) 214 to deliver to thedigital section 240. The digital section usesF OSC 214 to determine a PVT control bits value 216 that may be used by the IO interface to set a buffer impedance to mitigate potential PVT issues experienced by the overall IO interface circuitry. The overall IO interface circuit, as part of the standard aspects of an IO interface circuit, may make available a reference voltage (VREF) 206, a high voltage supply (VDD) 224, a low voltage supply/ground (VSS) 226, and a reference frequency (FREF) 218. The reference voltage (VREF) 206 may be a Band Gap Reference voltage (VBGR) of the IO interface circuit. - For the
embodiment 200 shown inFIG. 2 , in theanalog section 238, the voltage reduction system is comprised of an op-amp loop made up of anoperational amplifier 228 having various connections.V BGR 206 is connected to apositive input 230 of theoperational amplifier 228. The connection between thecurrent mirror system 234 and thedriver bit cell 236 is also connected to loop back to thenegative input 232 of theoperational amplifier 228 of thevoltage reduction system 242. The gain of theoperational amplifier 228 may be set to reduce the voltage at the output of the operational amplifier to substantially half ofV BGR 108, or VBGR/2 (108). VBGR/2 (108) is connected to an input of thecurrent mirror system 134. In the embodiment shown inFIG. 2 , thecurrent mirror system 234 is comprised of MOSFET devices indicating that thecurrent mirror system 234 is a MOS basedcurrent mirror circuit 234. Other types of current mirror systems may be available, but using MOS in a primarily CMOS based IC is desirable. Thecurrent mirror system 234 also connects a high supply voltage connection point of thecurrent mirror system 234 to the high supply voltage (VDD) 224 of the overall IO interface circuit for each shown MOS device. Thecurrent mirror system 234 further connects a primary current output to one end of adriver bit cell 236 with the other end of thedriver bit cell 236 connected to the low supply voltage/ground (VSS) 226. Accordingly, a current 222 flows fromV DD 224 to VSS/ground 226 through thedriver bit cell 236. Thedriver bit cell 236 may affect the current 222 in a manner that reflects the overall PVT effects on the IO interface for the variations of the current 222 flowing through thedriver bit cell 236. Consequently, the current 222 flowing through thedriver bit cell 236 may be referred to as the PVT current (IPVT) 222. Thecurrent mirror system 234 also has a mirrored current output that is connected to the compensated current controlled oscillator (CCO) 102. The mirrored current output provides a mirrored current 220 that is proportional 210 to IPVT 222. The mirrored current 220 may then be used by an embodiment to control the oscillation frequency of theCCO 202 connected to the mirrored current, so the mirrored current 220 may be referred to as the control current (ICNTL) 220. TheCCO 202 changes frequency with changes in ICNTL 220 to produce oscillations at a frequency (FOSC) 214 dependent onI CNTL 220. TheCCO 202 delivers theF OSC 214 signal to thedigital section 240, and thedigital system 204 in particular of thedigital section 240. Thedigital system 204 may also perform calculations to calibrate capacitance of theCCO 202 in order to remove process variation of comb/fringe capacitors that make up theCCO 202. Thedigital system 104 may deliver the calibration values to theCCO 202 ascapacitor calibration bits 212 such that theCCO 202 would be beneficially implemented as a digitallytunable CCO 202. - The
digital system 204 represents thedigital section 240 of the embodiment of thePVT compensation circuit 200 shown inFIG. 2 . Thedigital system 204 need only be a processing circuit element and associated memory capable of performing the operations described herein. The processing and memory elements may be implemented as a single logical circuit and/or individual processing and/or memory elements may be implemented in multiple circuits and combined together to provide the necessary processing and memory features to perform the necessary operations for thedigital section 240 of an embodiment. - As also described above, the
digital system 204 has an input that receivesF OSC 214 from theCCO 202 and an output that deliverscapacitor calibration bits 212 to theCCO 202. The digital system also has an input to receive a reference (i.e., known) frequency (FREF) 218 that is typically available from the overall IO interface circuit. Thedigital system 204 may useF REF 218 to measure a desired count period to accumulate a count ofF OSC 214 oscillations in order to determine a frequency ofF OSC 214 based on the known frequency ofF REF 218. That is, sinceF REF 218 is known, a period may be measured by a number of oscillations ofF REF 218, and a count of oscillations ofF OSC 214 accumulated by thedigital system 204 during the known time period may then be divided by the known period time value to obtain the actual frequency ofF OSC 114. The digital system may then compare (in a comparator processor operation) theF OSC 114 generated by the CCO to a range ofF OSC 114 values determined by simulation to represent operation of the IO interface from slow to nominal to fast process corners. Further, an embodiment may also advantageously eliminate the calculation of theactual F OSC 214 and simply use the accumulated count value ofF OSC 124 measured by the digital system since theactual F OSC 214 are linearly dependent on each other and the division calculation is, therefore, unnecessary processing. However, if a system were to add the element of calculating the actual frequency ofF OSC 214, the system would still be an embodiment since the calculation of actual frequency does not provide a meaningful difference from the count value accumulated by thedigital system 204. - A correlation between
F OSC 214 count values and desired buffer impedance to correct for PVT for the IO interface may be established via simulation, or even by empirical test, of the IO interface circuit from the slow to fast process corners of the IO interface. The buffer impedance of the IO interface may be represented asPVT control bits 216 provided to the IO interface by thedigital system 204. Consequently, the correlation betweenF OSC 214 count values and buffer impedance may be established as a correlation betweenF OSC 214 and PVT control bit values 216. The correlation betweenF OSC 214 count values and PVT control bit values 216 may then be put into a look-up table that is stored as a predetermined look-up table in thedigital system 204. Thedigital system 204 may then use the count ofF OSC 214 oscillations accumulated during a desired count period as an input to the look-up table to obtain a correlating PVTcontrol bit value 216 to provide to the overall IO interface so the IO interface may adjust the buffer impedance of the IO interface accordingly. -
FIG. 3 is a circuit architecture block diagram 300 of the compensated current controlledoscillator 302 for an embodiment showing details of a capacitor calibration embodiment for the compensated current controlledoscillator 302.FIG. 3 shows additional detail of the self-tuning current controlledoscillator 330 as well as the calibration portions of the compensated current controlledoscillator 302. There is also a further breakdown of functionality of thedigital system 304 for an embodiment that may be utilized by the embodiment to carry out the functions of thedigital system 304. As may be seen in the self tuning current controlled oscillator, the capacitance loads CL 332-336 are connected in a ring structure to create the current controlled oscillator. When calibrationelectrical switch 328 is open, an embodiment may operate as previously described. During a calibration state/operation, the calibrationelectrical switch 328 may be closed engaging the circuit of the beta-multiplier 324 andcapacitor resistor 322. The capacitor resistor is a frequency varying resistor that may vary in value as a function of frequency received at a frequency input for theresistor 322 and the capacitance (CCALIB) of the self tuning current controlledoscillator 330 during the calibration operation. To calibrate the self tuning current controlledoscillator 330, FREF may be connected to the frequency input of the capacitor resistor (R) 322. A first end of capacitor resistor (R) 322 may be connected to VBGR/2 (308) and a second end may be connected to abeta multiplier system 324. Accordingly, the value of the capacitor resistor (R) 322 during calibration may, therefore, be found using Eq. 5 below. -
- The beta-
multiplier 324 may have a gain of one, or unity, such that the calibration current (ICALIB) 326 may be found using Eq. 6 below. -
- The
I CALIB 326 current may be used to determine the current value of CL of the loads 332-226 of the self tuning current controlledoscillator 330 using Eq. 7 below. -
- which may be updated to Eq. 8 below for the current value of CL during the calibration process.
-
- FOSCNominal and CLNominal are simulation determined values at a nominal process corner. Using the difference between FOSCNominal and
F OSC 314 along with FOSCNominal and CLNominal, thedigital system 304 is able to calculate the current CCALIB of the self tuning current controlledoscillator 330, and then send appropriatecapacitor calibration bits 312 to the self tuning current controlledoscillator 330 to tune process variation out of the capacitor loads CL 332-336. - The
digital system 304 of the embodiment illustrated inFIG. 3 shows three subsystems of thedigital system 304. An embodiment may implement a control Finite State Machine (FSM) 338 to handle the state control of the system, such as power-on, calibration, normal operation, etc. As described above, during normal operation calibrationelectrical switch 328 would be open and during calibration (which will typically occur at least at the power up state), calibrationelectrical switch 328 would close causing the self tuning current controlled oscillator to be controlled by ICALIB 326 instead of ICNTL 320 (which is proportional to IPVT). During either calibration or normal operation, the counter/accumulator 340 would determine countvalues 344 forF OSC 314 and deliver the count values 344 to the control FSM 338 (possibly for use in calibrating the self tuning CCO 330) and to the frequency compare plus Look-Up Table (LUT) 342 (possibly for use in looking up desired PVT control bit values 316 during normal operation). -
FIG. 4A is aflow chart 400 of the process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the analog section of the embodiment. Atprocess 402, VBGR is connected to the input of a voltage reduction system. Atprocess 404, the voltage reduction system reduces VBGR by substantially half to produce VBGR/2. Atprocess 406, VBGR/2 at the output of the voltage reduction system is connected to an input of the current mirror system. Atprocess 408, a high voltage supply connection point of the current mirror system is connected to the high supply voltage (VDD) of the IO interface circuit. Atprocess 410, one end of a driver bit cell is connected to ground/low supply voltage (VSS). Atprocess 412, the primary current output of the current mirror system is connected to the other end of the driver bit cell such that a PVT current (IPVT) flows through the driver bit cell. Atprocess 414, a mirrored current output of the current mirror system is connected to the compensated current controlled oscillator. Atprocess 416, the current mirror system mirrors IPVT on the mirrored current output of the current mirror system such that the compensated current controlled oscillator receives a control current (ICNTL) that is proportional to IPVT. For ease of operation/design, a one-to-one proportion may be chosen for an embodiment, but other linearly dependent proportional relationships may be used if so desired by a system designer. Atprocess 418, the compensated current controlled oscillator generates an oscillation frequency (FOSC) that is a function of ICNTL (which is substantially linearly proportional to IPVT). Via calibration of the compensated current controlled oscillator to remove process variation of the comb/fringe capacitors and choice of materials of the comb/fringe capacitors to limit voltage and temperature variations, the frequency FOSC of the current controlled oscillator may be substantially linearly dependent on the input ICNTL. Atprocess 420, the FOSC signal generated by the compensated current controlled oscillator is connected to a frequency input of the digital system. Atprocess 422, the FREF signal from the IO interface circuit is connected to a reference frequency input of the digital system. Offpage connector 424 directs the process toFIG. 4B on a separate drawing sheet. -
FIG. 4B is aflow chart 450 of the process of connecting and operating an embodiment of an external component-less PVT compensation circuit, with particular regard to the digital section of the embodiment. Offpage connector 424 indicates that theflow chart 450 is a continuation fromFIG. 4A on a separate drawing sheet. Atprocess 426, a desired count period for accumulating a count of FOSC oscillations is measured by the digital system based on the known FREF. Atprocess 428, an accumulator/counter of the digital system counts the oscillations of FOSC during a desired count period. Atprocess 430, the digital system looks up a PVT control bit value that correlates to the accumulated count of FOSC in a look-up table that contains a predetermined correlation of potential count values of FOSC to desired PVT control bit values. Atprocess 432, the digital system provides the looked up PVT control bit value to the IO interface. Atprocess 434, the IO interface sets the buffer impedance of the IO interface in accord with the looked up PVT control bit value. As noted at 436, processes 426-432 may be performed by the digital system of an embodiment. -
FIG. 5 is aflow chart 500 of the process of calibrating the capacitance of the compensated current controlled oscillator. Atprocess 502, the digital system may calculate capacitor calibration bits to compensate for process variation of the comb/fringe capacitors of the compensated current controlled oscillator. Atprocess 504, the calculated capacitor calibration bits are sent to the compensated current controlled oscillator from a calibration bits output of the digital system to a calibration bits input of the compensated current controlled oscillator. Notably, for the calibration bits to have any effect on the operation of the compensated current controlled oscillator, the compensated current controlled oscillator should be “digitally” tunable. Atprocess 506, the digitally tunable compensated current controlled oscillator calibrates the capacitance of the comb/fringe capacitors based on the capacitor calibration bits calculated by the digital system. -
FIG. 6 is a detailed flow chart of a process of calibrating a capacitance of the compensated current controlled oscillator for an embodiment. Atprocess 602, one end of the capacitor resistor (R) is connected to VBGR/2. The capacitor resistor may be a variable resistor that varies as a function of FREF and the capacitance (CL) of the compensated current controlled oscillator. Atprocess 604, the other end of the capacitor resistor (R) is connected to the beta-multiplier. Atprocess 606, FREF is connected to a frequency adjustment input to the capacitor resistor. Atprocess 608, the other side of the beta-multiplier is connected to a calibration electrical switch. The gain/K value for the beta-multiplier system is preferably one, or unity, for system simplicity, but this is not required. Atprocess 610, the other side of the calibration electrical switch is connected to the compensated current controlled oscillator. Atprocess 612, typically on overall IO interface power-up (i.e., start) and/or upon a specific request, the calibration electrical switch is closed causing the system to enter a calibration state where a calibration current ICALIB flows through the calibration electrical switch such that ICALIB controls the compensated current controlled oscillator in place of ICNTL, and FOSC at the compensated current controlled oscillator is a function of ICALIB. Atprocess 614, a desired count period for accumulating a count of FOSC oscillations is measured by the digital system based on the known FREF. Atprocess 616, an accumulator/counter of the digital system counts the oscillations of FOSC during a desired count period. Atprocess 618, the digital system calculates capacitor calibration bits as a function of a predetermined nominal FOSC value, a predetermined nominal CL value, and the counted FOSC value for ICALIB. The relationship among the variables is substantially the same as described in Eqs. 5-8 in the disclosure above with respect toFIG. 3 . Atprocess 620, the calculated capacitor calibration bits are sent to the compensated current controlled oscillator from a calibration bits output of the digital system to a calibration bits input of the compensated current controlled oscillator. Notably again, for the calibration bits to have any effect on the operation the compensated current controlled oscillator, the compensated current controlled oscillator should be “digitally” tunable. Atprocess 622, the digitally tunable compensated current controlled oscillator calibrates the capacitance of the comb/fringe capacitors based on the capacitor calibration bits calculated by the digital system. Atprocess 624, the calibration electrical switch is opened and system operation is returned to normal PVT compensation operation. - Various embodiments may be implemented using components that have substantially electrically similar characteristics. For instance, in place of one resistor, multiple resistors may be included that together have the same resistance characteristics as the resistors described herein.
- The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.
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WO2019054035A1 (en) * | 2017-09-13 | 2019-03-21 | 日立オートモティブシステムズ株式会社 | Current generation circuit and diagnostic circuit |
CN113064678A (en) * | 2021-03-25 | 2021-07-02 | 北京京东乾石科技有限公司 | Cache configuration method and device |
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US5331295A (en) * | 1993-02-03 | 1994-07-19 | National Semiconductor Corporation | Voltage controlled oscillator with efficient process compensation |
US5498977A (en) | 1995-03-03 | 1996-03-12 | Hewlett-Packard Company | Output driver having process, voltage and temperature compensation for delay and risetime |
US6762624B2 (en) | 2002-09-03 | 2004-07-13 | Agilent Technologies, Inc. | Current mode logic family with bias current compensation |
US7321254B2 (en) | 2004-12-03 | 2008-01-22 | Lsi Logic Corporation | On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method |
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US7446592B2 (en) | 2005-07-22 | 2008-11-04 | Freescale Semiconductor, Inc. | PVT variation detection and compensation circuit |
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WO2019054035A1 (en) * | 2017-09-13 | 2019-03-21 | 日立オートモティブシステムズ株式会社 | Current generation circuit and diagnostic circuit |
JPWO2019054035A1 (en) * | 2017-09-13 | 2020-10-01 | 日立オートモティブシステムズ株式会社 | Current generation circuit and diagnostic circuit |
US11604483B2 (en) | 2017-09-13 | 2023-03-14 | Hitachi Astemo, Ltd. | Current generator circuit and diagnostic circuit |
CN113064678A (en) * | 2021-03-25 | 2021-07-02 | 北京京东乾石科技有限公司 | Cache configuration method and device |
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