US20140133614A1 - Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability - Google Patents

Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability Download PDF

Info

Publication number
US20140133614A1
US20140133614A1 US13/947,134 US201313947134A US2014133614A1 US 20140133614 A1 US20140133614 A1 US 20140133614A1 US 201313947134 A US201313947134 A US 201313947134A US 2014133614 A1 US2014133614 A1 US 2014133614A1
Authority
US
United States
Prior art keywords
serial
signal
eye pattern
receiver
serial receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/947,134
Inventor
Alexander Neal Huntley
Roger Fawcett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of US20140133614A1 publication Critical patent/US20140133614A1/en
Assigned to IMAGE PROCESSING TECHNIQUES LIMITED reassignment IMAGE PROCESSING TECHNIQUES LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAWCETT, ROGER, HUNTLEY, ALEXANDER NEIL
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IMAGE PROCESSING TECHNIQUES LIMITED
Assigned to ALTERA CORPORATION reassignment ALTERA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0087Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/20Arrangements for detecting or preventing errors in the information received using signal quality detector
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31708Analysis of signal quality
    • G01R31/31709Jitter measurements; Jitter generators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31708Analysis of signal quality
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/20Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/205Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31708Analysis of signal quality
    • G01R31/31711Evaluation methods, e.g. shmoo plots

Definitions

  • the quality of a serial digital bitstream can be assessed by observing an accurate visual representation of the amplitude of the signal with respect to time. This can be performed by a traditional oscilloscope, or a dedicated electrical circuit designed specifically to look at serial bitstream signals.
  • An eye pattern displays various parameters by which the quality of a serial data signal is quantified such as: rise time, fall time, undershoot, overshoot, jitter, pulse width, amplitude, and distortion, and the variation in those parameters.
  • Eye patterns are often created using either a very high-speed analog-to-digital converter (ADC) or sample-and-hold integrated circuits (ICs), but now there are various ICs that incorporate serial receivers with this eye pattern ability built-in. For example, this ability may be found in:
  • serial receivers have a minimum operating frequency which can be above the data rate of some serial data streams: e.g. Standard definition SDI.
  • Our invention enables an eye pattern to be generated where the signal quality or signal frequency is not sufficient for an eye capable transceiver to lock onto, by the novel idea of using the slave/free-running mode of the transceiver to sample the unadulterated signal at the actual data rate. It achieves this by splitting the incoming signal, equalising one of the split signals and recovering a clock signal from the equalized signal. In this way, our invention allows a realistic eye pattern to be obtained for the unequalized signal, regardless of the quality of that unequalized signal.
  • Our invention provides a way to produce an eye pattern using the eye-pattern capability of a serial receiver where the signal of interest is of insufficient quality for the serial receiver's built-in eye pattern capability. It uses a signal splitter to generate two copies of the serial data signal, one of which is conditioned as required then fed to a “master” serial receiver that locks onto the input signal and recovers a serial clock. The other copy of the signal is fed to a “slave” serial receiver with embedded eye pattern capability which is set to “free-run” i.e. it does not attempt to lock onto its serial data input. Instead, the clock generated by the master serial receiver is used to the slave serial receiver, enabling it to produce the eye pattern of the unconditioned signal.
  • the conditioning applied could consist of amplification, filtering or cable equalisation.
  • the serial receivers used may be located either in the same integrated circuit or in separate ICs, depending on the data rate of the signal and the operating characteristics of the ICs.
  • FIGS. 1 , 2 and 3 illustrate three possible implementations of the invention.
  • FIG. 1 illustrates an implementation that can be used where the data rate of the serial data signal is within the operating frequency range of the eye-capable serial receiver.
  • FIG. 2 illustrates the alternative style of implementation that needs to be used where the IC's minimum operating frequency is higher than the data rate of the serial data signal.
  • FIG. 3 illustrates how the same basic arrangement may be used to extract eye pattern data from an unrelated serial data signal.
  • the serial data signal is split into two identical copies by the signal splitter 1 and one copy is then conditioned by the signal conditioning unit 2 prior to being passed to the master serial receiver 3 which recovers the serial clock 4 .
  • the other copy is passed to the slave serial receiver 5 .
  • the clock signal extracted from the serial data signal by the master serial receiver 3 is used to clock the slave serial receiver 5 , thereby allowing it to generate the required eye pattern.
  • the data signal is already of sufficient quality but its speed is below the capability of the eye-capable serial receiver 5 .
  • the master serial receiver 3 in FIG. 1 by a serial receiver 6 that has the appropriate characteristics for extracting the required clock, but which may not have embedded eye capability itself.
  • the signals to be presented to serial receivers 3 and 5 are independent. This arrangement may be used to assess the degree to which two serial data signals are synchronised.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Dc Digital Transmission (AREA)
  • Information Transfer Systems (AREA)

Abstract

The use of eye pattern circuitry associated with a serial receiver embedded in an integrated circuit (e.g. in an FPGA) relies on the signal quality and signal frequency being sufficient for the serial receiver to lock onto the signal: if this is not possible then it is not possible to obtain an eye pattern.
Our novel invention enables the use of this embedded circuitry where the signal quality and signal frequency are not sufficient by splitting the incoming signal, then using the clock recovered with further processing from one of the split signals together with the built-in eye pattern circuitry to obtain a realistic eye pattern for the unprocessed signal, regardless of the quality of that unprocessed signal.
The technique uses the free-running or ‘slave’ mode of these serial receivers in which the receiver does not lock to the incoming data. To date, this mode has been used for oversampling but not for sampling at the actual data rate with a recovered clock in order obtain eye pattern samples.

Description

    BACKGROUND OF THE INVENTION
  • In the field of serial data communications, the quality of a serial digital bitstream can be assessed by observing an accurate visual representation of the amplitude of the signal with respect to time. This can be performed by a traditional oscilloscope, or a dedicated electrical circuit designed specifically to look at serial bitstream signals.
  • When observing such a visual representation, the shape of the bitstream signal can resemble the general shape of the human eye; for this reason, the images created by circuits designed to look at serial bitstream signals are sometimes referred to as ‘Eye Patterns’.
  • An eye pattern displays various parameters by which the quality of a serial data signal is quantified such as: rise time, fall time, undershoot, overshoot, jitter, pulse width, amplitude, and distortion, and the variation in those parameters.
  • Eye patterns are often created using either a very high-speed analog-to-digital converter (ADC) or sample-and-hold integrated circuits (ICs), but now there are various ICs that incorporate serial receivers with this eye pattern ability built-in. For example, this ability may be found in:
      • Transceiver/Reclocker ICs
      • High-speed transceivers embedded in Field Programmable Gate Arrays (FPGAs)
      • Equaliser ICs
  • These circuits, however, require the signal to be of sufficient quality for the serial receiver to successfully lock onto the signal and recover the clock needed to produce eye pattern data. Using these circuits to generate an eye pattern at the receiver end of a transmission line can therefore be problematic as signals are typically degraded in transmission by cable losses. Signal-conditioning circuits can be used to improve the signal quality up to a level at which it becomes possible to produce an eye pattern but the pattern so produced shows the quality of the conditioned signal, not the raw signal quality.
  • Another limitation is that these serial receivers have a minimum operating frequency which can be above the data rate of some serial data streams: e.g. Standard definition SDI.
  • SUMMARY OF THE INVENTION
  • Our invention enables an eye pattern to be generated where the signal quality or signal frequency is not sufficient for an eye capable transceiver to lock onto, by the novel idea of using the slave/free-running mode of the transceiver to sample the unadulterated signal at the actual data rate. It achieves this by splitting the incoming signal, equalising one of the split signals and recovering a clock signal from the equalized signal. In this way, our invention allows a realistic eye pattern to be obtained for the unequalized signal, regardless of the quality of that unequalized signal.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Our invention provides a way to produce an eye pattern using the eye-pattern capability of a serial receiver where the signal of interest is of insufficient quality for the serial receiver's built-in eye pattern capability. It uses a signal splitter to generate two copies of the serial data signal, one of which is conditioned as required then fed to a “master” serial receiver that locks onto the input signal and recovers a serial clock. The other copy of the signal is fed to a “slave” serial receiver with embedded eye pattern capability which is set to “free-run” i.e. it does not attempt to lock onto its serial data input. Instead, the clock generated by the master serial receiver is used to the slave serial receiver, enabling it to produce the eye pattern of the unconditioned signal.
  • The conditioning applied could consist of amplification, filtering or cable equalisation. The serial receivers used may be located either in the same integrated circuit or in separate ICs, depending on the data rate of the signal and the operating characteristics of the ICs.
  • FIGS. 1, 2 and 3 illustrate three possible implementations of the invention. FIG. 1 illustrates an implementation that can be used where the data rate of the serial data signal is within the operating frequency range of the eye-capable serial receiver.
  • FIG. 2 illustrates the alternative style of implementation that needs to be used where the IC's minimum operating frequency is higher than the data rate of the serial data signal.
  • FIG. 3 illustrates how the same basic arrangement may be used to extract eye pattern data from an unrelated serial data signal.
  • In FIG. 1, the serial data signal is split into two identical copies by the signal splitter 1 and one copy is then conditioned by the signal conditioning unit 2 prior to being passed to the master serial receiver 3 which recovers the serial clock 4. The other copy is passed to the slave serial receiver 5. The clock signal extracted from the serial data signal by the master serial receiver 3 is used to clock the slave serial receiver 5, thereby allowing it to generate the required eye pattern.
  • In FIG. 2, the data signal is already of sufficient quality but its speed is below the capability of the eye-capable serial receiver 5. In these circumstances, the master serial receiver 3 in FIG. 1 by a serial receiver 6 that has the appropriate characteristics for extracting the required clock, but which may not have embedded eye capability itself. In FIG. 3, the signals to be presented to serial receivers 3 and 5 are independent. This arrangement may be used to assess the degree to which two serial data signals are synchronised.

Claims (6)

1. Eye pattern generating apparatus comprising:
a serial data stream signal splitter which generates two or more output versions of its input serial data stream
and a signal conditioning circuit applied to the serial data stream derived from the first output of the serial data stream signal splitter to produce a conditioned signal
and a “master” serial receiver or any clock recovery device to recover a clock from the conditioned signal
and a “slave” serial receiver with integrated eye pattern capability which derives its timing reference from the clock recovered by the “master” serial receiver or clock recovery device and the “slave” serial receiver produces eye pattern data from a non-conditioned signal which is derived from the second output of the serial data stream signal splitter.
2. Eye pattern generating apparatus comprising:
a serial data stream signal splitter which generates two or more output versions of its input serial data stream
and a “master” serial receiver or any clock recovery device to recover a clock from the first output of the serial data stream signal splitter
and a “slave” serial receiver with integrated eye pattern capability which derives its timing reference from the clock recovered by the “master” serial receiver or clock recovery device and the “slave” serial receiver produces eye pattern data from the second output of the serial data stream signal splitter.
3. Eye pattern generating apparatus comprising:
a “master” serial receiver or any clock recovery device used to recover a clock from a serial data signal
and a “slave” serial receiver with integrated eye pattern capability which derives its timing reference from the clock recovered by the “master” serial receiver or clock recovery device and the “slave” serial receiver produces eye pattern data from a second serial data signal.
4. The apparatus of claim 1 where eye pattern data is taken from both the “master” serial receiver or clock recovery device and the “slave” serial receiver and a comparison made to determine the effect of the signal conditioning circuit on the quality of the signal presented to the “master” serial receiver or clock recovery device.
5. The apparatus of claim 1 where eye pattern data is taken from both the “master” serial receiver or clock recovery device and the “slave” serial receiver and a comparison made to determine the effect of the signal conditioning circuit on the delay and phase of the signal presented to the “master” serial receiver or clock recovery device.
6. The apparatus of claim 3 where eye pattern data is taken from both the “master” serial receiver or clock recovery device and the “slave” serial receiver and a comparison made to determine the similarities and differences between two serial data signals.
US13/947,134 2012-08-17 2013-07-22 Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability Abandoned US20140133614A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB1214668.4 2012-08-17
GB1214668.4A GB2504989B (en) 2012-08-17 2012-08-17 Eye pattern generating apparatus

Publications (1)

Publication Number Publication Date
US20140133614A1 true US20140133614A1 (en) 2014-05-15

Family

ID=47016912

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/947,134 Abandoned US20140133614A1 (en) 2012-08-17 2013-07-22 Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability

Country Status (2)

Country Link
US (1) US20140133614A1 (en)
GB (1) GB2504989B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105929214A (en) * 2016-04-14 2016-09-07 烽火通信科技股份有限公司 Triggering signal generation device and method for high-speed optical eye diagram observation
US9590774B1 (en) 2015-09-25 2017-03-07 Microsoft Technology Licensing, Llc Circuit for introducing signal jitter
US11196559B2 (en) * 2018-08-08 2021-12-07 International Business Machines Corporation Secure communication using multichannel noise
WO2022160309A1 (en) * 2021-01-30 2022-08-04 华为技术有限公司 Receiver, electronic device, and eye diagram testing method for receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070121714A1 (en) * 2005-11-14 2007-05-31 Baker Daniel G Flexible timebase for EYE diagram

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621861B1 (en) * 2002-02-06 2003-09-16 Ciena Corporation System to optimize signal detection
US7460589B2 (en) * 2002-10-08 2008-12-02 Broadcom Corporation Eye monitoring and reconstruction using CDR and sub-sampling ADC
KR100795724B1 (en) * 2005-08-24 2008-01-17 삼성전자주식회사 Circuit for measuring eye size, receiver for data communication system, method of measuring the eye size
US8761325B2 (en) * 2010-06-28 2014-06-24 Ben WILLCOCKS Digital receivers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070121714A1 (en) * 2005-11-14 2007-05-31 Baker Daniel G Flexible timebase for EYE diagram

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9590774B1 (en) 2015-09-25 2017-03-07 Microsoft Technology Licensing, Llc Circuit for introducing signal jitter
CN105929214A (en) * 2016-04-14 2016-09-07 烽火通信科技股份有限公司 Triggering signal generation device and method for high-speed optical eye diagram observation
US11196559B2 (en) * 2018-08-08 2021-12-07 International Business Machines Corporation Secure communication using multichannel noise
WO2022160309A1 (en) * 2021-01-30 2022-08-04 华为技术有限公司 Receiver, electronic device, and eye diagram testing method for receiver

Also Published As

Publication number Publication date
GB201214668D0 (en) 2012-10-03
GB2504989B (en) 2019-11-06
GB2504989A (en) 2014-02-19

Similar Documents

Publication Publication Date Title
US20140133614A1 (en) Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability
RU2015134388A (en) BINAURAL AUDIO PROCESSING
EP3043477A3 (en) Apparatus and methods for clock and data recovery
WO2016130360A8 (en) Circuits for and methods of filtering inter-symbol interference for serdes applications
US8526551B2 (en) Multiple-input, on-chip oscilloscope
SG10201402576SA (en) Test Apparatus and Test Method based on DFDAU
TW200816725A (en) Parameter scanning for signal over-sampling
JP6846120B2 (en) Clock recovery devices and methods and programs for executing clock recovery methods
US20120033685A1 (en) Serial link voltage margin determination in mission mode
EP2833552A3 (en) Apparatus and methods for on-die instrumentation
MX2020011705A (en) Receiving device and data processing method.
US8855179B1 (en) Measuring impairments of digitized signals in data and timing recovery circuits
CN115706687A (en) For tapping accelerated TDECQ and machine learning of other measurements
CN110749763A (en) Triggering method based on I2S signal and oscilloscope
CN107770107B (en) Test and measurement system and method for employing DFE in test and measurement system
ATE546003T1 (en) APPARATUS AND METHOD FOR RECEIVING ORTHOGONAL FREQUENCY MULTIPLEX SIGNALS
US11018964B2 (en) Selective extraction of network link training information
WO2016046696A3 (en) Digital mri receiver coil with built-in received phase noise indicator
JP2016515321A (en) Method and apparatus for data assisted timing recovery in 10GBASE-T system
EP3072249B1 (en) Data serializer
KR101210686B1 (en) Receiving equalization device in communication system and receiving equalization method
US9467278B2 (en) Methods and apparatus for trimming of CDR clock buffer using phase shift of transmit data
DE502008001261D1 (en) PROCESS FOR GENERATING A CLOCK FREQUENCY
JP6043837B2 (en) Method for synchronizing OFDM symbols
Jin-ling et al. Stationary Wavelet Transform and New Threshold Function Used in ECG Signal Denoising

Legal Events

Date Code Title Description
AS Assignment

Owner name: IMAGE PROCESSING TECHNIQUES LIMITED, UNITED KINGDO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUNTLEY, ALEXANDER NEIL;FAWCETT, ROGER;REEL/FRAME:034168/0417

Effective date: 20141030

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMAGE PROCESSING TECHNIQUES LIMITED;REEL/FRAME:050093/0640

Effective date: 20190819

AS Assignment

Owner name: ALTERA CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:066353/0886

Effective date: 20231219