US20140106696A1 - Dynamic bandwidth control scheme of a frac-n pll in a receiver - Google Patents

Dynamic bandwidth control scheme of a frac-n pll in a receiver Download PDF

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Publication number
US20140106696A1
US20140106696A1 US13/943,701 US201313943701A US2014106696A1 US 20140106696 A1 US20140106696 A1 US 20140106696A1 US 201313943701 A US201313943701 A US 201313943701A US 2014106696 A1 US2014106696 A1 US 2014106696A1
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signal
control loop
bandwidth
receiver
blocker
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US13/943,701
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Sheng Ye
Paul Chominsky
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MaxLinear Inc
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MaxLinear Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Definitions

  • the present invention relates to communication systems, and more particularly to minimizing the effect of blocker signals in such systems.
  • Controlling the bandwidth of a PLL in conventional systems is often achieved by ensuring that the PLL has acceptable in-band as well as out-of-band phase/noise performance characteristics.
  • Such a PLL typically consumes a relatively large semiconductor area and/or power.
  • a receiver in accordance with one embodiment of the present invention, includes, in part, a mixer, a filter, a received signal strength indicator, and a control loop.
  • the mixer is adapted to convert the frequency of a received signal.
  • the filter is adapted to filter out undesired noise that may be present in the output signal of the mixer.
  • the received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and to generate a feedback signal in response.
  • the control loop is adapted to vary its bandwidth in response to an output signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer.
  • the control loop is adapted to have a first bandwidth in response to detection of the blocker, and a second bandwidth in response to absence of detection of the blocker signal.
  • the received signal strength indicator detects the blocker signal if the blocker signal is detected as having a strength greater than a predefined threshold value. The received signal strength indicator does not detect the blocker signal if the blocker signal is not detected as having a strength greater than the predefined threshold value.
  • the receiver is a wireless receiver.
  • the bandwidth of the control loop is varied by varying a current supplied to the control loop.
  • the control loop is a phase-locked loop.
  • the control is a delay-locked loop.
  • the control loop is a frequency-locked loop.
  • a method of controlling the bandwidth of a control loop includes in part, setting a feedback signal to a first state if the received signal is detected as having a strength greater than a first predefined threshold value, setting the feedback signal to a second state if the received signal is detected as not having a strength greater than the first predefined threshold value, and varying the bandwidth of the control loop in response to the feedback signal.
  • the method further includes, in part, using an output signal of the control loop to control a conversion frequency of the received signal. In one embodiment, the method further includes filtering the frequency converted signal.
  • the control loop is a phase-locked loop, a delay-locked loop, or a frequency-locked loop. In one embodiment, the signal is received wirelessly. In one embodiment, the bandwidth of the control loop is varied by varying a current supplied to the control loop.
  • FIG. 1 is a block diagram of a receiver adapted to dynamically control the bandwidth of the phase-locked loop disposed therein, in accordance with one embodiment of the present invention.
  • FIG. 2 shows plots of exemplary noise characteristic and bandwidth of a phase-locked loop in response to presence or absence of blocker signal, in accordance with one embodiment of the present invention.
  • FIG. 3 is an exemplary block diagram of a phase-locked loop whose bandwidth is dynamically controlled, in accordance with one embodiment of the present invention.
  • FIG. 1 is a block diagram of a receiver 100 adapted to dynamically control the bandwidth of the phase-locked loop (PLL) disposed therein so as to minimize the out-of-band phase noise of the local oscillator (LO) signal generated by the PLL, in accordance with one embodiment of the present invention.
  • Receiver 100 is shown as including, in part, a low-noise amplifier 102 , a mixer 104 , a low-pass filter 106 , a received signal strength indicator (RSSI) 108 , and a Frac-N PLL 110 .
  • RSSI received signal strength indicator
  • Low-noise amplifier (LNA) 102 amplifies the incoming signal it receives from antenna 150 and supplies the amplified signal to mixer 104 , which in response, converts the frequency of the signal it receives.
  • Low-pass filter 106 is adapted to filter out undesired signals that may be present in the output signal of mixer 104 .
  • RSSI 108 is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of low-pass filter 106 and supply a signal to frac-N PLL 110 accordingly.
  • frac-N PLL (alternatively referred to herein as PLL) 110 provides a local oscillator (LO) signal to mixer 104 which mixer 104 uses to convert the frequency of the signal it receives from LNA 102 .
  • LO local oscillator
  • the bandwidth of PLL 110 is dynamically controlled in response to the output signal of RSSI 108 .
  • RSSI 108 monitors the strength of any blocker signal that may be present in the output signal of low-pass filter 106 . If the blocker signal detected by RSSI 108 has a strength greater than a predefined threshold value, the output signal P of RSSI 108 is set to a first logic level (e.g., low logic level). Conversely, if the blocker signal detected by RSSI 108 has a strength smaller than or equal to a predefined threshold value, the output signal P of RSSI 108 is set to a second, complementary logic level (e.g., high logic level). Signal P is a feedback signal that is used to control the bandwidth of PLL 110 .
  • a first logic level e.g., low logic level
  • a second, complementary logic level e.g., high logic level
  • PLL 110 's bandwidth is reduced so as to minimize the out-of-band noise of the LO signal supplied by PLL 110 to mixer 104 .
  • PLL 110 's bandwidth is increased, thereby causing a decrease in the in-band noise of the LO signal supplied by PLL 110 to mixer 104 .
  • Plot 210 of FIG. 2 shows an exemplary noise characteristic of PLL 110 when no blocker signal has been detected by RSSI 108 , thereby causing the PLL to have a wider bandwidth.
  • Plot 220 of FIG. 2 shows the noise characteristic of PLL 110 when RSSI 108 detects a blocker signal, thereby causing the PLL to have a narrower bandwidth.
  • FIG. 3 is a block diagram of an exemplary embodiment of PLL 110 .
  • PLL 110 is shown as including a phase/frequency detector 170 , a charge pump 172 , a low-pass filter 174 , a voltage controlled oscillator (VCO) 178 , and a divider 178 .
  • Signal P generated by RSSI 108 (see FIG. 1 ) is shown as being applied to charge pump 172 to control the amount of current that charge pump 172 supplies.
  • a first current level I 1 is supplied to charge pump 172 .
  • PLL 110 is programmable to have two bandwidths.
  • both currents I 1 and I 2 are delivered to charge pump 172 , thereby causing PLL 110 to have a relatively higher bandwidth, as shown, for example, in plot 220 of FIG. 2 .
  • only current I 1 is delivered to charge pump 172 , thereby causing PLL 110 to have a relatively lower bandwidth, as shown, for example, in plot 210 of FIG. 2 .
  • the dynamic control of the PLL bandwidth meets the signal-to-noise ratio (SNR) of the receiver when the desired signal is strong and no blocker signal is detected, and further when an enhanced total phase noise from the local oscillator is required. Furthermore, the dynamic control of the PLL achieves low out-of-band phase noise requirement when a blocker signal is detected. The dynamic control of the PLL also relaxes the PLL design constraints.
  • SNR signal-to-noise ratio

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

A receiver includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired signals that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to the feedback signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application is a continuation application of U.S. patent application Ser. No. 12/944,521 filed Nov. 11, 2010, which claims benefit under 35 USC 119(e) of U.S. Provisional Appln. No. 61/260,312 filed Nov. 11, 2009, entitled “Dynamic Bandwidth Control Scheme Of A Frac-N PLL In A Receiver,” the contents of which are incorporated herein by reference in their entirety.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to communication systems, and more particularly to minimizing the effect of blocker signals in such systems.
  • Controlling the bandwidth of a PLL in conventional systems is often achieved by ensuring that the PLL has acceptable in-band as well as out-of-band phase/noise performance characteristics. Such a PLL typically consumes a relatively large semiconductor area and/or power.
    • BRIEF SUMMARY OF THE INVENTION
  • A receiver, in accordance with one embodiment of the present invention, includes, in part, a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired noise that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and to generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to an output signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer.
  • In one embodiment, the control loop is adapted to have a first bandwidth in response to detection of the blocker, and a second bandwidth in response to absence of detection of the blocker signal. In one embodiment, the received signal strength indicator detects the blocker signal if the blocker signal is detected as having a strength greater than a predefined threshold value. The received signal strength indicator does not detect the blocker signal if the blocker signal is not detected as having a strength greater than the predefined threshold value. In one embodiment, the receiver is a wireless receiver. In one embodiment, the bandwidth of the control loop is varied by varying a current supplied to the control loop. In one embodiment, the control loop is a phase-locked loop. In another embodiment, the control is a delay-locked loop. In yet another embodiment, the control loop is a frequency-locked loop.
  • A method of controlling the bandwidth of a control loop, in accordance with one embodiment of the present invention, includes in part, setting a feedback signal to a first state if the received signal is detected as having a strength greater than a first predefined threshold value, setting the feedback signal to a second state if the received signal is detected as not having a strength greater than the first predefined threshold value, and varying the bandwidth of the control loop in response to the feedback signal.
  • In one embodiment, the method further includes, in part, using an output signal of the control loop to control a conversion frequency of the received signal. In one embodiment, the method further includes filtering the frequency converted signal. In one embodiment, the control loop is a phase-locked loop, a delay-locked loop, or a frequency-locked loop. In one embodiment, the signal is received wirelessly. In one embodiment, the bandwidth of the control loop is varied by varying a current supplied to the control loop.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram of a receiver adapted to dynamically control the bandwidth of the phase-locked loop disposed therein, in accordance with one embodiment of the present invention.
  • FIG. 2 shows plots of exemplary noise characteristic and bandwidth of a phase-locked loop in response to presence or absence of blocker signal, in accordance with one embodiment of the present invention.
  • FIG. 3 is an exemplary block diagram of a phase-locked loop whose bandwidth is dynamically controlled, in accordance with one embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 is a block diagram of a receiver 100 adapted to dynamically control the bandwidth of the phase-locked loop (PLL) disposed therein so as to minimize the out-of-band phase noise of the local oscillator (LO) signal generated by the PLL, in accordance with one embodiment of the present invention. Receiver 100 is shown as including, in part, a low-noise amplifier 102, a mixer 104, a low-pass filter 106, a received signal strength indicator (RSSI) 108, and a Frac-N PLL 110. Although the following description of the embodiments of the present invention is described with respect to a phase-locked loop, it is understood that the embodiments of the present invention are applicable to any other control loop disposed in a receiver, such as a delay-locked loop, frequency- locked loop, and the like.
  • Low-noise amplifier (LNA) 102 amplifies the incoming signal it receives from antenna 150 and supplies the amplified signal to mixer 104, which in response, converts the frequency of the signal it receives. Low-pass filter 106 is adapted to filter out undesired signals that may be present in the output signal of mixer 104. RSSI 108 is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of low-pass filter 106 and supply a signal to frac-N PLL 110 accordingly. In response, frac-N PLL (alternatively referred to herein as PLL) 110 provides a local oscillator (LO) signal to mixer 104 which mixer 104 uses to convert the frequency of the signal it receives from LNA 102. As described further below, in accordance with embodiments of the present invention, the bandwidth of PLL 110 is dynamically controlled in response to the output signal of RSSI 108.
  • During operation, RSSI 108 monitors the strength of any blocker signal that may be present in the output signal of low-pass filter 106. If the blocker signal detected by RSSI 108 has a strength greater than a predefined threshold value, the output signal P of RSSI 108 is set to a first logic level (e.g., low logic level). Conversely, if the blocker signal detected by RSSI 108 has a strength smaller than or equal to a predefined threshold value, the output signal P of RSSI 108 is set to a second, complementary logic level (e.g., high logic level). Signal P is a feedback signal that is used to control the bandwidth of PLL 110. In response to the first logic level of signal P, i.e., in response to detecting that the blocker signal has a value higher than the predefined threshold value, PLL 110's bandwidth is reduced so as to minimize the out-of-band noise of the LO signal supplied by PLL 110 to mixer 104. In response to the second logic level of signal P, i.e., in response to detecting that the blocker signal has a value lower than or equal to the predefined threshold value, which in turn indicates that the desired signal has a sufficiently strong value relative to the blocker signal, PLL 110's bandwidth is increased, thereby causing a decrease in the in-band noise of the LO signal supplied by PLL 110 to mixer 104.
  • Plot 210 of FIG. 2 shows an exemplary noise characteristic of PLL 110 when no blocker signal has been detected by RSSI 108, thereby causing the PLL to have a wider bandwidth. Plot 220 of FIG. 2 shows the noise characteristic of PLL 110 when RSSI 108 detects a blocker signal, thereby causing the PLL to have a narrower bandwidth.
  • FIG. 3 is a block diagram of an exemplary embodiment of PLL 110. PLL 110 is shown as including a phase/frequency detector 170, a charge pump 172, a low-pass filter 174, a voltage controlled oscillator (VCO) 178, and a divider 178. Signal P generated by RSSI 108 (see FIG. 1) is shown as being applied to charge pump 172 to control the amount of current that charge pump 172 supplies. When a blocker signal is detected and signal P is placed in the first logic state, a first current level I1 is supplied to charge pump 172. When a blocker signal is not detected and signal P is placed in the second logic state, a second current level defined by the sum of currents I1 and I2 is supplied to charge pump 172. To achieve this, switch S is closed in response to the second logic state of signal P to enable current I2 to also be supplied to the charge pump. Accordingly, PLL 110 is programmable to have two bandwidths. When a blocker signal is not detected, both currents I1 and I2 are delivered to charge pump 172, thereby causing PLL 110 to have a relatively higher bandwidth, as shown, for example, in plot 220 of FIG. 2. When a blocker signal is detected, only current I1 is delivered to charge pump 172, thereby causing PLL 110 to have a relatively lower bandwidth, as shown, for example, in plot 210 of FIG. 2.
  • In accordance with embodiments of the present invention and as described above, the dynamic control of the PLL bandwidth meets the signal-to-noise ratio (SNR) of the receiver when the desired signal is strong and no blocker signal is detected, and further when an enhanced total phase noise from the local oscillator is required. Furthermore, the dynamic control of the PLL achieves low out-of-band phase noise requirement when a blocker signal is detected. The dynamic control of the PLL also relaxes the PLL design constraints.
  • The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. Other additions, subtractions or modifications are obvious in view of the present invention and are intended to fall within the scope of the appended claims.

Claims (12)

What is claimed is:
1. A receiver comprising:
a mixer;
a filter responsive to the mixer;
a received signal strength indicator (RSSI) adapted to detect one or more blocker signals; and
a control loop adapted to vary its bandwidth in response to an output signal of the RSSI, said control loop supplying an oscillating signal to said mixer.
2. The receiver of claim 1 wherein said control loop is adapted to have a first bandwidth in response to detection of the blocker signal by the RSSI, and a second bandwidth in response to no detection of the blocker signal by the RSSI.
3. The receiver of claim 1 wherein said RSSI detects the blocker signal if the blocker signal is detected as having a strength greater than a predefined threshold value, and wherein said RSSI does not detect the blocker signal if the blocker signal is not detected as having a strength greater than the predefined threshold value
4. The receiver of claim 1 wherein said receiver is a wireless receiver.
5. The receiver of claim 1 wherein the bandwidth of the control loop is varied by varying a current supplied to a charge pump disposed in the control loop.
6. The receiver of claim 1 wherein said control loop is selected from a group consisting of a phased-locked loop and a delay-locked loop.
7. A method of controlling a bandwidth of a control loop, the method comprising:
setting a feedback signal to a first state if the received signal is detected as having a strength greater than a first predefined threshold value;
setting the feedback signal to a second state if the received signal is detected as not having a strength greater than the first predefined threshold value; and
varying a bandwidth of a control loop in response to the feedback signal.
8. The method of claim 7 further comprising:
using an output signal of the control loop to control a conversion frequency of the received signal.
9. The method of claim 8 further comprising:
filtering the frequency converted signal.
10. The method of claim 8 wherein said control loop is a phase-locked loop.
11. The method of claim 8 wherein said received signal is received wirelessly.
12. The method of claim 8 further comprising:
varying a bandwidth of a control loop in response to the feedback signal by varying a current supplied to the control loop.
US13/943,701 2009-11-11 2013-07-16 Dynamic bandwidth control scheme of a frac-n pll in a receiver Abandoned US20140106696A1 (en)

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US26031209P 2009-11-11 2009-11-11
US12/944,521 US8515375B2 (en) 2009-11-11 2010-11-11 Dynamic bandwidth control scheme of a Frac-N PLL in a receiver
US13/943,701 US20140106696A1 (en) 2009-11-11 2013-07-16 Dynamic bandwidth control scheme of a frac-n pll in a receiver

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WO2011060198A1 (en) 2009-11-11 2011-05-19 Maxlinear, Inc. Crystal control scheme to improve preformance of a receiver
US9246436B2 (en) * 2012-07-16 2016-01-26 Linear Technology Corporation Low power radio receiver
US8862087B2 (en) * 2013-02-19 2014-10-14 Broadcom Corporation Reciprocal mixing noise cancellation in the presence of a modulated blocker
KR101929242B1 (en) * 2013-07-03 2018-12-17 삼성전자주식회사 Super-regenerative receiving method and super-regenerative receiver circuit with high frequency-selectivity
JP5646018B1 (en) * 2013-08-07 2014-12-24 三菱電機株式会社 Installation location development support method, terminal device, installation location development support system, and program
US9148186B1 (en) * 2014-04-08 2015-09-29 Broadcom Corporation Highly linear receiver front-end with thermal and phase noise cancellation
WO2019140698A1 (en) * 2018-01-22 2019-07-25 海能达通信股份有限公司 Method and device for controlling bandwidth of loop filter

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US5422911A (en) 1993-09-17 1995-06-06 Motorola, Inc. Frequency walled phase lock loop
CA2467201A1 (en) * 2004-05-13 2005-11-13 Sirific Wireless Corporation Dynamic and static spurious correction and control
US7532160B1 (en) 2004-07-30 2009-05-12 Novariant, Inc. Distributed radio frequency ranging signal receiver for navigation or position determination
US8243864B2 (en) 2004-11-19 2012-08-14 Qualcomm, Incorporated Noise reduction filtering in a wireless communication system
US8295371B2 (en) * 2006-07-14 2012-10-23 Qualcomm Incorporated Multi-carrier receiver for wireless communication
US8437721B2 (en) * 2009-04-26 2013-05-07 Qualcomm Incorporated Jammer detection based adaptive PLL bandwidth adjustment in FM receiver

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