US20140103386A1 - Light emitting diode package and method of manufacturing the same - Google Patents
Light emitting diode package and method of manufacturing the same Download PDFInfo
- Publication number
- US20140103386A1 US20140103386A1 US14/106,446 US201314106446A US2014103386A1 US 20140103386 A1 US20140103386 A1 US 20140103386A1 US 201314106446 A US201314106446 A US 201314106446A US 2014103386 A1 US2014103386 A1 US 2014103386A1
- Authority
- US
- United States
- Prior art keywords
- metal
- led chip
- led
- metal substrate
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 218
- 239000002184 metal Substances 0.000 claims abstract description 218
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 238000000034 method Methods 0.000 description 37
- 230000017525 heat dissipation Effects 0.000 description 16
- 238000000465 moulding Methods 0.000 description 15
- 229910052782 aluminium Inorganic materials 0.000 description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 14
- 238000007743 anodising Methods 0.000 description 13
- 230000008901 benefit Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229920006336 epoxy molding compound Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 229910052593 corundum Inorganic materials 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000012811 non-conductive material Substances 0.000 description 2
- 150000007524 organic acids Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
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- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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Definitions
- the present invention relates to a light emitting diode (LED) package and a method of manufacturing the same.
- LED light emitting diode
- an LED is widely used as a light source because it has a number of advantages such as low power consumption and high brightness.
- the LED is being adopted as a backlight unit for lighting devices and liquid crystal displays (LCD).
- LED is provided in the form of package which is easily mounted on various devices such as a lighting device and so on.
- An LED package should not only protect the LED and have a connection structure with devices, but also should have a heat dissipation function for dissipating heat generated from the LED.
- the heat dissipation performance is a package condition which is considered to be important in backlight units for lighting device and LCD, which require a high-power LED.
- the performance and lifespan of the LED in the LED package may exponentially decrease, as the operation temperature thereof increases.
- the package may discolor. Therefore, the heat generated from the LED should be dissipated so that the operation temperature should be optimally maintained.
- An advantage of the present invention is that it provides an LED package in which an anodizing process is performed on an aluminum substrate having via holes formed therein so as to enhance heat dissipation performance and optical characteristic of the LED package, and a high-power LED chip as well as a low-power LED chip can be used.
- Another advantage of the invention is that it provides a method of manufacturing an LED package.
- an LED package comprises a metal substrate that has one or more via holes formed therein; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and an LED chip that is mounted on a metal pattern among the plurality of metal patterns.
- the metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the top surface of the metal substrate which is exposed by partially removing the insulating layer.
- any one of the metal patterns formed at the bottom surface of the metal substrate may be formed on the bottom surface of the metal substrate which is exposed by partially removing the insulating layer.
- the LED package may further include a wire that connects the LED chip to a metal pattern on which the LED chip is not mounted.
- the LED chip may be a vertical LED chip.
- the LED package may further include a first wire that electrically connects the LED chip to a metal pattern on which the LED chip is not mounted; and a second wire that electrically connects the LED chip to the metal pattern having the LED chip mounted thereon.
- the LED package may further include first and second wires that electrically connect the LED chip to the metal patterns on which the LED chip is not mounted.
- the metal pattern connected to the first or second wire may be formed on the top surface of the metal substrate which is exposed by partially removing the insulating layer.
- the metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the top surface of a cavity formed by partially removing the insulating layer and the metal substrate.
- the LED package may further include a molding portion that covers the LED chip.
- the molding portion may be composed of any one selected from the group consisting of silicon resin, epoxy resin, and epoxy molding compound (EMC).
- the molding portion may be formed by any one of an injection molding method, a transfer molding method, and a pin gate molding method, and may have a trapezoid, rectangular, or hemispherical cross-sectional shape.
- the metal substrate may be composed of aluminum.
- the insulating layer may be formed through an anodizing process.
- the anodizing process may be performed using any one of organic acid, sulfuric acid, and mixed acid thereof.
- a method of manufacturing an LED package comprises forming a plurality of via holes passing through a metal substrate; forming an insulating layer on a surface of the metal substrate including inner surfaces of the via holes; partially exposing the top and bottom surfaces of the metal substrate by partially removing the insulating layer; forming a metal layer on the insulating layer including the exposed portions of the metal substrate; patterning the metal layer so as to form a plurality of metal patterns on the exposed portions of the metal substrate and the insulating layer, the metal patterns being electrically isolated from one another; mounting LED chips on some metal patterns among the plurality of metal patterns; and dicing the metal substrate such that each of the diced substrates includes one LED chip and one or more via holes.
- the LED chips may be mounted on the metal patterns formed on the exposed top surface of the metal substrate.
- the method may further comprise forming wires which electrically connects the LED chips to the metal patterns; and forming molding portions which covers the LED chips and the wires, after the mounting of the LED chips.
- the method may further comprise forming a cavity with a predetermined depth by etching the exposed top surface of the metal substrate, after the exposing of the top and bottom surfaces of the metal substrate.
- the dicing of the metal substrate may be performed using a dicing blade or cutting mold.
- an LED package comprises a metal substrate that has two or more via holes; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and an LED chip that is mounted on one metal pattern among the plurality of metal patterns.
- the metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the top surface of the metal substrate which is exposed by partially removing the insulating layer.
- the metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the bottom surface of a cavity formed by partially removing the insulating layer and the metal substrate.
- the LED package may further comprise a wire that electrically connects the LED chip to a metal pattern on which the LED chip is not mounted.
- the LED chip may be a vertical LED chip.
- the LED package may further comprise first and second wires that electrically connect the LED chip to the metal patterns on which the LED chip is not mounted.
- the LED chip may be a horizontal LED chip.
- the LED chip may have a pair of connection elements formed on the bottom surface thereof, the connection elements being electrically connected to the metal patterns, respectively, which are electrically isolated from each other.
- the LED package may further comprise a molding portion that covers the LED chip.
- the metal substrate may have a cavity with a predetermined depth which is provided at a position where the LED chip is mounted.
- a method of manufacturing an LED chip comprises forming a plurality of via holes passing through a metal substrate; forming an insulating layer on a surface of the metal substrate including inner surfaces of the via holes; forming a metal layer on the insulating layer; patterning the metal layer so as to form a plurality of metal patterns which are electrically isolated from one another; mounting LED chips on some metal patterns among the plurality of metal patterns; and dicing the metal substrate such that each of the diced substrates includes one LED chip and two or more via holes.
- the method may further comprise forming wires which electrically connects the LED chips to the metal patterns on which the LED chips are not formed; and forming molding portions which covers the LED chips and the wires, after the mounting of the LED chips.
- FIGS. 1 and 2 are cross-sectional views of an LED package according to a first embodiment of the invention
- FIGS. 3 and 4 are cross-sectional views showing an example where a horizontal LED chip is mounted on the LED package according to the first embodiment of the invention
- FIG. 5 is a cross-sectional view of an LED package according to a modification of the first embodiment of the invention.
- FIGS. 6 to 12 are process diagrams sequentially showing a method of manufacturing an LED package according to the first embodiment of the invention.
- FIG. 13 is a cross-sectional view of an LED package according to a second embodiment of the invention.
- FIGS. 14 to 18 are cross-sectional views of LED packages according to modifications of the second embodiment of the invention.
- FIG. 19 is a cross-sectional view showing an example where a horizontal LED chip is mounted on the LED package according to the second embodiment of the invention.
- FIG. 20 is a cross-sectional view showing an example where a flip-chip LED chip is mounted on the LED package according to the second embodiment of the invention.
- FIGS. 21 to 26 are process diagrams sequentially showing a method of manufacturing an LED package according to the second embodiment of the invention.
- FIGS. 1 to 4 an LED package according to a first embodiment of the invention will be described.
- FIGS. 1 and 2 are cross-sectional views of an LED package according to a first embodiment of the invention.
- the LED package according to the first embodiment of the invention includes a metal substrate 100 having one or more via holes 110 formed therein, an insulating layer 120 which is formed on the surface of the metal substrate 100 including the inner surface of the Via hole 110 , a plurality of metal patterns 130 which are formed on the insulating layer 120 and are electrically isolated from each other, and an LED chip 140 mounted on a metal pattern 130 among the plurality of metal patterns 130 .
- the metal substrate 100 may be formed of metal with excellent heat conductivity, such as aluminum (Al).
- the insulating layer 120 which is an oxide film layer (Al 2 O 3 ), may be formed on the metal substrate 100 composed of aluminum through an anodizing process.
- the anodizing process may be performed using organic acid, sulfuric acid, or mixed acid thereof.
- Aluminum is a metallic material which can be obtained at a relatively low price, and has excellent heat conductivity. Further, the oxide film layer (Al 2 O 3 ) obtained through the anodizing process also has relatively high heat conductivity of 10-30 W/mK, and can be formed with a small thickness, thereby implementing low thermal resistance.
- the metallic substrate 100 exhibits more excellent heat dissipation performance than the conventional substrate formed of copper or ceramic.
- the anodizing process for anodizing aluminum is a relatively simple process, and the process cost and time thereof are relatively low and short.
- the via hole 110 may be formed by a drilling, punching, or etching process, and may serve to electrically connect the metal patterns 130 formed on the top and bottom surfaces of the metal substrate 100 .
- the via hole 100 may be completely filled up with the insulating layer 120 and the metal patterns 130 which are formed on the inner surface of the via hole 110 . As shown in FIG. 1 , however, when the insulating layer 120 and the metal patterns 130 are sequentially formed with a small thickness along the inner surface of the via hole 110 , the inside of the via hole 110 may not be filled up completely. In this case, the internal space of the via hole 110 may be filled up with a via-hole filler 135 .
- the via-hole filler 135 may be composed of a conductive material such as metal or a non-conductive material such as epoxy.
- the metal pattern 130 having the LED chip 140 mounted thereon may be formed on the top surface of the metal substrate 100 which is exposed by partially removing the insulating layer 120 .
- the LED chip 140 may be mounted on the metal pattern 130 formed on the top surface of the metal substrate 100 , as described above, but may be mounted across the metal pattern 130 formed on the top surface of the metal substrate 100 and the insulating layer 120 adjacent to the metal pattern 130 .
- the metal pattern 130 having the LED chip 140 mounted thereon is hot formed on the insulating layer 120 but is directly connected to the top surface of the metal substrate 100 , heat generated from the LED chip 140 can be effectively dissipated to the outside.
- another metal pattern 130 may be formed at a position corresponding to the metal pattern 130 having the LED chip 140 mounted thereon, and serves to effectively dissipate heat generated from the LED chip 140 .
- the metal pattern 130 which is formed on the bottom surface of the metal substrate 100 so as to correspond to the LED chip 140 , may be electrically isolated from the adjacent metal patterns 130 so as to serve as only a heat dissipation layer, as shown in FIG. 1 .
- the metal pattern 130 may extend so as to be electrically connected to an adjacent metal pattern 130 , thereby serving as both a heat dissipation layer and an electrode.
- the LED chip 140 may be a vertical LED chip.
- any one electrode (not shown) of the LED chip 140 may be electrically connected to the metal pattern 130 having the LED chip 140 mounted thereon, and another electrode (not shown) of the LED chip 140 may be electrically connected to a metal pattern 130 , where the LED chip is not mounted, through a wire 150 .
- the metal pattern 130 connected to the LED chip 140 through the wire 150 is formed so as to extend to the bottom surface of the metal substrate 100 through the via hole 110 .
- the wire 150 may be formed of gold, aluminum, or copper.
- a molding portion 160 is formed so as to cover the LED chip 140 and the wire 150 .
- the molding portion 160 may be formed in a desired shape through an injection molding, transfer molding, or pin-gate molding method using silicon resin, epoxy resin, or epoxy molding compound (EMC).
- EMC epoxy molding compound
- the molding portion 160 is formed in a hemispherical shape, as shown in FIGS. 1 and 2 . Without being limited thereto, however, the molding portion 160 may be formed in various shapes such as a trapezoid, a rectangle, and so on.
- FIGS. 3 and 4 are cross-sectional views showing an example where a horizontal LED chip is mounted on the LED package according to the first embodiment of the invention.
- a horizontal LED chip may be used as the LED chip 140 , instead of the vertical LED chip.
- any one electrode (not shown) of the horizontal LED chip 140 may be electrically connected to the metal pattern 130 , where the LED chip 140 is not mounted, through a first wire 150 a, and another electrode (not shown) thereof may be electrically connected to the metal pattern 130 having the LED chip 140 mounted thereon through a second wire 150 b.
- the second wire 150 b may not be electrically connected to the metal pattern 130 having the LED chip 140 mounted thereon, as described above, but may be electrically connected to a separate metal pattern 130 where the LED chip 140 is not mounted, as shown in FIG. 4 .
- the separate metal pattern 130 connected to the second wire 150 b may be formed on the top surface of the metal substrate 100 which is exposed by partially removing the insulating layer 120 .
- the metal pattern 130 connected to the via hole 110 and the metal substrate 100 are used as electrodes which are electrically connected to the LED chip 140 .
- Any one metal pattern 130 among the metal patterns 130 formed on the bottom surface of the metal substrate 100 may be formed on the bottom surface of the metal substrate 100 , which is exposed by partially removing the insulating layer 120 , so as to be directly connected to the metal substrate 100 .
- the metal substrate 100 formed of aluminum where the via hole 110 is formed it is possible to obtain an excellent heat dissipation effect. Therefore, a high-power LED chip with a relatively large calorific value as well as a low-power LED chip with a relatively low calorific value may be used, which makes it possible to enhance an optical characteristic of the LED package.
- the insulating layer 120 is formed on the metal substrate 100 through the anodizing process, the insulating layer 120 is integrally formed with the metal substrate 100 , which makes it possible to enhance the durability of the package.
- FIG. 5 is a cross-sectional view of an LED package according to a modification of the first embodiment of the invention.
- the metal pattern 130 having the LED chip 140 mounted thereon, among the plurality of metal patterns 130 may be formed on the top surface of a cavity 105 which is formed by partially removing the insulating layer 120 and the metal substrate 100 .
- the thickness of the metal substrate 100 under the LED chip 140 can be reduced. Therefore, since the heat dissipation path of the LED chip 140 is reduced, it is possible to further enhance the heat dissipation performance of the LED package.
- FIGS. 6 to 12 a method of manufacturing an LED package according to the first embodiment of the invention will be described.
- FIGS. 6 to 12 are process diagrams sequentially showing a method of manufacturing an LED package according to the first embodiment of the invention.
- a metal substrate 100 is prepared.
- the metal substrate 100 may be an aluminum plate which has been subjected to a process for cleaning contaminants such as organic matters existing on the surface of the aluminum plate.
- the metal substrate 100 may be formed in a square shape. Depending on the processed aluminum plate, the metal substrate 100 may be formed in various shapes such as a rectangle, a circle and so on. The thickness of the metal substrate 100 may be set to more than about 0.1 mm, in consideration of the process and the reliability of products after the process.
- the via holes 110 may be formed by a drilling, punching, or etching process.
- an insulating layer 120 is formed on the surface of the metal substrate 100 including the inner surfaces of the via holes 110 , through an anodizing process.
- the insulating layer 120 is partially removed in such a manner that the top and bottom surfaces of the metal substrate 100 are partially exposed.
- the removing of the insulating layer 120 may be performed by an etching process.
- the exposed top surface of the metal substrate 100 may be additionally etched so as to form a cavity 105 with a predetermined depth, as shown in FIG. 5 .
- FIG. 9A shows a state where the top surface of the metal substrate 100 is partially exposed
- FIG. 9B shows a state where the bottom surface of the metal substrate 100 is partially exposed.
- a metal layer 130 a is formed on the insulating layer 120 including the exposed portions of the metal substrate 100 .
- the metal layer 130 a may be formed through an electroplating method, an electroless plating method, or a metal deposition method.
- the via holes 110 may be completely filled up with the metal layer 130 a.
- the via holes 110 may be not be filled up completely.
- a process for filling up the via holes 110 with a via-hole filler 135 may be additionally performed, or may be not performed.
- the via-hole filler 135 may be composed of a conductive or non-conductive material.
- the metal layer 130 a is patterned so as to form a plurality of metal patterns 130 on the exposed portions of the top and bottom surfaces of the metal substrate 100 and the insulating layer 120 , the metal patterns 130 being electrically isolated from one another.
- LED chips 140 are mounted on the metal patterns 130 .
- the LED chips 140 may be mounted on the metal patterns 130 formed on the exposed top surface of the metal substrate 100 .
- a die bonding method may be used, in which silver paste, transparent epoxy, or solder is applied on the metal patterns 130 on which the LED chips 140 are to be mounted, and the LED chips 140 mounted on the metal patterns 130 are heat-treated at a predetermined temperature.
- a fluxless or flux eutectic bonding method may be used.
- the LED chips 140 are mounted on the metal patterns 130 which are directly connected to the top surface of the metal substrate 100 , heat generated from the LED chips 140 can be effectively dissipated to the outside through the metal substrate 100 .
- wires 150 for electrically connecting the LED chips 140 to the metal patterns 130 on which the LED chips 140 are not mounted are formed.
- molding portions 160 are formed on the metal substrate 100 so as to cover the LED chips 140 and the wires 150 .
- the metal substrate 100 is diced along a dicing line so as to manufacture a plurality of unit LED packages.
- the unit LED package includes one LED chip 140 and one or more via holes 110 .
- a dicing blade or a cutting mold may be used.
- FIGS. 13 to 20 an LED package according to a second embodiment of the invention will be described.
- the duplicated descriptions of the same components as those of the first embodiment will be omitted.
- FIG. 13 is a cross-sectional view of an LED package according to a second embodiment of the invention.
- FIGS. 14 to 18 are cross-sectional views of LED packages according to modifications of the second embodiment of the invention.
- the LED package according to the second embodiment of the invention has almost the same construction as that of the LED package according to the first embodiment, but is different from the first embodiment only in that two or more via holes 110 are formed.
- the LED package according to the second embodiment of the invention includes a metal substrate 100 having two or more via holes 110 formed therein, an insulating layer 120 which is formed on the surface of the metal substrate including the inner surfaces of the via holes 110 , a plurality of metal patterns 130 which are formed on the insulating layer 120 and are electrically isolated from each other, and an LED chip 140 which is mounted on a metal pattern 130 among the plurality of metal patterns 130 .
- the metal substrate 100 may be formed of aluminum, and the insulating layer 120 may be composed of an oxide film layer (Al 2 O 3 ) which is formed through an anodizing process.
- Al 2 O 3 oxide film layer
- the metal substrate 100 may have a cavity 105 provided in a position where the LED chip 140 is mounted, the cavity 105 having a predetermined depth.
- the thickness of the metal substrate 100 under the LED chip 140 can be reduced, which makes it possible to increase a heat dissipation effect where heat generated from the LED chip 140 is dissipated to the outside through the metal substrate 100 .
- a metal pattern 130 may be formed in a position corresponding to the portion where the LED chip 140 is mounted, and serves to effectively dissipate heat generated from the LED chip 140 .
- the metal pattern 130 which is formed on the bottom surface of the metal substrate 100 so as to correspond to the LED chip 140 , may be electrically isolated from the adjacent metal patterns 130 so as to serve as only a heat dissipation layer, as shown in FIG. 13 . However, as shown in FIG. 15 , the metal pattern 130 may extend so as to be electrically connected to an adjacent metal pattern 130 , thereby serving as both a heat dissipation layer and an electrode.
- the metal pattern 130 which is formed on the bottom surface of the metal substrate 100 so as to correspond to the LED chip 140 , may be formed on the insulating layer 120 formed on the bottom surface of the metal substrate 100 , as shown in FIG. 13 .
- the metal pattern 130 may be formed so as to be directly connected to the bottom surface of the metal substrate 100 which is exposed by partially removing the insulating layer 120 . In this case, it is possible to further increase a heat dissipation effect.
- the metal pattern 130 having the LED chip 140 mounted thereon may be formed on the top surface of the insulating layer 120 , as shown in FIG. 13 .
- the metal pattern 130 may be formed on the top surface of the metal substrate 100 which is exposed by partially removing the insulating layer 120 .
- the heat generated from the LED chip 140 can be effectively dissipated to the outside through the metal substrate 100 .
- the metal pattern 130 having the LED chip 140 mounted thereon may be formed on the top surface of a cavity 105 which is formed by partially removing the insulating layer 120 and the metal substrate 100 .
- the thickness of the metal substrate 100 under the LED chip 140 can be reduced. Therefore, it is possible to maximize the heat dissipation effect where the heat generated from the LED chip 140 is dissipated to the outside through the metal substrate 100 .
- the LED chip 140 may be a vertical, horizontal, or flip-chip LED chip.
- any one electrode (not shown) of the LED chip 140 may be electrically connected to the metal pattern 130 having the LED chip 140 mounted thereon, and another electrode (not shown) thereof may be electrically connected to the metal pattern 130 , where the LED chip 140 is not mounted, through a wire 150 , as shown in FIGS. 13 to 18 .
- a molding portion 160 is formed so as to cover the LED chip 140 and the wire 150 .
- FIG. 19 is a cross-sectional view showing an example where a horizontal LED chip is mounted on the LED package according to the second embodiment of the invention.
- FIG. 20 is a cross-sectional view showing an example where a flip-chip LED chip is mounted on the LED package according to the second embodiment of the invention.
- any one electrode (not shown) of the horizontal LED chip 140 may be electrically connected to a metal pattern 130 , where the LED chip 140 is not mounted, through a first wire 150 a, and another electrode (not shown) thereof may be electrically connected to another metal pattern 130 , where the LED chip 140 is not mounted, through a second wire 150 b, as shown in FIG. 19 .
- connection elements 145 are formed on the bottom surface of the LED chip 140 so as to be electrically connected to the electrodes of the LED chip 140 , as shown in FIG. 20 .
- the respective connection elements 145 may be electrically connected to the metal patterns 130 which are electrically isolated from each other.
- connection elements 145 may be composed of solder balls, bumps, or pads.
- the LED chip is mounted on the metal substrate which is formed of aluminum and has been subjected to the anodizing process, it is possible to obtain the same operation and effect as that of the first embodiment.
- FIGS. 21 to 26 a method of manufacturing an LED package according to the second embodiment of the invention will be described.
- the duplicated descriptions of the same components as those of the first embodiment will be omitted.
- FIGS. 21 to 26 are process diagrams sequentially showing a method of manufacturing an LED package according to the second embodiment of the invention.
- a metal substrate 100 is prepared.
- a plurality of via holes 110 are formed so as to pass through the metal substrate 100 .
- an insulating layer 120 is formed on the surface of the metal substrate including the inner surfaces of the via holes 110 ; through an anodizing process.
- a metal layer 130 a is formed on the insulating layer 120 .
- a process for filling up the via holes 110 with a via-hole filler 135 may be additionally performed.
- the metal layer 130 a is patterned so as to form a plurality of metal patterns 130 on the insulating layer 120 , the metal patterns 130 being electrically isolated from one another.
- LED chips 140 are mounted on some metal patterns 130 , and wires 150 for electrically connecting the LED chips 140 to other metal patterns 130 , where the LED chips 140 are not mounted, are formed.
- molding portions 160 are formed on the metal substrate 100 so as to cover the LED chips 140 and the wires 150 .
- the metal substrate 100 is diced along a dicing line so as to manufacture a plurality of unit LED packages.
- the unit LED package includes one LED chip 140 and two or more via holes 110 .
- the heat generated from the LED chip can be effectively dissipated to the outside through the metal substrate. Therefore, it is possible to enhance the heat dissipation performance of the LED package.
- a high-power LED chip with a relatively large calorific value as well as a low-power LED chip with a relatively low calorific value may be used, which makes it possible to enhance an optical characteristic of the LED package and to expand the lifespan of the LED package.
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Abstract
Provided is an LED package including a metal substrate that has one or more via holes formed therein; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and an LED chip that is mounted on a metal pattern among the plurality of metal patterns.
Description
- This application claims the benefit of Korean Patent Application No. 10-2008-0076339 filed with the Korea Intellectual Property Office on Aug. 5, 2008, the disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a light emitting diode (LED) package and a method of manufacturing the same.
- 2. Description of the Related Art
- In general, an LED is widely used as a light source because it has a number of advantages such as low power consumption and high brightness.
- In particular, the LED is being adopted as a backlight unit for lighting devices and liquid crystal displays (LCD). LED is provided in the form of package which is easily mounted on various devices such as a lighting device and so on. An LED package should not only protect the LED and have a connection structure with devices, but also should have a heat dissipation function for dissipating heat generated from the LED.
- The heat dissipation performance is a package condition which is considered to be important in backlight units for lighting device and LCD, which require a high-power LED.
- That is, the performance and lifespan of the LED in the LED package may exponentially decrease, as the operation temperature thereof increases. When the operation temperature of the LED increases to more than predetermined temperature, the package may discolor. Therefore, the heat generated from the LED should be dissipated so that the operation temperature should be optimally maintained.
- Accordingly, a variety of researches on LED packages have been recently conducted, in order to expand the lifespan of the LED packages by simplifying the structure and enhancing the heat dissipation performance.
- An advantage of the present invention is that it provides an LED package in which an anodizing process is performed on an aluminum substrate having via holes formed therein so as to enhance heat dissipation performance and optical characteristic of the LED package, and a high-power LED chip as well as a low-power LED chip can be used.
- Another advantage of the invention is that it provides a method of manufacturing an LED package.
- Additional aspect and advantages of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
- According to an aspect of the invention, an LED package comprises a metal substrate that has one or more via holes formed therein; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and an LED chip that is mounted on a metal pattern among the plurality of metal patterns.
- The metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the top surface of the metal substrate which is exposed by partially removing the insulating layer.
- Any one of the metal patterns formed at the bottom surface of the metal substrate may be formed on the bottom surface of the metal substrate which is exposed by partially removing the insulating layer.
- The LED package may further include a wire that connects the LED chip to a metal pattern on which the LED chip is not mounted. The LED chip may be a vertical LED chip.
- Alternatively, the LED package may further include a first wire that electrically connects the LED chip to a metal pattern on which the LED chip is not mounted; and a second wire that electrically connects the LED chip to the metal pattern having the LED chip mounted thereon.
- Alternatively, the LED package may further include first and second wires that electrically connect the LED chip to the metal patterns on which the LED chip is not mounted.
- The metal pattern connected to the first or second wire may be formed on the top surface of the metal substrate which is exposed by partially removing the insulating layer.
- The metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the top surface of a cavity formed by partially removing the insulating layer and the metal substrate.
- The LED package may further include a molding portion that covers the LED chip. The molding portion may be composed of any one selected from the group consisting of silicon resin, epoxy resin, and epoxy molding compound (EMC).
- The molding portion may be formed by any one of an injection molding method, a transfer molding method, and a pin gate molding method, and may have a trapezoid, rectangular, or hemispherical cross-sectional shape.
- The metal substrate may be composed of aluminum.
- The insulating layer may be formed through an anodizing process. The anodizing process may be performed using any one of organic acid, sulfuric acid, and mixed acid thereof.
- According to another aspect of the invention, a method of manufacturing an LED package comprises forming a plurality of via holes passing through a metal substrate; forming an insulating layer on a surface of the metal substrate including inner surfaces of the via holes; partially exposing the top and bottom surfaces of the metal substrate by partially removing the insulating layer; forming a metal layer on the insulating layer including the exposed portions of the metal substrate; patterning the metal layer so as to form a plurality of metal patterns on the exposed portions of the metal substrate and the insulating layer, the metal patterns being electrically isolated from one another; mounting LED chips on some metal patterns among the plurality of metal patterns; and dicing the metal substrate such that each of the diced substrates includes one LED chip and one or more via holes.
- The LED chips may be mounted on the metal patterns formed on the exposed top surface of the metal substrate.
- The method may further comprise forming wires which electrically connects the LED chips to the metal patterns; and forming molding portions which covers the LED chips and the wires, after the mounting of the LED chips.
- The method may further comprise forming a cavity with a predetermined depth by etching the exposed top surface of the metal substrate, after the exposing of the top and bottom surfaces of the metal substrate.
- The dicing of the metal substrate may be performed using a dicing blade or cutting mold.
- According to a further aspect of the invention, an LED package comprises a metal substrate that has two or more via holes; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and an LED chip that is mounted on one metal pattern among the plurality of metal patterns.
- The metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the top surface of the metal substrate which is exposed by partially removing the insulating layer.
- The metal pattern having the LED chip mounted thereon among the plurality of metal patterns may be formed on the bottom surface of a cavity formed by partially removing the insulating layer and the metal substrate.
- The LED package may further comprise a wire that electrically connects the LED chip to a metal pattern on which the LED chip is not mounted. The LED chip may be a vertical LED chip.
- Alternatively, the LED package may further comprise first and second wires that electrically connect the LED chip to the metal patterns on which the LED chip is not mounted. The LED chip may be a horizontal LED chip.
- The LED chip may have a pair of connection elements formed on the bottom surface thereof, the connection elements being electrically connected to the metal patterns, respectively, which are electrically isolated from each other.
- The LED package may further comprise a molding portion that covers the LED chip.
- The metal substrate may have a cavity with a predetermined depth which is provided at a position where the LED chip is mounted.
- According to a still further aspect of the invention, a method of manufacturing an LED chip comprises forming a plurality of via holes passing through a metal substrate; forming an insulating layer on a surface of the metal substrate including inner surfaces of the via holes; forming a metal layer on the insulating layer; patterning the metal layer so as to form a plurality of metal patterns which are electrically isolated from one another; mounting LED chips on some metal patterns among the plurality of metal patterns; and dicing the metal substrate such that each of the diced substrates includes one LED chip and two or more via holes.
- The method may further comprise forming wires which electrically connects the LED chips to the metal patterns on which the LED chips are not formed; and forming molding portions which covers the LED chips and the wires, after the mounting of the LED chips.
- These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
-
FIGS. 1 and 2 are cross-sectional views of an LED package according to a first embodiment of the invention; -
FIGS. 3 and 4 are cross-sectional views showing an example where a horizontal LED chip is mounted on the LED package according to the first embodiment of the invention; -
FIG. 5 is a cross-sectional view of an LED package according to a modification of the first embodiment of the invention; -
FIGS. 6 to 12 are process diagrams sequentially showing a method of manufacturing an LED package according to the first embodiment of the invention; -
FIG. 13 is a cross-sectional view of an LED package according to a second embodiment of the invention; -
FIGS. 14 to 18 are cross-sectional views of LED packages according to modifications of the second embodiment of the invention; -
FIG. 19 is a cross-sectional view showing an example where a horizontal LED chip is mounted on the LED package according to the second embodiment of the invention; -
FIG. 20 is a cross-sectional view showing an example where a flip-chip LED chip is mounted on the LED package according to the second embodiment of the invention; and -
FIGS. 21 to 26 are process diagrams sequentially showing a method of manufacturing an LED package according to the second embodiment of the invention. - Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below in order to explain the present general inventive concept by referring to the figures.
- Hereinafter, an LED package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
- Structure of LED package according to first embodiment
- Referring to
FIGS. 1 to 4 , an LED package according to a first embodiment of the invention will be described. -
FIGS. 1 and 2 are cross-sectional views of an LED package according to a first embodiment of the invention. - As shown in
FIG. 1 , the LED package according to the first embodiment of the invention includes ametal substrate 100 having one or more viaholes 110 formed therein, an insulatinglayer 120 which is formed on the surface of themetal substrate 100 including the inner surface of theVia hole 110, a plurality ofmetal patterns 130 which are formed on the insulatinglayer 120 and are electrically isolated from each other, and anLED chip 140 mounted on ametal pattern 130 among the plurality ofmetal patterns 130. - The
metal substrate 100 may be formed of metal with excellent heat conductivity, such as aluminum (Al). - The insulating
layer 120, which is an oxide film layer (Al2O3), may be formed on themetal substrate 100 composed of aluminum through an anodizing process. The anodizing process may be performed using organic acid, sulfuric acid, or mixed acid thereof. - Aluminum is a metallic material which can be obtained at a relatively low price, and has excellent heat conductivity. Further, the oxide film layer (Al2O3) obtained through the anodizing process also has relatively high heat conductivity of 10-30 W/mK, and can be formed with a small thickness, thereby implementing low thermal resistance.
- Therefore, the
metallic substrate 100 exhibits more excellent heat dissipation performance than the conventional substrate formed of copper or ceramic. Further, the anodizing process for anodizing aluminum is a relatively simple process, and the process cost and time thereof are relatively low and short. - The via
hole 110 may be formed by a drilling, punching, or etching process, and may serve to electrically connect themetal patterns 130 formed on the top and bottom surfaces of themetal substrate 100. - The via
hole 100 may be completely filled up with the insulatinglayer 120 and themetal patterns 130 which are formed on the inner surface of the viahole 110. As shown inFIG. 1 , however, when the insulatinglayer 120 and themetal patterns 130 are sequentially formed with a small thickness along the inner surface of the viahole 110, the inside of the viahole 110 may not be filled up completely. In this case, the internal space of the viahole 110 may be filled up with a via-hole filler 135. The via-hole filler 135 may be composed of a conductive material such as metal or a non-conductive material such as epoxy. - Among the plurality of
metal patterns 130, themetal pattern 130 having theLED chip 140 mounted thereon may be formed on the top surface of themetal substrate 100 which is exposed by partially removing the insulatinglayer 120. In this case, theLED chip 140 may be mounted on themetal pattern 130 formed on the top surface of themetal substrate 100, as described above, but may be mounted across themetal pattern 130 formed on the top surface of themetal substrate 100 and the insulatinglayer 120 adjacent to themetal pattern 130. - As the
metal pattern 130 having theLED chip 140 mounted thereon is hot formed on the insulatinglayer 120 but is directly connected to the top surface of themetal substrate 100, heat generated from theLED chip 140 can be effectively dissipated to the outside. - On the bottom surface of the
metal substrate 100, anothermetal pattern 130 may be formed at a position corresponding to themetal pattern 130 having theLED chip 140 mounted thereon, and serves to effectively dissipate heat generated from theLED chip 140. - In this case, the
metal pattern 130, which is formed on the bottom surface of themetal substrate 100 so as to correspond to theLED chip 140, may be electrically isolated from theadjacent metal patterns 130 so as to serve as only a heat dissipation layer, as shown inFIG. 1 . However, as shown inFIG. 2 , themetal pattern 130 may extend so as to be electrically connected to anadjacent metal pattern 130, thereby serving as both a heat dissipation layer and an electrode. - The
LED chip 140 may be a vertical LED chip. In this case, any one electrode (not shown) of theLED chip 140 may be electrically connected to themetal pattern 130 having theLED chip 140 mounted thereon, and another electrode (not shown) of theLED chip 140 may be electrically connected to ametal pattern 130, where the LED chip is not mounted, through awire 150. At this time, themetal pattern 130 connected to theLED chip 140 through thewire 150 is formed so as to extend to the bottom surface of themetal substrate 100 through the viahole 110. - The
wire 150 may be formed of gold, aluminum, or copper. - On the
metal substrate 100, amolding portion 160 is formed so as to cover theLED chip 140 and thewire 150. - The
molding portion 160 may be formed in a desired shape through an injection molding, transfer molding, or pin-gate molding method using silicon resin, epoxy resin, or epoxy molding compound (EMC). - The
molding portion 160 is formed in a hemispherical shape, as shown inFIGS. 1 and 2 . Without being limited thereto, however, themolding portion 160 may be formed in various shapes such as a trapezoid, a rectangle, and so on. -
FIGS. 3 and 4 are cross-sectional views showing an example where a horizontal LED chip is mounted on the LED package according to the first embodiment of the invention. - In the first embodiment of the invention, a horizontal LED chip may be used as the
LED chip 140, instead of the vertical LED chip. In this case, as shown inFIG. 3 , any one electrode (not shown) of thehorizontal LED chip 140 may be electrically connected to themetal pattern 130, where theLED chip 140 is not mounted, through afirst wire 150 a, and another electrode (not shown) thereof may be electrically connected to themetal pattern 130 having theLED chip 140 mounted thereon through asecond wire 150 b. - At this time, the
second wire 150 b may not be electrically connected to themetal pattern 130 having theLED chip 140 mounted thereon, as described above, but may be electrically connected to aseparate metal pattern 130 where theLED chip 140 is not mounted, as shown inFIG. 4 . Theseparate metal pattern 130 connected to thesecond wire 150 b may be formed on the top surface of themetal substrate 100 which is exposed by partially removing the insulatinglayer 120. - In the LED package according to the first embodiment of the invention, the
metal pattern 130 connected to the viahole 110 and themetal substrate 100 are used as electrodes which are electrically connected to theLED chip 140. Any onemetal pattern 130 among themetal patterns 130 formed on the bottom surface of themetal substrate 100 may be formed on the bottom surface of themetal substrate 100, which is exposed by partially removing the insulatinglayer 120, so as to be directly connected to themetal substrate 100. - Further, by using the
metal substrate 100 formed of aluminum where the viahole 110 is formed, it is possible to obtain an excellent heat dissipation effect. Therefore, a high-power LED chip with a relatively large calorific value as well as a low-power LED chip with a relatively low calorific value may be used, which makes it possible to enhance an optical characteristic of the LED package. - Further, as the insulating
layer 120 is formed on themetal substrate 100 through the anodizing process, the insulatinglayer 120 is integrally formed with themetal substrate 100, which makes it possible to enhance the durability of the package. -
FIG. 5 is a cross-sectional view of an LED package according to a modification of the first embodiment of the invention. As shown inFIG. 5 , themetal pattern 130 having theLED chip 140 mounted thereon, among the plurality ofmetal patterns 130, may be formed on the top surface of acavity 105 which is formed by partially removing the insulatinglayer 120 and themetal substrate 100. - When the
LED chip 140 is mounted within thecavity 105, the thickness of themetal substrate 100 under theLED chip 140 can be reduced. Therefore, since the heat dissipation path of theLED chip 140 is reduced, it is possible to further enhance the heat dissipation performance of the LED package. - Referring to
FIGS. 6 to 12 , a method of manufacturing an LED package according to the first embodiment of the invention will be described. -
FIGS. 6 to 12 are process diagrams sequentially showing a method of manufacturing an LED package according to the first embodiment of the invention. - As shown in
FIG. 6 , ametal substrate 100 is prepared. - The
metal substrate 100 may be an aluminum plate which has been subjected to a process for cleaning contaminants such as organic matters existing on the surface of the aluminum plate. - As shown in
FIG. 6 , themetal substrate 100 may be formed in a square shape. Depending on the processed aluminum plate, themetal substrate 100 may be formed in various shapes such as a rectangle, a circle and so on. The thickness of themetal substrate 100 may be set to more than about 0.1 mm, in consideration of the process and the reliability of products after the process. - Next, as shown in
FIG. 7 , a plurality of viaholes 110 passing through themetal substrate 100 are formed. As described above, the viaholes 110 may be formed by a drilling, punching, or etching process. - Then, as shown in
FIG. 8 , an insulatinglayer 120 is formed on the surface of themetal substrate 100 including the inner surfaces of the via holes 110, through an anodizing process. - Next, as shown in
FIGS. 9A and 9B , the insulatinglayer 120 is partially removed in such a manner that the top and bottom surfaces of themetal substrate 100 are partially exposed. The removing of the insulatinglayer 120 may be performed by an etching process. - After the top and bottom surfaces of the
metal substrate 100 are partially exposed, the exposed top surface of themetal substrate 100 may be additionally etched so as to form acavity 105 with a predetermined depth, as shown inFIG. 5 . -
FIG. 9A shows a state where the top surface of themetal substrate 100 is partially exposed, andFIG. 9B shows a state where the bottom surface of themetal substrate 100 is partially exposed. - Next, as shown in
FIG. 10 , ametal layer 130 a is formed on the insulatinglayer 120 including the exposed portions of themetal substrate 100. Themetal layer 130 a may be formed through an electroplating method, an electroless plating method, or a metal deposition method. - While the
metal layer 130 a is formed, the viaholes 110 may be completely filled up with themetal layer 130 a. When themetal layer 130 a is thinly formed along the inner surfaces of the via holes 110, the viaholes 110 may be not be filled up completely. When the via holes 110 are not filled up completely, a process for filling up the viaholes 110 with a via-hole filler 135 may be additionally performed, or may be not performed. The via-hole filler 135 may be composed of a conductive or non-conductive material. - Next, as shown in
FIG. 11 , themetal layer 130 a is patterned so as to form a plurality ofmetal patterns 130 on the exposed portions of the top and bottom surfaces of themetal substrate 100 and the insulatinglayer 120, themetal patterns 130 being electrically isolated from one another. - Then, as shown in
FIG. 12 ,LED chips 140 are mounted on themetal patterns 130. In this case, theLED chips 140 may be mounted on themetal patterns 130 formed on the exposed top surface of themetal substrate 100. - When the LED chips 140 are mounted, a die bonding method may be used, in which silver paste, transparent epoxy, or solder is applied on the
metal patterns 130 on which theLED chips 140 are to be mounted, and theLED chips 140 mounted on themetal patterns 130 are heat-treated at a predetermined temperature. Alternatively, a fluxless or flux eutectic bonding method may be used. - As the
LED chips 140 are mounted on themetal patterns 130 which are directly connected to the top surface of themetal substrate 100, heat generated from theLED chips 140 can be effectively dissipated to the outside through themetal substrate 100. - Next,
wires 150 for electrically connecting theLED chips 140 to themetal patterns 130 on which theLED chips 140 are not mounted are formed. Although not shown, molding portions 160 (refer toFIG. 1 ) are formed on themetal substrate 100 so as to cover theLED chips 140 and thewires 150. - Then, the
metal substrate 100 is diced along a dicing line so as to manufacture a plurality of unit LED packages. The unit LED package includes oneLED chip 140 and one or more viaholes 110. When themetal substrate 100 is diced, a dicing blade or a cutting mold may be used. - Referring to
FIGS. 13 to 20 , an LED package according to a second embodiment of the invention will be described. In the construction of the second embodiment, the duplicated descriptions of the same components as those of the first embodiment will be omitted. -
FIG. 13 is a cross-sectional view of an LED package according to a second embodiment of the invention.FIGS. 14 to 18 are cross-sectional views of LED packages according to modifications of the second embodiment of the invention. - As shown in
FIG. 13 , the LED package according to the second embodiment of the invention has almost the same construction as that of the LED package according to the first embodiment, but is different from the first embodiment only in that two or more viaholes 110 are formed. - That is, the LED package according to the second embodiment of the invention includes a
metal substrate 100 having two or more viaholes 110 formed therein, an insulatinglayer 120 which is formed on the surface of the metal substrate including the inner surfaces of the via holes 110, a plurality ofmetal patterns 130 which are formed on the insulatinglayer 120 and are electrically isolated from each other, and anLED chip 140 which is mounted on ametal pattern 130 among the plurality ofmetal patterns 130. - The
metal substrate 100 may be formed of aluminum, and the insulatinglayer 120 may be composed of an oxide film layer (Al2O3) which is formed through an anodizing process. - As shown in
FIG. 14 , themetal substrate 100 may have acavity 105 provided in a position where theLED chip 140 is mounted, thecavity 105 having a predetermined depth. When thecavity 105 is provided in themetal substrate 100, the thickness of themetal substrate 100 under theLED chip 140 can be reduced, which makes it possible to increase a heat dissipation effect where heat generated from theLED chip 140 is dissipated to the outside through themetal substrate 100. - On the bottom surface of the
metal substrate 100, ametal pattern 130 may be formed in a position corresponding to the portion where theLED chip 140 is mounted, and serves to effectively dissipate heat generated from theLED chip 140. - The
metal pattern 130, which is formed on the bottom surface of themetal substrate 100 so as to correspond to theLED chip 140, may be electrically isolated from theadjacent metal patterns 130 so as to serve as only a heat dissipation layer, as shown inFIG. 13 . However, as shown inFIG. 15 , themetal pattern 130 may extend so as to be electrically connected to anadjacent metal pattern 130, thereby serving as both a heat dissipation layer and an electrode. - The
metal pattern 130, which is formed on the bottom surface of themetal substrate 100 so as to correspond to theLED chip 140, may be formed on the insulatinglayer 120 formed on the bottom surface of themetal substrate 100, as shown inFIG. 13 . However, as shown inFIG. 16 , themetal pattern 130 may be formed so as to be directly connected to the bottom surface of themetal substrate 100 which is exposed by partially removing the insulatinglayer 120. In this case, it is possible to further increase a heat dissipation effect. - Among the plurality of
metal patterns 130, themetal pattern 130 having theLED chip 140 mounted thereon may be formed on the top surface of the insulatinglayer 120, as shown inFIG. 13 . However, as shown inFIG. 17 , themetal pattern 130 may be formed on the top surface of themetal substrate 100 which is exposed by partially removing the insulatinglayer 120. In this case, as themetal pattern 130 having theLED chip 140 mounted thereon is electrically connected to the top surface of themetal substrate 100, the heat generated from theLED chip 140 can be effectively dissipated to the outside through themetal substrate 100. - As shown in
FIG. 18 , themetal pattern 130 having theLED chip 140 mounted thereon may be formed on the top surface of acavity 105 which is formed by partially removing the insulatinglayer 120 and themetal substrate 100. - When the
LED chip 140 is mounted in thecavity 105, the thickness of themetal substrate 100 under theLED chip 140 can be reduced. Therefore, it is possible to maximize the heat dissipation effect where the heat generated from theLED chip 140 is dissipated to the outside through themetal substrate 100. - The
LED chip 140 may be a vertical, horizontal, or flip-chip LED chip. - When the
LED chip 140 is a vertical LED chip, any one electrode (not shown) of theLED chip 140 may be electrically connected to themetal pattern 130 having theLED chip 140 mounted thereon, and another electrode (not shown) thereof may be electrically connected to themetal pattern 130, where theLED chip 140 is not mounted, through awire 150, as shown inFIGS. 13 to 18 . - On the
metal substrate 100, amolding portion 160 is formed so as to cover theLED chip 140 and thewire 150. -
FIG. 19 is a cross-sectional view showing an example where a horizontal LED chip is mounted on the LED package according to the second embodiment of the invention.FIG. 20 is a cross-sectional view showing an example where a flip-chip LED chip is mounted on the LED package according to the second embodiment of the invention. - When the
LED chip 140 is a horizontal LED chip, any one electrode (not shown) of thehorizontal LED chip 140 may be electrically connected to ametal pattern 130, where theLED chip 140 is not mounted, through afirst wire 150 a, and another electrode (not shown) thereof may be electrically connected to anothermetal pattern 130, where theLED chip 140 is not mounted, through asecond wire 150 b, as shown inFIG. 19 . - When the
LED chip 140 is a flip-chip LED chip, a pair ofconnection elements 145 are formed on the bottom surface of theLED chip 140 so as to be electrically connected to the electrodes of theLED chip 140, as shown inFIG. 20 . Therespective connection elements 145 may be electrically connected to themetal patterns 130 which are electrically isolated from each other. - The
connection elements 145 may be composed of solder balls, bumps, or pads. - In the LED package according to the second embodiment of the invention, as the LED chip is mounted on the metal substrate which is formed of aluminum and has been subjected to the anodizing process, it is possible to obtain the same operation and effect as that of the first embodiment.
- Referring to
FIGS. 21 to 26 , a method of manufacturing an LED package according to the second embodiment of the invention will be described. In the construction of the second embodiment, the duplicated descriptions of the same components as those of the first embodiment will be omitted. -
FIGS. 21 to 26 are process diagrams sequentially showing a method of manufacturing an LED package according to the second embodiment of the invention. - First, as shown in
FIG. 21 , ametal substrate 100 is prepared. - Next, as shown in
FIG. 22 , a plurality of viaholes 110 are formed so as to pass through themetal substrate 100. - Then, as shown in
FIG. 23 , an insulatinglayer 120 is formed on the surface of the metal substrate including the inner surfaces of the via holes 110; through an anodizing process. - Next, as shown in
FIG. 24 , ametal layer 130 a is formed on the insulatinglayer 120. - When the via holes 110 are not filled up completely with the
metal layer 130 a during the forming of themetal layer 130 a, a process for filling up the viaholes 110 with a via-hole filler 135 may be additionally performed. - Then, as shown in
FIG. 25 , themetal layer 130 a is patterned so as to form a plurality ofmetal patterns 130 on the insulatinglayer 120, themetal patterns 130 being electrically isolated from one another. - Next, as shown in
FIG. 26 ,LED chips 140 are mounted on somemetal patterns 130, andwires 150 for electrically connecting theLED chips 140 toother metal patterns 130, where theLED chips 140 are not mounted, are formed. - Although not shown, molding portions 160 (refer to
FIG. 13 ) are formed on themetal substrate 100 so as to cover theLED chips 140 and thewires 150. - Next, the
metal substrate 100 is diced along a dicing line so as to manufacture a plurality of unit LED packages. The unit LED package includes oneLED chip 140 and two or more viaholes 110. - According to the present invention, as the LED chip is mounted on the metal substrate formed of aluminum, the heat generated from the LED chip can be effectively dissipated to the outside through the metal substrate. Therefore, it is possible to enhance the heat dissipation performance of the LED package.
- In the LED package, a high-power LED chip with a relatively large calorific value as well as a low-power LED chip with a relatively low calorific value may be used, which makes it possible to enhance an optical characteristic of the LED package and to expand the lifespan of the LED package.
- Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
Claims (2)
1. A light emitting diode (LED) package comprising:
a metal substrate that has one or more via holes formed therein;
an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes;
a plurality of metal patterns that are formed on the insulating layer and are electrically isolated from one another; and
an LED chip that is mounted on a metal pattern among the plurality of metal patterns.
2.-41. (canceled)
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US14/106,446 US20140103386A1 (en) | 2008-08-05 | 2013-12-13 | Light emitting diode package and method of manufacturing the same |
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KR10-2008-0076339 | 2008-08-05 | ||
KR1020080076339A KR100958024B1 (en) | 2008-08-05 | 2008-08-05 | Light emitting diode package and method of manufacturing the same |
US12/238,663 US8610146B2 (en) | 2008-08-05 | 2008-09-26 | Light emitting diode package and method of manufacturing the same |
US14/106,446 US20140103386A1 (en) | 2008-08-05 | 2013-12-13 | Light emitting diode package and method of manufacturing the same |
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US12/238,663 Continuation US8610146B2 (en) | 2008-08-05 | 2008-09-26 | Light emitting diode package and method of manufacturing the same |
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US20140103386A1 true US20140103386A1 (en) | 2014-04-17 |
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US12/238,663 Expired - Fee Related US8610146B2 (en) | 2008-08-05 | 2008-09-26 | Light emitting diode package and method of manufacturing the same |
US14/106,446 Abandoned US20140103386A1 (en) | 2008-08-05 | 2013-12-13 | Light emitting diode package and method of manufacturing the same |
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Also Published As
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KR100958024B1 (en) | 2010-05-17 |
US8610146B2 (en) | 2013-12-17 |
US20100032705A1 (en) | 2010-02-11 |
KR20100016737A (en) | 2010-02-16 |
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