US20140097492A1 - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- US20140097492A1 US20140097492A1 US13/645,668 US201213645668A US2014097492A1 US 20140097492 A1 US20140097492 A1 US 20140097492A1 US 201213645668 A US201213645668 A US 201213645668A US 2014097492 A1 US2014097492 A1 US 2014097492A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000000052 comparative effect Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 230000005669 field effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Definitions
- the disclosure relates in general to a semiconductor structure and more particularly to a semiconductor device of LDMOS, EDMOS, or FDMOS, etc.
- BVD breakdown voltage
- LDMOS lateral double diffused metal-oxide-semiconductor field-effect transistor
- EDMOS extended drain metal-oxide-semiconductor field-effect transistor
- FDMOS field drift metal-oxide-semiconductor field-effect transistor
- a semiconductor structure comprises a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure.
- the semiconductor substrate has an upper substrate surface.
- the dielectric layer is on the upper substrate surface.
- the dielectric structure is in the semiconductor substrate.
- the dielectric structure and the semiconductor substrate have opposing first and second interfaces.
- the first interface is more adjacent to the dielectric layer than the second interface.
- the electrode structure comprises an electrode truck portion and at least one electrode branch portion.
- the at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure.
- the electrode truck portion is on the dielectric structure and the dielectric layer on opposing sides of the at least one electrode branch portion.
- the at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 ⁇ therebetween.
- a semiconductor structure comprises a semiconductor substrate, a first source/drain, a second source/drain, a dielectric structure, a dielectric layer and an electrode structure.
- the semiconductor substrate has an upper substrate surface.
- the first source/drain is formed in the semiconductor substrate.
- the second source/drain is formed in the semiconductor substrate.
- the dielectric structure is in the semiconductor substrate between the first source/drain and the second source/drain.
- the dielectric layer is on the upper substrate surface between the first source/drain and the second source/drain.
- the electrode structure comprises an electrode truck portion and at least two electrode branch portions.
- the electrode truck portion is on the dielectric structure and the dielectric layer.
- the electrode branch portions are extended from the electrode truck portion down into the dielectric structure and separated from each other by the dielectric structure.
- FIG. 1 illustrates a cross-section view of a semiconductor structure according to one embodiment
- FIG. 2 illustrates a cross-section view of a semiconductor structure according to one embodiment
- FIG. 3 illustrates a cross-section view of a semiconductor structure according to one embodiment
- FIG. 4 illustrates a cross-section view of a semiconductor structure according to one embodiment
- FIG. 5 illustrates a cross-section view of a semiconductor structure according to one embodiment
- FIG. 6 illustrates a cross-section view of a semiconductor structure according to one embodiment.
- FIG. 1 illustrates a cross-section view of a semiconductor structure according to one embodiment.
- a semiconductor substrate 102 has an upper substrate surface 104 .
- a dielectric layer 106 may be formed on the upper substrate surface 104 .
- the semiconductor substrate 102 may comprise a doped region formed by doping a silicon material substrate, an active region defined by an isolation element not shown, an epitaxial, or other suitable materials.
- the dielectric layer 106 may comprise an oxide or a nitride, such as silicon oxide or silicon nitride, or other suitable materials.
- the dielectric layer 106 may be formed by a method comprising a thermal growth method, a deposition method such as CVD, PVD, etc.
- a dielectric structure 108 is formed on the semiconductor substrate 102 .
- the dielectric structure 108 has a lower dielectric surface 110 below the upper substrate surface 104 .
- the semiconductor substrate 102 may have a trench 112 etched from the upper substrate surface 104 down into the semiconductor substrate 102 , and the trench 112 is filled with the dielectric structure 108 .
- the trench 112 may have a depth D, which may be defined as a distance between the upper substrate surface 104 and the lower dielectric surface 110 .
- the depth D may be varied according to process generation. In some embodiments, the depth D of the trench 112 is about 0.4 ⁇ m.
- the dielectric structure 108 is not limited to STI as shown in FIG. 1 .
- the dielectric structure 108 comprises LOCOS or other suitable structures (not shown).
- the dielectric structure 108 may comprise an oxide or a nitride, such as silicon oxide or silicon nitride, or other suitable materials.
- the dielectric structure 108 may be formed by a method comprising a thermal growth method, a deposition method such as CVD, PVD, etc.
- the dielectric structure 108 and the semiconductor substrate 102 have a first interface 114 and a second interface 116 .
- the first interface 114 is opposite to the second interface 116 .
- the first interface 114 is more adjacent to the dielectric layer 106 than the second interface 116 .
- the first interface 114 and the second interface 116 have a gap distance W therebetween.
- the gap distance W may be adjusted according to operation voltage of the device. For example, the gap distance W is about 4 ⁇ m.
- an electrode structure 118 comprises an electrode truck portion 120 and a single electrode branch portion 122 .
- the electrode branch portion 122 is extended from the electrode truck portion 120 down into the dielectric structure 108 .
- the electrode truck portion 120 is extended on the dielectric structure 108 and the dielectric layer 106 on opposing sidewalls of the electrode branch portion 122 .
- the most right sidewall of the electrode structure 118 i.e. the most right sidewall of the electrode truck portion 120 in this embodiment, is not extended beyond the second interface 116 .
- a lower surface of the electrode branch portion 122 is not extended beyond the lower dielectric surface 110 of the dielectric structure 108 .
- the electrode branch portion 122 has a length L which may be defined as a distance between a lower surface of the electrode truck portion 120 and the lower surface of the electrode branch portion 122 .
- the length L is about 0.3 ⁇ m.
- the electrode branch portion 122 has a width K.
- the width K may be adjusted properly according to actual demands.
- the minimum of the width K may be the critical feature according to manufacturing processes.
- the width K is about 0.1 ⁇ m.
- the electrode branch portion 122 and the first interface 114 have the smallest gap distance S therebetween.
- the smallest gap distance S is bigger than 300 ⁇ substantially.
- the smallest gap distance S is about 350 ⁇ .
- the electrode structure 118 comprising the electrode truck portion 120 and the electrode branch portion 122 may comprise suitable conductive materials such as a polysilicon, a metal, a metal silicide, etc.
- suitable conductive materials such as a polysilicon, a metal, a metal silicide, etc.
- the concept of the electrode structure 118 can improve a device to have higher efficiency such as higher BVD or lower Ron.
- the semiconductor structure is a MOS device.
- a doped well 124 may be formed in the semiconductor substrate 102 adjacent to the first interface 114 by a doping step.
- a first source/drain 126 and a heavily doped region 128 may be formed in the doped well 124 by a doping step.
- a second source/drain 130 may be formed in the semiconductor substrate 102 adjacent to the second interface 116 by a doping step.
- the dielectric layer 106 on the upper substrate surface 104 between the first source/drain 126 and the first interface 114 is used as a gate insulating layer.
- the electrode structure 118 comprising the electrode branch portion 122 and the electrode truck portion 120 is used as a gate electrode.
- the semiconductor structure as shown in FIG. 1 is a lateral double diffused metal-oxide-semiconductor field-effect transistor (LDMOS).
- LDMOS metal-oxide-semiconductor field-effect transistor
- the semiconductor substrate 102 , the first source/drain 126 and the second source/drain 130 have a first type conductivity.
- the doped well 124 and the heavily doped region 128 have a second type conductivity opposite to the first type conductivity.
- the semiconductor structure being an NMOS
- the first type conductivity is N-type conductivity
- the second type conductivity is P-type conductivity.
- the semiconductor structure can have an increased BVD and a decreased Ron at the same time.
- the concept of the electrode structure 118 is not limited to applying for the LDMOS. It can be applied for other kinds of semiconductor devices.
- the semiconductor structure in FIG. 2 is different from the semiconductor structure in FIG. 1 in that a doped well 132 may be formed in the semiconductor substrate 102 by a doping step.
- the first source/drain 126 and the heavily doped region 128 may be formed in the semiconductor substrate 102 adjacent to the first interface 114 .
- the second source/drain 130 may be formed in the doped well 132 adjacent to the second interface 116 by a doping step.
- the semiconductor structure in FIG. 2 is an extended drain metal-oxide-semiconductor field-effect transistor (EDMOS).
- EMOS extended drain metal-oxide-semiconductor field-effect transistor
- the first source/drain 126 , the second source/drain 130 and the doped well 132 have the first type conductivity
- the heavily doped region 128 and the semiconductor substrate 102 have the second type conductivity.
- the semiconductor structure being a NMOS
- the first type conductivity is N-type conductivity
- the second type conductivity is P-type conductivity.
- the semiconductor structure is not limited to the electrode structure 118 having the single electrode branch portion 122 as shown in FIG. 1 and FIG. 2 .
- the electrode structure of the semiconductor structure may comprise at least two the electrode branch portions.
- the semiconductor structures in FIG. 3 and FIG. 4 are different from the semiconductor structure in FIG. 1 in that the electrode structure 118 A ( FIG. 3 ) comprises the two electrode branch portions 122 , and the electrode structure 118 B ( FIG. 4 ) comprises the three electrode branch portions 122 .
- the electrode structure having any other numbers of the electrode branch portion 122 may be used.
- the electrode branch portions 122 are extended from the electrode truck portion 120 down into the dielectric structure 108 and are separated from each other by the dielectric structure 108 .
- the electrode branch portions 122 have a gap distance M therebetween.
- the minimum of the gap distance M may be the critical feature according to manufacturing processes.
- the maximum of the gap distance M would not be greater than one third of a width of the dielectric structure 108 that may be regarded as the gap distance W between the first interface 114 and the second interface 116 .
- the gap distance M is about 0.1 ⁇ m.
- the electrode branch portions 122 have the width
- the minimum of the width K may be the critical feature according to manufacturing processes.
- the maximum of the width K would not be greater than one third of the width of the dielectric structure 108 that may be regarded as the gap distance W between the first interface 114 and the second interface 116 .
- the width K is about 0.1 ⁇ m.
- the most right sidewall of the electrode structures 118 A, 118 B i.e. the most right sidewall of the electrode branch portion 122 in this embodiment, is not extended beyond the second interface 116 .
- the lower surface of the electrode branch portion 122 is not extended beyond the lower dielectric surface 110 of the dielectric structure 108 .
- the electrode branch portions 122 have the length L respectively. In one embodiment, the length L is about 0.3 ⁇ m.
- the electrode branch portion 122 and the first interface 114 close to a channel region has the smallest gap distance S substantially bigger than 300 ⁇ , such as about 350 ⁇ .
- the electrode truck portion may be extended laterally beyond the most right electrode branch portion according to concepts similar with that for the semiconductor structures as shown in FIG. 1 , FIG. 2 .
- the concept of the electrode structure comprising the plurality of the electrode branch portions can be applied to the semiconductor structure as shown in FIG. 2 .
- the concept of the electrode structure according to embodiments can improve a device to have higher efficiency such as higher BVD or lower Ron.
- Table 1 shows characteristics of the semiconductor structure in embodiments 1 ⁇ 4 and comparative examples 5 ⁇ 7.
- the semiconductor structures in embodiment 1, embodiment 2, embodiment 3 and embodiment 4 comprise one electrode branch portion 122 ( FIG. 1 ), three electrode branch portions 122 ( FIG. 4 ), five electrode branch portions 122 , and seven electrode branch portions 122 .
- the electrode branch portion(s) 122 and the first interface 114 have the smallest gap distance S about 350 ⁇ therebetween.
- the electrode structure 218 comprises only the electrode truck portion 120 extended on the dielectric layer 106 and the dielectric structure 108 as shown in FIG. 5 .
- the electrode truck portion 120 of the electrode structure 318 is extended on the dielectric structure 108 and the dielectric layer 106 only on the single sidewall of the electrode branch portion 122 as shown in FIG. 6 .
- the difference between comparative example 6 and comparative example 7 is that the smallest gap distance S between the electrode branch portions 122 and the first interface 114 are about 350 ⁇ and 125 ⁇ respectively.
- Table 1 also shows that as compared to comparative examples 5 ⁇ 7, embodiments 1 ⁇ 4 can have higher BVD and lower Ron at the same time, which can be indicated by a smaller figure of merit (Ron/BVD). Therefore, the semiconductor structures in embodiments 1 ⁇ 4 have higher efficiency.
- the results in embodiments 1 ⁇ 4 also show that the figure of merit (Ron/BVD) is decreased as the number of the electrode branch portions 122 is increased.
Abstract
Description
- 1. Technical Field
- The disclosure relates in general to a semiconductor structure and more particularly to a semiconductor device of LDMOS, EDMOS, or FDMOS, etc.
- 2. Description of the Related Art
- In the semiconductor technology, the feature size of the semiconductor structure has been reduced. In the meantime, the rate, the efficiency, the density and the cost per integrated circuit unit have been improved.
- For example, many methods have been proposed for increasing a breakdown voltage (BVD) of a semiconductor structure such as a lateral double diffused metal-oxide-semiconductor field-effect transistor (LDMOS), an extended drain metal-oxide-semiconductor field-effect transistor (EDMOS) or a field drift metal-oxide-semiconductor field-effect transistor (FDMOS) and so on. However, an on-state resistance (Ron) of the semiconductor structure would be increased due to the conventional methods. Therefore, the semiconductor structure could not obtain a trade off between the BVD and the Ron for obtaining a desired small figure of merit (FOM=Ron/BVD).
- A semiconductor structure is provided. The semiconductor structure comprises a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure. The semiconductor substrate has an upper substrate surface. The dielectric layer is on the upper substrate surface. The dielectric structure is in the semiconductor substrate. The dielectric structure and the semiconductor substrate have opposing first and second interfaces. The first interface is more adjacent to the dielectric layer than the second interface. The electrode structure comprises an electrode truck portion and at least one electrode branch portion. The at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure. The electrode truck portion is on the dielectric structure and the dielectric layer on opposing sides of the at least one electrode branch portion. The at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 Å therebetween.
- A semiconductor structure is provided. The semiconductor structure comprises a semiconductor substrate, a first source/drain, a second source/drain, a dielectric structure, a dielectric layer and an electrode structure. The semiconductor substrate has an upper substrate surface. The first source/drain is formed in the semiconductor substrate. The second source/drain is formed in the semiconductor substrate. The dielectric structure is in the semiconductor substrate between the first source/drain and the second source/drain. The dielectric layer is on the upper substrate surface between the first source/drain and the second source/drain. The electrode structure comprises an electrode truck portion and at least two electrode branch portions. The electrode truck portion is on the dielectric structure and the dielectric layer. The electrode branch portions are extended from the electrode truck portion down into the dielectric structure and separated from each other by the dielectric structure.
- The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
-
FIG. 1 illustrates a cross-section view of a semiconductor structure according to one embodiment; -
FIG. 2 illustrates a cross-section view of a semiconductor structure according to one embodiment; -
FIG. 3 illustrates a cross-section view of a semiconductor structure according to one embodiment; -
FIG. 4 illustrates a cross-section view of a semiconductor structure according to one embodiment; -
FIG. 5 illustrates a cross-section view of a semiconductor structure according to one embodiment; and -
FIG. 6 illustrates a cross-section view of a semiconductor structure according to one embodiment. -
FIG. 1 illustrates a cross-section view of a semiconductor structure according to one embodiment. Asemiconductor substrate 102 has anupper substrate surface 104. Adielectric layer 106 may be formed on theupper substrate surface 104. For example, thesemiconductor substrate 102 may comprise a doped region formed by doping a silicon material substrate, an active region defined by an isolation element not shown, an epitaxial, or other suitable materials. Thedielectric layer 106 may comprise an oxide or a nitride, such as silicon oxide or silicon nitride, or other suitable materials. Thedielectric layer 106 may be formed by a method comprising a thermal growth method, a deposition method such as CVD, PVD, etc. - Referring to
FIG. 1 , adielectric structure 108 is formed on thesemiconductor substrate 102. Thedielectric structure 108 has a lowerdielectric surface 110 below theupper substrate surface 104. For example, thesemiconductor substrate 102 may have atrench 112 etched from theupper substrate surface 104 down into thesemiconductor substrate 102, and thetrench 112 is filled with thedielectric structure 108. In some embodiments, thetrench 112 may have a depth D, which may be defined as a distance between theupper substrate surface 104 and the lowerdielectric surface 110. The depth D may be varied according to process generation. In some embodiments, the depth D of thetrench 112 is about 0.4 μm. However, in the present disclosure, thedielectric structure 108 is not limited to STI as shown inFIG. 1 . In some embodiments, thedielectric structure 108 comprises LOCOS or other suitable structures (not shown). Thedielectric structure 108 may comprise an oxide or a nitride, such as silicon oxide or silicon nitride, or other suitable materials. Thedielectric structure 108 may be formed by a method comprising a thermal growth method, a deposition method such as CVD, PVD, etc - Referring to
FIG. 1 , thedielectric structure 108 and thesemiconductor substrate 102 have afirst interface 114 and asecond interface 116. Thefirst interface 114 is opposite to thesecond interface 116. Thefirst interface 114 is more adjacent to thedielectric layer 106 than thesecond interface 116. Thefirst interface 114 and thesecond interface 116 have a gap distance W therebetween. The gap distance W may be adjusted according to operation voltage of the device. For example, the gap distance W is about 4 μm. - Referring to
FIG. 1 , in this embodiment, anelectrode structure 118 comprises anelectrode truck portion 120 and a singleelectrode branch portion 122. Theelectrode branch portion 122 is extended from theelectrode truck portion 120 down into thedielectric structure 108. In addition, theelectrode truck portion 120 is extended on thedielectric structure 108 and thedielectric layer 106 on opposing sidewalls of theelectrode branch portion 122. In the arrangement design, the most right sidewall of theelectrode structure 118, i.e. the most right sidewall of theelectrode truck portion 120 in this embodiment, is not extended beyond thesecond interface 116. Moreover, a lower surface of theelectrode branch portion 122 is not extended beyond thelower dielectric surface 110 of thedielectric structure 108. Theelectrode branch portion 122 has a length L which may be defined as a distance between a lower surface of theelectrode truck portion 120 and the lower surface of theelectrode branch portion 122. For example, the length L is about 0.3 μm. Theelectrode branch portion 122 has a width K. The width K may be adjusted properly according to actual demands. For example, the minimum of the width K may be the critical feature according to manufacturing processes. In one embodiment, the width K is about 0.1 μm. In embodiments, theelectrode branch portion 122 and thefirst interface 114 have the smallest gap distance S therebetween. The smallest gap distance S is bigger than 300 Å substantially. For example, the smallest gap distance S is about 350 Å. Theelectrode structure 118 comprising theelectrode truck portion 120 and theelectrode branch portion 122 may comprise suitable conductive materials such as a polysilicon, a metal, a metal silicide, etc. The concept of theelectrode structure 118 can improve a device to have higher efficiency such as higher BVD or lower Ron. - Referring to
FIG. 1 , in embodiments, the semiconductor structure is a MOS device. For example, a doped well 124 may be formed in thesemiconductor substrate 102 adjacent to thefirst interface 114 by a doping step. A first source/drain 126 and a heavily dopedregion 128 may be formed in the doped well 124 by a doping step. A second source/drain 130 may be formed in thesemiconductor substrate 102 adjacent to thesecond interface 116 by a doping step. Thedielectric layer 106 on theupper substrate surface 104 between the first source/drain 126 and thefirst interface 114 is used as a gate insulating layer. Theelectrode structure 118 comprising theelectrode branch portion 122 and theelectrode truck portion 120 is used as a gate electrode. In some embodiments, the semiconductor structure as shown inFIG. 1 is a lateral double diffused metal-oxide-semiconductor field-effect transistor (LDMOS). In this case, thesemiconductor substrate 102, the first source/drain 126 and the second source/drain 130 have a first type conductivity. The doped well 124 and the heavily dopedregion 128 have a second type conductivity opposite to the first type conductivity. In a case of the semiconductor structure being an NMOS, the first type conductivity is N-type conductivity, and the second type conductivity is P-type conductivity. In embodiments, the semiconductor structure can have an increased BVD and a decreased Ron at the same time. In embodiments, the concept of theelectrode structure 118 is not limited to applying for the LDMOS. It can be applied for other kinds of semiconductor devices. - The semiconductor structure in
FIG. 2 is different from the semiconductor structure inFIG. 1 in that a doped well 132 may be formed in thesemiconductor substrate 102 by a doping step. The first source/drain 126 and the heavily dopedregion 128 may be formed in thesemiconductor substrate 102 adjacent to thefirst interface 114. The second source/drain 130 may be formed in the doped well 132 adjacent to thesecond interface 116 by a doping step. In one embodiment, the semiconductor structure inFIG. 2 is an extended drain metal-oxide-semiconductor field-effect transistor (EDMOS). In this case, the first source/drain 126, the second source/drain 130 and the doped well 132 have the first type conductivity, and the heavily dopedregion 128 and thesemiconductor substrate 102 have the second type conductivity. In a case of the semiconductor structure being a NMOS, the first type conductivity is N-type conductivity, and the second type conductivity is P-type conductivity. - The semiconductor structure is not limited to the
electrode structure 118 having the singleelectrode branch portion 122 as shown inFIG. 1 andFIG. 2 . In other embodiments, the electrode structure of the semiconductor structure may comprise at least two the electrode branch portions. - For example, the semiconductor structures in
FIG. 3 andFIG. 4 are different from the semiconductor structure inFIG. 1 in that theelectrode structure 118A (FIG. 3 ) comprises the twoelectrode branch portions 122, and theelectrode structure 118B (FIG. 4 ) comprises the threeelectrode branch portions 122. In other embodiments, the electrode structure having any other numbers of the electrode branch portion 122 (not shown) may be used. - Referring to
FIG. 3 andFIG. 4 , theelectrode branch portions 122 are extended from theelectrode truck portion 120 down into thedielectric structure 108 and are separated from each other by thedielectric structure 108. For example, theelectrode branch portions 122 have a gap distance M therebetween. For example, the minimum of the gap distance M may be the critical feature according to manufacturing processes. The maximum of the gap distance M would not be greater than one third of a width of thedielectric structure 108 that may be regarded as the gap distance W between thefirst interface 114 and thesecond interface 116. In one embodiment, the gap distance M is about 0.1 μm. Theelectrode branch portions 122 have the width - K respectively. The minimum of the width K may be the critical feature according to manufacturing processes. The maximum of the width K would not be greater than one third of the width of the
dielectric structure 108 that may be regarded as the gap distance W between thefirst interface 114 and thesecond interface 116. For example, the width K is about 0.1 μm. In the arrangement design, the most right sidewall of theelectrode structures electrode branch portion 122 in this embodiment, is not extended beyond thesecond interface 116. Moreover, the lower surface of theelectrode branch portion 122 is not extended beyond thelower dielectric surface 110 of thedielectric structure 108. Theelectrode branch portions 122 have the length L respectively. In one embodiment, the length L is about 0.3 μm. In embodiments, theelectrode branch portion 122 and thefirst interface 114 close to a channel region has the smallest gap distance S substantially bigger than 300 Å, such as about 350 Å. - In other embodiments (not shown), for the electrode structure comprising the plurality of the electrode branch portions, the electrode truck portion may be extended laterally beyond the most right electrode branch portion according to concepts similar with that for the semiconductor structures as shown in
FIG. 1 ,FIG. 2 . - The concept of the electrode structure comprising the plurality of the electrode branch portions can be applied to the semiconductor structure as shown in
FIG. 2 . The concept of the electrode structure according to embodiments can improve a device to have higher efficiency such as higher BVD or lower Ron. - Table 1 shows characteristics of the semiconductor structure in embodiments 1˜4 and comparative examples 5˜7. The semiconductor structures in embodiment 1, embodiment 2, embodiment 3 and embodiment 4 comprise one electrode branch portion 122 (
FIG. 1 ), three electrode branch portions 122 (FIG. 4 ), fiveelectrode branch portions 122, and sevenelectrode branch portions 122. The electrode branch portion(s) 122 and thefirst interface 114 have the smallest gap distance S about 350 Å therebetween. In comparative example 5, theelectrode structure 218 comprises only theelectrode truck portion 120 extended on thedielectric layer 106 and thedielectric structure 108 as shown inFIG. 5 . In comparative examples 6˜7, theelectrode truck portion 120 of theelectrode structure 318 is extended on thedielectric structure 108 and thedielectric layer 106 only on the single sidewall of theelectrode branch portion 122 as shown inFIG. 6 . In addition, the difference between comparative example 6 and comparative example 7 is that the smallest gap distance S between theelectrode branch portions 122 and thefirst interface 114 are about 350 Å and 125 Å respectively. Table 1 also shows that as compared to comparative examples 5˜7, embodiments 1˜4 can have higher BVD and lower Ron at the same time, which can be indicated by a smaller figure of merit (Ron/BVD). Therefore, the semiconductor structures in embodiments 1˜4 have higher efficiency. The results in embodiments 1˜4 also show that the figure of merit (Ron/BVD) is decreased as the number of theelectrode branch portions 122 is increased. -
amount of smallest electrode gap branch distance Ron Ron/ portion S (Å) BVD (V) (mohm * mm2) BVD Embodiment 1 1 350 46 52.00 1.13 Embodiment 2 3 350 50 50.91 1.02 Embodiment 3 5 350 51 49.56 0.97 Embodiment 4 7 350 52 48.66 0.94 Comparative 0 NA 46 56.84 1.24 example 5 Comparative 1 350 36 53.08 1.47 example 6 Comparative 1 125 32 52.60 1.64 example 7 - While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (6)
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