US20140084382A1 - Dual metal fill and dual threshold voltage for replacement gate metal devices - Google Patents
Dual metal fill and dual threshold voltage for replacement gate metal devices Download PDFInfo
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- US20140084382A1 US20140084382A1 US14/089,982 US201314089982A US2014084382A1 US 20140084382 A1 US20140084382 A1 US 20140084382A1 US 201314089982 A US201314089982 A US 201314089982A US 2014084382 A1 US2014084382 A1 US 2014084382A1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 69
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates generally to semiconductor devices and more particularly to integrated circuits including metal gate MOS transistor devices and fabrication methods for making the same.
- FETs Field effect transistors
- MOSFETs metal-oxide-semiconductor field-effect transistors
- a gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric.
- the gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate.
- the threshold voltage (Vt) is the gate voltage value required to render the channel conductive by formation of an inversion layer at the surface of the semiconductor channel.
- the threshold voltage is dependent upon, among other things, the workfunction difference between the gate and the substrate materials. In various circuit designs, it is desirable to have transistors with different threshold voltages within the same IC (integrated circuit) chip.
- the workfunction of a material is a measure of the energy required to move an electron in the material outside of a material atom from the Fermi level, and is usually expressed in electron volts (eV).
- eV electron volts
- Vt threshold voltages
- a method for forming two transistors having different threshold voltages comprises forming a first gate cavity in a first transistor and a second gate cavity in a second transistor, depositing a gate dielectric film in the gate cavity of the first and second transistors, depositing a first workfunction metal in the gate cavity of the first and second transistors, depositing a titanium layer in the gate cavity of the first and second transistors, removing the titanium layer from the gate cavity of the second transistor, depositing a first fill metal in the gate cavity of the first transistor, depositing a second workfunction metal in the gate cavity of the second transistor, depositing a second fill metal in the gate cavity of the second transistor, and planarizing the first and second transistors.
- a method for forming two transistors having different threshold voltages comprises forming a first gate cavity in a first transistor and a second gate cavity in a second transistor, depositing a gate dielectric film in the gate cavity of the first and second transistors, depositing a first workfunction metal in the gate cavity of the first and second transistors, depositing a titanium layer in the gate cavity of the first and second transistors, depositing a hardmask layer in the gate cavity of the first and second transistors, removing a portion of the hardmask layer from the gate cavity of the second transistor, removing the titanium layer from the gate cavity of the second transistor, removing the hardmask layer from the gate cavity of the first transistor, depositing a first fill metal in the gate cavity of the first transistor, depositing a second workfunction metal in the gate cavity of the second transistor, depositing a second fill metal in the gate cavity of the second transistor, and planarizing the first and second transistors.
- a semiconductor structure in another embodiment, comprises a first field effect transistor comprising a first gate cavity, a second field effect transistor comprising a second gate cavity, a first fill metal disposed in the first gate cavity, and a second fill metal disposed in the second gate cavity.
- FIGs. The figures are intended to be illustrative, not limiting.
- cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
- FIG. 1 shows a semiconductor structure 100 at a starting point for fabrication of an embodiment of the present invention.
- FIG. 2 shows a semiconductor structure at a subsequent point in the fabrication process where a gate dielectric film is deposited.
- FIG. 3 shows a semiconductor structure at a subsequent point in the fabrication process where a first workfunction metal is deposited.
- FIG. 4 shows a semiconductor structure at a subsequent point in the fabrication process where a titanium layer is deposited.
- FIG. 5 shows a semiconductor structure at a subsequent point in the fabrication process where a hardmask layer is deposited.
- FIG. 6 shows a semiconductor structure at a subsequent point in the fabrication process where a portion of the hardmask layer is removed.
- FIG. 7 shows a semiconductor structure at a subsequent point in the fabrication process where a portion of the titanium layer is removed.
- FIG. 8 shows a semiconductor structure at a subsequent point in the fabrication process where the remaining hardmask portion is removed.
- FIG. 9 shows a semiconductor structure at a subsequent point in the fabrication process where a first fill metal is deposited.
- FIG. 10 shows a semiconductor structure at a subsequent point in the fabrication process where a second workfunction metal is deposited.
- FIG. 11 shows a semiconductor structure at a subsequent point in the fabrication process where a second fill metal is deposited.
- FIG. 12 shows a semiconductor structure at a subsequent point in the fabrication process after planarization.
- FIG. 13 shows a flowchart indicating process steps in accordance with an embodiment of the present invention.
- FIG. 14 shows a block diagram of an exemplary design flow.
- FIG. 1 shows a semiconductor structure at a starting point for fabrication of an embodiment of the present invention.
- a silicon layer 102 forms the bottom of the structure.
- dielectric layer 110 Disposed on silicon layer 102 is dielectric layer 110 .
- a first gate cavity 106 and second gate cavity 104 are formed within the dielectric layer 110 .
- Spacers 108 form the interior walls of the gate cavity 104 and gate cavity 106 .
- the spacers 108 may be comprised of nitride.
- FIG. 2 shows a semiconductor structure 200 at a subsequent point in the fabrication process where gate dielectric film 212 is deposited in the first gate cavity 206 and second gate cavity 204 .
- the gate dielectric film comprises one of hafnium oxide, silicon oxide, or a compound of the form HfSiOx.
- similar elements may be referred to by similar numbers in various figures of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure.
- some reference numbers may be omitted in certain drawings.
- spacer 208 of FIG. 2 is similar to spacer 108 of FIG. 1 .
- FIG. 3 shows a semiconductor structure 300 at a subsequent point in the fabrication process where a first workfunction metal 314 is deposited in the first gate cavity 306 and the second gate cavity 304 .
- the first workfunction metal 314 may be deposited via atomic layer deposition.
- the first workfunction metal may be comprised of titanium nitride (TiN).
- FIG. 4 shows a semiconductor structure 400 at a subsequent point in the fabrication process where a titanium layer 416 is deposited in the first gate cavity 406 and the second gate cavity 404 .
- the titanium layer may be deposited via numerous methods, including, but not limited to, plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).
- PECVD plasma-enhanced chemical vapor deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- FIG. 5 shows a semiconductor structure 500 at a subsequent point in the fabrication process where a hardmask layer 518 is deposited onto the semiconductor structure 500 , filling the two gate cavities (compare with 404 and 406 of FIG. 4 ).
- FIG. 6 shows a semiconductor structure 600 at a subsequent point in the fabrication process where a portion of the hardmask layer is removed, exposing gate cavity 604 , whereas a portion of the hardmask layer 618 remains, and fills the other gate cavity.
- Industry-standard lithographic and patterning methods may be used in the application and removal of the hardmask layer.
- FIG. 7 shows a semiconductor structure 700 at a subsequent point in the fabrication process where a portion of the titanium layer is removed from gate cavity 704 , whereas a portion of the titanium layer 716 remains, and is disposed within the other gate cavity.
- the removed portion of the titanium layer may be removed from gate cavity 704 via a sputter etch.
- FIG. 8 shows a semiconductor structure 800 at a subsequent point in the fabrication process where the remaining hardmask portion (see 718 of FIG. 7 ) is removed. At this point gate cavity 804 and gate cavity 806 are both exposed. Gate cavity 806 has titanium layer 816 disposed within it, whereas gate cavity 804 does not have a corresponding titanium layer.
- FIG. 9 shows a semiconductor structure 900 at a subsequent point in the fabrication process where a first fill metal 920 is deposited.
- the first fill metal may be aluminum, and may be deposited via methods including, but not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD).
- the aluminum has selective deposition properties, and only deposits on titanium layer 916 . Hence, aluminum does not deposit in gate cavity 904 .
- the titanium layer 916 can serve two purposes. In addition to enabling the selective deposition, it can also contribute to the threshold voltage of the transistor.
- FIG. 10 shows a semiconductor structure 1000 at a subsequent point in the fabrication process where a second workfunction metal 1022 is deposited.
- the second workfunction metal 1022 is comprised of titanium aluminum nitride.
- the second workfunction metal 1022 is comprised of tantalum carbide.
- FIG. 11 shows a semiconductor structure 1100 at a subsequent point in the fabrication process where a second fill metal 1124 is deposited.
- the second fill metal 1124 is comprised of tungsten.
- the second fill metal 1124 may be comprised a material including, but not limited to, cobalt, molybdenum, ruthenium, nickel, tungsten, or combinations thereof.
- FIG. 12 shows a semiconductor structure 1200 in accordance with an embodiment of the present invention after a planarization step.
- the planarization may be performed via a chemical mechanical polish (CMP).
- CMP chemical mechanical polish
- Transistor 1244 and transistor 1246 have different fill metals.
- Transistor 1246 has fill metal 1220 which may be comprised of aluminum.
- Transistor 1244 has fill metal 1224 which may be comprised of tungsten.
- Transistor 1246 has a titanium layer 1216 disposed under fill metal 1220 , whereas transistor 1244 does not have a corresponding titanium layer disposed under fill metal 1224 .
- transistor 1244 has a second workfunction metal 1222 disposed under fill metal 1224
- transistor 1246 does not have a corresponding second workfunction metal disposed under fill metal 1220 .
- the workfunction metals used in transistor 1244 and transistor 1246 may include, but are not limited to, pure metals, nitrides, carbides, and combinations thereof.
- Such workfunction metals may include, but are not limited to, TaC, TiAl, TiAlN, WN, Ti, Ta, TaN, TaAlC, and TaAlN.
- embodiments of the present invention provide a way to achieve this goal without the disadvantages of additional masks or yield-impacting techniques that leave residual metals, which results in large threshold voltage variation amongst fabricated devices.
- embodiments of the present invention are suitable for other device types, such as “3D” structures such as FinFETs.
- FIG. 13 shows a flowchart 1350 indicating process steps in accordance with an embodiment of the present invention.
- gate cavities are formed (see 104 and 106 of FIG. 1 ).
- a gate dielectric film is deposited (see 212 of FIG. 2 ).
- a first workfunction metal is deposited (see 314 of FIG. 3 ).
- a titanium layer is deposited (see 416 of FIG. 4 ).
- a portion of the titanium layer is removed (see 716 of FIG. 7 ).
- a first fill metal is deposited (see 920 of FIG. 9 ).
- process step 1364 a second workfunction metal is deposited (see 1022 of FIG. 10 ).
- process step 1366 a second fill metal is deposited (see 1124 of FIG. 11 ).
- process step 1368 the structure is planarized (see 1200 of FIG. 12 ).
- FIG. 14 shows a block diagram of an exemplary design flow 1600 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture.
- Design flow 1600 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in FIGS. 1-13 .
- the design structures processed and/or generated by design flow 1600 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems.
- Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system.
- machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).
- Design flow 1600 may vary depending on the type of representation being designed.
- a design flow 1600 for building an application specific IC (ASIC) may differ from a design flow 1600 for designing a standard component or from a design flow 1600 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
- ASIC application specific IC
- PGA programmable gate array
- FPGA field programmable gate array
- FIG. 14 illustrates multiple such design structures including an input design structure 1620 that is preferably processed by a design process 1610 .
- Design structure 1620 may be a logical simulation design structure generated and processed by design process 1610 to produce a logically equivalent functional representation of a hardware device.
- Design structure 1620 may also or alternatively comprise data and/or program instructions that when processed by design process 1610 , generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 1620 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer.
- ECAD electronic computer-aided design
- design structure 1620 When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 1620 may be accessed and processed by one or more hardware and/or software modules within design process 1610 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in FIGS. 1-13 .
- design structure 1620 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design.
- Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.
- HDL hardware-description language
- Design process 1610 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in FIGS. 1-13 to generate a Netlist 1680 which may contain design structures such as design structure 1620 .
- Netlist 1680 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design.
- Netlist 1680 may be synthesized using an iterative process in which netlist 1680 is resynthesized one or more times depending on design specifications and parameters for the device.
- netlist 1680 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array.
- the medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
- Design process 1610 may include using a variety of inputs; for example, inputs from library elements 1630 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1640 , characterization data 1650 , verification data 1660 , design rules 1670 , and test data files 1685 (which may include test patterns and other testing information). Design process 1610 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- Design process 1610 preferably translates an embodiment of the invention as shown in FIGS. 1-13 , along with any additional integrated circuit design or data (if applicable), into a second design structure 1690 .
- Design structure 1690 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures).
- Design structure 1690 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as described above with reference to FIGS. 1-13 .
- Design structure 1690 may then proceed to a stage 1695 where, for example, design structure 1690 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
- Embodiments of the present invention utilize a selective deposition process involving titanium and aluminum to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
Abstract
A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
Description
- The present invention relates generally to semiconductor devices and more particularly to integrated circuits including metal gate MOS transistor devices and fabrication methods for making the same.
- Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric. The gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate.
- In operation of the resulting MOS transistor, the threshold voltage (Vt) is the gate voltage value required to render the channel conductive by formation of an inversion layer at the surface of the semiconductor channel. The threshold voltage is dependent upon, among other things, the workfunction difference between the gate and the substrate materials. In various circuit designs, it is desirable to have transistors with different threshold voltages within the same IC (integrated circuit) chip.
- The workfunction of a material is a measure of the energy required to move an electron in the material outside of a material atom from the Fermi level, and is usually expressed in electron volts (eV). For CMOS products, it is desirable to provide predictable, repeatable, and stable threshold voltages (Vt) for the NMOS and PMOS transistors. To establish Vt values, the workfunctions of the PMOS and NMOS gate contact and the corresponding channel materials are independently tuned or adjusted through gate and channel engineering, respectively.
- The use of different workfunction metals may be used to tune threshold voltages. However, this technique often requires additional mask levels, resulting in higher complexity and cost for fabrication. Furthermore, residual work function metals on respective devices may cause unacceptable levels of yield and device variability. Therefore, it is desirable to have an improved method and structure for achieving multiple threshold voltages within a chip.
- In one embodiment, a method for forming two transistors having different threshold voltages is provided. The method comprises forming a first gate cavity in a first transistor and a second gate cavity in a second transistor, depositing a gate dielectric film in the gate cavity of the first and second transistors, depositing a first workfunction metal in the gate cavity of the first and second transistors, depositing a titanium layer in the gate cavity of the first and second transistors, removing the titanium layer from the gate cavity of the second transistor, depositing a first fill metal in the gate cavity of the first transistor, depositing a second workfunction metal in the gate cavity of the second transistor, depositing a second fill metal in the gate cavity of the second transistor, and planarizing the first and second transistors.
- In another embodiment, a method for forming two transistors having different threshold voltages is provided. The method comprises forming a first gate cavity in a first transistor and a second gate cavity in a second transistor, depositing a gate dielectric film in the gate cavity of the first and second transistors, depositing a first workfunction metal in the gate cavity of the first and second transistors, depositing a titanium layer in the gate cavity of the first and second transistors, depositing a hardmask layer in the gate cavity of the first and second transistors, removing a portion of the hardmask layer from the gate cavity of the second transistor, removing the titanium layer from the gate cavity of the second transistor, removing the hardmask layer from the gate cavity of the first transistor, depositing a first fill metal in the gate cavity of the first transistor, depositing a second workfunction metal in the gate cavity of the second transistor, depositing a second fill metal in the gate cavity of the second transistor, and planarizing the first and second transistors.
- In another embodiment, a semiconductor structure is provided. The semiconductor structure comprises a first field effect transistor comprising a first gate cavity, a second field effect transistor comprising a second gate cavity, a first fill metal disposed in the first gate cavity, and a second fill metal disposed in the second gate cavity.
- The structure, operation, and advantages of the present invention will become further apparent upon consideration of the following description taken in conjunction with the accompanying figures (FIGs.). The figures are intended to be illustrative, not limiting.
- Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
- Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG).
-
FIG. 1 shows asemiconductor structure 100 at a starting point for fabrication of an embodiment of the present invention. -
FIG. 2 shows a semiconductor structure at a subsequent point in the fabrication process where a gate dielectric film is deposited. -
FIG. 3 shows a semiconductor structure at a subsequent point in the fabrication process where a first workfunction metal is deposited. -
FIG. 4 shows a semiconductor structure at a subsequent point in the fabrication process where a titanium layer is deposited. -
FIG. 5 shows a semiconductor structure at a subsequent point in the fabrication process where a hardmask layer is deposited. -
FIG. 6 shows a semiconductor structure at a subsequent point in the fabrication process where a portion of the hardmask layer is removed. -
FIG. 7 shows a semiconductor structure at a subsequent point in the fabrication process where a portion of the titanium layer is removed. -
FIG. 8 shows a semiconductor structure at a subsequent point in the fabrication process where the remaining hardmask portion is removed. -
FIG. 9 shows a semiconductor structure at a subsequent point in the fabrication process where a first fill metal is deposited. -
FIG. 10 shows a semiconductor structure at a subsequent point in the fabrication process where a second workfunction metal is deposited. -
FIG. 11 shows a semiconductor structure at a subsequent point in the fabrication process where a second fill metal is deposited. -
FIG. 12 shows a semiconductor structure at a subsequent point in the fabrication process after planarization. -
FIG. 13 shows a flowchart indicating process steps in accordance with an embodiment of the present invention. -
FIG. 14 shows a block diagram of an exemplary design flow. -
FIG. 1 shows a semiconductor structure at a starting point for fabrication of an embodiment of the present invention. Asilicon layer 102 forms the bottom of the structure. Disposed onsilicon layer 102 isdielectric layer 110. Afirst gate cavity 106 andsecond gate cavity 104 are formed within thedielectric layer 110.Spacers 108 form the interior walls of thegate cavity 104 andgate cavity 106. Thespacers 108 may be comprised of nitride. -
FIG. 2 shows asemiconductor structure 200 at a subsequent point in the fabrication process where gatedielectric film 212 is deposited in thefirst gate cavity 206 andsecond gate cavity 204. Most any suitable gate dielectric material can be used. In one embodiment, the gate dielectric film comprises one of hafnium oxide, silicon oxide, or a compound of the form HfSiOx. As stated previously, similar elements may be referred to by similar numbers in various figures of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure. Furthermore, for clarity, some reference numbers may be omitted in certain drawings. For example,spacer 208 ofFIG. 2 is similar tospacer 108 ofFIG. 1 . -
FIG. 3 shows asemiconductor structure 300 at a subsequent point in the fabrication process where afirst workfunction metal 314 is deposited in thefirst gate cavity 306 and thesecond gate cavity 304. Thefirst workfunction metal 314 may be deposited via atomic layer deposition. The first workfunction metal may be comprised of titanium nitride (TiN). -
FIG. 4 shows asemiconductor structure 400 at a subsequent point in the fabrication process where atitanium layer 416 is deposited in thefirst gate cavity 406 and thesecond gate cavity 404. The titanium layer may be deposited via numerous methods, including, but not limited to, plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). -
FIG. 5 shows asemiconductor structure 500 at a subsequent point in the fabrication process where ahardmask layer 518 is deposited onto thesemiconductor structure 500, filling the two gate cavities (compare with 404 and 406 ofFIG. 4 ). -
FIG. 6 shows asemiconductor structure 600 at a subsequent point in the fabrication process where a portion of the hardmask layer is removed, exposinggate cavity 604, whereas a portion of thehardmask layer 618 remains, and fills the other gate cavity. Industry-standard lithographic and patterning methods may be used in the application and removal of the hardmask layer. -
FIG. 7 shows asemiconductor structure 700 at a subsequent point in the fabrication process where a portion of the titanium layer is removed fromgate cavity 704, whereas a portion of thetitanium layer 716 remains, and is disposed within the other gate cavity. The removed portion of the titanium layer may be removed fromgate cavity 704 via a sputter etch. -
FIG. 8 shows asemiconductor structure 800 at a subsequent point in the fabrication process where the remaining hardmask portion (see 718 ofFIG. 7 ) is removed. At thispoint gate cavity 804 andgate cavity 806 are both exposed.Gate cavity 806 hastitanium layer 816 disposed within it, whereasgate cavity 804 does not have a corresponding titanium layer. -
FIG. 9 shows asemiconductor structure 900 at a subsequent point in the fabrication process where afirst fill metal 920 is deposited. The first fill metal may be aluminum, and may be deposited via methods including, but not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). The aluminum has selective deposition properties, and only deposits ontitanium layer 916. Hence, aluminum does not deposit ingate cavity 904. Thetitanium layer 916 can serve two purposes. In addition to enabling the selective deposition, it can also contribute to the threshold voltage of the transistor. -
FIG. 10 shows asemiconductor structure 1000 at a subsequent point in the fabrication process where asecond workfunction metal 1022 is deposited. In one embodiment, thesecond workfunction metal 1022 is comprised of titanium aluminum nitride. In another embodiment, thesecond workfunction metal 1022 is comprised of tantalum carbide. -
FIG. 11 shows asemiconductor structure 1100 at a subsequent point in the fabrication process where asecond fill metal 1124 is deposited. In one embodiment, thesecond fill metal 1124 is comprised of tungsten. In other embodiments, thesecond fill metal 1124 may be comprised a material including, but not limited to, cobalt, molybdenum, ruthenium, nickel, tungsten, or combinations thereof. -
FIG. 12 shows asemiconductor structure 1200 in accordance with an embodiment of the present invention after a planarization step. The planarization may be performed via a chemical mechanical polish (CMP). From this point forward, industry-standard semiconductor fabrication techniques may be used to complete the fabrication oftransistor 1244 andtransistor 1246.Transistor 1244 andtransistor 1246 have different fill metals.Transistor 1246 hasfill metal 1220 which may be comprised of aluminum.Transistor 1244 hasfill metal 1224 which may be comprised of tungsten.Transistor 1246 has atitanium layer 1216 disposed underfill metal 1220, whereastransistor 1244 does not have a corresponding titanium layer disposed underfill metal 1224. - Furthermore,
transistor 1244 has asecond workfunction metal 1222 disposed underfill metal 1224, whereastransistor 1246 does not have a corresponding second workfunction metal disposed underfill metal 1220. The workfunction metals used intransistor 1244 andtransistor 1246 may include, but are not limited to, pure metals, nitrides, carbides, and combinations thereof. Such workfunction metals may include, but are not limited to, TaC, TiAl, TiAlN, WN, Ti, Ta, TaN, TaAlC, and TaAlN. - Since the threshold voltage of a transistor is affected by both workfunction metals and fill metals, the ability to fabricate transistors on the same chip with different fill metals and workfunction metals allows for fabrication of transistors on the same chip with different threshold voltages. For design purposes, it is often desirable to have transistors with different threshold voltages on the same chip. Hence, embodiments of the present invention provide a way to achieve this goal without the disadvantages of additional masks or yield-impacting techniques that leave residual metals, which results in large threshold voltage variation amongst fabricated devices. Furthermore, while the example disclosed illustrated use of an embodiment of the invention with a planar technology such as ETSOI (extremely thin silicon-on-insulator), embodiments of the present invention are suitable for other device types, such as “3D” structures such as FinFETs.
-
FIG. 13 shows aflowchart 1350 indicating process steps in accordance with an embodiment of the present invention. Inprocess step 1352, gate cavities are formed (see 104 and 106 ofFIG. 1 ). Inprocess step 1354, a gate dielectric film is deposited (see 212 ofFIG. 2 ). Inprocess step 1356, a first workfunction metal is deposited (see 314 ofFIG. 3 ). Inprocess step 1358, a titanium layer is deposited (see 416 ofFIG. 4 ). Inprocess step 1360, a portion of the titanium layer is removed (see 716 ofFIG. 7 ). Inprocess step 1362, a first fill metal is deposited (see 920 ofFIG. 9 ). Inprocess step 1364, a second workfunction metal is deposited (see 1022 ofFIG. 10 ). Inprocess step 1366, a second fill metal is deposited (see 1124 ofFIG. 11 ). Inprocess step 1368, the structure is planarized (see 1200 ofFIG. 12 ). -
FIG. 14 shows a block diagram of anexemplary design flow 1600 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture.Design flow 1600 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown inFIGS. 1-13 . The design structures processed and/or generated bydesign flow 1600 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array). -
Design flow 1600 may vary depending on the type of representation being designed. For example, adesign flow 1600 for building an application specific IC (ASIC) may differ from adesign flow 1600 for designing a standard component or from adesign flow 1600 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc. -
FIG. 14 illustrates multiple such design structures including aninput design structure 1620 that is preferably processed by adesign process 1610.Design structure 1620 may be a logical simulation design structure generated and processed bydesign process 1610 to produce a logically equivalent functional representation of a hardware device.Design structure 1620 may also or alternatively comprise data and/or program instructions that when processed bydesign process 1610, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features,design structure 1620 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium,design structure 1620 may be accessed and processed by one or more hardware and/or software modules withindesign process 1610 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 1-13 . As such,design structure 1620 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. -
Design process 1610 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown inFIGS. 1-13 to generate aNetlist 1680 which may contain design structures such asdesign structure 1620.Netlist 1680 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design.Netlist 1680 may be synthesized using an iterative process in which netlist 1680 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein,netlist 1680 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means. -
Design process 1610 may include using a variety of inputs; for example, inputs fromlibrary elements 1630 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.),design specifications 1640,characterization data 1650,verification data 1660,design rules 1670, and test data files 1685 (which may include test patterns and other testing information).Design process 1610 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used indesign process 1610 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow. -
Design process 1610 preferably translates an embodiment of the invention as shown inFIGS. 1-13 , along with any additional integrated circuit design or data (if applicable), into asecond design structure 1690.Design structure 1690 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures).Design structure 1690 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as described above with reference toFIGS. 1-13 .Design structure 1690 may then proceed to astage 1695 where, for example, design structure 1690: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. - Embodiments of the present invention utilize a selective deposition process involving titanium and aluminum to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
- Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, certain equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.) the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application.
Claims (8)
1-13. (canceled)
14. A semiconductor structure comprising:
a first field effect transistor comprising a first gate cavity;
a second field effect transistor comprising a second gate cavity;
a first fill metal disposed in the first gate cavity; and
a second fill metal disposed in the second gate cavity.
15. The semiconductor structure of claim 14 , wherein the first fill metal comprises aluminum.
16. The semiconductor structure of claim 15 , wherein the second fill metal comprises tungsten.
17. The semiconductor structure of claim 15 , wherein a titanium layer is disposed under the first fill metal and is not disposed under the second fill metal.
18. The semiconductor structure of claim 17 , further comprising a first workfunction metal disposed under the titanium layer, and a second workfunction metal disposed under the second fill metal.
19. The semiconductor structure of claim 18 , wherein the first workfunction metal comprises titanium nitride.
20. The semiconductor structure of claim 18 , wherein the second workfunction metal is comprised of a material selected from the group consisting of titanium aluminum nitride and tantalum carbide.
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2012
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2013
- 2013-11-26 US US14/089,982 patent/US20140084382A1/en not_active Abandoned
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US20110198699A1 (en) * | 2010-02-17 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated semiconductor structure for sram and fabrication methods thereof |
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US8796128B2 (en) | 2014-08-05 |
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