US20140002166A1 - Accurate low-power delay circuit - Google Patents
Accurate low-power delay circuit Download PDFInfo
- Publication number
- US20140002166A1 US20140002166A1 US13/551,835 US201213551835A US2014002166A1 US 20140002166 A1 US20140002166 A1 US 20140002166A1 US 201213551835 A US201213551835 A US 201213551835A US 2014002166 A1 US2014002166 A1 US 2014002166A1
- Authority
- US
- United States
- Prior art keywords
- delay
- capacitor
- circuitry
- circuit
- delay circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/00143—Avoiding variations of delay due to temperature
Definitions
- the present invention relates to delay circuits and, in particular, to delay circuits for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.
- Delay circuits are an important part of both analog and digital systems.
- a common approach to implementing a delay circuit involves delaying an input signal using a reference current (or resistor) and capacitor, and comparing the resulting signal to a reference voltage using a comparator to generate the delayed version of the input. Assuming the use of components that are stable over voltage and temperature, such an approach can be used to provide very accurate and stable delay circuits.
- the use of a comparator and the associated reference voltage circuit consumes considerable die area and requires some amount of quiescent current.
- a delay circuit includes first delay circuitry configured to receive an input signal and generate an intermediate signal.
- the first delay circuitry includes a first capacitor, first charging circuitry configured to charge and discharge the first capacitor in response to the input signal, and a first gate circuit having a first threshold voltage.
- the first delay circuitry contributes a first delay component of a total delay through the delay circuit.
- Second delay circuitry is configured to receive the intermediate signal and generate an output signal.
- the second delay circuitry includes a second capacitor, second charging circuitry configured to charge and discharge the second capacitor in response to the intermediate signal, and a second gate circuit having a second threshold voltage.
- the second delay circuitry contributes a second delay component of the total delay.
- the first and second threshold voltages of the first and second gate circuits change in response to a temperature change or a supply voltage change such that a resulting change in the first delay component of the total delay is substantially offset by a resulting change in the second delay component of the total delay such that the total delay remains substantially constant.
- a delay circuit includes first delay circuitry configured to receive an input signal and generate an intermediate signal.
- the first delay circuitry contributes a first delay component of a total delay through the delay circuit.
- Second delay circuitry is configured to receive the intermediate signal and generate an output signal.
- the second delay circuitry contributes a second delay component of the total delay.
- a first operational parameter of the first delay circuitry and a second operational parameter of the second delay circuitry change in response to a temperature change or a supply voltage change such that a resulting change in the first delay component of the total delay is substantially offset by a resulting change in the second delay component of the total delay such that the total delay remains substantially constant.
- a method of operating a delay circuit includes first delay circuitry configured to receive an input signal and generate an intermediate signal.
- the first delay circuitry also includes a first gate circuit having a first threshold voltage, and a first capacitor coupled between an input of the first gate circuit and a supply voltage of the delay circuit.
- the delay circuit further includes second delay circuitry configured to receive the intermediate signal and generate an output signal.
- the second delay circuitry includes a second gate circuit having a second threshold voltage, and a second capacitor coupled between an input of the second gate circuit and a reference of the delay circuit.
- the first capacitor is charged and discharged in response to transitions of the input signal.
- the first delay circuitry contributes a first delay component of a total delay through the delay circuit.
- the second capacitor is charged and discharged in response to transitions of the intermediate signal corresponding to the transitions of the input signal.
- the second delay circuitry contributes a second delay component of the total delay.
- the first and second threshold voltages of the first and second gate circuits change in response to a temperature change or a supply voltage change such that a resulting change in the first delay component of the total delay is substantially offset by a resulting change in the second delay component of the total delay such that the total delay remains substantially constant.
- FIG. 1 is a simplified schematic diagram of a specific implementation of a delay circuit.
- FIG. 2 shows waveforms illustrating operation of a specific implementation of a delay circuit.
- FIG. 3 shows waveforms illustrating operation of a specific implementation of a delay circuit.
- FIG. 4 is a simplified schematic diagram of a specific implementation of a delay circuit.
- FIG. 1 is a schematic diagram of a specific implementation of a delay circuit 100 that includes a first delay circuit referred to as “Dly 1 Block” that generates a first component of a total delay, and a second delay circuit referred to as “Dly 2 Block” that generates a second component of the total delay.
- the depicted delay circuit does not employ a comparator or reference voltage and therefore does not require quiescent current.
- an accurate and stable (e.g., over voltage and temperature) delay may be achieved with delay circuit 100 without the area penalty associated with conventional delay circuits.
- delay circuit 100 may be understood with reference to the waveforms of FIG. 2 .
- the input voltage IN is low (e.g., 0 volts)
- pmos device 102 is on and pulls the input of inverter 104 up to near Vsupply (e.g., 5 volts), i.e., voltage VC 1 is high.
- the voltage INDLY tracks VC 1 through inverters 104 and 106 and is therefore also high.
- nmos device 108 is on and pulls the voltage VC 2 at input of inverter 110 down toward the circuit's reference voltage, e.g., ground.
- the output voltage OUT (through the double inversion of inverters 110 and 112 ) is therefore also low.
- the time difference between the rising edge of the input voltage IN and the rising edge of the output voltage OUT is the total delay (“Delay”) through delay circuit 100 .
- this total delay has two components, one denoted “Dly 1 ” contributed by the “Dly 1 Block” and one denoted “Dly 2 ” contributed by the “Dly 2 Block.”
- Dly 1 the total delay
- Dly 2 the total delay
- the relevance of these two delay components to the stability of the total delay through delay circuit 100 will become apparent with reference to the following description.
- the degree to which the values of R 1 , C 1 , R 2 , and C 2 are stable will determine the consistency and stability of the voltages VC 1 and VC 2 , and is at least partially determinative of the stability of the total delay through delay circuit 100 .
- the precision and stability of these components may be selected to support a desired level of stability for the total delay for a given application.
- the values of these components are selected such that the time constants R 1 *C 1 and R 2 *C 2 are substantially the same (taking into account the tolerance of the components used).
- Vth the voltages at which inverters 104 and 110 switch, i.e., Vth
- Vth the voltages at which inverters 104 and 110 switch
- the operational parameters of inverters 104 and 110 are sufficiently matched (sufficient for a desired level of stability)
- the effect of the variations in Vth on the total delay may be substantially reduced. That is, the total delay may be held substantially constant (within the desired range) even though the delay components Dly 1 and Dly 2 vary. How this is accomplished may be understood with reference to FIG. 3 .
- FIG. 3 shows the waveforms for VC 1 and VC 2 for two different conditions.
- the top set of waveforms largely corresponds to the condition represented by the waveforms of FIG. 2 .
- the bottom set of waveforms illustrates the condition in which the respective threshold voltages, Vth, of inverters 104 and 110 have increased, e.g., due to a change in temperature.
- Vth the respective threshold voltages
- the inverters have been selected or fabricated to ensure that their operational parameters are matched to a desired level of precision
- their respective threshold voltages respond substantially similarly to whatever stimulus or environmental condition causes the change. For example, Vth will change substantially the same amount for both inverters in response to a temperature change experienced by both. Again, some variation between the two may be acceptable depending on the level of stability desired.
- the effect of the increase in the Vth of inverter 104 is that inverter 104 switches sooner than in the upper set of waveforms, and the delay component Dly 1 is correspondingly reduced.
- the effect of the increase in the Vth of inverter 110 is that inverter 110 switches later, and the delay component Dly 2 is correspondingly increased.
- the reduction in delay component Dly 1 is substantially offset by the increase in delay component Dly 2 , resulting in the total delay being held substantially constant (within the desired range).
- delay circuits designed as described herein may have a substantially constant delay over a significant temperature range.
- the curves of VC 1 and VC 2 for the depicted implementation are not straight lines and that therefore there may be some variation between the size of the decrease of one delay component as compared to the size of the offsetting increase of the other delay component even where the change in Vth is identical. It should also be noted that the drawings are not necessarily to scale and that for a given range of variation in Vth and a given acceptable range of stability in the total delay, the approximation of these curves as straight lines is a good one for most cases.
- the total delay through the delay circuit is dependent on the values of R 1 , C 1 , R 2 , and C 2 , and therefore the contribution of these components to the variability of the total delay may be controlled to a desired degree of precision by careful selection and/or manufacture of these components.
- the delay components Dly 1 and Dly 2 are also dependent on the supply voltage (Vsupply). But because the threshold voltage (Vth) of an inverter changes proportionally with its supply voltage, any increase in Vsupply will have a similar effect on the threshold voltages of inverters 104 and 110 .
- delay circuits designed as described herein may also be substantially immune to changes in supply voltage.
- delay circuit 400 An alternative implementation of a delay circuit is illustrated in FIG. 4 .
- the operation of delay circuit 400 is similar to that of delay circuit 100 of FIG. 1 with the primary difference relating to the use of current sources Ic (where Ic is proportional to Vsupply) to charge the capacitors in each block.
- Ic current sources
- inverters 404 and 410 are sufficiently well matched, changes in their respective threshold voltages will track over voltage and temperature, resulting in the desired level of stability for the total delay through delay circuit 400 .
- delay circuits as described herein may be characterized by one or more advantages. For example, because comparators and reference voltages are not required, a significant reduction in the silicon area required to implement a delay circuit may be realized. In another example, because no voltage reference is required, placement of the delay circuit is not constrained by the necessity to connect with a reference. This is particular useful in the digital design domain. So, it should be understood that various implementations may be equally suitable for use in analog or digital systems. In another example, delay circuits may be implemented entirely with components which do not require quiescent current, therefore reducing overall system power dissipation.
- Delay circuits as described herein may be represented (without limitation) in software (object code or machine code in non-transitory computer-readable media), in varying stages of compilation, as one or more netlists (e.g., a SPICE netlist), in a simulation language, in a hardware description language (e.g., Verilog, VHDL), by a set of semiconductor processing masks, and as partially or completely realized semiconductor devices (e.g., an ASIC).
- netlists e.g., a SPICE netlist
- VHDL hardware description language
- semiconductor processing masks e.g., Verilog, VHDL
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Abstract
Description
- The present application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/667,266 filed Jul. 2, 2012 (Attorney Docket No. SNDKP634P/SDD-1974P), the entire disclosure of which is incorporated herein by reference for all purposes.
- The present invention relates to delay circuits and, in particular, to delay circuits for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.
- Delay circuits are an important part of both analog and digital systems. A common approach to implementing a delay circuit involves delaying an input signal using a reference current (or resistor) and capacitor, and comparing the resulting signal to a reference voltage using a comparator to generate the delayed version of the input. Assuming the use of components that are stable over voltage and temperature, such an approach can be used to provide very accurate and stable delay circuits. However, the use of a comparator and the associated reference voltage circuit consumes considerable die area and requires some amount of quiescent current.
- According to the present invention, a delay circuit is provided. According to a particular implementation, a delay circuit includes first delay circuitry configured to receive an input signal and generate an intermediate signal. The first delay circuitry includes a first capacitor, first charging circuitry configured to charge and discharge the first capacitor in response to the input signal, and a first gate circuit having a first threshold voltage. The first delay circuitry contributes a first delay component of a total delay through the delay circuit. Second delay circuitry is configured to receive the intermediate signal and generate an output signal. The second delay circuitry includes a second capacitor, second charging circuitry configured to charge and discharge the second capacitor in response to the intermediate signal, and a second gate circuit having a second threshold voltage. The second delay circuitry contributes a second delay component of the total delay. The first and second threshold voltages of the first and second gate circuits change in response to a temperature change or a supply voltage change such that a resulting change in the first delay component of the total delay is substantially offset by a resulting change in the second delay component of the total delay such that the total delay remains substantially constant.
- According to another implementation, a delay circuit includes first delay circuitry configured to receive an input signal and generate an intermediate signal. The first delay circuitry contributes a first delay component of a total delay through the delay circuit. Second delay circuitry is configured to receive the intermediate signal and generate an output signal. The second delay circuitry contributes a second delay component of the total delay. A first operational parameter of the first delay circuitry and a second operational parameter of the second delay circuitry change in response to a temperature change or a supply voltage change such that a resulting change in the first delay component of the total delay is substantially offset by a resulting change in the second delay component of the total delay such that the total delay remains substantially constant.
- According to another implementation, a method of operating a delay circuit is provided. The delay circuit includes first delay circuitry configured to receive an input signal and generate an intermediate signal. The first delay circuitry also includes a first gate circuit having a first threshold voltage, and a first capacitor coupled between an input of the first gate circuit and a supply voltage of the delay circuit. The delay circuit further includes second delay circuitry configured to receive the intermediate signal and generate an output signal. The second delay circuitry includes a second gate circuit having a second threshold voltage, and a second capacitor coupled between an input of the second gate circuit and a reference of the delay circuit. The first capacitor is charged and discharged in response to transitions of the input signal. The first delay circuitry contributes a first delay component of a total delay through the delay circuit. The second capacitor is charged and discharged in response to transitions of the intermediate signal corresponding to the transitions of the input signal. The second delay circuitry contributes a second delay component of the total delay. The first and second threshold voltages of the first and second gate circuits change in response to a temperature change or a supply voltage change such that a resulting change in the first delay component of the total delay is substantially offset by a resulting change in the second delay component of the total delay such that the total delay remains substantially constant.
- A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
-
FIG. 1 is a simplified schematic diagram of a specific implementation of a delay circuit. -
FIG. 2 shows waveforms illustrating operation of a specific implementation of a delay circuit. -
FIG. 3 shows waveforms illustrating operation of a specific implementation of a delay circuit. -
FIG. 4 is a simplified schematic diagram of a specific implementation of a delay circuit. - Reference will now be made in detail to specific embodiments of the invention including the best modes contemplated by the inventors for carrying out the invention. Examples of these specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In addition, well known features may not have been described in detail to avoid unnecessarily obscuring the invention.
-
FIG. 1 is a schematic diagram of a specific implementation of adelay circuit 100 that includes a first delay circuit referred to as “Dly1 Block” that generates a first component of a total delay, and a second delay circuit referred to as “Dly2 Block” that generates a second component of the total delay. As can be seen, the depicted delay circuit does not employ a comparator or reference voltage and therefore does not require quiescent current. And as will be discussed, an accurate and stable (e.g., over voltage and temperature) delay may be achieved withdelay circuit 100 without the area penalty associated with conventional delay circuits. - The operation of
delay circuit 100 may be understood with reference to the waveforms ofFIG. 2 . When the input voltage IN is low (e.g., 0 volts),pmos device 102 is on and pulls the input ofinverter 104 up to near Vsupply (e.g., 5 volts), i.e., voltage VC1 is high. The voltage INDLY tracks VC1 throughinverters nmos device 108 is on and pulls the voltage VC2 at input ofinverter 110 down toward the circuit's reference voltage, e.g., ground. The output voltage OUT (through the double inversion ofinverters 110 and 112) is therefore also low. - When input voltage IN goes high,
pmos device 102 turns off andnmos device 114 turns on, charging capacitor C1 through resistor R1. As a result, the voltage VC1 falls close to ground according to a time constant based largely on R1 and C1 as shown inFIG. 2 . When the voltage at VC1 crosses the threshold voltage Vth ofinverter 104, bothinverters - When INDLY goes low,
nmos device 108 turns off andpmos device 116 turns on, charging capacitor C2 through resistor R2. As a result, the voltage VC2 rises close to Vsupply according to a time constant based largely on R2 and C2. When VC2 crosses Vth ofinverter 110, bothinverters - The time difference between the rising edge of the input voltage IN and the rising edge of the output voltage OUT is the total delay (“Delay”) through
delay circuit 100. As can be seen inFIG. 2 , this total delay has two components, one denoted “Dly1” contributed by the “Dly1 Block” and one denoted “Dly2” contributed by the “Dly2 Block.” The relevance of these two delay components to the stability of the total delay throughdelay circuit 100 will become apparent with reference to the following description. - The degree to which the values of R1, C1, R2, and C2 are stable (e.g., over voltage and temperature) will determine the consistency and stability of the voltages VC1 and VC2, and is at least partially determinative of the stability of the total delay through
delay circuit 100. Thus, the precision and stability of these components may be selected to support a desired level of stability for the total delay for a given application. According to various embodiments, the values of these components are selected such that the time constants R1*C1 and R2*C2 are substantially the same (taking into account the tolerance of the components used). - On the other hand, the voltages at which
inverters inverters FIG. 3 . -
FIG. 3 shows the waveforms for VC1 and VC2 for two different conditions. The top set of waveforms largely corresponds to the condition represented by the waveforms ofFIG. 2 . The bottom set of waveforms illustrates the condition in which the respective threshold voltages, Vth, ofinverters - As can be seen in
FIG. 3 , the effect of the increase in the Vth ofinverter 104 is thatinverter 104 switches sooner than in the upper set of waveforms, and the delay component Dly1 is correspondingly reduced. On the other hand, the effect of the increase in the Vth ofinverter 110 is thatinverter 110 switches later, and the delay component Dly2 is correspondingly increased. However, because the change in Vth for each inverter is similar, the reduction in delay component Dly1 is substantially offset by the increase in delay component Dly2, resulting in the total delay being held substantially constant (within the desired range). Thus, delay circuits designed as described herein may have a substantially constant delay over a significant temperature range. - It should be noted that the curves of VC1 and VC2 for the depicted implementation are not straight lines and that therefore there may be some variation between the size of the decrease of one delay component as compared to the size of the offsetting increase of the other delay component even where the change in Vth is identical. It should also be noted that the drawings are not necessarily to scale and that for a given range of variation in Vth and a given acceptable range of stability in the total delay, the approximation of these curves as straight lines is a good one for most cases.
- As discussed above, the total delay through the delay circuit is dependent on the values of R1, C1, R2, and C2, and therefore the contribution of these components to the variability of the total delay may be controlled to a desired degree of precision by careful selection and/or manufacture of these components. However, the delay components Dly1 and Dly2 are also dependent on the supply voltage (Vsupply). But because the threshold voltage (Vth) of an inverter changes proportionally with its supply voltage, any increase in Vsupply will have a similar effect on the threshold voltages of
inverters inverters - An alternative implementation of a delay circuit is illustrated in
FIG. 4 . As can be seen, the operation ofdelay circuit 400 is similar to that ofdelay circuit 100 ofFIG. 1 with the primary difference relating to the use of current sources Ic (where Ic is proportional to Vsupply) to charge the capacitors in each block. Again, becauseinverters delay circuit 400. - Various implementations of delay circuits as described herein may be characterized by one or more advantages. For example, because comparators and reference voltages are not required, a significant reduction in the silicon area required to implement a delay circuit may be realized. In another example, because no voltage reference is required, placement of the delay circuit is not constrained by the necessity to connect with a reference. This is particular useful in the digital design domain. So, it should be understood that various implementations may be equally suitable for use in analog or digital systems. In another example, delay circuits may be implemented entirely with components which do not require quiescent current, therefore reducing overall system power dissipation.
- While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, various implementations are contemplated as being implemented using any of a variety of standard or proprietary CMOS processes. However, it should be noted that implementations are contemplated that may employ a much wider range of semiconductor materials and manufacturing processes including, for example, GaAs, SiGe, etc. Delay circuits as described herein may be represented (without limitation) in software (object code or machine code in non-transitory computer-readable media), in varying stages of compilation, as one or more netlists (e.g., a SPICE netlist), in a simulation language, in a hardware description language (e.g., Verilog, VHDL), by a set of semiconductor processing masks, and as partially or completely realized semiconductor devices (e.g., an ASIC). The various alternatives for each of the foregoing as understood by those of skill in the art are also within the scope of the invention.
- Finally, although various advantages, aspects, and objects of the present invention have been discussed herein with reference to various embodiments, it will be understood that the scope of the invention should not be limited by reference to such advantages, aspects, and objects. Rather, the scope of the invention should be determined with reference to the appended claims.
Claims (15)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/551,835 US8624652B1 (en) | 2012-07-02 | 2012-07-18 | Accurate low-power delay circuit |
CN201380040114.2A CN104508979B (en) | 2012-07-02 | 2013-06-19 | Accurate low-power delay circuit |
PCT/US2013/046547 WO2014007989A1 (en) | 2012-07-02 | 2013-06-19 | Accurate low-power delay circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261667266P | 2012-07-02 | 2012-07-02 | |
US13/551,835 US8624652B1 (en) | 2012-07-02 | 2012-07-18 | Accurate low-power delay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20140002166A1 true US20140002166A1 (en) | 2014-01-02 |
US8624652B1 US8624652B1 (en) | 2014-01-07 |
Family
ID=49777494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/551,835 Active US8624652B1 (en) | 2012-07-02 | 2012-07-18 | Accurate low-power delay circuit |
Country Status (3)
Country | Link |
---|---|
US (1) | US8624652B1 (en) |
CN (1) | CN104508979B (en) |
WO (1) | WO2014007989A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7465200B2 (en) * | 2020-11-17 | 2024-04-10 | エイブリック株式会社 | Delay Circuit |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068553A (en) * | 1988-10-31 | 1991-11-26 | Texas Instruments Incorporated | Delay stage with reduced Vdd dependence |
US5955907A (en) | 1995-03-03 | 1999-09-21 | Advantest Corp. | Temperature compensation circuit and method for providing a constant delay |
JP2000013204A (en) * | 1998-06-18 | 2000-01-14 | Fujitsu Ltd | Delay circuit and oscillation circuit using the delay circuit |
KR100331257B1 (en) | 1998-06-30 | 2002-08-21 | 주식회사 하이닉스반도체 | Delay circuit with constant delay |
WO2001044913A1 (en) | 1999-12-15 | 2001-06-21 | Hitachi, Ltd. | Interface device and information processing system |
US6747500B2 (en) * | 2001-10-19 | 2004-06-08 | Mitutoyo Corporation | Compact delay circuit for CMOS integrated circuits used in low voltage low power devices |
KR100512934B1 (en) | 2002-01-09 | 2005-09-07 | 삼성전자주식회사 | Semiconductor memory device |
US6753708B2 (en) * | 2002-06-13 | 2004-06-22 | Hewlett-Packard Development Company, L.P. | Driver circuit connected to pulse shaping circuitry and method of operating same |
KR100532507B1 (en) | 2004-03-05 | 2005-11-30 | 삼성전자주식회사 | Amplifier having stable output swing width and stable delay time |
CN100353667C (en) * | 2004-11-16 | 2007-12-05 | 矽成积体电路股份有限公司 | Input buffer circuit for stabilizing logic converting point |
US7208991B2 (en) * | 2005-01-28 | 2007-04-24 | Altera Corporation | Digitally programmable delay circuit with process point tracking |
JP4971699B2 (en) * | 2006-06-26 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | Delay circuit |
US7557631B2 (en) | 2006-11-07 | 2009-07-07 | Micron Technology, Inc. | Voltage and temperature compensation delay system and method |
US7932764B2 (en) * | 2007-12-06 | 2011-04-26 | Elite Semiconductor Memory Technology Inc. | Delay circuit with constant time delay independent of temperature variations |
JP2011138571A (en) | 2009-12-26 | 2011-07-14 | Elpida Memory Inc | Nonvolatile semiconductor memory and control method of the same |
-
2012
- 2012-07-18 US US13/551,835 patent/US8624652B1/en active Active
-
2013
- 2013-06-19 CN CN201380040114.2A patent/CN104508979B/en active Active
- 2013-06-19 WO PCT/US2013/046547 patent/WO2014007989A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US8624652B1 (en) | 2014-01-07 |
CN104508979A (en) | 2015-04-08 |
CN104508979B (en) | 2017-07-07 |
WO2014007989A1 (en) | 2014-01-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9356554B2 (en) | Relaxation oscillator with current and voltage offset cancellation | |
US20160112042A1 (en) | Gate Leakage Based Low Power Circuits | |
KR101293845B1 (en) | Delay circuit | |
US20080180154A1 (en) | Digital delay circuit | |
US20120044021A1 (en) | Differential amplifier circuit | |
US8941437B2 (en) | Bias circuit | |
US20140111259A1 (en) | Power-on reset circuit | |
US8692623B2 (en) | Relaxation oscillator circuit including two clock generator subcircuits having same configuration operating alternately | |
JP3338758B2 (en) | Delay circuit | |
CN109690948B (en) | Method and apparatus for low power relaxation oscillator | |
US6894467B2 (en) | Linear voltage regulator | |
JP2002033651A (en) | Load capacitance measurement circuit and output buffer | |
CN106961266B (en) | Power-on reset circuit | |
US8624652B1 (en) | Accurate low-power delay circuit | |
US9401719B2 (en) | Oscillator circuit and method of providing temperature compensation therefor | |
US10879858B2 (en) | Oscillator circuit using comparator | |
KR20160108433A (en) | Sizing power-gated sections by constraining voltage droop | |
US10812059B2 (en) | Comparator | |
CN112583355A (en) | High-precision relaxation oscillator | |
TWI629492B (en) | System and method for testing reference voltage circuit | |
US20140300191A1 (en) | Semiconductor integrated circuit and method of controlling power supply | |
CN117767923A (en) | Delay circuit and semiconductor device | |
US20150200653A1 (en) | Power-on reset circuit | |
WO2002015382A2 (en) | Oscillator having reduced sensitivity to supply voltage changes | |
Rjoub et al. | An efficient low-power bus architecture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BHUIYAN, EKRAM H.;CHI, STEVE X.;REEL/FRAME:028581/0790 Effective date: 20120716 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES LLC, TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038807/0898 Effective date: 20160516 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |