US20130336021A1 - Variable frequency timing circuit for a power supply control circuit - Google Patents
Variable frequency timing circuit for a power supply control circuit Download PDFInfo
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- US20130336021A1 US20130336021A1 US13/971,605 US201313971605A US2013336021A1 US 20130336021 A1 US20130336021 A1 US 20130336021A1 US 201313971605 A US201313971605 A US 201313971605A US 2013336021 A1 US2013336021 A1 US 2013336021A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
Abstract
A timing circuit of a controller generates a clock signal having a switching period for use by a pulse width modulation (PWM) circuit to control a switch of a power supply. The switching period of the clock signal is based on a charging time plus a discharging time of a capacitor included in the timing circuit. A first current source charges the capacitor while the timing circuit is in a normal charging mode. A second current source charges the capacitor while the timing circuit is in an alternative charging mode that is when the on time of the switch exceeds a threshold time. The current provided by the second current source is less than the current provided by the first current source such that the switching period of the clock signal is increased in response to the timing circuit entering the alternative charging mode.
Description
- This application is a continuation of U.S. patent application Ser. No. 13/193,434, filed Jul. 28, 2011, now pending. U.S. patent application Ser. No. 13/193,434 is hereby incorporated by reference. This application is also related to co-pending U.S. application Ser. No. 13/193,411, attorney docket no. 5510P210, entitled “Varying Switching Frequency and Period of a Power Supply Controller,” filed on Jul. 28, 2011.
- 1. Field of the Invention
- The present invention relates generally to power supplies, and more specifically, the present invention relates to controllers for switched mode power supplies.
- 2. Background
- Electronic devices use power to operate. Switched mode power supplies are commonly used due to their high efficiency, small size and low weight to power many of today's electronics. Conventional wall sockets provide a high voltage alternating current. In a switching power supply a high voltage alternating current (ac) input is converted to provide a well regulated direct current (dc) output through an energy transfer element. In operation, a switch is utilized to provide the desired output by varying the duty cycle (typically the ratio of the on-time of the switch to the total switching period), varying the switching frequency or varying the number of pulses per unit time of the switch in a switched mode power supply.
- The switched mode power supply also includes a controller which usually provides output regulation by sensing and controlling the output in a closed loop. The controller may receive a feedback signal representative of the output and the controller varies one or more parameters in response to the feedback signal to regulate the output to a desired quantity. Various modes of control may be utilized. One mode of control is known as pulse width modulation (PWM) peak current mode control. In PWM peak current mode control, the switch remains on until the current in the switch reaches a current limit. Once the current limit is reached, the controller turns the switch off for the remainder of the switching period. In general, a higher current limit results in a longer on-time of the switch and a bigger duty ratio. However, for controllers operating in continuous conduction mode (CCM) with large duty ratios (typically for duty ratios greater than 50%), small error signal perturbations may cause sub-harmonic oscillation to occur.
- Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
-
FIG. 1 is a diagram illustrating an example switched mode power supply utilizing a controller, in accordance with embodiments of the present invention. -
FIG. 2A is a diagram illustrating an example switching current waveform of the switched mode power supply ofFIG. 1 . -
FIG. 2B is a diagram illustrating a further example of a switching current waveform of the switched mode power supply ofFIG. 1 utilizing current mode pulse width modulation (PWM) control. -
FIG. 3 is a diagram illustrating an example switching current waveform ofFIG. 1 utilizing a control scheme in accordance with embodiments of the present invention. -
FIG. 4 is a block diagram illustrating a controller in accordance with embodiments of the present invention. -
FIG. 5A is a diagram illustrating an example voltage waveform of the timing circuit ofFIG. 4 . -
FIG. 5B is a diagram illustrating another example voltage waveform of the timing circuit ofFIG. 4 . -
FIG. 5C is a diagram illustrating another example voltage waveform utilizing a non-linear slope of the timing circuit ofFIG. 4 . -
FIG. 6 is a diagram illustrating various embodiments of the voltage waveform ofFIGS. 5A and 5B . -
FIG. 7 is a function block diagram of a timing circuit, in accordance with embodiments of the present invention. -
FIG. 8 is a timing diagram illustrating various waveforms of voltages and currents of the timing circuit ofFIG. 7 . -
FIG. 9 is a functional block diagram of a timing circuit, in accordance with embodiments of the present invention. -
FIG. 10 is a timing diagram illustrating various waveforms of voltages and currents of the timing circuit ofFIG. 9 . - Embodiments of a controller with a variable switching frequency and period are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
- Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
- Various modes of control may be utilized to regulate the output of a power supply. One mode of control is known as pulse width modulation (PWM) current mode control. In PWM current mode control, the switch remains on until the current in the switch reaches a current limit or the maximum duty ratio has been reached. In one embodiment, the current limit is the peak current of the switch. Once the current limit is reached, the controller turns the switch off for the remainder of the switching period. In general, a higher current limit results in a longer on-time of the switch and a larger duty ratio. However, for controllers operating in continuous conduction mode (CCM) with large duty ratios (typically for duty ratios greater than 50%), small error signal perturbations may cause sub-harmonic oscillation to occur. In particular, sub-harmonic oscillation may occur for conventional PWM current mode control where the switching frequency (and therefore the switching period TS) does not vary.
- Typical methods to prevent sub-harmonic oscillation include varying the current limit with the duty ratio. In such a case, the current limit is not fixed and the current limit is a linearly decreasing ramp as the duty ratio increases. This is typically known as slope compensation. However, there are disadvantages to utilizing slope compensation. For example, in continuous conduction mode (CCM), output power is proportional to the peak current of the switch and the peak current decreases as the current limit linearly decreases. As a result the output power would decrease for high duty ratios. Slope compensation also erodes the loop bandwidth and phase margin benefits of PWM current mode control. To offset the decrease in output power, the current limit may be increased overall. However, power supply components, such as the switch, transformer, clamp circuit, and output rectifier, would need to be rated for higher current values. This approach has its drawbacks, since the higher the current rating for a component typically means an increase in the size of the component. As a result, utilizing current limit slope compensation would result in tradeoffs between size and output power.
- With conventional PWM peak current mode control, where the switching frequency is not varied by the controller, sub-harmonic oscillation may occur at high duty ratios when in continuous conduction mode. As a result of sub-harmonic oscillation, the off-times of the switch may vary dramatically from one switching period to the next creating large ripple at the output voltage. Sub-harmonic oscillation may also reduce the maximum output power capability of the power supply. Thus, embodiments of the present invention reduce the likelihood of sustained sub-harmonic oscillation and the resultant large variations in off-time by varying the switching frequency (and therefore the switching period TS) after some critical time tC when sub-harmonic oscillation may occur. In one embodiment, the total switching period TS is varied by a multiple of the difference between the on-time tON and the critical time tC. In a further embodiment, the off-time tOFF of the switch is varied by a multiple of the difference between the on-time tON and the critical time tC.
- In one embodiment, the multiple is a fractional amount. In one example, this results in a substantially fixed off-time tOFF over consecutive switching cycles. By varying the switching frequency when the on-time is greater than the critical time tC, the likelihood of sustained sub-harmonic oscillation is reduced. As will be further discussed, embodiments of the present invention include altering a timing circuit voltage to vary the switching frequency.
- Referring first to
FIG. 1 , a diagram of an example switchedmode power supply 100 is illustrated includinginput V IN 102, an energytransfer element T1 104, a primary winding 106 of the energytransfer element T1 104, a secondary winding 108 of the energytransfer element T1 104, aswitch S1 110, aclamp circuit 112, arectifier D1 114, anoutput capacitor C1 116, aload 118, an output quantity UO, an output voltage VO, an output current IO, afeedback circuit 120, acontroller 122, afeedback signal U FB 124, acurrent sense input 126, adrive signal 128, and switchcurrent I D 130. The topology of the example switchedmode power supply 100 illustrated inFIG. 1 is of the flyback regulator type, which is just one example of a switched mode power supply topology which may benefit from the teachings of the present invention. It is appreciated that other known topologies and configurations of switched mode power supply regulators may also benefit from the teachings of the present invention. - The switched
mode power supply 100 provides output power to theload 118 from anunregulated input V IN 102. In one embodiment theinput V IN 102 is a rectified and filtered ac line voltage. In another embodiment, theinput voltage V IN 102 is a dc input voltage. Theinput V IN 102 is coupled to the energytransfer element T1 104. In some embodiments of the present invention the energytransfer element T1 104 may be a coupled inductor. In some other embodiments of the present invention the energytransfer element T1 104 may be transformer. In the example ofFIG. 1 , the energytransfer element T1 104 includes two windings, a primary winding 106 and secondary winding 108. NP and NS are the number of turns for the primary winding 106 and secondary winding 108 respectively. The primary winding 106 is further coupled to theactive switch S1 110, which is then further coupled to theinput return 111. In addition, theclamp circuit 112 is coupled across the primary winding 106 of the energytransfer element T1 104. The secondary winding 108 of the energytransfer element T1 104 is coupled to therectifier D1 114. In the example illustrated inFIG. 1 , therectifier D1 114 is exemplified as a diode and the secondary winding 108 is coupled to the anode end of the diode. However, in some embodiments therectifier D1 114 may be a transistor used as a synchronous rectifier. Both theoutput capacitor C1 116 and theload 118 are coupled to therectifier D1 114. In the example ofFIG. 1 , therectifier D1 114 is exemplified as a diode and both theoutput capacitor C1 116 and theload 118 are coupled to the cathode end of the diode. An output is provided to theload 118 and may be provided as either an output voltage VO, output current IO, or a combination of the two. - In addition, the switched
mode power supply 100 further comprises circuitry to regulate the output which is exemplified as output quantity UO. In general, the output quantity UO is either an output voltage VO, output current IO, or a combination of the two. Afeedback circuit 120 is coupled to sense the output quantity UO. In one embodiment, thefeedback circuit 120 may sense the output quantity UO from the output of thepower supply 100. In another embodiment, thefeedback circuit 120 may sense the output quantity from an additional winding of the energytransfer element T1 104.Controller 122 is further coupled to thefeedback circuit 120 and comprises several terminals. At one terminal, thecontroller 122 receives afeedback signal U FB 124 from thefeedback circuit 120. Thecontroller 122 further includes terminals for thecurrent sense input 126 and thedrive signal 128. Thecurrent sense input 126 senses the switch current ID 130 inswitch S1 110. In addition, thecontroller 122 provides adrive signal 128 to theswitch S1 110 to control various switching parameters. Examples of such parameters may include switching frequency, switching period, duty cycle, or respective on and off times of theswitch S1 110. - In operation, the switched
mode power supply 100 ofFIG. 1 provides output power to theload 118 from anunregulated input V IN 102, such as an unregulated input voltage. The switchedmode power supply 100 utilizes the energytransfer element T1 104 to transform the voltage from theinput V IN 102 between the primary 106 and secondary 108 windings. Theclamp circuit 112 is coupled to the primary winding 106 of the energytransfer element T1 104 to limit the maximum voltage on theswitch S1 110. In one embodiment, theclamp circuit 112 limits the maximum voltage on theswitch S1 110.Switch S1 110 is opened and closed in response to thedrive signal 128 received from thecontroller 122. In some embodiments, theswitch S1 110 may be a transistor and thecontroller 122 may include integrated circuits and/or discrete electrical components. In one embodiment,controller 122 and switchS1 110 are included together into a singleintegrated circuit 132. In one example, integratedcircuit 132 is a monolithic integrated circuit. In another example, integratedcircuit 132 is a hybrid integrated circuit. - In operation, the switching of
switch S1 110 produces a pulsating current at therectifier D1 114. The current inrectifier D1 114 is filtered byoutput capacitor C1 116 to produce a substantially constant output voltage VO, output current IO, or a combination of the two at theload 118. - The
feedback circuit 120 senses the output quantity UO to provide thefeedback signal U FB 124 to thecontroller 122. In the example ofFIG. 1 , thecontroller 122 also receives thecurrent sense input 126 which relays the sensed current ID 130 in theswitch S1 110. The switch current ID 130 may be sensed in a variety of ways, such as for example the voltage across a discrete resistor or the voltage across the transistor when the transistor is conducting. - The
controller 122 outputs adrive signal 128 to operate theswitch S1 110 in response to various system inputs to substantially regulate the output quantity UO to the desired value. With the use of thefeedback circuit 120 and thecontroller 122, the output of the switchedmode power supply 100 is regulated in a closed loop. In addition, thecontroller 122 includes a timing circuit (discussed in more detail below) which defines the switching cycle of theswitch S1 110 with a switching period of TS and a switching frequency of fS, where TS=1/fS. - In one embodiment of the present invention, the
controller 122 may utilize a control scheme which varies the switching frequency fS when the on-time tON of theswitch S1 110 is greater than a critical time tC. In a further embodiment, thecontroller 122 decreases the switching frequency fS (or in other words, extends the switching period TS) when the on-time tON of theswitch S1 110 is greater than a critical time tC. For a fixed load, the switching period (and switching frequency) of thecontroller 122 may be a fixed period when the on-time is less than the critical time and thecontroller 122 varies the switching period (or switching frequency) when the on-time tON of theswitch S1 110 is greater than a critical time tC. - As mentioned above, the switching period TS may vary by some multiple of the difference between the on-time tON and the critical time tC. In some embodiments, the multiple is a value less than 1. By varying the switching frequency fS when the switch has an on-time tON longer than a critical time tC, which corresponds to a large duty ratio, sub-harmonic oscillation may be prevented. In accordance with one embodiment of the present invention, sub-harmonic oscillation may be prevented by modulating the switching frequency fS (and the switching period TS) of
switch S1 110 in response to the on-time tON of theswitch S1 110. As will be further discussed, when the on-time tON of theswitch S1 110 is greater than the critical time tC, a timing circuit included in the controller changes to an alternative charging mode. Once theswitch S1 110 turns off, the timing circuit resumes to a normal charging mode. By selecting the rate of charge of the timing circuit capacitor during the alternative charging mode, sub-harmonic oscillation may be prevented. - The switching current of various conduction modes is illustrated in
FIG. 2A . A diagram of an example switching current waveform of thepower supply 100 ofFIG. 1 is illustrated including aswitching period T S 204, a switch on-time t ON 206, a switch off-time t OFF 208,trapezoidal shape 210, andtriangular shape 212.FIG. 2A illustrates the general waveforms of the switch current ID 202 over time in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). - During any
switching period T S 204,switch S1 110 may conduct in response to thedrive signal 128 from thecontroller 122 to regulate the output UO. Theswitching period T S 204 may be separated into two sections of time: switch on-time t ON 206 and switch off-time t OFF 208. Switch on-time t ON 206 denotes the portion of theswitching period T S 202 which theswitch S1 110 is conducting. Switch off-time t OFF 208 denotes the remaining portion of theswitching period T S 202 when theswitch S1 110 is not conducting. The current waveform ofFIG. 2 shows two fundamental modes of operation. Thetrapezoidal shape 210 is characteristic of continuous conduction mode (CCM) whereas thetriangular shape 212 is characteristic of discontinuous conduction mode (DCM). During CCM, the switch current ID 202 is substantially non-zero immediately after the start of the switch on-time t ON 206 and steadily increases throughout the switch on-time t ON 208. At DCM, the switch current ID 202 is substantially zero immediately after the beginning of the switch on-time t ON 206 and steadily increases throughout the switch on-time t ON 206. During the switch off-time t OFF 204, the switch current ID 202 is substantially zero for both CCM and DCM. - Sub-harmonic oscillation generally occurs when conventional controllers utilize PWM current mode control and operate in CCM at duty ratios greater than or equal to 50%.
FIG. 2B demonstrates the general waveform of switch current ID ofFIG. 1 with respect to time when PWM current mode control of theswitch S1 110 is used to regulate the output quantity UO.FIG. 2B illustrates switchcurrent I D 214, switchingperiod T S 216, switch on-time t ON 218, switch off-time IOFF 220, and acurrent limit I LIM 222. In the example ofFIG. 2B , thecontroller 122 is operating in CCM. - The
switch S1 110 conducts at the beginning of eachswitching period T S 216.Switch S1 110 conducts until the switch current ID 214 reaches thecurrent limit I LIM 222. In one example, control of the current limit ILIM 222 at a constant switching period TS 216 (otherwise known as fixed switching frequency fS) maintains the peak of the switch current ID 214 at a value required to regulate the output quantity UO. In general, a higher current limit ILIM 222 results in a longer switch on-time t ON 218. In some embodiments of the present invention, the current limit ILIM 222 is also the peak primary current IPEAK. The regulation is accomplished by a PWM technique known as fixed frequency PWM current mode control, fixed frequency PWM current programmed control, and/or peak current mode control. - It should be appreciated however, that the term “fixed frequency control” does not necessarily entail that the switching frequency fS of the
switch S1 110 remains unchanged. Instead, the use of the term “fixed frequency control” may merely indicate that the switching frequency fS of the switch is not used as a control variable to regulate the output quantity UO. For the example of fixed frequency PWM current mode control, the value of the current limit ILIM 222 is utilized as the control variable to regulate the output quantity UO. For various embodiments, varying the switching frequency fS to prevent sub-harmonic oscillation may still be utilized along fixed frequency control modes since the switching frequency fS is not utilized as a control variable to regulate the output quantity UO. In addition, frequency modulation for EMI emissions (also referred to as frequency jitter) may also be utilized with varying of the switching frequency to prevent sub-harmonic oscillation. - Referring next to
FIG. 3 , a diagram of example switching current waveform ID of thepower supply 100 utilizing a control scheme which varies the switching frequency fS and the off-time tOFF of the switch is illustrated including switch current ID 302, switchingperiods T base period T0 312,critical time t C 314, a firstcurrent limit ILIM1 316, a secondcurrent limit ILIM2 318, a thirdcurrent limit ILIM3 320, and a fourthcurrent limit ILIM4 322. In addition, eachswitching period T FIG. 3 , switchingperiods T extension periods TX - As mentioned above with respect to
FIG. 2B , switchS1 110 conducts at the beginning of every switching period TS until the current limit for the respective switching period TS is reached.FIG. 3 illustrates thecontroller 122 operating in CCM and utilizing current mode control. As mentioned above, a larger current limit typically results in a longer on-time tON. In general, how quickly the switch current ID 302 increases to the current limit is partially dependant on theinput voltage V IN 102 and the inductance LP of the primary winding 106. - During switching
period T S 304, the switch current ID 302 increases until it reaches the firstcurrent limit I LIM1 316. As illustrated, the on-time tON during theswitching period T S 304 is less than thecritical time t C 314. As a result, theswitching period TS 304 and the off-time tOFF are not altered and as a result theswitching period T S 304 is fixed to be substantially equal to thebase period T0 312. In one embodiment,critical time t C 314 is substantially equal to one half thebase period T0 312, or mathematically: -
- The value of the critical time tC is the point in time which sub-harmonic oscillation may occur if the switching frequency does not change.
- During switching
period T S 306, the switch current ID 302 increases until it reaches the secondcurrent limit I LIM2 318. As illustrated, the on-time tON during switchingperiod T S 306 is substantially equal tocritical time t C 314 and theswitching period T S 306 and the off-time tOFF are not altered. Thus theswitching period T S 306 is also fixed to be substantially equal to thebase period T0 312. When the on-time tON is substantially less than or equal tocritical time t C 314, as shown in switchingperiods T controller 122 is in a normal operating mode where switchingperiods T - However, during switching
period T S 308, the switch current ID 302 increases until it reaches the thirdcurrent limit I LIM3 320. As illustrated, the on-time tON during switchingperiod T S 308 is greater thancritical time t C 314. In accordance with the embodiment ofFIG. 3 , theswitching period T S 308 is extended beyond thebase period T0 312 byextension period TX 324. As will be further discussed, the length ofextension period TX 324 is dependent on how long the on time tON extends past thecritical time tc 314. In other words, how much theswitching period T S 308 is extended depends on the difference between the on-time tON and thecritical time t C 314, also shown as extended on-time IONX in switching period TS 308 (tONX=tON−tC). - During switching
period T S 310, the switch current ID 302 increases until it reaches the fourthcurrent limit I LIM4 322. As illustrated, the on-time tON during switchingperiod T S 310 is greater thancritical time t C 314 and theswitching period T S 310 and as a result is extended beyond thebase period T0 312 byextension period TX 326. The length of theextension period TX 326 is dependent on the extended on-time IONX during switchingperiod T S 310. - As illustrated by switching
periods base period T0 312 and the extension period TX: -
T S =T0+TX (1) - The length of the extension period TX is dependent on the extended on-time tONX during the respective switching period TS. As described above with reference to switching
periods base period T0 312 when the on-time tON is less than or equal to thecritical time t C 314. Also, theextension periods TX -
TX=k(t ON −t C)=kt oNX (2) - Where k is an extension coefficient and 0≦k. In one embodiment, the extension coefficient k is a constant. In another embodiment, the extension coefficient k is not constant (as will be further discussed). It should be appreciated, that an extension in the switching period TS results in a decrease in the switching frequency fS. In one embodiment, the value of the extension coefficient k may depend on various parameters of the controller 122 (such as parameters of a timing circuit of the
controller 122, extended on-time tONX, base period T0, on-time tON, or the duty ratio D). By determining the value of the extension coefficient k, sub-harmonic oscillation may be prevented. In other words, by determining how much the extended on-time tONX affects the switching period TS, sub-harmonic oscillation may be prevented. As illustrated byequations critical time t C 314. - Further, the off-time tOFF may vary from the base off-time tOFFB and the amount of variation is also dependant on the difference between the on-time tON and the critical time tC 314 (tONX). As illustrated, the off-time tOFF may be expressed as a function of the base off-time tOFFB and extension period TX when the on-time tON is greater than the critical time tC 314:
-
t OFF =t OFFB +TX (3) - where the base off-time tOFFB is the difference between the
base period T0 312 and the on-time tON: tOFFB=T0−tON. In other words, the base off-time tOFFB represents the value of the off-time tOFF if the switching period TS was not extended past thebase period T0 312 in accordance with embodiments. It should be noted that the off-time tOFF is substantially equal to the base off-time tOFFB when the on-time tON is less than or equal to thecritical time t C 314. By substituting equation (2) into equation (3), the off-time may be expressed as: -
t OFF =t OFFB +kt ONX (4) - As shown by equation 4, the off-time tOFF may vary by a multiple of the difference between the on-time tON and the
critical time t C 314. - Further, sub-harmonic oscillation may also be prevented by ensuring the off-time tOFF is greater than or equal to a limit determined by the base period T0 and the on-time tON:
-
- Utilizing equation (5), the switching period TS may be expressed as:
-
- Utilizing equations (5) and (6), the switching period TS may then be manipulated and expressed as a function of the base period T0, the extended on-time tONX, and the extension coefficient k such as equations (1) and (2):
-
- From equation (7), the extension coefficient k is a function of the extended on-time tONX and the base period T0:
-
- As such, in one embodiment, sub-harmonic oscillation may be prevented when the switching period TS is greater than or equal to the quantity illustrated in equation (7).
- Referring next to
FIG. 4 , a block diagram of an example ofcontroller 122 is illustrated including a pulse width modulation (PWM) block 402 and atiming circuit 404. ThePWM block 402 includes acomparator 406, an ORgate 408, and alatch 412. Further illustrated inFIG. 4 is thefeedback circuit 120,feedback signal U FB 124,current sense signal 126,drive signal 128,DCMAX signal 410,clock signal 416, and on-time signal U ON 418. - The
controller 122 includes PWM block 402 andtiming circuit 404.PWM block 402 is coupled to receive thecurrent sense signal 126 andfeedback signal U FB 124. ThePWM block 402 is also coupled to thetiming circuit 404 to receive theclock signal 416. Optionally, the PWM block 402 may also receive DCMAX signal 410 from thetiming circuit 404. Utilizing theclock signal 416,DCMAX signal 410,current sense signal 126 and thefeedback signal U FB 124, the PWM block 402 outputs thedrive signal 128. - PWM block 402 further includes
comparator 406, ORgate 408, andlatch 412. Thecomparator 406 is coupled to receivecurrent sense signal 126 andfeedback signal U FB 124. In the example shown, thecurrent sense signal 126 is received at the non-inverting input ofcomparator 406 while thefeedback signal U FB 124 is received at the non-inverting input ofcomparator 406. In one embodiment, thefeedback signal U FB 124 is a voltage signal or a current signal and may be representative of the current limit of theswitch S1 110. In another embodiment,comparator 406 receives a variable current limit that is determined responsive to a value offeedback signal U FB 124. Further, thecurrent sense signal 126 is a voltage signal or a current signal and is representative of the switchcurrent I D 130. When the value of thecurrent sense signal 126 is greater than the value of the current limit provided by thefeedback signal U FB 124, the output ofcomparator 406 is logic high. Otherwise, the output ofcomparator 406 is logic low. - The output of
comparator 406 couples to one input of ORgate 408. The other input of ORgate 408 is coupled to receive theDCMAX signal 410.DCMAX signal 410 is a rectangular waveform with varying lengths of logic high and logic low sections. In one example, the falling edge of the logic high section corresponds to the maximum duty ratio DMAX. In another example, the length of the logic high section is substantially the same as the maximum on-time TMAX (corresponding to the maximum duty ratio DMAX) of theswitch S1 110. However, the small circle at the input of theOR gate 408 indicates that theOR gate 408 receives the invertedDCMAX signal 410. - The
latch 412 couples to ORgate 408 and totiming circuit 404. In the example shown, thelatch 412 is an S-R latch and thetiming circuit 404 is coupled to provide theclock signal 416 to the set-input oflatch 412. Theclock signal 416 is a rectangular pulse waveform and the amount of time between consecutive rising edges is substantially equal to the switching period TS. Further, the output of ORgate 408 is coupled to the reset-input oflatch 412. Thelatch 412 then outputs thedrive signal 128 to theswitch S1 110.Drive signal 128 is a rectangular waveform with varying lengths of logic high and logic low sections. In one embodiment, the logic high sections correspond to an on-time ofswitch S1 110 while logic low sections correspond to an off-time ofswitch S1 110. - The
timing circuit 404 receives the on-time signal U ON 418 and outputs theclock signal 416 to thePWM block 402. Optionally, thetiming circuit 404 may also output theDCMAX signal 410 to thePWM block 402. In one embodiment, on-time signal U ON 418 provides information regarding the on-time of theswitch S1 110 and is a rectangular pulse waveform with varying lengths of logic high and logic low sections. In one example, thedrive signal 128 may be utilized for the on-time signal, such that thetiming circuit 404 is coupled to an output oflatch 412 to receive on-time signal U ON 418A. Alternatively, thecurrent sense signal 126 may be utilized for the on-time signal U ON 418, such that thetiming circuit 404 is coupled to receive on-time signal UON 418B. In yet another example, the output ofcomparator 406 may be utilized for the on-time signal U ON 418, such that thetiming circuit 404 is coupled to the output ofcomparator 406 to receive on-time signal U ON 418C. - The
timing circuit 404 provides the switching period TS to the PWM block 402 via theclock signal 416. That is, in one example, the period ofclock signal 416 is the switching period TS. In one example, an oscillator may be utilized for thetiming circuit 404. Utilizing the on-time tON of theswitch S1 110 provided by the on-time signal U ON 418, thetiming circuit 404 varies the switching period TS by a multiple of the difference between the on-time tON and the critical time tC. In embodiments, thetiming circuit 404 does not vary the switching period TS unless the on-time tON is greater than the critical time tC. In one embodiment, theclock signal 416 is a rectangular pulse waveform. In one embodiment, the rising edge of theclock signal 416 indicates the beginning of switching period TS. - In operation, when the
clock signal 416 pulses to a logic high value signaling the beginning of a switching period TS. The output of thelatch 412 transitions to a logic high value (due to the logic high at the S-input) and thedrive signal 128 turns theswitch S1 110 on. In one embodiment,clock signal 416 quickly falls to a logic low value and the output of thelatch 412 remains at the logic high value. If either the output ofcomparator 406 is logic high (corresponding to when the value of thecurrent sense signal 126 is greater than the value of the current limit provided by the feedback signal UFB 124) or the invertedDCMAX signal 410 is logic high (or both), the output of ORgate 408 is logic high. When thelatch 412 receives a logic high value at the reset-input, the drive signal 128 (i.e. output of the latch 412) transitions to a logic low value and theswitch S1 110 is turned off. Examples of timing waveforms for theclock signal 416 and DCMAX signal 410 will be discussed with respect toFIG. 8 . - Referring next to
FIG. 5A , a diagram illustrating an example voltage waveform VTIM 528 of thetiming circuit 404 ofFIG. 4 is shown including a lowerreference voltage V L 530, an upperreference voltage V H 532, acritical voltage V C 531, a max dutyratio voltage V DM 533, andcritical time t C 514. Further illustrated inFIG. 5A is switchcurrent I D 502, switchingperiods T base period T0 512,critical time t C 514, a firstcurrent limit ILIM1 516, a secondcurrent limit ILIM2 518, a thirdcurrent limit ILIM3 520, and a fourthcurrent limit ILIM4 522. In addition, eachswitching period T FIG. 5A , switchingperiods T extension periods TX - The waveform representing the switch current ID 502 is similar to the switch current ID 302 illustrated in
FIG. 3 along with corresponding reference numbers.FIG. 5A further illustrates one example of atiming voltage VTIM 528 for the respective switchcurrent I D 502. In one embodiment,timing circuit 404 includes a timing capacitor (discussed below), wherein thetiming voltage VTIM 528 is the voltage across the timing capacitor. In each switching period, thetiming voltage VTIM 528 increases until it reaches the upperreference voltage V H 532 and then decreases with slope m3 until the lowerreference voltage V L 530 is reached. However,timing circuit 404 may include two modes for charging the capacitor to the upperreference voltage V H 532. In a normal charging mode thetiming voltage VTIM 528 increases with a slope m1 until the upperreference voltage V H 532 is reached. When the on-time tON is greater than the critical time tC, thetiming circuit 404 switches to an alternative charging mode and thetiming voltage VTIM 528 charges with two or more slopes (e.g., m1 and m2), that are either positive or zero. In one embodiment, at the end of the on-time tON, thetiming circuit 404 changes from the alternative charging mode to the normal charging mode (i.e., returns to charging with slope m1). In addition, thetiming circuit 404 may utilize four reference voltages (e.g., the upper reference voltage VH, the lower reference voltage VL, the max duty ratio voltage VDM, and the critical voltage VC). The critical voltage VC indicates when the timing circuit is at 50% of thebase period T0 512. - At the beginning of each switching period, the
timing voltage VTIM 528 begins at the lowerreference voltage V L 530 and increases to the upperreference voltage V H 532. Once at the upperreference voltage V H 532, thetiming voltage VTIM 528 decreases until it reaches the lowerreference voltage V L 530. When thetiming voltage VTIM 528 reaches the lowerreference voltage V L 530, the current switching period has ended and a new switching period has begun. As such, the time for thetiming voltage VTIM 528 to rise to the upperreference voltage V H 532 and subsequently decrease to the lowerreference voltage V L 530 determines the length of the switching period TS. - During switching
period T S 504, the on-time tON is less than thecritical time t C 514 and theswitching period T S 504 is not extended beyond thebase period T0 512. As a result, thetiming circuit 404 operates in a normal charging mode. As shown byFIG. 5A , thetiming voltage VTIM 528 rises to the upperreference voltage V H 532 with slope m1 and falls to the lowerreference voltage V L 530 with slope m3 without interruption. In one embodiment, the magnitude of slope m3 is a multiple of the magnitude of slope m1, or mathematically: |m3|=α|m1|, where α≧1. In one embodiment: α=3. - During switching
period T S 506, the on-time tON is substantially equal to thecritical time t C 514 and theswitching period T S 506 is not extended beyond thebase period T0 512. Similar to switchingperiod T S 504, thetiming circuit 404 operates in a normal charging mode and thetiming voltage VTIM 528 rises to the upperreference voltage V H 532 with slope m1 and falls to the lowerreference voltage V L 530 with slope m3 without interruption. - During switching
period T S 508, the on-time tON is greater than thecritical time t C 514. As a result, thetiming circuit 404 operates in an alternative charging mode and theswitching period T S 508 is extended beyond thebase period T0 512. In the example ofFIG. 5A , the timingvoltage waveform VTIM 528 rises with slope m1 until the on-time tON is substantially equal to thecritical time t C 514. When thecritical time t C 514 is reached, thetiming circuit 404 switches to an alternative charging mode and the slope oftiming voltage VTIM 528 then decreases to a slope m2. As further shown inFIG. 5A , thecritical voltage V C 531 corresponds to the value of thetiming voltage VTIM 528 when the on-time tON is substantially equal to thecritical time t C 514. In another embodiment, when the timingvoltage waveform VTIM 528 reaches thecritical voltage V C 531, thetiming circuit 404 switches to the alternative charging mode and the timingvoltage waveform VTIM 528 increases with slope m2. - In the example shown in
FIG. 5A , the slope m2 is equal to zero; m2=0. Thus, in this example, when the slope oftiming voltage VTIM 528 is zero (i.e., slope m2=0) then thetiming voltage VTIM 528 is maintained at a constant value. As will be further discussed, the ratio between slope m2 and slope m3 (and subsequently slope m1) may be expressed in terms of the duty ratio. Thetiming voltage VTIM 528 is maintained with slope m2 until theswitch S1 110 is turned off. Once theswitch S1 110 is turned off, the timingvoltage waveform VTIM 528 rises again with slope m1 until the upperreference voltage V H 532 and then falls with slope m3 to the lowerreference voltage V L 530.FIG. 5A illustrates that slope m2 is constant. In another embodiment, slope m2 is not constant, resulting in a non-linear increase of the timing voltage VTIM. - During switching
period T S 510, the on-time tON is greater than thecritical time t C 514. However, the on-time tON during switchingperiod T S 510 is longer than the on-time tON during switchingperiod T S 508. In other words, the extended on-time tONX during switchingperiod T S 510 is longer than the extended on-time tONX during switchingperiod T S 508. Similar to the previous switching period, thetiming voltage VTIM 528 rises with slope m1 until the on-time tON is substantially equal to thecritical time t C 514. Once thecritical time t C 514 is reached, thetiming voltage VTIM 528 is maintained with slope m2 for the remainder of the on-time tON. Once theswitch S1 110 is turned off, thetiming voltage VTIM 528 rises again with slope m1 until the upperreference voltage V H 532 and then falls with slope m3 to the lowerreference voltage V L 530. - As mentioned above with respect to
FIG. 3 , the switching period TS may be expressed in terms of thebase period T0 512 and the extension period TX. Further, the extension period TX may be expressed in terms of the extended on-time tONX. By combining equations (1) and (2), the switching period TS may be expressed as: -
T S =T0+kt ONX (8) - where tONX=tON−tC. As mentioned above, the value of the extension coefficient k may be partially determined by the properties of the
controller 122 and thetiming circuit 404. Fortiming circuit 404 with an alternative charging mode, once the on-time tON is greater than the critical time tC, the extension coefficient k may be proportional to the ratio of slop m2 to m1. For example, the extension coefficient k may be the difference between the value of one and the ratio of slope m2 to slope m1, expressed as: -
- By combining equation (8) and equation (9), the switching period TS may be expressed as:
-
- As illustrated in equation (10), the switching period TS may vary by some multiple of the difference between the on-time tON and the critical time tC. Further, the switching period TS can also be expressed in terms of the duty ratio D, slope m1, slope m2, and the base period T0:
-
- As mentioned above, the compensation coefficient k may equal:
-
- By comparing equation (10) with equation (7), we can determine a boundary relationship for slope m2 and m1. For stability:
-
- Which can be simplified to:
-
- In one embodiment, sub-harmonic oscillation may be prevented by utilizing equation (13) to determine the ratio between slope m2 and slope m1.
In another embodiment of the present invention, for a constant slope m2, the ratio of slope m2 and m1 is partially determined by the maximum duty ratio: -
- As such, the boundary equation for the compensation coefficient k of equation (9) may also be expressed as:
-
- For the example of
FIG. 5A , slope m2 is substantially zero and the extension coefficient k is substantially one. As such, the extension period TX (the amount of time which the switching period TS is extended beyond the base period T0 512) is substantially equal to the extended on-time tONX. As will be further discussed with respect toFIG. 5C , the slope m2 may vary as a function of the duty ratio and/or on-time tON. -
FIG. 5B further illustrates another example timing voltage waveform VTIM 528 of thetiming circuit 404 ofFIG. 4 . Similar toFIG. 5A ,FIG. 5B illustrates the lowerreference voltage V L 530, the upperreference voltage V H 532,critical voltage V C 531, max dutyratio voltage V DM 533 andcritical time t C 514. Further illustrated inFIG. 5B is switchcurrent I D 502, switchingperiods T base period T0 512,critical time t C 514, firstcurrent limit ILIM1 516, secondcurrent limit ILIM2 518, thirdcurrent limit ILIM3 520, and fourthcurrent limit ILIM4 522. In addition, eachswitching period T FIG. 5B , switchingperiods T extension periods TX -
FIG. 5B illustrates a similarvoltage waveform VTIM 528 asFIG. 5A , however, the slope m2 shown is a non-zero slope. As illustrated in switchingperiods T voltage waveform VTIM 528 rises with slope m1 until the on-time tON is substantially equal to thecritical time t C 514. Once thecritical time t C 514 is reached, thetiming voltage VTIM 528 increases with slope m2 for the remainder of the on-time tON. Once theswitch S1 110 is turned off, thetiming voltage VTIM 528 rises again with slope m1 until the upperreference voltage V H 532 and then falls with slope m3 to the lowerreference voltage V L 530.FIG. 5B illustrates that slope m2 is constant, resulting in a linear increase of the timing voltage VTIM. In another embodiment, slope m2 is not constant, resulting in a non-linear increase of the timing voltage VTIM. - Further illustrated in
FIG. 5B is max dutyratio voltage V DM 533. As will be further discussed with respect toFIGS. 7 and 8 , if the timingvoltage waveform VTIM 528 reaches the max dutyratio voltage V DM 533 before theswitch S1 110 is turned off, theDCMAX signal 410 is enabled and theswitch S1 110 is turned off. Fixing the max dutyratio voltage V DM 533 ensures a minimum off-time tOFF of theswitch S1 110 and further prevents sub-harmonic oscillation. - For the example shown in
FIG. 5B , the maximum duty ratio DMAX is substantially 66%. By utilizing equation (14) and (15) the slope m2 is substantially one-half of slope m1, or mathematically: -
- As a result, the extension coefficient k is substantially one-half (as shown in equation 9) and the extension period TX (the amount of time which the switching period TS is extended beyond the base period T0 512) is substantially equal to one-half the extended on-time tONX.
-
FIG. 5C illustrates a similarvoltage waveform VTIM 528 asFIGS. 5A and 5B , however, the slope m2 is a variable slope. As illustrated in switchingperiods T voltage waveform VTIM 528 rises with slope m1 until the on-time tON is substantially equal to thecritical time t C 514. Once thecritical time t C 514 is reached, thetiming voltage VTIM 528 increases with variable slope m2 for the remainder of the on-time tON. Once theswitch S1 110 is turned off, thetiming voltage VTIM 528 rises again with slope m1 until the upperreference voltage V H 532 and then falls with slope m3 to the lowerreference voltage V L 530. However, the slope m2 is variable. In one embodiment, the slope m2 may vary as a function of the duty ratio D. - As mentioned above with regards to equation (14), when slope m2 is constant, the ratio between slope m2 and slope m1 may be expressed in terms of the maximum duty ratio DMAX:
-
- However, by varying the slope m2 within each switching period, the switching frequency fS may very less from the base frequency than if the slope m2 was kept constant. In other words, by varying the slope m2, there is less of a reduction in the switching frequency than if a constant slope m2 was utilized. Similar to equation (14), in one embodiment, the ratio between the slope m2 and slope m1 may be expressed in terms of the duty ratio:
-
- Equation (9) illustrates that the extension coefficient k may be expressed as a function of slope m2 and slope m1. As such, the extension coefficient k is also variable and adaptable with the duty ratio D. Further, by substituting equation (16) into equation (10) above, the switching period TS may be expressed in terms of the duty ratio D and the base period T0 when slope m2 is non-zero:
-
- In yet another embodiment, slope m2 is equal to zero, where equation (17) can be further simplified to:
-
- Referring next to
FIG. 6 , a diagram illustrating various embodiments of the timingvoltage waveform VTIM 602 with slope m2 oftiming circuit 404 is shown including a lowerreference voltage V L 604, an upperreference voltage V H 606, acritical voltage V C 605, a max dutyratio voltage V DM 607, a critical time IC 608, an on-time t ON 610, an extended on-time t ONX 612, a base off-time t OFFB 614, aslope m 1 616, aslope m 2 618 and a slope m3 619. Further illustrated is timingwaveforms 622, 624, and 626.FIG. 6 illustrates the changes to the respective switching period TS and off-time tOFF of eachtiming waveform 622, 624, 626 with varying values ofslope m 2 618. Further included inFIG. 6 is waveform 620 (in dashed lines) which illustrates the properties of a conventional controller that does not include an alternative charging mode as disclosed herein. - As shown in
FIG. 6 , thetiming voltage VTIM 602 increases until the upperreference voltage V H 606. Once the upperreference voltage V H 606 is reached thetiming voltage VTIM 602 decreases until the lowerreference voltage V L 604 is reached. The time it takes for thetiming voltage VTIM 602 to reach the upperreference voltage V H 606 and then fall to the lowerreference voltage V L 604 is substantially the switching period TS for the particular switching cycle. In examples, thetiming circuit 404 may alter the switching period or switching frequency by altering the rate of increase to the upperreference voltage V H 606, the rate of decrease to the lowerreference voltage V L 604, or both. - In further embodiments, the
controller 122, and subsequently thetiming circuit 404, switches to an alternative charging mode when the on-time t ON 610 is greater than thecritical time t C 608. In other words, the switching period and switching frequency are varied once the on-time t ON 610 is greater than thecritical time t C 608. In addition, illustrated inFIG. 6 iscritical voltage V C 605 which corresponds to the value of thetiming voltage VTIM 602 when the on-time t ON 610 is substantially equal to thecritical time t C 608. In one embodiment, thecontroller 122, and subsequently thetiming circuit 404, switches to an alternative charging mode when thetiming voltage VTIM 602 reaches thecritical voltage V C 605. As will be illustrated, how much the switching period and switching frequency are varied depends partially on the properties of the alternative charging mode oftiming circuit 404. -
Waveforms 622, 624, and 626 each illustrate thetiming voltage VTIM 602 increasing at the beginning of on-time t ON 610 withslope m 1 616 until the on-time t ON 610 is substantially equal to thecritical time t C 608. Once thecritical time t C 608 is reached or thecritical voltage V C 605 is reached, thetiming voltage VTIM 602 switches to an alternative charging mode if theswitch S1 110 is still on. In other words,timing voltage VTIM 602 increases withslope m 2 618 for the remainder of the on-time t ON 610 past thecritical time t C 608, otherwise referred to as extended on-time t ONX 612. - However,
waveform 620 illustrates a timing voltage of a conventional controller that does not include an alternative charging mode as disclosed herein. As a result, the switching period TS forwaveform 620 is substantially equal to thebase period T0 628. In addition, the off-time forwaveform 620 is substantially equal to the base off-time t OFFB 614. As shown inFIG. 6 , theresultant waveform 620 is the same as the timing waveform when the on-time tON is less than or equal to the critical time tC. Thus, sub-harmonic oscillation may still occur when duty ratios are greater than 50%. - For
waveform 622,slope m 2 618 is substantially equal one-half slope m 1 616, or mathematically: -
- As a result (and further shown by equation (10)), the
switching period T1 630 ofwaveform 622 is extended past thebase period T0 628 by one-half the extended on-time t ONX 612, or mathematically: -
- In addition, the off-time tOFF1 of
waveform 622 is also extended past the base off-time t OFFB 614 by one-half the extended on-time t ONX 612. - For waveform 624,
slope m 2 618 is substantially equal one-quarter slope m 1 616, or mathematically: -
- As a result (and further shown by equation (10)), the
switching period T2 632 of waveform 624 is extended past thebase period T0 628 by three-quarters of the extended on-time t ONX 612, or mathematically: -
- In addition, the off-time tOFF2 of waveform 624 is also extended past the base off-
time t OFFB 614 by three-quarters the extended on-time t ONX 612. - For waveform 626,
slope m 2 618 is substantially equal to zero, or mathematically: m2=0. As a result (and further shown by equation (10)), theswitching period T3 634 of waveform 626 is extended past thebase period T0 628 by the extended on-time t ONX 612, or mathematically: T1=T0+tONX The off-time tOFF3 of waveform 626 is also extended past the base off-time t OFFB 614 by the extended on-time t ONX 612. In particular, whenslope m 2 618 is substantially equal to zero, the off-time tOFF3 is substantially fixed for each switching cycle. Thus, in one embodiment, the off-time of the switch is fixed by holding thetiming voltage VTIM 602 to a constant value until theswitch S1 110 turns off. Continuing with this example, after theswitch S1 110 turns off, thetiming voltage VTIM 602 is allowed to resume increasing to the upper reference voltage at slope m1. Accordingly, the off-time is fixed to the remaining time that it takesVTIM 602 to reach the upperreference voltage V H 606 plus the time it takesVTIM 602 to fall to the lowerreference voltage V L 604. This fixed off-time is exemplified inFIG. 6 as tOFF3. - For
waveforms 622, 624, and 626, once theswitch S1 110 turns off and the off-time begins, the timing circuit 404 (and as a result the timing voltage VTIM 602) returns to a normal charging mode. As discussed above, thetiming voltage VTIM 602 continues to increases withslope m 1 616 until the upperreference voltage V H 606 is reached. Thetiming voltage VTIM 602 then decreases with slope m3 619 until the lowerreference voltage V L 604 is reached. - By selecting the value of
slope m 2 618, sub-harmonic oscillation may be prevented. As mentioned above, when the ratio betweenslope m 2 618 and the magnitude ofslope m 1 616 adheres to: -
- sub-harmonic oscillation may be prevented. In one embodiment,
slope m 2 618 is one-half ofslope m 1 616. As shown inFIG. 6 , the smaller the value ofslope m 2 618 with respect toslope m 1 616, the longer the switching period TS is extended beyond thebase period T0 628. However, output power of thepower supply 100 for a given core size of an energy transfer element is proportional to the switching frequency fS. The longer the switching period TS, the smaller the switching frequency fS, may result in needing a larger core to deliver the amount of output power needed. - As mentioned above, frequency modulation for EMI emissions (also referred to as frequency jitter) may also be utilized with varying of the switching frequency in accordance with embodiments described. In one embodiment, frequency jitter may be accomplished by varying the
slope m 1 616. In another embodiment, frequency jitter may be accomplished by varying theslope m 2 618. - Referring next to
FIG. 7 , an example timing circuit 704 (which may be utilized astiming circuit 404 ofFIG. 4 ) is illustrated, including a lowerreference voltage V L 702, an upperreference voltage V H 701, max dutyratio voltage V DM 705,comparators latch 710, acurrent source 712 with charge current IC, acurrent sink 714 with discharge current IDIS, acurrent source 716 with extension current IEXT, and capacitor 718 (i.e., a timing capacitor) with timing voltage VTIM. Thetiming circuit 704 further includes ANDgates monostable multivibrators comparator 727 and alatch 728. Further illustrated inFIG. 7 areDCMAX signal 410,clock signal 416, on-time signal U ON 418, critical signal (CRT) 730, and extension signal (EXT) 732. Further shown are switches S2, S3 and S4. - The
current sources charge capacitor 718 with charge current IC and extension current IEXT, respectively, to an upperreference voltage V H 701. The magnitudes of the charge current IC and the extension current IEXT determine the value of slopes m1 and m2, respectively, discussed with respect toFIGS. 5A , 5B, 5C and 6. Once the timing voltage VTIM of thecapacitor 718 reaches the upperreference voltage V H 701, thecapacitor 718 is discharged throughcurrent sink 714 with discharge current IDIS until the timing voltage VTIM across thecapacitor 718 reaches the lowerreference voltage V L 702. The magnitude of the discharge current IDIS determines the value of slope m3. In one embodiment, an additional current source (not shown) coupled tocapacitor 718, in addition tocurrent sources - The difference between the upper
reference voltage V H 701 and the lowerreference voltage V L 702 is referred herein as the amplitude swing of thetiming circuit 404. In one embodiment, the amplitude swing of thetiming circuit 404 is fixed. When the amplitude swing is fixed, the time it takes for the voltage VTIM ofcapacitor 718 to charge to the upperreference voltage V H 701 and discharge to the lowerreference voltage V L 702 determines the frequency and period oftiming circuit 404. The timing voltage VTIM ofcapacitor 718 increases and decreases depending on the value of the charge current IC, extension current IEXT, and discharge current IDIS. In other words, the magnitudes of the charge current IC, extension current IEXT, and discharge current IDIS may determine the frequency oftiming circuit 404 and therefore vary the switching frequency fS and switching period TS ofswitch S1 110. - As mentioned above, in some embodiments the
timing circuit 404 varies the switching frequency fS and switching period TS when the on-time tON of theswitch S1 110 is greater than a critical time tC. As will be further discussed, in oneexample timing circuit 404 utilizes the extension current IEXT to vary the frequency oftiming circuit 404 and therefore vary the switching frequency fS and switching period TS ofswitch S1 110 when the on-time tON of theswitch S1 110 is greater than a critical time tC. An example of the altered frequency of thetiming circuit 404 due to the magnitude of the extension current IEXT is illustrated with respect toFIGS. 5A , 5B, 5C, 6, and 8. -
Capacitor 718 is coupled tocomparators comparator 706 and the non-inverting terminal ofcomparator 708. Further, the non-inverting terminal ofcomparator 706 receives the lowerreference voltage V L 702 while the inverting terminal ofcomparator 708 receives the upperreference voltage V H 701. The timing voltage VTIM waveform is illustrated inFIG. 8 as waveform VTIM. Further examples of timing voltage VTIM waveform may be found with respect toFIGS. 5A , 5B, 5C and 6. The outputs ofcomparators latch 710. In the example shown, the output ofcomparator 706 is received at the S-input oflatch 710 while the output ofcomparator 708 is received at the R-input oflatch 710. - Further, the output of
comparator 706 is received atmonostable multivibrator 726 to generate theclock signal 416. In one embodiment, themonostable multivibrator 726 outputs a pulse at the rising edge (in other words, the transition from a logic low value to a logic high value) of the output ofcomparator 706. In other words, themonostable multivibrator 726 outputs a pulse when the timing voltage VTIM is equal to the lowerreference voltage V L 702. In embodiments, thetiming circuit 704 alters the amount of time it takes for the timing voltage VTIM to reach the lowerreference voltage V L 702 by altering the speed at which thecapacitor 718 charges to the upperreference voltage V H 701 and therefore altering the switching frequency fS and switching period of TS of theswitch S1 110. - Outputs of
comparators latch 710. One output oflatch 710 is received at ANDgate 722 while the other output oflatch 710 is coupled to control switching of the switch S3. ANDgate 722 is coupled to receiveextension signal EXT 732 from ANDgate 720. However, the small circle at the input of ANDgate 722 which receives theextension signal EXT 732 denotes that the ANDgate 722 receives the inverse of theextension signal EXT 732. In the example shown,extension signal EXT 732 is generated from on-time signal U ON 418 and the output ofmonostable multivibrator 724.Monostable multivibrator 724 receives on-time signal U ON 418 and outputs a pulse at the rising of the on-time signal U ON 418, herein referred to as thecritical signal CRT 730. The length of the pulse ofcritical signal CRT 730 is substantially equal to the critical time tC and the time between rising edges of thecritical signal 730 is substantially equal to the switching period of TS.Critical signal CRT 730 provides information regarding the critical time tC. In the example shown, the small circle at the input of ANDgate 720 which receives thecritical signal 730 denotes that the ANDgate 720 receives the inverse of thecritical signal 730. As will be further shown inFIG. 8 , theextension signal EXT 732 is logic high when thedrive signal 128 is logic high and the critical signal CRT is logic low. In other words, theextension signal EXT 732 is logic high when the on-time tON is greater than the critical time tC and the length of the logic high section is the extended on-time tONX as discussed withFIGS. 5A , 5B, 5C, and 6. TheEXT signal 732 provides information regarding the extended on-time tONX as discussed withFIGS. 5A , 5B, 5C, 6 and 8. Theextension signal EXT 732 is coupled to control switching of the switch S4. -
Capacitor 718 is coupled tocomparator 727 such that the timing voltage VTIM is received at the non-inverting input ofcomparator 727. Further, the max dutyratio voltage V DM 705 is received at the inverting input ofcomparator 727. As mentioned above, the max dutyratio voltage V DM 705 ensures a minimum off-time of theswitch S1 110. The max dutyratio voltage V DM 705 corresponds to the value of the timing voltage VTIM when theswitch S1 110 has reached the maximum duty ratio DMAX. In one embodiment, the maximum duty ratio is 62%. On-time signal U ON 418 is received at one input oflatch 728. In the example shown, the on-time signal U ON 418 is received at the S-input oflatch 728. Thelatch 728 also receives the output ofcomparator 727. Utilizing the output ofcomparator 727 and the on-time signal U ON 418, latch 728 outputs theDCMAX signal 410. In operation, at the rising edge of on-time signal U ON 418, DCMAX signal 410 transitions to a logic high value. TheDCMAX signal 410 then transitions to a logic low value when the output ofcomparator 708 is logic low. In other words, the DCMAX signal 410 transitions to a logic low value when the timing voltage VTIM is equal to the max dutyratio voltage V DM 705. - As mentioned above, the inverse of the
extension signal EXT 722 is received at one input of ANDgate 722 while the output oflatch 710 is received at another input of ANDgate 722. The output of ANDgate 722 is coupled to control switching of switch S2. The output of ANDgate 722 is logic high (corresponding to a closed switch S2) when the output oflatch 710 is logic high and theextension signal EXT 732 is logic low. In other words, the switch S2 is closed when the output oflatch 710 is logic high and theswitch S1 110 is not in the extended on-time tONX. - In operation, the
capacitor 718 charges when switch S2 is closed at the beginning of the switching period and the timing voltage VTIM increases with a slope determined by the charging current IC and the size ofcapacitor 718. When the timing voltage VTIM reaches the upperreference voltage V H 701, switch S2 turns off, switch S3 turns on and thecapacitor 718 discharges with a slope determined by discharge current IDIS and the size ofcapacitor 718 until the timing voltage VTIM reaches the lowerreference voltage V L 702. - However, if the controller switches to an alternative charging mode because on-time tON is greater than the critical time tC (otherwise known as the extended on-time tONX), the
extension signal EXT 732 transitions to a logic high value. If the timing voltage VTIM is also less than the upperreference voltage V H 701, switch S2 opens and switch S4 closes and thecapacitor 718 charges with a slope determined by extension current IEXT. Thecapacitor 718 may return to the normal charging mode (e.g., where thecapacitor 718 charges with a slope determined by the charging current IC only) when the switch S4 turns off and switch S2 turns on. The switch S4 turns off and switch S2 turns on when theswitch S1 110 turns off or the max dutyratio voltage V DM 705 is reached. Thus, in the illustrated embodiment,capacitor 718 is charged withcurrent source 712 only when timingcircuit 704 is in the normal charging mode and is charged withcurrent source 716 only when timingcircuit 704 is in the alternative charging mode, where current IEXT is less than current IC. - Referring next to
FIG. 8 , a timing diagram illustrating various waveforms of voltages and currents of thetiming circuit 704 ofFIG. 7 is shown including a switchcurrent ID 802, a on-time signal U ON 804, acritical signal CRT 806, anextension signal EXT 808, atiming voltage VTIM 810, aclock signal CLK 812, and aDCMAX signal 814. Further illustrated inFIG. 8 are switchingperiods T switching period T Switching periods T timing voltage VTIM 810 also illustrates an upper reference voltage VH, a max duty ratio voltage VDM, and a lower reference voltage VL. In addition,timing voltage VTIM 810 may increase to the upper reference voltage VH with slope m1 or slope m2. - During switching
period T S 816, the on-time tON is less than the critical time tC. At the beginning of switchingperiod T S 816, theclock signal CLK 812 pulses to a logic high value and thedrive signal 804 transitions to a logic high value. As shown inFIG. 8 , theclock signal CLK 812 quickly falls to a logic low value. Theswitch S1 110 turns on and the switchcurrent ID 802 begins to increases. When the switchcurrent ID 802 reaches the current limit ILIM, theswitch S1 110 turns off and the on-time signal U ON 804 transitions to the logic low value. Thecritical signal CRT 806 is logic high at the start of theswitching period T S 816 and transitions to the logic low value at the critical time tC. However, since there is no portion of time in which the on-time signal U ON 804 is logic high and thecritical signal CRT 806 is logic low, theextension signal EXT 808 is logic low for the entirety of switchingperiod T S 816. As a result, switch S4 does not turn on and thetiming voltage VTIM 810 increases with slope m1 (corresponding to whencapacitor 718 is charged bycurrent source 712 with charge current IC) until the upper reference voltage VH is reached. - As shown, DC MAX signal 814 transitions to the logic high value at the start of the
switching period T S 816 and transitions to the logic low value when the max duty ratio voltage VDM is reached. Once thetiming voltage VTIM 810 reaches the upper reference voltage VH, switch S2 turns off while switch S3 turns on and thetiming voltage VTIM 810 decreases with slope m3 (corresponding to capacitor 718 discharging throughcurrent sink 714 with discharge current IDIS) until the lower reference voltage VL is reached. As shown inFIG. 8 , the magnitude of slope m3 is three times the magnitude of slope m1.Clock signal CLK 812 pulses to the logic high value indicating the start of switchingperiod T S 818 when the lower reference voltage VL is reached. - During switching
period T S 818, the on-time tON is greater than the critical time tC, however, the switchcurrent ID 802 reaches the current limit ILIM before the DC MAX signal 814 transitions to the logic low value. Theclock signal CLK 812 pulses to a logic high value and theswitch S1 110 turns on. The on-time signal U ON 418 transitions to a logic high value and the switchcurrent ID 802 begins to increase. As shown inFIG. 8 , the switchcurrent ID 802 has not yet reached the current limit ILIM at the critical time tC. When the critical time tC is reached, thecritical signal CRT 806 transitions to the logic low value. Since the on-time signal U ON 804 is still logic high when thecritical signal 806 is logic low, theextension signal EXT 808 is logic high for the portion of theswitching period T S 818 when the on-time tON is greater than the critical time tC. The length of time which theextension signal EXT 808 is logic high is substantially equal to the extended on-time tONX. - At the beginning of switching
period T S 818, when theextension signal EXT 808 is logic low, switch S4 is off and switch S2 is on. Thetiming voltage VTIM 810 charges with slope m1 (corresponding to whencapacitor 718 is charged bycurrent source 712 with charge current IC) while theextension signal EXT 808 continues in the logic low state. When theextension signal EXT 808 transitions to the logic high value, switch S2 turns off while switch S4 turns on and thetiming voltage VTIM 810 charges with slope m2 (corresponding to whencapacitor 718 is charged bycurrent source 716 with extension current IEXT). Once theextension signal EXT 808 transitions to the logic low value (corresponding to theswitch S1 110 turns off and the on-time signal U ON 804 transitions to the logic low value), switch S4 turns off while switch S2 turns on and thetiming voltage VTIM 810 resumes charging with slope m1 until the upper reference voltage VH is reached. Once thetiming voltage VTIM 810 reaches the upper reference voltage VH, switch S2 turns off while switch S3 turns on and thetiming voltage VTIM 810 decreases with slope m3 (corresponding to capacitor 718 discharging throughcurrent sink 714 with discharge current IDIS) until the lower reference voltage VL is reached.Clock signal CLK 812 pulses to the logic high value indicating the start of switchingperiod T S 820 when the lower reference voltage VL is reached. - During switching
period T S 820, the on-time tON is greater than the critical time tC, however, the switchcurrent ID 802 does not reach the current limit ILIM before the DC MAX signal 814 transitions to the logic low value. As a result, thedrive signal 804 transitions to the logic low value because the maximum duty ratio DMAX was reached. At the beginning of switchingperiod T S 820, theclock signal CLK 812 pulses to a logic high value and switchS1 110 turns on. The on-time signal U ON 418 transitions to a logic high value and the switchcurrent ID 802 begins to increases. As shown inFIG. 8 , the switchcurrent ID 802 has not reached the current limit ILIM at the critical time tC. When the critical time tC is reached, thecritical signal CRT 806 transitions to the logic low value. Since thedrive signal 804 is still logic high when thecritical signal 806 is logic low, theextension signal EXT 808 is logic high for the remainder of the on-time tON which is greater than the critical time tC. When theextension signal EXT 808 is logic low, switch S4 is off and switch S2 is on and thetiming voltage VTIM 810 charges with slope m1. When theextension signal EXT 808 transitions to the logic high value, switch S2 turns off while switch S4 turns on and thetiming voltage VTIM 810 charges with slope m2. The DC MAX signal 814 transitions to the logic high value at the start of theswitching period T S 818 and transitions to the logic low value when timingvoltage VTIM 810 reaches the max duty ratio voltage VDM. As illustrated in switchingperiod T S 820, thetiming voltage VTIM 810 reaches the max duty ratio voltage VDM before the switchcurrent ID 802 reaches the current limit ILIM. As a result, thedrive signal 128 transitions to the logic low value in response to the DC MAX signal 814 and theswitch S1 110 turns off (corresponding to the end of the on-time tON as shown by on-time signal U ON 418 in switching period TS 820). In addition, switch S4 turns off and switch S2 turns on and thetiming voltage VTIM 810 increases with slop m1 until the upper reference voltage VH is reached. Once thetiming voltage VTIM 810 reaches the upper reference voltage VH, switch S2 turns off while switch S3 turns on and thetiming voltage VTIM 810 decreases with slope m3 until the lower reference voltage VL is reached.Extension signal EXT 808 also transitions to the logic low value because the on-time signal U ON 418 has transitioned to the logic low value. - Referring next to
FIG. 9 , another example timing circuit 904 (which may be utilized astiming circuit 404 ofFIG. 4 ) is illustrated including an upperreference voltage V H 901, a lowerreference voltage V L 902, acritical voltage V C 903, a max dutyratio voltage V DM 905,comparators latch 910, acurrent source 912 with charge current IC, acurrent sink 914 with discharge current IDIS, acurrent source 916 with extension current IEXT, andcapacitor 918 with timing voltage VTIM. Thetiming circuit 904 further includes ANDgates comparator 924,monostable multivibrator 726, acomparator 927 and alatch 928. Further illustrated inFIG. 9 areDCMAX signal 410,clock signal 416, on-time signal U ON 418,critical signal CRT 930, andextension signal EXT 932.FIG. 9 illustrates the use of voltage thresholds to determine the critical time tC and thus, when to turn on and off switches S2, S3, and S4. - Many of the elements illustrated in
FIG. 9 couple and function as mentioned above to similarly named and numbered elements ofFIG. 7 . However, instead ofmonostable multivibrator 724 to generate thecritical signal CRT 730,comparator 924 is utilized to generate thecritical signal CRT 930.Comparator 924 is coupled tocapacitor 918 and receives the timing voltage VTIM. In one embodiment, the timing voltage VTIM is received at the non-inverting input ofcomparator 924. Thecomparator 924 further receives thecritical voltage V C 903 at the inverting input. As mentioned above, thecritical voltage V C 903 corresponds to the value of the timing voltage VTIM when the on-time tON is substantially equal to the critical time tC.Comparator 924 utilizes the timing voltage VTIM and thecritical voltage V C 903 to output thecritical signal CRT 930 to one input of ANDgate 920. When the timing voltage VTIM is less than thecritical voltage V C 903, the output ofcomparator 924 is logic low. Once the timing voltage VTIM reaches thecritical voltage V C 903, the output of thecomparator 924 transitions to a logic high value. The output of AND gate 920 (extension signal EXT 932) is logic high when both thecritical signal CRT 930 is logic high and the on-time signal U ON 418 is logic high. - Referring next to
FIG. 10 , another timing diagram illustrating various waveforms of voltages and currents of thetiming circuit 904 ofFIG. 9 is shown including aswitch current ID 1002, a on-time signal U ON 1004, acritical signal CRT 1006, anextension signal EXT 1008, atiming voltage VTIM 1010, aclock signal CLK 1012, and aDCMAX signal 1014. Further illustrated inFIG. 10 are switchingperiods T switching period T Switching periods T timing voltage VTIM 1010 also illustrates an upper reference voltage VH, a max duty ratio voltage VDM, a critical voltage VC, and a lower reference voltage VL. In addition,timing voltage VTIM 1010 may increase to the upper reference voltage VH with slope m1 or slope m2 while thetiming voltage VTIM 1010 may decrease to the lower reference voltage VL with slope m3. - The waveforms illustrated in
FIG. 10 are comparable to similarly named and numbered waveforms ofFIG. 8 . However, due to the use ofcomparator 724 and thecritical voltage V C 903, thecritical signal CRT 1006 varies fromcritical signal CRT 806 illustrated inFIG. 8 . In the example illustrated inFIG. 8 , thecritical signal CRT 806 shown was logic high at the beginning of each switching period TS and remained logic high until the on-time tON was substantially equal to the critical time tC. Once a time period substantially equal to the critical time elapsed, thecritical signal CRT 806 transitioned to the logic low value for the remainder of the switching period. Theextension signal EXT 808 would only transition to the logic high value when thedrive signal 804 was logic high at the same time that thecritical signal CRT 806 was logic low. - In the example illustrated in
FIG. 10 , thecritical signal CRT 1006 is at the logic low value at the beginning of eachswitching period T critical signal CRT 1006 transitions to the logic high value when thetiming voltage VTIM 1010 reaches the critical voltage VC, (corresponding to output ofcomparator 924 inFIG. 9 ). Thecritical signal CRT 1006 remains at the logic high value as thetiming voltage VTIM 1010 increases to the upper reference voltage VH (with either slope m1, slope m2, or both). As thetiming voltage VTIM 1010 decreases to the lower reference voltage VL, thecritical signal CRT 1006 remains at the logic high value until thetiming voltage VTIM 1010 falls below the critical voltage VC. Once theVTIM 1010 falls below the critical voltage VC, thecritical signal CRT 1006 transitions to the logic low value for the remainder of the switching period. - While the invention herein disclosed has been described by means of specific embodiments, examples and applications thereof, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope of the invention set forth in the claims.
Claims (12)
1. A controller for use in a power supply, the controller comprising,
a pulse width modulation (PWM) circuit to generate a drive signal to control a switch to regulate an output of the power supply in response to a switch current flowing through the switch and in response to a clock signal having a switching period; and
a timing circuit coupled to the PWM circuit to provide the clock signal, wherein the timing circuit includes:
a timing capacitor, where the switching period of the clock signal is based on a charging time that the timing capacitor charges to an upper reference voltage plus a discharging time that the timing capacitor discharges to a lower reference voltage;
a first current source coupled to charge the timing capacitor while the timing circuit is in a normal charging mode that is when an on time of the switch is less than a threshold time; and
a second current source coupled to charge the timing capacitor while the timing circuit is in an alternative charging mode that is when the on time of the switch exceeds the threshold time, wherein a magnitude of the current provided by the second current source is less than a magnitude of the current provided by the first current source such that the switching period of the clock signal is increased in response to the timing circuit entering the alternative charging mode.
2. The controller of claim 1 , wherein the timing circuit further comprises:
a first comparator coupled to compare a voltage on the timing capacitor with the lower reference voltage; and
a first monostable multivibrator coupled to generate a pulse of the clock signal in response to an output of the first comparator indicating that the timing capacitor has discharged to the lower reference voltage.
3. The controller of claim 1 , wherein the timing circuit further comprises:
a second monostable multivibrator coupled to output a pulse in response to the drive signal indicating the beginning of the on time of the switch, wherein a length of the pulse is equal to the threshold time; and
a logic gate coupled to receive the drive signal and the pulse of the second monostable multivibrator, wherein an output of the logic gate is coupled to enable the second current source and to disable the first current source if the on time of the switch exceeds the length of the pulse.
4. The controller of claim 3 , wherein the logic gate is configured to keep the second current source enabled and the first current source disabled until an end of the on time of the switch.
5. The controller of claim 1 , wherein the switching period of the clock signal is a fixed switching period when the on time of the switch is less than the threshold time.
6. The controller of claim 5 , wherein the threshold time is equal to one-half the fixed switching period.
7. The controller of claim 1 , wherein the timing circuit increases the switching period by an amount of time that is responsive to a difference in time between the on time of the switch and the threshold time.
8. The controller of claim 7 , wherein the amount of time that the timing circuit increases the switching period is proportional to the difference in time between the on time of the switch and the threshold time.
9. The controller of claim 1 , wherein the PWM circuit is coupled to turn off the switch in response to the switch current reaching a current limit.
10. The controller of claim 9 , wherein the PWM circuit is coupled to receive a feedback signal representative of the output of the power supply and wherein the current limit is a variable current limit responsive to the feedback signal.
11. The controller of claim 1 , wherein the second current source charges the timing capacitor for a remainder of the on time in response to the timing circuit entering the alternative charging mode.
12. The controller of claim 1 , wherein the magnitude of the current provided by the second current source is less than or equal to one-half the magnitude of the current provided by the first current source.
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US13/971,605 US8665620B2 (en) | 2011-07-28 | 2013-08-20 | Variable frequency timing circuit for a power supply control circuit |
US14/079,453 US9124186B2 (en) | 2011-07-28 | 2013-11-13 | Varying switching frequency and period of a power supply controller |
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US13/193,434 US8531853B2 (en) | 2011-07-28 | 2011-07-28 | Variable frequency timing circuit for a power supply control circuit |
US13/971,605 US8665620B2 (en) | 2011-07-28 | 2013-08-20 | Variable frequency timing circuit for a power supply control circuit |
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US13/971,605 Expired - Fee Related US8665620B2 (en) | 2011-07-28 | 2013-08-20 | Variable frequency timing circuit for a power supply control circuit |
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US (2) | US8531853B2 (en) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3014752A4 (en) * | 2014-02-11 | 2017-04-19 | Opulent Electronics International PTE Ltd. | Device and method for providing regulated current to an electrical load |
WO2023018272A1 (en) * | 2021-08-12 | 2023-02-16 | 엘지이노텍 주식회사 | Converter |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8611116B2 (en) | 2011-07-28 | 2013-12-17 | Power Integrations, Inc. | Varying switching frequency and period of a power supply controller |
US8531853B2 (en) | 2011-07-28 | 2013-09-10 | Power Integrations, Inc. | Variable frequency timing circuit for a power supply control circuit |
US9164133B2 (en) * | 2012-11-02 | 2015-10-20 | Power Integrations, Inc. | Switched averaging error amplifier |
CN103066872B (en) | 2013-01-17 | 2015-06-17 | 矽力杰半导体技术(杭州)有限公司 | Integration switch power supply controller and switch power supply using the same |
CN103151910B (en) | 2013-03-25 | 2015-05-13 | 矽力杰半导体技术(杭州)有限公司 | Undervoltage protection circuit, under-voltage protection method and switching power supply |
KR102095064B1 (en) * | 2013-08-12 | 2020-03-30 | 솔루엠 (허페이) 세미컨덕터 씨오., 엘티디. | Circuit for driving power switch, power supply apparatus and method for driving power switch |
US20150091539A1 (en) * | 2013-10-02 | 2015-04-02 | Infineon Technologies Autria AG | Half-bridge gate driver control |
TWI499183B (en) * | 2013-12-05 | 2015-09-01 | Richtek Technology Corp | Power factor correction circuit of power converter |
US9577527B2 (en) * | 2015-03-20 | 2017-02-21 | Active-Semi, Inc. | Current metering for transitioning between operating modes in switching regulators |
CN104779799B (en) | 2015-04-28 | 2017-05-31 | 矽力杰半导体技术(杭州)有限公司 | Control circuit, control method and apply its inverse excitation type converter |
FR3044843B1 (en) * | 2015-12-04 | 2018-01-05 | Sagem Defense Securite | METHOD FOR CONTROLLING CONTINUOUS / CONTINUOUS CONVERTER AND CONTINUOUS / CONTINUOUS CONVERTER FOR IMPLEMENTING SUCH A CONTROL METHOD. |
US10205394B2 (en) * | 2016-09-16 | 2019-02-12 | Power Integrations, Inc. | Switched mode power converter controller with ramp time modulation with jitter frequency |
US10148181B2 (en) * | 2016-10-07 | 2018-12-04 | Semiconductor Components Industries, Llc | Switched mode power supply with dynamic frequency foldback |
IT201700022236A1 (en) * | 2017-02-28 | 2018-08-28 | St Microelectronics Srl | TESTING CIRCUIT, POWER SUPPLY, EQUIPMENT AND CORRESPONDENT PROCEDURE |
US10199918B2 (en) * | 2017-07-10 | 2019-02-05 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device |
DE102018123729A1 (en) * | 2018-09-26 | 2020-03-26 | Tridonic Gmbh & Co Kg | Control gear for illuminants with power measurement and corresponding measuring method |
TWI832742B (en) * | 2023-03-31 | 2024-02-11 | 宏碁股份有限公司 | Boost converter for suppressing magnetic saturation |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5903452A (en) | 1997-08-11 | 1999-05-11 | System General Corporation | Adaptive slope compensator for current mode power converters |
JP3233099B2 (en) | 1998-03-27 | 2001-11-26 | 株式会社村田製作所 | DC-DC converter |
US6396718B1 (en) * | 2000-12-19 | 2002-05-28 | Semiconductor Components Industries Llc | Switch mode power supply using transformer flux sensing for duty cycle control |
JP2005506827A (en) | 2002-10-17 | 2005-03-03 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Frequency-modulated self-oscillating switching power supply |
US7272025B2 (en) * | 2005-01-18 | 2007-09-18 | Power Integrations, Inc. | Method and apparatus to control either a regulated or an unregulated output of a switching power supply |
US7593245B2 (en) * | 2005-07-08 | 2009-09-22 | Power Integrations, Inc. | Method and apparatus to limit maximum switch current in a switching power supply |
US7746050B2 (en) * | 2007-04-06 | 2010-06-29 | Power Integrations, Inc. | Method and apparatus for controlling the maximum output power of a power converter |
JP2010041832A (en) * | 2008-08-06 | 2010-02-18 | Panasonic Corp | Switching power supply controller and semiconductor apparatus used for the same |
JP5277952B2 (en) | 2008-12-25 | 2013-08-28 | 富士電機株式会社 | Switching power supply circuit |
US8222882B2 (en) * | 2009-01-30 | 2012-07-17 | Power Integrations, Inc. | Power supply controller with input voltage compensation for efficiency and maximum power output |
US7965151B2 (en) * | 2009-06-02 | 2011-06-21 | Power Integrations, Inc. | Pulse width modulator with two-way integrator |
US8427848B2 (en) * | 2010-12-22 | 2013-04-23 | Power Integrations, Inc. | Variable time clamp for a power supply controller |
US8611116B2 (en) | 2011-07-28 | 2013-12-17 | Power Integrations, Inc. | Varying switching frequency and period of a power supply controller |
US8531853B2 (en) | 2011-07-28 | 2013-09-10 | Power Integrations, Inc. | Variable frequency timing circuit for a power supply control circuit |
-
2011
- 2011-07-28 US US13/193,434 patent/US8531853B2/en not_active Expired - Fee Related
-
2012
- 2012-07-27 TW TW101127111A patent/TWI466419B/en not_active IP Right Cessation
- 2012-07-27 KR KR1020120082230A patent/KR101302258B1/en not_active IP Right Cessation
- 2012-07-30 CN CN201210268566.3A patent/CN102904447B/en not_active Expired - Fee Related
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- 2013-08-20 US US13/971,605 patent/US8665620B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3014752A4 (en) * | 2014-02-11 | 2017-04-19 | Opulent Electronics International PTE Ltd. | Device and method for providing regulated current to an electrical load |
WO2023018272A1 (en) * | 2021-08-12 | 2023-02-16 | 엘지이노텍 주식회사 | Converter |
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TWI466419B (en) | 2014-12-21 |
KR20130014403A (en) | 2013-02-07 |
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US20130027996A1 (en) | 2013-01-31 |
US8531853B2 (en) | 2013-09-10 |
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US8665620B2 (en) | 2014-03-04 |
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