US20130319613A1 - Cut-very-last dual-epi flow - Google Patents

Cut-very-last dual-epi flow Download PDF

Info

Publication number
US20130319613A1
US20130319613A1 US13/545,456 US201213545456A US2013319613A1 US 20130319613 A1 US20130319613 A1 US 20130319613A1 US 201213545456 A US201213545456 A US 201213545456A US 2013319613 A1 US2013319613 A1 US 2013319613A1
Authority
US
United States
Prior art keywords
fins
array
masking material
epitaxial
epitaxial material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US13/545,456
Other versions
US8592290B1 (en
Inventor
Veeraraghavan S. Basker
Huiming Bu
Kangguo Cheng
Balasubramanian S. Haran
Nicolas Loubet
Shom Ponoth
Stefan Schmitz
Theodorus E. Standaert
Tenko Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
GlobalFoundries US Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US13/545,456 priority Critical patent/US8592290B1/en
Application granted granted Critical
Publication of US8592290B1 publication Critical patent/US8592290B1/en
Publication of US20130319613A1 publication Critical patent/US20130319613A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BASKER, VEERARAGHAVAN S., CHENG, KANGGUO, LOUBET, NICOLAS, PONOTH, SHOM, SCHMITZ, STEFAN, BU, HUIMING, HARAN, BALASUBRAMANIAN S., STANDAERT, THEODORUS E., YAMASHITA, TENKO
Assigned to STMICROELECTRONICS, INC. reassignment STMICROELECTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LOUBET, NICOLAS
Assigned to STMICROELECTRONICS, INC. reassignment STMICROELECTRONICS, INC. QUITCLAIM ASSIGNMENT Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Definitions

  • the exemplary embodiments of this invention relate generally to field effect transistors (FETs) and, more specifically, relate to dual-epi FETs.
  • a method in an exemplary aspect includes adding a first epitaxial material to an array of fins.
  • the method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins.
  • Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method.
  • the method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • an apparatus in another exemplary aspect includes a processor and a memory storing program instructions.
  • the memory and the program instructions are configured to, with the processor, cause the apparatus to perform actions.
  • the actions include adding a first epitaxial material to an array of fins.
  • the actions also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins.
  • Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the actions.
  • the actions also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • a computer program product includes program instructions embodied on a tangible computer-readable medium, execution of the program instructions resulting in operations.
  • the operations include adding a first epitaxial material to an array of fins.
  • the operations also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins.
  • Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the operations.
  • the operations also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • an apparatus in another exemplary aspect includes means for adding a first epitaxial material to an array of fins.
  • the apparatus also includes means for covering at least a first portion of the array of fins using a first masking material and means for removing the first epitaxial material from an uncovered portion of the array of fins.
  • Means for adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the apparatus.
  • the apparatus also includes means for covering a second portion of the array of fins using a second masking material and means for performing a directional etch using the first masking material and the second masking material.
  • FIGS. 1A and 1B collectively referred to as FIG. 1 , illustrate a top-down view ( FIG. 1A ) and a cross-section view ( FIG. 1B ) of fin FETs created in accordance with an exemplary embodiment.
  • FIGS. 2A and 2B collectively referred to as FIG. 2 , illustrate a top-down view ( FIG. 2A ) and a cross-section view ( FIG. 2B ) of the FinFETs during a stage of creation in accordance with an exemplary embodiment.
  • FIGS. 3A and 3B collectively referred to as FIG. 3 , illustrate a top-down view ( FIG. 3A ) and a cross-section view ( FIG. 3B ) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIGS. 4A and 4B collectively referred to as FIG. 4 , illustrate a top-down view ( FIG. 4A ) and a cross-section view ( FIG. 4B ) of the FinFETs during a further stage of creation in accordance with an exemplary embodiment.
  • FIGS. 5A and 5B collectively referred to as FIG. 5 , illustrate a top-down view ( FIG. 5A ) and a cross-section view ( FIG. 5B ) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIGS. 6A and 6B collectively referred to as FIG. 6 , illustrate a top-down view ( FIG. 6A ) and a cross-section view ( FIG. 6B ) of the FinFETs during a further stage of creation in accordance with an exemplary embodiment.
  • FIGS. 7A and 7B collectively referred to as FIG. 7 , illustrate a top-down view ( FIG. 7A ) and a cross-section view ( FIG. 7B ) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIGS. 8A and 8B collectively referred to as FIG. 8 , illustrate a top-down view ( FIG. 8A ) and a cross-section view ( FIG. 8B ) of the FinFETs during a further stage of creation in accordance with an exemplary embodiment.
  • FIGS. 9A and 9B collectively referred to as FIG. 9 , illustrate a top-down view ( FIG. 9A ) and a cross-section view ( FIG. 9B ) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIG. 10 shows a simplified block diagram of exemplary electronic devices that are suitable for use in practicing various exemplary embodiments.
  • FIG. 11 is a logic flow diagram that illustrates the operation of an exemplary method, and a result of execution of computer program instructions embodied on a computer readable memory, in accordance with various exemplary embodiments.
  • FIGS. 12A and 12B collectively referred to as FIG. 12 , illustrate a top-down view ( FIG. 3A ) and a cross-section view ( FIG. 3B ) of the FinFETs during an alternative stage of creation in accordance with an exemplary embodiment.
  • a field effect transistor is a transistor having a source, a gate, and a drain.
  • the action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, may be controlled by a transverse electric field under the gate.
  • P-type FETs As known to those skilled in the art, P-type FETs (PFETs) turn ON to allow current flow from source to drain when the gate terminal is at a low or negative potential with respect to the source. When the gate potential is positive or the same as the source, the P-type FET is OFF, and does not conduct current.
  • N-type FETs NFETs
  • NFETs N-type FETs
  • More than one gate can be used to more effectively control the channel.
  • the length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (such as the distance between the source and drain).
  • Multi-gate FETs are considered to be promising candidates to scale down complementary metal-oxide semiconductor (CMOS) FET technology.
  • CMOS complementary metal-oxide semiconductor
  • MOS metal-oxide semiconductor
  • a FET employing such a channel structure may be referred to as a FinFET.
  • CMOS devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate.
  • the gate controls the channel more strongly because it extends over more than one side (surface) of the channel. For example, the gate can enclose three surfaces of the three-dimensional channel, rather than being disposed only across the top surface of the traditional planar channel.
  • halo implant may include arsenic, phosphorous, boron and/or indium.
  • Silicon-on-insulator (SOI) wafers have been used to exploit the improved quality of monocrystalline silicon provided thereby in an active layer formed on an insulator over a bulk silicon “handling” substrate. Similar attributes can be developed in similar structures of other semiconductor materials and alloys thereof.
  • the improved quality of the semiconductor material of the active layer allows transistors and other devices to be scaled to extremely small sizes with good uniformity of electrical properties.
  • An exemplary embodiment is a cut-very-last processing flow which enables dual-epi for FinFET.
  • the epi-merge of the fins in the source/drain (S/D) regions is very challenging if independent epi control is used for NFET and PFET.
  • independent epi control may require mitigation of any unwanted epi-shorting between devices in the SRAM.
  • the new processing flow is a single-mask solution enabling dual-epi and resolves any epi-shorting that might occur between various devices.
  • dummy fins remain until the end of device fabrication and are cut in the last stage of the device fabrication (after source/drain formation).
  • fins are defined by sidewall image transfer (SIT) and unwanted dummy fins are cut (removed) immediately following SIT.
  • Device fabrication such as gate, spacer, source/drain are then formed after fin cut.
  • FIGS. 1A and 1B illustrate a non-limiting example of finFETs created in accordance with an exemplary embodiment.
  • NFETs 110 are shown with P-doped Si 115 .
  • the PFETs 120 have BSiGe 125 .
  • Layered on top of the FinFETs 110 , 120 is gate 102 .
  • the FinFETs 110 , 120 are located on a substrate 140 . Each FinFET includes a cap 128 .
  • the FinFETs 110 , 120 are regularly spaced with the distance 135 between the PFETs 120 and their neighbor FinFET (either the other PFET 120 or an NFET 110 ) is twice the fin pitch 130 (or distance between adjacent fins of NFETs 110 ).
  • FIGS. 2A and 2B illustrate the finFETs 110 , 120 during a stage of creation in accordance with an exemplary embodiment.
  • an array of fins 104 (which will become FinFETs 110 , 120 ) is positioned on the substrate 140 .
  • a gate reactive ion etch (RIE) may be used to ensure the array of fins 104 is clean of unwanted debris. Note that for a regular array of fin 104 , the fins 104 are evenly spaced such that the distance between adjacent fins (or fin pitch) 130 is the same for all fins 104 .
  • FIGS. 3A and 3B illustrate the finFETs 110 , 120 during another stage of creation in accordance with an exemplary embodiment.
  • a first epitaxial material (BSiGe 125 ) is added to merge all fins 104 .
  • FIGS. 4A and 4B illustrate the finFETs 110 , 120 during a further stage of creation in accordance with an exemplary embodiment.
  • a thin nitride deposition 410 is layered over the fins 104 and the BSiGe 125 . This may be done using an in-situ radical assisted deposition (iRAD).
  • iRAD in-situ radical assisted deposition
  • FIGS. 5A and 5B illustrate the finFETs 110 , 120 during another stage of creation in accordance with an exemplary embodiment. At this stage, the NFET 110 areas are exposed by removing the nitride deposition 410 covering these areas.
  • FIGS. 6A and 6B illustrate the finFETs 110 , 120 during a further stage of creation in accordance with an exemplary embodiment.
  • the BSiGe 125 is removed from the exposed NFET 110 areas.
  • the BSiGe 125 may be removed using an HCl etch.
  • FIGS. 7A and 7B illustrate the finFETs 110 , 120 during another stage of creation in accordance with an exemplary embodiment.
  • a second epitaxial material P-doped Si- 115
  • FIGS. 6 and 7 can be performed in a single step on epi-platform.
  • FIGS. 8A and 8B illustrate the finFETs 110 , 120 during a further stage of creation in accordance with an exemplary embodiment.
  • the active areas are defined by adding a masking material 810 which will protect some fins while unwanted dummy fins are not protected by this mask.
  • FIG. 9 illustrates the finFETs 110 , 120 during another stage of creation in accordance with an exemplary embodiment.
  • a direction etch (or cut) is made using the masking material 810 (shown in FIGS. 8A and 8B ) and the nitride deposition 410 as masking materials. This removes the non-active BSiGe 125 , P-Doped Si 115 and some of the non-masked fins 104 .
  • the etch also removes the masking material 810 and the non-masked nitride deposition 410 .
  • the cut may (or may not) also remove a portion of the substrate 140 .
  • the finFETs 110 , 120 may be constructed with the locations of the PFETs 120 and NFETs 110 switched. Accordingly, the epitaxial material (such as BSiGe 125 and P-Doped Si 115 ) may also be switched as well as any accompanying changes to the masking material (masking material 810 and nitride deposition 410 ).
  • the epitaxial material such as BSiGe 125 and P-Doped Si 115
  • the epitaxial material (BSiGe 125 and P-Doped Si 115 ) may be of any type suitable to the local technical environment and may be implemented using any suitable technology.
  • the masking material (masking material 810 and nitride deposition 410 ) may be of any type suitable to the local technical environment and may be implemented using any suitable technology.
  • FIGS. 12A and 12B illustrate the finFETs 110 , 120 during an alternative stage of creation in accordance with an exemplary embodiment.
  • the first epitaxial material (BSiGe 125 ) is added to the fins 104 . While the epitaxial growth is sufficient to be on the fins, the epitaxial material does not physically merge the fins.
  • additional spacer material may be added to cover and isolate “dummy’ channels underneath the gate that may remain after the cut. These channels are undoped and are invisible from a parasitic point of view.
  • An exemplary cut-very-last process resolves unwanted epi-shorting between devices as well as wrap-around of epi at gate line-ends, especially SRAM.
  • the cut-very-last approach uses dummy/sacrificial fins. These dummy fins are placed at every N-to-P transition (boundary between N-FETs and P-FETs). Thus, the spacing of pull-ups (PUs), pass-down and pass-gate devices in the SRAM is at 2 ⁇ fin pitch.
  • the P-Doped Si 115 may be slightly thicker for the NFET extension/P-doped Si; however, the lateral HCl etch provides minimal end-device impact. Additionally, the total spacer increase for the S/D may be accounted for.
  • FIG. 10 for illustrating a simplified block diagram of various electronic devices and apparatus that are suitable for use in practicing exemplary embodiments.
  • computer 1010 may be used to control a lithography process in accordance with an exemplary embodiment.
  • the computer 1010 includes a controller, such as a computer or a data processor (DP) 1014 and a computer-readable memory medium embodied as a memory (MEM) 1016 that stores a program of computer instructions (PROG) 1018 .
  • a controller such as a computer or a data processor (DP) 1014 and a computer-readable memory medium embodied as a memory (MEM) 1016 that stores a program of computer instructions (PROG) 1018 .
  • DP data processor
  • MEM memory
  • PROG program of computer instructions
  • the PROGs 1018 is assumed to include program instructions that, when executed by the associated DP 1014 , enable the device to operate in accordance with exemplary embodiments, as will be discussed below in greater detail.
  • various exemplary embodiments may be implemented at least in part by computer software executable by the DP 1014 of the computer 1010 , or by hardware, or by a combination of software and hardware (and firmware).
  • the computer 1010 may also include dedicated processors, for example lithography controller 1015 .
  • the computer readable MEM 1016 may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory.
  • the DP 1014 may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on a multicore processor architecture, as non-limiting examples.
  • exemplary embodiments may be implemented in conjunction with a program storage device (e.g., at least one memory) readable by a machine, tangibly embodying a program of instructions (e.g., a program or computer program) executable by the machine for performing operations.
  • the operations comprise steps of utilizing the exemplary embodiments or steps of the method.
  • FIG. 11 is a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions (such as PROG 1018 ), in accordance with exemplary embodiments.
  • a method performs, at Block 1110 , a step of adding a first epitaxial material to an array of fins.
  • a step of covering at least a first portion of the array of fins using a first masking material is performed by the method at Block 1120 .
  • the method performs a step of removing the first epitaxial material from an uncovered portion of the array of fins at Block 1130 .
  • the method performs a step of adding a second epitaxial material to the fins in the uncovered portion of the array of fins.
  • a step of covering a second portion of the array of fins using a second masking material is performed by the method at Block 1150 .
  • the method performs a step of performing a directional etch using the first masking material and the second masking material at Block 1160 .
  • the various blocks shown in FIG. 11 may be viewed as method steps, and/or as operations that result from operation of computer program code, and/or as a plurality of coupled logic circuit elements constructed to carry out the associated function(s).
  • An exemplary embodiment provides a method for making dual-epi FinFETs.
  • the method includes adding a first epitaxial material to an array of fins.
  • the method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins.
  • Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method.
  • the method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • the method also includes performing a reactive ion etch.
  • the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • the method also includes, in response to covering at least the first portion of the merged array of fins using the first masking material, removing the first masking material from a second portion of the merged array of fins.
  • removing the first epitaxial material includes removing the first epitaxial using an HCl etch.
  • removing the first epitaxial material and adding the second epitaxial material is performed in a single step on an epi-platform.
  • performing the directional etch removes at least one fin in the array of fins.
  • the apparatus includes a processor and a memory storing program instructions.
  • the memory and the program instructions are configured to, with the processor, cause the apparatus to perform actions.
  • the actions include adding a first epitaxial material to an array of fins.
  • the actions also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins.
  • Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the actions.
  • the actions also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • the actions also include performing a reactive ion etch.
  • the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • the actions also include, in response to covering at least the first portion of the merged array of fins using the first masking material, removing the first masking material from a second portion of the merged array of fins.
  • removing the first epitaxial material includes removing the first epitaxial using an HCl etch.
  • removing the first epitaxial material and adding the second epitaxial material is performed in a single step on an epi-platform.
  • performing the directional etch removes at least one fin in the array of fins.
  • the apparatus is embodied in an application-specific integrated circuit.
  • the apparatus is embodied in an integrated circuit.
  • the computer program product includes program instructions embodied on a tangible computer-readable medium, execution of the program instructions resulting in operations.
  • the operations include adding a first epitaxial material to an array of fins.
  • the operations also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins.
  • Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the operations.
  • the operations also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • the operations also include performing a reactive ion etch.
  • the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • the operations also include, in response to covering at least the first portion of the merged array of fins using the first masking material, removing the first masking material from a second portion of the merged array of fins.
  • removing the first epitaxial material includes removing the first epitaxial using an HCl etch.
  • removing the first epitaxial material and adding the second epitaxial material is performed in a single step on an epi-platform.
  • performing the directional etch removes at least one fin in the array of fins.
  • the computer-readable medium is a non-transitory computer readable medium (e.g., CD-ROM, RAM, flash memory, etc.).
  • the computer-readable medium is a storage medium.
  • the apparatus includes means for adding a first epitaxial material to an array of fins.
  • the apparatus also includes means for covering at least a first portion of the array of fins using a first masking material and means for removing the first epitaxial material from an uncovered portion of the array of fins.
  • Means for adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the apparatus.
  • the apparatus also includes means for covering a second portion of the array of fins using a second masking material and means for performing a directional etch using the first masking material and the second masking material.
  • the apparatus also includes means for performing a reactive ion etch.
  • the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • the apparatus also includes means for removing the first masking material from a second portion of the merged array of fins in response to covering at least the first portion of the merged array of fins using the first masking material.
  • the means for removing the first epitaxial material includes means for removing the first epitaxial using an HCl etch.
  • performing the directional etch removes at least one fin in the array of fins.
  • connection or coupling should be interpreted to indicate any such connection or coupling, direct or indirect, between the identified elements.
  • one or more intermediate elements may be present between the “coupled” elements.
  • the connection or coupling between the identified elements may be, as non-limiting examples, physical, electrical, magnetic, logical or any suitable combination thereof in accordance with the described exemplary embodiments.
  • the connection or coupling may comprise one or more printed electrical connections, wires, cables, mediums or any suitable combination thereof.
  • various exemplary embodiments can be implemented in different mediums, such as software, hardware, logic, special purpose circuits or any combination thereof.
  • some aspects may be implemented in software which may be run on a computing device, while other aspects may be implemented in hardware.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

Description

    TECHNICAL FIELD
  • The exemplary embodiments of this invention relate generally to field effect transistors (FETs) and, more specifically, relate to dual-epi FETs.
    • BACKGROUND
  • This section is intended to provide a background or context. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
  • Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. In the microelectronics industry as well as in other industries involving construction of microscopic structures (such as micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization, in general, allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost.
  • Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors. Circuit chips with hundreds of millions of such devices are not uncommon. Further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates.
    • BRIEF SUMMARY
  • In an exemplary aspect a method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • In another exemplary aspect an apparatus includes a processor and a memory storing program instructions. The memory and the program instructions are configured to, with the processor, cause the apparatus to perform actions. The actions include adding a first epitaxial material to an array of fins. The actions also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the actions. The actions also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • In a further exemplary aspect a computer program product includes program instructions embodied on a tangible computer-readable medium, execution of the program instructions resulting in operations. The operations include adding a first epitaxial material to an array of fins. The operations also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the operations. The operations also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • In another exemplary aspect an apparatus includes means for adding a first epitaxial material to an array of fins. The apparatus also includes means for covering at least a first portion of the array of fins using a first masking material and means for removing the first epitaxial material from an uncovered portion of the array of fins. Means for adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the apparatus. The apparatus also includes means for covering a second portion of the array of fins using a second masking material and means for performing a directional etch using the first masking material and the second masking material.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The foregoing and other aspects of exemplary embodiments are made more evident in the following Detailed Description, when read in conjunction with the attached Drawing Figures, wherein:
  • FIGS. 1A and 1B, collectively referred to as FIG. 1, illustrate a top-down view (FIG. 1A) and a cross-section view (FIG. 1B) of fin FETs created in accordance with an exemplary embodiment.
  • FIGS. 2A and 2B, collectively referred to as FIG. 2, illustrate a top-down view (FIG. 2A) and a cross-section view (FIG. 2B) of the FinFETs during a stage of creation in accordance with an exemplary embodiment.
  • FIGS. 3A and 3B, collectively referred to as FIG. 3, illustrate a top-down view (FIG. 3A) and a cross-section view (FIG. 3B) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIGS. 4A and 4B, collectively referred to as FIG. 4, illustrate a top-down view (FIG. 4A) and a cross-section view (FIG. 4B) of the FinFETs during a further stage of creation in accordance with an exemplary embodiment.
  • FIGS. 5A and 5B, collectively referred to as FIG. 5, illustrate a top-down view (FIG. 5A) and a cross-section view (FIG. 5B) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIGS. 6A and 6B, collectively referred to as FIG. 6, illustrate a top-down view (FIG. 6A) and a cross-section view (FIG. 6B) of the FinFETs during a further stage of creation in accordance with an exemplary embodiment.
  • FIGS. 7A and 7B, collectively referred to as FIG. 7, illustrate a top-down view (FIG. 7A) and a cross-section view (FIG. 7B) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIGS. 8A and 8B, collectively referred to as FIG. 8, illustrate a top-down view (FIG. 8A) and a cross-section view (FIG. 8B) of the FinFETs during a further stage of creation in accordance with an exemplary embodiment.
  • FIGS. 9A and 9B, collectively referred to as FIG. 9, illustrate a top-down view (FIG. 9A) and a cross-section view (FIG. 9B) of the FinFETs during another stage of creation in accordance with an exemplary embodiment.
  • FIG. 10 shows a simplified block diagram of exemplary electronic devices that are suitable for use in practicing various exemplary embodiments.
  • FIG. 11 is a logic flow diagram that illustrates the operation of an exemplary method, and a result of execution of computer program instructions embodied on a computer readable memory, in accordance with various exemplary embodiments.
  • FIGS. 12A and 12B, collectively referred to as FIG. 12, illustrate a top-down view (FIG. 3A) and a cross-section view (FIG. 3B) of the FinFETs during an alternative stage of creation in accordance with an exemplary embodiment.
    •  DETAILED DESCRIPTION
  • The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
  • B—SiGe boron-doped silicon-germanium
  • CMOS complementary metal-oxide semiconductor
  • epi epitaxial/epitaxy
  • FET field effect transistor
  • HCl hydrogen chloride
  • MOS metal-oxide semiconductor
  • NFET n-type FET
  • PFET p-type FET
  • SIT sidewall image transfer
  • SOI silicon-on-insulator
  • A field effect transistor (FET) is a transistor having a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, may be controlled by a transverse electric field under the gate.
  • As known to those skilled in the art, P-type FETs (PFETs) turn ON to allow current flow from source to drain when the gate terminal is at a low or negative potential with respect to the source. When the gate potential is positive or the same as the source, the P-type FET is OFF, and does not conduct current. On the other hand, N-type FETs (NFETs) turn ON to allow current flow from source to drain when the gate terminal is high or positive with respect to the source. When the gate potential is negative or the same as the source, the N-type FET is OFF, and does not conduct current. Note that in each of these cases there is a threshold voltage (such as at the gate terminal) for triggering actuation of the FET.
  • More than one gate (multi-gate) can be used to more effectively control the channel. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (such as the distance between the source and drain). Multi-gate FETs are considered to be promising candidates to scale down complementary metal-oxide semiconductor (CMOS) FET technology. However, such small dimensions necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current and the parasitic resistance that is present in a multi-gate FET.
  • The size of FETs has been successfully reduced through the use of one or more fin-shaped channels. A FET employing such a channel structure may be referred to as a FinFET. Previously, CMOS devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate. The gate controls the channel more strongly because it extends over more than one side (surface) of the channel. For example, the gate can enclose three surfaces of the three-dimensional channel, rather than being disposed only across the top surface of the traditional planar channel.
  • One technique for affecting the threshold voltage (such as increasing the threshold voltage, encouraging a more constant threshold voltage over different gate lengths) is to use locally implanted dopants under the gate edge(s). This is referred to as a “halo” implant. As non-limiting examples, the halo implant may include arsenic, phosphorous, boron and/or indium.
  • Silicon-on-insulator (SOI) wafers have been used to exploit the improved quality of monocrystalline silicon provided thereby in an active layer formed on an insulator over a bulk silicon “handling” substrate. Similar attributes can be developed in similar structures of other semiconductor materials and alloys thereof. The improved quality of the semiconductor material of the active layer allows transistors and other devices to be scaled to extremely small sizes with good uniformity of electrical properties.
  • An exemplary embodiment is a cut-very-last processing flow which enables dual-epi for FinFET. The epi-merge of the fins in the source/drain (S/D) regions is very challenging if independent epi control is used for NFET and PFET. In addition, independent epi control may require mitigation of any unwanted epi-shorting between devices in the SRAM. In contrast, the new processing flow is a single-mask solution enabling dual-epi and resolves any epi-shorting that might occur between various devices.
  • In the cut-very-last processing flow, dummy fins remain until the end of device fabrication and are cut in the last stage of the device fabrication (after source/drain formation). However, in a conventional finFET process, fins are defined by sidewall image transfer (SIT) and unwanted dummy fins are cut (removed) immediately following SIT. Device fabrication such as gate, spacer, source/drain are then formed after fin cut.
  • FIGS. 1A and 1B illustrate a non-limiting example of finFETs created in accordance with an exemplary embodiment. In the top-down view of FIG. 1A, NFETs 110 are shown with P-doped Si 115. The PFETs 120 have BSiGe 125. Layered on top of the FinFETs 110, 120 is gate 102.
  • Shown FIG. 1B (the cross-section view), the FinFETs 110, 120 are located on a substrate 140. Each FinFET includes a cap 128. The FinFETs 110, 120 are regularly spaced with the distance 135 between the PFETs 120 and their neighbor FinFET (either the other PFET 120 or an NFET 110) is twice the fin pitch 130 (or distance between adjacent fins of NFETs 110).
  • FIGS. 2A and 2B illustrate the finFETs 110, 120 during a stage of creation in accordance with an exemplary embodiment. At this stage, an array of fins 104 (which will become FinFETs 110, 120) is positioned on the substrate 140. A gate reactive ion etch (RIE) may be used to ensure the array of fins 104 is clean of unwanted debris. Note that for a regular array of fin 104, the fins 104 are evenly spaced such that the distance between adjacent fins (or fin pitch) 130 is the same for all fins 104.
  • FIGS. 3A and 3B illustrate the finFETs 110, 120 during another stage of creation in accordance with an exemplary embodiment. At this stage, a first epitaxial material (BSiGe 125) is added to merge all fins 104.
  • FIGS. 4A and 4B illustrate the finFETs 110, 120 during a further stage of creation in accordance with an exemplary embodiment. Here, a thin nitride deposition 410 is layered over the fins 104 and the BSiGe 125. This may be done using an in-situ radical assisted deposition (iRAD).
  • FIGS. 5A and 5B illustrate the finFETs 110, 120 during another stage of creation in accordance with an exemplary embodiment. At this stage, the NFET 110 areas are exposed by removing the nitride deposition 410 covering these areas.
  • FIGS. 6A and 6B illustrate the finFETs 110, 120 during a further stage of creation in accordance with an exemplary embodiment. During this stage, the BSiGe 125 is removed from the exposed NFET 110 areas. As a non-limiting example, the BSiGe 125 may be removed using an HCl etch.
  • FIGS. 7A and 7B illustrate the finFETs 110, 120 during another stage of creation in accordance with an exemplary embodiment. Here, a second epitaxial material (P-doped Si-115) is added to merge the NFET 110 fins 104. Note that the stages shown in FIGS. 6 and 7 can be performed in a single step on epi-platform.
  • FIGS. 8A and 8B illustrate the finFETs 110, 120 during a further stage of creation in accordance with an exemplary embodiment. The active areas are defined by adding a masking material 810 which will protect some fins while unwanted dummy fins are not protected by this mask.
  • FIG. 9 illustrates the finFETs 110, 120 during another stage of creation in accordance with an exemplary embodiment. In this stage, a direction etch (or cut) is made using the masking material 810 (shown in FIGS. 8A and 8B) and the nitride deposition 410 as masking materials. This removes the non-active BSiGe 125, P-Doped Si 115 and some of the non-masked fins 104. The etch also removes the masking material 810 and the non-masked nitride deposition 410. The cut may (or may not) also remove a portion of the substrate 140.
  • Note that in a further exemplary embodiment the finFETs 110, 120 may be constructed with the locations of the PFETs 120 and NFETs 110 switched. Accordingly, the epitaxial material (such as BSiGe 125 and P-Doped Si 115) may also be switched as well as any accompanying changes to the masking material (masking material 810 and nitride deposition 410).
  • The epitaxial material (BSiGe 125 and P-Doped Si 115) may be of any type suitable to the local technical environment and may be implemented using any suitable technology. Likewise, the masking material (masking material 810 and nitride deposition 410) may be of any type suitable to the local technical environment and may be implemented using any suitable technology.
  • FIGS. 12A and 12B illustrate the finFETs 110, 120 during an alternative stage of creation in accordance with an exemplary embodiment. At this stage, which would replace the stage shown in FIGS. 3A and 3B, the first epitaxial material (BSiGe 125) is added to the fins 104. While the epitaxial growth is sufficient to be on the fins, the epitaxial material does not physically merge the fins.
  • In another embodiment, additional spacer material may be added to cover and isolate “dummy’ channels underneath the gate that may remain after the cut. These channels are undoped and are invisible from a parasitic point of view.
  • By performing the cut last, this enables a uniform gate profile and extension across all fins. Accordingly, the voltage threshold (Vt) to width dependence is improved.
  • An exemplary cut-very-last process resolves unwanted epi-shorting between devices as well as wrap-around of epi at gate line-ends, especially SRAM. The cut-very-last approach uses dummy/sacrificial fins. These dummy fins are placed at every N-to-P transition (boundary between N-FETs and P-FETs). Thus, the spacing of pull-ups (PUs), pass-down and pass-gate devices in the SRAM is at 2×fin pitch.
  • The P-Doped Si 115 may be slightly thicker for the NFET extension/P-doped Si; however, the lateral HCl etch provides minimal end-device impact. Additionally, the total spacer increase for the S/D may be accounted for.
  • Reference is made to FIG. 10 for illustrating a simplified block diagram of various electronic devices and apparatus that are suitable for use in practicing exemplary embodiments. For example, computer 1010 may be used to control a lithography process in accordance with an exemplary embodiment.
  • The computer 1010 includes a controller, such as a computer or a data processor (DP) 1014 and a computer-readable memory medium embodied as a memory (MEM) 1016 that stores a program of computer instructions (PROG) 1018.
  • The PROGs 1018 is assumed to include program instructions that, when executed by the associated DP 1014, enable the device to operate in accordance with exemplary embodiments, as will be discussed below in greater detail.
  • That is, various exemplary embodiments may be implemented at least in part by computer software executable by the DP 1014 of the computer 1010, or by hardware, or by a combination of software and hardware (and firmware).
  • The computer 1010 may also include dedicated processors, for example lithography controller 1015.
  • The computer readable MEM 1016 may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. The DP 1014 may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on a multicore processor architecture, as non-limiting examples.
  • The exemplary embodiments, as discussed herein and as particularly described with respect to exemplary methods, may be implemented in conjunction with a program storage device (e.g., at least one memory) readable by a machine, tangibly embodying a program of instructions (e.g., a program or computer program) executable by the machine for performing operations. The operations comprise steps of utilizing the exemplary embodiments or steps of the method.
  • Based on the foregoing it should be apparent that various exemplary embodiments provide a method, apparatus and computer program(s) to make dual-epi FinFETs.
  • FIG. 11 is a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions (such as PROG 1018), in accordance with exemplary embodiments. In accordance with these exemplary embodiments a method performs, at Block 1110, a step of adding a first epitaxial material to an array of fins. A step of covering at least a first portion of the array of fins using a first masking material is performed by the method at Block 1120. The method performs a step of removing the first epitaxial material from an uncovered portion of the array of fins at Block 1130. At Block 1140, the method performs a step of adding a second epitaxial material to the fins in the uncovered portion of the array of fins. A step of covering a second portion of the array of fins using a second masking material is performed by the method at Block 1150. The method performs a step of performing a directional etch using the first masking material and the second masking material at Block 1160.
  • The various blocks shown in FIG. 11 may be viewed as method steps, and/or as operations that result from operation of computer program code, and/or as a plurality of coupled logic circuit elements constructed to carry out the associated function(s).
  • An exemplary embodiment provides a method for making dual-epi FinFETs. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • In a further exemplary embodiment of the method above, the method also includes performing a reactive ion etch.
  • In another exemplary embodiment of any one of the methods above, the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • In a further exemplary embodiment of any one of the methods above, the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • In another exemplary embodiment of any one of the methods above, the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • In a further exemplary embodiment of any one of the methods above, the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • In another exemplary embodiment of any one of the methods above, the method also includes, in response to covering at least the first portion of the merged array of fins using the first masking material, removing the first masking material from a second portion of the merged array of fins.
  • In a further exemplary embodiment of any one of the methods above, removing the first epitaxial material includes removing the first epitaxial using an HCl etch.
  • In another exemplary embodiment of any one of the methods above, removing the first epitaxial material and adding the second epitaxial material is performed in a single step on an epi-platform.
  • In a further exemplary embodiment of any one of the methods above, performing the directional etch removes at least one fin in the array of fins.
  • Another exemplary embodiment provides an apparatus for making dual-epi FinFETs. The apparatus includes a processor and a memory storing program instructions. The memory and the program instructions are configured to, with the processor, cause the apparatus to perform actions. The actions include adding a first epitaxial material to an array of fins. The actions also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the actions. The actions also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • In a further exemplary embodiment of the apparatus above, the actions also include performing a reactive ion etch.
  • In another exemplary embodiment of any one of the apparatus above, the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • In a further exemplary embodiment of any one of the apparatus above, the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • In another exemplary embodiment of any one of the apparatus above, the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • In a further exemplary embodiment of any one of the apparatus above, the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • In another exemplary embodiment of any one of the apparatus above, the actions also include, in response to covering at least the first portion of the merged array of fins using the first masking material, removing the first masking material from a second portion of the merged array of fins.
  • In a further exemplary embodiment of any one of the apparatus above, removing the first epitaxial material includes removing the first epitaxial using an HCl etch.
  • In another exemplary embodiment of any one of the apparatus above, removing the first epitaxial material and adding the second epitaxial material is performed in a single step on an epi-platform.
  • In a further exemplary embodiment of any one of the apparatus above, performing the directional etch removes at least one fin in the array of fins.
  • In another exemplary embodiment of any one of the apparatus above, the apparatus is embodied in an application-specific integrated circuit.
  • In a further exemplary embodiment of any one of the apparatus above, the apparatus is embodied in an integrated circuit.
  • Another exemplary embodiment provides a computer program product for making dual-epi FinFETs. The computer program product includes program instructions embodied on a tangible computer-readable medium, execution of the program instructions resulting in operations. The operations include adding a first epitaxial material to an array of fins. The operations also include covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the operations. The operations also include covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material.
  • In a further exemplary embodiment of the computer program product above, the operations also include performing a reactive ion etch.
  • In another exemplary embodiment of any one of the computer program products above, the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • In a further exemplary embodiment of any one of the computer program products above, the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • In another exemplary embodiment of any one of the computer program products above, the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • In a further exemplary embodiment of any one of the computer program products above, the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • In another exemplary embodiment of any one of the computer program products above, the operations also include, in response to covering at least the first portion of the merged array of fins using the first masking material, removing the first masking material from a second portion of the merged array of fins.
  • In a further exemplary embodiment of any one of the computer program products above, removing the first epitaxial material includes removing the first epitaxial using an HCl etch.
  • In another exemplary embodiment of any one of the computer program products above, removing the first epitaxial material and adding the second epitaxial material is performed in a single step on an epi-platform.
  • In a further exemplary embodiment of any one of the computer program products above, performing the directional etch removes at least one fin in the array of fins.
  • In another exemplary embodiment of any one of the computer program products above, the computer-readable medium is a non-transitory computer readable medium (e.g., CD-ROM, RAM, flash memory, etc.).
  • In a further exemplary embodiment of any one of the computer program products above, the computer-readable medium is a storage medium.
  • Another exemplary embodiment provides an apparatus for making dual-epi FinFETs. The apparatus includes means for adding a first epitaxial material to an array of fins The apparatus also includes means for covering at least a first portion of the array of fins using a first masking material and means for removing the first epitaxial material from an uncovered portion of the array of fins. Means for adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the apparatus. The apparatus also includes means for covering a second portion of the array of fins using a second masking material and means for performing a directional etch using the first masking material and the second masking material.
  • In a further exemplary embodiment of the apparatus above, the apparatus also includes means for performing a reactive ion etch.
  • In another exemplary embodiment of any one of the apparatus above, the first epitaxial material is SiGe, in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
  • In a further exemplary embodiment of any one of the apparatus above, the second epitaxial material is p-doped Si or undoped silicon. If undoped silicon is used, it may be doped after the cut, for example, using Arsenic.
  • In another exemplary embodiment of any one of the apparatus above, the first masking material is a nitride deposition, a thin oxide film, an oxy-nitride film or a carbon containing silicon nitride film.
  • In a further exemplary embodiment of any one of the apparatus above, the second masking material is a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and/or a multi-layer stack.
  • In another exemplary embodiment of any one of the apparatus above, the apparatus also includes means for removing the first masking material from a second portion of the merged array of fins in response to covering at least the first portion of the merged array of fins using the first masking material.
  • In a further exemplary embodiment of any one of the apparatus above, the means for removing the first epitaxial material includes means for removing the first epitaxial using an HCl etch.
  • In another exemplary embodiment of any one of the apparatus above, where the means for removing the first epitaxial material and the means for adding the second epitaxial material are configured to operate in a single step on an epi-platform.
  • In a further exemplary embodiment of any one of the apparatus above, performing the directional etch removes at least one fin in the array of fins.
  • Any use of the terms “connected”, “coupled” or variants thereof should be interpreted to indicate any such connection or coupling, direct or indirect, between the identified elements. As a non-limiting example, one or more intermediate elements may be present between the “coupled” elements. The connection or coupling between the identified elements may be, as non-limiting examples, physical, electrical, magnetic, logical or any suitable combination thereof in accordance with the described exemplary embodiments. As non-limiting examples, the connection or coupling may comprise one or more printed electrical connections, wires, cables, mediums or any suitable combination thereof.
  • Generally, various exemplary embodiments can be implemented in different mediums, such as software, hardware, logic, special purpose circuits or any combination thereof. As a non-limiting example, some aspects may be implemented in software which may be run on a computing device, while other aspects may be implemented in hardware.
  • The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the best method and apparatus presently contemplated by the inventors for carrying out various exemplary embodiments. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications will still fall within the scope of the teachings of the exemplary embodiments.
  • Furthermore, some of the features of the preferred embodiments could be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles, and not in limitation thereof.

Claims (21)

1-20. (canceled)
21. An apparatus comprising at least one data processor, wherein the at least one data processor is operable to perform operations comprising:
to add a first epitaxial material to an array of fins;
to cover at least a first portion of the array of fins using a first masking material;
to remove the first epitaxial material from an uncovered portion of the array of fins;
to add a second epitaxial material to the fins in the uncovered portion of the array of fins;
to cover a second portion of the array of fins using a second masking material; and
to perform a directional etch using the first masking material and the second masking material.
22. The apparatus as in claim 21, where the operations further comprise to perform a reactive ion etch.
23. The apparatus as in claim 21, where the first epitaxial material is one of: SiGe, in-situ B-doped (ISBD) SiGe and Indium doped SiGe.
24. The apparatus as in claim 21, where the second epitaxial material is p-doped Si or undoped silicon.
25. The apparatus as in claim 21, where the first masking material is one of: a nitride deposition, a thin oxide film, an oxy-nitride film and a carbon containing silicon nitride film.
26. The apparatus as in claim 21, where the second masking material is one of: a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and a multi-layer stack.
27. The apparatus as in claim 21, where the operations further comprise, in response to covering at least the first portion of the merged array of fins using the first masking material, to remove the first masking material from a second portion of the merged array of fins.
28. The apparatus as in claim 21, when removing the first epitaxial material, the operations further comprise to remove the first epitaxial using an HCl etch.
29. The apparatus as in claim 21, when performing the directional etch, the operations further comprise to remove at least one fin in the array of fins.
30. The apparatus as in claim 21, where the second epitaxial material is undoped silicon and the operations further comprise, in response to performing the directional etch, to dope the second epitaxial material.
31. An apparatus comprising:
means for adding a first epitaxial material to an array of fins;
means for covering at least a first portion of the array of fins using a first masking material;
means for removing the first epitaxial material from an uncovered portion of the array of fins;
means for adding a second epitaxial material to the fins in the uncovered portion of the array of fins;
means for covering a second portion of the array of fins using a second masking material; and
means for performing a directional etch using the first masking material and the second masking material.
32. The apparatus as in claim 31, further comprising means for performing a reactive ion etch.
33. The apparatus as in claim 31, where the first epitaxial material is one of: SiGe, in-situ B-doped (ISBD) SiGe and Indium doped SiGe.
34. The apparatus as in claim 31, where the second epitaxial material is p-doped Si or undoped silicon.
35. The apparatus as in claim 31, where the first masking material is one of: a nitride deposition, a thin oxide film, an oxy-nitride film and a carbon containing silicon nitride film.
36. The apparatus as in claim 31, where the second masking material is one of: a resist film, an organic planarizing layer, a silicon layer containing an anti-reflection coating and a resist, and a multi-layer stack.
37. The apparatus as in claim 31, further comprising means for removing the first masking material from a second portion of the merged array of fins in response to covering at least the first portion of the merged array of fins using the first masking material.
38. The apparatus as in claim 31, where the first epitaxial material removing means comprises means for removing the first epitaxial using an HCl etch.
39. The apparatus as in claim 31, the the directional etch performing means further comprises means for removing at least one fin in the array of fins.
40. The apparatus as in claim 31, where the second epitaxial material is undoped silicon and the apparatus further comprises means for doping the second epitaxial material in response to performing the directional etch.
US13/545,456 2012-06-04 2012-07-10 Cut-very-last dual-EPI flow Active US8592290B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/545,456 US8592290B1 (en) 2012-06-04 2012-07-10 Cut-very-last dual-EPI flow

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/487,413 US8569152B1 (en) 2012-06-04 2012-06-04 Cut-very-last dual-epi flow
US13/545,456 US8592290B1 (en) 2012-06-04 2012-07-10 Cut-very-last dual-EPI flow

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/487,413 Continuation US8569152B1 (en) 2012-06-04 2012-06-04 Cut-very-last dual-epi flow

Publications (2)

Publication Number Publication Date
US8592290B1 US8592290B1 (en) 2013-11-26
US20130319613A1 true US20130319613A1 (en) 2013-12-05

Family

ID=49448560

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/487,413 Active US8569152B1 (en) 2012-06-04 2012-06-04 Cut-very-last dual-epi flow
US13/545,456 Active US8592290B1 (en) 2012-06-04 2012-07-10 Cut-very-last dual-EPI flow

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13/487,413 Active US8569152B1 (en) 2012-06-04 2012-06-04 Cut-very-last dual-epi flow

Country Status (1)

Country Link
US (2) US8569152B1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140346574A1 (en) * 2013-05-24 2014-11-27 International Business Machines Corporation Asymmetric finfet semiconductor devices and methods for fabricating the same
US20150041911A1 (en) * 2013-08-08 2015-02-12 GlobalFoundries, Inc. 3d transistor channel mobility enhancement
US9627278B2 (en) 2015-06-16 2017-04-18 International Business Machines Corporation Method of source/drain height control in dual epi finFET formation
US20180190640A1 (en) * 2013-08-28 2018-07-05 Socionext Inc. Semiconductor integrated circuit device
US10475886B2 (en) * 2014-12-16 2019-11-12 International Business Machines Corporation Modified fin cut after epitaxial growth

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8889561B2 (en) * 2012-12-10 2014-11-18 Globalfoundries Inc. Double sidewall image transfer process
US9184101B2 (en) * 2013-03-11 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method for removing semiconductor fins using alternating masks
US20150035064A1 (en) * 2013-08-01 2015-02-05 International Business Machines Corporation Inverse side-wall image transfer
US9054218B2 (en) 2013-08-07 2015-06-09 International Business Machines Corporation Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same
CN104658908A (en) * 2013-11-18 2015-05-27 中芯国际集成电路制造(上海)有限公司 Method for manufacturing FinFET
US9299706B1 (en) * 2014-09-25 2016-03-29 International Business Machines Corporation Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins
US9577099B2 (en) 2015-03-09 2017-02-21 Globalfoundries Inc. Diamond shaped source drain epitaxy with underlying buffer layer
US9799560B2 (en) * 2015-03-31 2017-10-24 Qualcomm Incorporated Self-aligned structure
US9391074B1 (en) 2015-04-21 2016-07-12 International Business Machines Corporation Structure for FinFET fins
US9576979B2 (en) 2015-05-27 2017-02-21 International Business Machines Corporation Preventing strained fin relaxation by sealing fin ends
US9659786B2 (en) 2015-07-14 2017-05-23 International Business Machines Corporation Gate cut with high selectivity to preserve interlevel dielectric layer
US9659785B2 (en) 2015-09-01 2017-05-23 International Business Machines Corporation Fin cut for taper device
US10177240B2 (en) 2015-09-18 2019-01-08 International Business Machines Corporation FinFET device formed by a replacement metal-gate method including a gate cut-last step
US9536750B1 (en) 2015-09-30 2017-01-03 International Business Machines Corporation Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
US9425108B1 (en) * 2015-12-05 2016-08-23 International Business Machines Corporation Method to prevent lateral epitaxial growth in semiconductor devices
US9947586B2 (en) * 2016-02-12 2018-04-17 International Business Machines Corporation Tunneling fin type field effect transistor with epitaxial source and drain regions
US10026615B2 (en) 2016-05-12 2018-07-17 International Business Machines Corporation Fin patterns with varying spacing without Fin cut
US9722024B1 (en) * 2016-06-09 2017-08-01 Globalfoundries Inc. Formation of semiconductor structures employing selective removal of fins
US10170591B2 (en) 2016-06-10 2019-01-01 International Business Machines Corporation Self-aligned finFET formation
US9768072B1 (en) 2016-06-30 2017-09-19 International Business Machines Corporation Fabrication of a vertical fin field effect transistor with reduced dimensional variations
US10388576B2 (en) 2016-06-30 2019-08-20 International Business Machines Corporation Semiconductor device including dual trench epitaxial dual-liner contacts
US10083961B2 (en) 2016-09-07 2018-09-25 International Business Machines Corporation Gate cut with integrated etch stop layer
US10217867B2 (en) 2016-09-07 2019-02-26 International Business Machines Corporation Uniform fin dimensions using fin cut hardmask
US10128239B2 (en) 2016-10-17 2018-11-13 International Business Machines Corporation Preserving channel strain in fin cuts
US9721848B1 (en) 2016-10-28 2017-08-01 International Business Machines Corporation Cutting fins and gates in CMOS devices
US10916478B2 (en) 2018-02-20 2021-02-09 Globalfoundries U.S. Inc. Methods of performing fin cut etch processes for FinFET semiconductor devices
US10483375B1 (en) 2018-07-17 2019-11-19 International Business Machines Coporation Fin cut etch process for vertical transistor devices
US10529831B1 (en) 2018-08-03 2020-01-07 Globalfoundries Inc. Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging
US10727133B2 (en) 2018-09-18 2020-07-28 Globalfoundries Inc. Method of forming gate structure with undercut region and resulting device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6894326B2 (en) 2003-06-25 2005-05-17 International Business Machines Corporation High-density finFET integration scheme
JP2005116969A (en) 2003-10-10 2005-04-28 Toshiba Corp Semiconductor device and its manufacturing method
US7709893B2 (en) 2007-01-31 2010-05-04 Infineon Technologies Ag Circuit layout for different performance and method
US8937353B2 (en) 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140346574A1 (en) * 2013-05-24 2014-11-27 International Business Machines Corporation Asymmetric finfet semiconductor devices and methods for fabricating the same
US9583597B2 (en) * 2013-05-24 2017-02-28 GlobalFoundries, Inc. Asymmetric FinFET semiconductor devices and methods for fabricating the same
US20150041911A1 (en) * 2013-08-08 2015-02-12 GlobalFoundries, Inc. 3d transistor channel mobility enhancement
US9023697B2 (en) * 2013-08-08 2015-05-05 International Business Machines Corporation 3D transistor channel mobility enhancement
US9275907B2 (en) 2013-08-08 2016-03-01 Globalfoundries Inc. 3D transistor channel mobility enhancement
US20180190640A1 (en) * 2013-08-28 2018-07-05 Socionext Inc. Semiconductor integrated circuit device
US10236283B2 (en) * 2013-08-28 2019-03-19 Socionext Inc. Semiconductor integrated circuit device having a first cell row and a second cell row
US10692849B2 (en) 2013-08-28 2020-06-23 Socionext Inc. Semiconductor device having a first cell row and a second cell row
US11056477B2 (en) 2013-08-28 2021-07-06 Socionext Inc. Semiconductor device having a first cell row and a second cell row
US10475886B2 (en) * 2014-12-16 2019-11-12 International Business Machines Corporation Modified fin cut after epitaxial growth
US9627278B2 (en) 2015-06-16 2017-04-18 International Business Machines Corporation Method of source/drain height control in dual epi finFET formation

Also Published As

Publication number Publication date
US8569152B1 (en) 2013-10-29
US8592290B1 (en) 2013-11-26
CN103456642A (en) 2013-12-18

Similar Documents

Publication Publication Date Title
US8592290B1 (en) Cut-very-last dual-EPI flow
US8981493B2 (en) FinFET and method of fabrication
US10074726B2 (en) Fin semiconductor device including dummy gate on isolation layer
US9214360B2 (en) Methods of patterning features having differing widths
US9859281B2 (en) Dual FIN integration for electron and hole mobility enhancement
US20090289304A1 (en) Co-integration of multi-gate fet with other fet devices in cmos technology
US10566330B2 (en) Dielectric separation of partial GAA FETs
US8426917B2 (en) Body-tied asymmetric P-type field effect transistor
US10177157B2 (en) Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate
US9466703B2 (en) Method for fabricating semiconductor device
US8643107B2 (en) Body-tied asymmetric N-type field effect transistor
US9960086B2 (en) Methods, apparatus and system for self-aligned retrograde well doping for finFET devices
TWI734180B (en) Methods, apparatus, and manufacturing system for finfet devices with reduced parasitic capacitance
KR20150091661A (en) Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device
US20180061832A1 (en) Methods, apparatus and system for sti recess control for highly scaled finfet devices
US20210036120A1 (en) Finfet semiconductor device
US20110233674A1 (en) Design Structure For Dense Layout of Semiconductor Devices
CN103456642B (en) The method and apparatus manufacturing field-effect transistor
US10685881B2 (en) Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a semiconductor device
Mahmoud et al. UTBB FD-SOI Variability Characterization Using Programmable Transistor Arrays
US8895444B2 (en) Hard mask removal during FinFET formation
TWI834335B (en) Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
Shin et al. Quasi-Planar Trigate (QPT) Bulk MOSFET

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASKER, VEERARAGHAVAN S.;BU, HUIMING;CHENG, KANGGUO;AND OTHERS;SIGNING DATES FROM 20120530 TO 20120531;REEL/FRAME:045493/0829

Owner name: STMICROELECTRONICS, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LOUBET, NICOLAS;REEL/FRAME:045493/0841

Effective date: 20150309

Owner name: STMICROELECTRONICS, INC., TEXAS

Free format text: QUITCLAIM ASSIGNMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:045879/0950

Effective date: 20170815

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001

Effective date: 20201022

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001

Effective date: 20201117

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8