US20130318256A1 - Dynamic table sharing of memory space within a network device - Google Patents
Dynamic table sharing of memory space within a network device Download PDFInfo
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- US20130318256A1 US20130318256A1 US13/875,068 US201313875068A US2013318256A1 US 20130318256 A1 US20130318256 A1 US 20130318256A1 US 201313875068 A US201313875068 A US 201313875068A US 2013318256 A1 US2013318256 A1 US 2013318256A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/742—Route cache; Operation thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/12—Protocol engines
Definitions
- the present invention relates to a network device for processing data in a network and more particularly to use of memory in a network device that allows for static and dynamic sharing of tables.
- a network may include one or more network devices, such as Ethernet switches, each of which includes several modules that are used to process information that is transmitted through the device.
- the device may include port interface modules, designed to send and receive data over a network, a Memory Management Unit (MMU), to store that data until it is forwarded or further processed and resolution modules, that allow the data to be reviewed and processed according to instructions.
- MMU Memory Management Unit
- the resolution modules include switching functionalities for determining to which destination port data should be directed.
- One of the ports on the network device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
- Many network devices operate as Ethernet switches, where packets enter the device from multiple ports, where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU.
- the process of determining an egress port for a packet involves examining the packet to determine attributes.
- Part of the process of determining the packet attributes includes searching of table entries in memory to determine quantities to direct and modify the packet. For example, an IP destination address may be derived from the packet header, that may not, without table lookups, determine an egress port of the network device that the packet should be sent from to reach that destination IP address. Such a decision process requires a lookup in the memory tables. However, memory available to the device is finite and requirements for tables and table sizes may not be known definitively until the network device is put into service. Thus, there is a need for a network device that allows for more flexible usage of tables in memory to comport with different network traffic situations.
- FIG. 1 illustrates a network device in which an embodiment of the present invention may be implemented
- FIG. 2 illustrates a block diagram illustrating the communication using ports of the network device of FIG. 1 according to an embodiment of the instant invention
- FIGS. 3A-3B illustrate memory structures to be used with the network device of FIG. 1 , with FIG. 3A illustrating the shared memory that is external to the network device and FIG. 3B illustrating the Cell Buffer Pool of the shared memory architecture;
- FIG. 4 illustrates buffer management mechanisms that are used by the memory management unit to impose resource allocation limitations and thereby ensure fair access to resource
- FIG. 5 illustrates a two stage parser, according to certain embodiments of the present invention
- FIG. 6 illustrates another parser for use with interconnected port, according to certain embodiments of the present invention.
- FIG. 7 illustrates a result matcher, according to certain embodiments of the present invention.
- FIG. 8 illustrates a configuration of an egress port arbitration implemented in the present invention.
- FIGS. 9A-9C illustrate sharing of tables, according to several embodiments of the present invention, with FIG. 9A illustrating static table separation, FIG. 9B illustrating dynamically updated tables and FIG. 9C illustrating table separation based on a key format.
- FIG. 1 illustrates a network device, such as a switching chip, in which an embodiment the present invention may be implemented.
- Device 100 includes ingress/egress modules 112 and 113 , a MMU 115 , a parser 130 and a search engine 120 .
- Ingress/egress modules are used for buffering of data and forwarding the data to the parser.
- the parser 130 parses the data received and performs look ups based on the parsed data using the search engine 120 .
- the primary function of MMU 115 is to efficiently manage cell buffering and packet pointer resources in a predictable manner, even under severe congestion scenarios. Through these modules, packet modification can occur and the packet can be transmitted to an appropriate destination port.
- the device 100 may also include one internal fabric high speed port, for example a HiGigTM port or high speed port, 108 , one or more external Ethernet ports 109 a - 109 x, and a CPU port 110 .
- High speed port 108 is used to interconnect various network devices in a system and thus form an internal switching fabric for transporting packets between external source ports and one or more external destination ports. As such, high speed port 108 may not externally visible outside of a system that includes the multiple interconnected network devices.
- CPU port 110 is used to send and receive information to and from external switching/routing control entities or CPUs. According to an embodiment of the invention, CPU port 110 may be considered as one of external Ethernet ports 109 a - 109 x.
- Device 100 interfaces with external/off-chip CPUs through a CPU processing module 111 , such as a CMIC, which interfaces with a PCI bus that connects device 100 to an external CPU.
- the search engine module 120 may be composed of additional search engine modules, 122 , 124 and 126 , that are used to perform particular look ups that are used in the characterization and modification of data being processed by the network device 100 .
- the parser 130 also includes additional modules that are directed to parsing data received from the internal fabric high speed port 134 and the other ports 138 , with other modules 132 and 136 for forwarding data back to the ports of the network device.
- the high speed port 134 and the two stage 138 parsers are discussed in greater detail below.
- a series of serializing/deserializing modules 103 send and receive data, where data received as each port is managed by a port manager 102 A-L.
- the series of port managers have a timing generator 104 and a bus agent 105 that facilitate their operation.
- the data received and transmitted to a port information base so that the flow can be monitored.
- high speed port 108 has similar functionalities but does not require as many elements since only one port is being managed.
- device 100 is built around a shared memory architecture, as shown in FIGS. 3A-3B wherein MMU 115 enables sharing of a packet buffer among different ports while providing for resource guarantees for every ingress port, egress port and class of service queue associated with each egress port.
- FIG. 3A illustrates the shared memory architecture of the present invention.
- the memory resources of device 100 include a Cell Buffer Pool (CBP) memory 302 and a Transaction Queue (XQ) memory 304 .
- CBP memory 302 is an off-chip resource that is made of, according to some embodiments, 4 DRAM chips 306 a - 306 d.
- each DRAM chip has a capacity of 288 Mbits, wherein the total capacity of CBP memory 302 is 122 Mbytes of raw storage.
- CBP memory 302 is divided into 256K 576-byte cells 308 a - 308 x, each of which includes a 32 byte header buffer 310 , up to 512 bytes for packet data 312 and 32 bytes of reserved space 314 .
- each incoming packet consumes at least one full 576 byte cell 308 (e.g., byte cells 308 a - 308 x ). Therefore in an example where an incoming packet includes a 64 byte frame, the incoming packet will have 576 bytes reserved for it even though only 64 bytes of the 576 bytes is used by the frame.
- XQ memory 304 includes a list of packet pointers 316 a - 316 x into CBP memory 302 , wherein different XQ pointers 316 may be associated with each port.
- a cell count of CBP memory 302 and a packet count of XQ memory 304 is tracked on an ingress port, egress port and class of service basis. As such, device 100 can provide resource guarantees on a cell and/or packet basis.
- FIG. 4 illustrates buffer management mechanisms that are used by MMU 115 to impose resource allocation limitations and thereby ensure fair access to resources.
- MMU 115 includes an ingress backpressure mechanism 404 , a head of line mechanism 406 and a weighted random early detection mechanism 408 .
- the ingress backpressure mechanism 404 supports lossless behaviour and manages buffer resources fairly across ingress ports.
- Head of line mechanism 406 supports access to buffering resources while optimizing throughput in the system.
- Weighted random early detection mechanism 408 improves overall network throughput.
- the ingress backpressure mechanism 404 uses packet or cell counters to track the number of packets or cells used on an ingress port basis.
- the ingress backpressure mechanism 404 includes registers for a set of 8 individually configurable thresholds and registers used to specify which of the 8 thresholds are to be used for every ingress port in the system.
- the set of thresholds include a limit threshold 412 , a discard limit threshold 414 and a reset limit threshold 416 . If a counter associated with the ingress port packet/cell usage rises above discard limit threshold 414 , packets at the ingress port will be dropped.
- a pause flow control is used to stop traffic from arriving on an ingress port that have used more than its fair share of buffering resources, thereby stopping traffic from an offending ingress port and relieving congestion caused by the offending ingress port.
- each ingress port keeps track of whether or not it is in an ingress backpressure state based on ingress backpressure counters relative to the set of thresholds.
- pause flow control frames with a timer value of (0xFFFF) are periodically sent out of that ingress port.
- the pause flow control frame with a timer value of 0x00 is sent out of the ingress port and traffic is allowed to flow again. If an ingress port is not currently in an ingress backpressure state and the packet counter rises above limit threshold 412 , the status for the ingress port transitions into the ingress backpressure state. If the ingress port is in the ingress backpressure state and the packet counter falls below reset limit threshold 416 , the status for the port will transition out of the backpressure state.
- the head of line mechanism 406 is provided to support fair access to buffering resources while optimizing throughput in the system.
- the head of line mechanism 406 relies on packet dropping to manage buffering resources and improve the overall system throughput.
- the head of line mechanism 406 uses egress counters and predefined thresholds to track buffer usage on a egress port and class of service basis and thereafter makes decisions to drop any newly arriving packets on the ingress ports destined to a particular oversubscribed egress port/class of service queue.
- Head of line mechanism 406 supports different thresholds depending on the color of the newly arriving packet. Packets may be colored based on metering and marking operations that take place in the ingress module and the MMU acts on these packets differently depending on the color of the packet.
- head of line mechanism 406 is configurable and operates independently on every class of service queue and across all ports, including the CPU port.
- Head of line mechanism 406 uses counters that track XQ memory 304 and CBP memory 302 usage and thresholds that are designed to support a static allocation of CBP memory buffers 302 and dynamic allocation of the available XQ memory buffers 304 .
- a discard threshold 422 is defined for all cells in CBP memory 302 , regardless of color marking. When the cell counter associated with a port reaches discard threshold 422 , the port is transition to a head of line status. Thereafter, the port may transition out of the head of line status if its cell counter falls below a reset limit threshold 424 .
- a guaranteed fixed allocation of XQ buffers for each class of service queue is defined by a XQ entry value 430 a - 430 h.
- Each of XQ entry value 430 a - 430 h defines how many buffer entries should be reserved for an associated queue. For example, if 100 bytes of XQ memory are assigned to a port, the first four class of service queues associated with XQ entries 430 a - 430 d respectively may be assigned the value of 10 bytes and the last four queues associated with XQ entries 430 d - 430 h respectively may be assigned the value of 5 bytes.
- the head of line mechanism 406 may not assign the unused buffer to another queue. Nevertheless, the remaining unassigned 40 bytes of XQ buffers for the port may be shared among all of the class of service queues associated with the port. Limits on how much of the shared pool of the XQ buffer may be consumed by a particular class of service queue is set with a XQ set limit threshold 432 . As such, set limit threshold 432 may be used to define the maximum number of buffers that can be used by one queue and to prevent one queue from using all of the available XQ buffers.
- the available pool of XQ buffer for each port is tracked using a port dynamic count register 434 , wherein the dynamic count register 434 keeps track of the number of available shared XQ buffers for the port.
- the initial value of dynamic count register 434 is the total number of XQ buffers associated with the port minus a sum of the number of XQ entry values 430 a - 430 h.
- Dynamic count register 434 is decremented when a class of service queue uses an available XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 430 . Conversely, dynamic count register 434 is incremented when a class of service queue releases a XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 430 .
- head of line mechanism 406 determines if all entries used by the queue is less than the XQ entry value 430 for the queue and grants the buffer request if the used entries are less then the XQ entry value 430 . If however, the used entries are greater than the XQ entry value 430 for the queue, head of line mechanism 406 determines if the amount requested is less than the total available buffer or less then the maximum amount set for the queue by the associated set limit threshold 432 .
- Set limit threshold 432 is in essence a discard threshold that is associated with the queue, regardless of the color marking of the packet. As such, when the packet count associated with the packet reaches set limit threshold 432 , the queue/port enters into a head of line status. When head of line mechanism 406 detects a head of line condition, it sends an update status so that packets can be dropped on the congested port.
- the dynamic pool of XQ pointers is reduced by a predefined amount.
- the port is transition to the head of line status and an update status is sent to by MMU 115 to the ports, thereby reducing the number of packets that may be dropped by MMU 115 .
- the XQ packet count for the queue must fall below a reset limit threshold 436 .
- intermediate discard thresholds 438 and 439 may also be defined for packets containing specific color markings, wherein each intermediate discard threshold defines when packets of a particular color should be dropped.
- intermediate discard threshold 438 may be used to define when packets that are colored yellow should be dropped and intermediate discard threshold 439 may be used to define when packets that are colored red should be dropped.
- packets may be colored one of green, yellow or red depending on the priority level assigned to the packet.
- one embodiment of the present invention includes a virtual maximum threshold 440 .
- Virtual maximum threshold 440 is equal to the number of unassigned and available buffers divided by the sum of the number of queues and the number of currently used buffers. Virtual maximum threshold 440 ensures that the packets associated with each color are processed in a relative proportion. Therefore, if the number of available unassigned buffers is less than the set limit threshold 432 for a particular queue and the queue requests access to all of the available unassigned buffers, head of line mechanism 406 calculates the virtual maximum threshold 440 for the queue and processes a proportional amount of packets associated with each color relative to the defined ratios for each color.
- the XQ thresholds may be expressed in a compressed form, wherein each unit represents a group of XQ entries.
- the group size is dependent upon the number of XQ buffers that are associated with a particular egress port/class of service queue.
- Weighted random early detection mechanism 408 is a queue management mechanism that preemptively drops packets based on a probabilistic algorithm before XQ buffers 304 are exhausted. Weighted random early detection mechanism 408 is therefore used to optimize the overall network throughput. Weighted random early detection mechanism 408 includes an averaging statistic that is used to track each queue length and drop packets based on a drop profile defined for the queue. The drop profile defines a drop probability given a specific average queue size. According to an embodiment of the invention, weighted random early detection mechanism 408 may defined separate profiles on based on a class of service queue and packet.
- the MMU 115 receives packet data for storage from the parser 130 .
- the parser 130 includes a two stage parser, where that portion is illustrated schematically in FIG. 5 .
- the data are received at ports 501 of the network device, as discussed above. Data may also be received through the CMIC 502 , where that data is passed to an ingress CMIC interface 503 .
- the interface acts to convert the CMIC data from a P-bus format to an ingress data format. In one embodiment, the data is converted from 45-bit to 168-bit format, such that the latter format includes 128-bit data, 16-bit control and possibly a 24-bit high speed header.
- the data are thereafter sent in 64-bit bursts to the ingress arbiter 504 .
- the ingress arbiter 504 receives data from the ports 501 and the ingress CMIC interface 503 , and multiplexes those inputs based on time division multiplexing arbitration. Thereafter, the data are sent to the MMU 510 , where any high speed header is removed and the format is set to a MMU interface format. Packet attributes are checked, such as end-to-end, Interrupted Bernoulli Process (IBP) or Head of Line (HOL) packets. In addition, the first 128 bytes of data are snooped and the high speed header is passed to the parser ASM 525 . If the burst of data received contains an end marker, the CRC result is sent to the result matcher 515 . Also, the packet length is estimated from the burst length and a 126-bit packet ID is generated for debugging purposes.
- IBP Interrupted Bernoulli Process
- HOL Head of Line
- the parser ASM 525 converts the 64 data burst, at 4 cycles per burst, into 128-byte burst, at 8 cycles per burst.
- the 128-byte burst data is forwarded to both the tunnel parser 530 and the parser FIFO 528 at the same time to maintain the same packet order.
- the tunnel parser 530 determines whether any type of tunnel encapsulation, including MPLS and IP tunnelling, is being employed. In addition, the tunnel parser also checks for outer and inner tags. Through the parsing process, the session initiated protocol (SIP) is provided for subnet based VLAN, where the SIP parsing occurs if the packet is an address resolution protocol (ARP), reverse ARP (RARP) or IP packet.
- a trunk port grid ID is also constructed based on the source trunk map table, unless there is no trunking or if the trunk ID is obtained from the high speed header.
- the tunnel parser 530 works with the tunnel checker 531 .
- the tunnel checker checks the checksum of the IP header, and characteristics of UDP tunnelling and IPv6 over IPv4 packets.
- the tunnel parser 530 utilizes the search engine 520 to determine the tunnel type through preconfigured tables.
- the parser FIFO 528 stores 128 bytes of packet headers and 12 bytes of high speed headers that is parsed again by the deep parser 540 .
- the header bytes are stored while the search engine completes a search and is ready for the deeper search.
- Other attributes are also maintained by the FIFO, such as packet length, high speed header status and the packet ID.
- the deep parser 540 provides three different types of data, including search results from the search engine 520 that are “flow through,” inner parser results and high speed module header. Special packet types are determined and passed along to the search engine.
- the deep parser 540 reads the data from the parser FIFO, where pre-defined fields are parsed.
- the search engine provides lookup results based on the values passed to the search engine, where the packet ID is checked to maintain packet order.
- the deep parser 540 also uses the protocol checker 541 to check the inner IP header checksum, check for denial of service attack attributes, errors in the high speed module header and perform a martian check.
- the deep parser also works with the field processor parser 542 , to parse predefined fields and user defined fields.
- the predefined fields are received from the deep parser. These fields include MAC destination address, MAC source address, inner and outer tags, Ether type, IP destination and source addresses, Type of Service, IPP, IP flags, TDS, TSS, TTL, TCP flags and flow labels.
- User defined fields are also parsible, up to 128-bit lengths.
- high speed port 108 has its own buffers and data flows from the port to its own parser 134 .
- the high speed parser is illustrated in greater detail than FIG. 6 .
- the structure is similar to the two stage parser, illustrated in FIG. 5 , with several differences.
- Data received at the high speed port 601 is forwarded to the high speed port assembler 604 .
- the assembler receives the data and high speed header in 64 byte bursts, with a similar format as used for the local ports.
- the data are sent to the MMU 610 without the high speed header and in a MMU interface format.
- the first 128 bytes of the data is snooped and sent, along with the high speed header, to the deep parser 640 .
- end-to-end message are checked, with the parsed results being sent in a side band.
- the CRC and packet lengths are checked by the result matcher 615 .
- a 16 bit packet ID is generated for use in debugging and tracking the flow of the packet.
- the high speed version of the deep parser 640 is a subset of the two stage deep parser 540 , and performs similar functions. There is, however, no pass through of information from the search engine 620 , it cannot skip the MPLS header and parse the payload only and does not send deep data to the search engine. In function, the high speed version of the FP parser 642 is the same as the FP parser 542 discussed above.
- the result matcher is illustrated in greater detail in FIG. 7 . It is noted that the result matcher may be used commonly between the parsers or each parser may utilize its own result matcher. In the embodiment illustrated, both types of ports 710 & 720 receive data and forward quantities to the result checker through the actions of the ingress assembler 715 and the ingress arbiter 725 .
- the quantities include port number, presence of EOF, the CRC and the packet length.
- the result matcher acts as a series of FIFOs to match search results through the use of the search engine 705 .
- the tag and the Management Information Base (MIB) event are matched with the packet length and the CRC status on a per port basis.
- MIB Management Information Base
- the MIB event, CRC and port are also reported to the Ingress MIB 707 .
- the search results are provided every 4 cycles for both network ports and high speed port.
- the structure allows for results to be stored in the result matcher per port if there is a delay that is longer than the incoming packet time and awaiting the end of packet results when the search delay is shorter than the incoming packet time.
- a forwarding decision is made with regard to the received information.
- the forwarding decision is generally made as to what destination port the packet data should be sent to, although the decision can be made to drop a packet or forward a packet to a CPU or other controller through the CMIC 111 .
- the packet is modified based on the parsing and evaluation of the network device. Such modification can include tagging, modification of header information or addition of a module header, if the egress port is the high speed port. The modification is performed on a cell basis to avoid delays in the forwarding of the packet data.
- FIG. 8 illustrates a configuration of an egress port arbitration implemented in the present invention.
- MMU 115 also includes a scheduler 802 that provides arbitration across the eight class of service queues 804 a - 804 h associated with each egress port to provide minimum and maximum bandwidth guarantees. It is noted that while eight classes of service are discussed, other formulations of classes of service are also supported.
- Scheduler 802 is integrated with a set of minimum and maximum metering mechanisms 806 a - 806 h that each monitors traffic flows on a class of service basis and an overall egress port basis.
- Metering mechanisms 806 a - 806 h support traffic shaping functions and guarantee minimum bandwidth specifications on a class of service queue and/or egress port basis, wherein scheduling decisions by schedule 802 are configured largely via traffic shaping mechanisms 806 a - 406 h along with a set of control masks that modify how scheduler 802 uses traffic shaping mechanisms 806 a - 806 h.
- minimum and maximum metering mechanisms 806 a - 806 h monitor traffic flows on a class of service queue basis and an overall egress port basis.
- Maximum and minimum bandwidth meters 806 a - 806 h are used to feed state information to scheduler 802 which responds by modifying its service order across class of service queues 804 .
- the network device 100 therefore enables system vendors to implement a quality of service model by configuring class of service queues 804 to support an explicit minimum and maximum bandwidth guarantee.
- metering mechanisms 806 a - 806 h monitor traffic flow on a class of service queue basis, provides state information regarding whether or nor a class of service flow is above or below a specified minimum and maximum bandwidth specification, and transmits the information into scheduler 802 which uses the metering information to modify its scheduling decisions.
- metering mechanisms 806 a - 806 h aid in partitioning class of service queues 804 into a set of queues that have not met the minimum bandwidth specification, a set that have met its minimum bandwidth but not its maximum bandwidth specification and a set that have exceeded its maximum bandwidth specification. If a queue is in the set that have not met its minimum bandwidth specification and there are packets in the queue, scheduler 802 services the queue according to the configured scheduling discipline.
- scheduler 802 services the queue according to the configured scheduling discipline. If a queue is in the set that have exceeded its maximum bandwidth specification or if the queue is empty, scheduler 802 does not service the queue.
- the minimum and maximum bandwidth metering mechanisms 806 a - 806 h may be implemented using a simple leaky bucket mechanism which tracks whether or not a class of service queue 804 has consumed its minimum or maximum bandwidth.
- the range of the minimum and maximum bandwidth setting for each class of service 804 is between 64 kbps to 16 Gbps, in 64 kbps increments.
- the leaky bucket mechanism has a configurable number of tokens “leaking” out of buckets, each of which is associated with one of queues 804 a - 804 h, at a configurable rate.
- the leaky bucket mechanism includes a refresh update interface and a minimum bandwidth which defines how many tokens are to be removed every refresh time unit.
- a minimum threshold is set to indicate whether a flow has satisfied at least its minimum rate and a fill threshold is set to indicate how many tokens are in leaky bucket. When the fill threshold rises above minimum threshold, a flag which indicates that the flow has satisfied its minimum bandwidth specification is set to true. When fill threshold falls below minimum threshold, the flag is set to false.
- the scheduler 802 ceases to service the queue and the queue is classified as being in the set of queues that have exceeded it maximum bandwidth specification. A flag is then set to indicate that the queue has exceeded its maximum bandwidth. Thereafter, the queue will only receive service from scheduler 802 when its fill threshold falls below high threshold and the flag indicating that it has exceeded its maximum bandwidth is reset.
- Maximum rate metering mechanism 808 is used to indicate that the maximum bandwidth specified for a port has been exceeded and operates in the same manner as meter mechanisms 806 a - 806 h when the maximum total bandwidth has been exceeded. According to an embodiment of the invention, the maximum metering mechanism on a queue and port basis generally affects whether or not queue 804 or a port is to be included in scheduling arbitration. As such, the maximum metering mechanism only has a traffic limiting effect on scheduler 802 .
- minimum metering on a class of service queue 804 basis has a more complex interaction with scheduler 802 .
- scheduler 802 is configured to support a variety of scheduling disciplines that mimic the bandwidth sharing capabilities of a weighted fair queuing scheme.
- the weighted fair queue scheme is a weighted version of packet based fair queuing scheme, which is defined as a method for providing “bit-based round robin” scheduling of packets. As such, packets are scheduled for access to an egress port based on their delivery time, which is computed as if the scheduler is capable of providing bit-based round robin service.
- a relative weight field influences the specifics of how the scheduler makes use of the minimum metering mechanism, wherein the scheduler attempts to provide a minimum bandwidth guarantee.
- the minimum bandwidth guarantee is a relative bandwidth guarantee wherein a relative field determines whether or not scheduler 802 will treat the minimum bandwidth metering settings as a specification for a relative or an absolute bandwidth guarantee. If the relative field is set, the scheduler treats minimum bandwidth 806 setting as a relative bandwidth specification. Scheduler 802 then attempts to provide relative bandwidth sharing across backlogged queues 804 .
- the present invention allows for more flexible use and configuration of lookup tables in memory. It should be noted that for particular embodiments discussed above, where lookup tables are set up in memory external to the network device, the concept of table sharing may be important in allowing more tables to be kept in smaller memory areas. Three memory sharing process are discussed below, where those processes may be used separately or together.
- the first table sharing process involves the setting of static block boundaries, as illustrated in FIG. 9A .
- the memory space is broken into blocks that can be designated as Table A, Table B, etc.
- the assignment of blocks is statically configured by software and the network device does not change the configuration.
- a table 901 - a may be configured into a first table containing L2 entries and a second table containing L3 entries.
- the same table 901 - b may be configured through different blocks, to tables having L2, L3v4 and L3v6 entries.
- the software at start up has the option of partitioning the blocks as needed for the environment in which the network device is being used.
- the table is separated into four blocks.
- FIG. 9B Another table sharing process involves more use of the hardware of the network device to control the table sharing.
- the table entries of the table 902 are inserted in two directions.
- the memory space is broken into blocks, for example eight blocks, that can be designated as Table A or Table B.
- Table A grows top down, while Table B grows bottom up.
- block 0 When the hardware is instructed to insert an entry into Table A for the first time, it designates block 0 as Table A.
- the hardware When the hardware is instructed to insert an entry into Table B for the first time, it designates, for example, block 7 as Table B.
- a block becomes full a new block is assigned to dynamically grow the table either up or down.
- the two tables meet i.e. there are no further blocks left to grow, the tables are full.
- the table can be constructed on the fly by the network device to respond to its processing needs.
- a third table sharing process involves the separation of a table based on key format.
- the table type is encoded into the key itself, so that there is an entry by entry sharing of the memory space.
- FIG. 9C illustrates the process. In the embodiment illustrated, no blocks are needed, but the key is used to determine whether a particular table is used.
- the key and result entries are in table 905 .
- Static table boundaries allow a customer to mold the tables into a configuration that is customized for their particular environment.
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Abstract
Description
- This application is a continuation application of U.S. Utility application Ser. No. 11/084,482, filed on Mar. 21, 2005, which claims priority of U.S. Provisional Patent Application Ser. No. 60/653,943, filed on Feb. 18, 2005. The subject matter of this earlier filed applications are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to a network device for processing data in a network and more particularly to use of memory in a network device that allows for static and dynamic sharing of tables.
- 2. Description of the Related Art
- A network may include one or more network devices, such as Ethernet switches, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device may include port interface modules, designed to send and receive data over a network, a Memory Management Unit (MMU), to store that data until it is forwarded or further processed and resolution modules, that allow the data to be reviewed and processed according to instructions. The resolution modules include switching functionalities for determining to which destination port data should be directed. One of the ports on the network device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
- Many network devices operate as Ethernet switches, where packets enter the device from multiple ports, where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU. The process of determining an egress port for a packet involves examining the packet to determine attributes.
- Part of the process of determining the packet attributes includes searching of table entries in memory to determine quantities to direct and modify the packet. For example, an IP destination address may be derived from the packet header, that may not, without table lookups, determine an egress port of the network device that the packet should be sent from to reach that destination IP address. Such a decision process requires a lookup in the memory tables. However, memory available to the device is finite and requirements for tables and table sizes may not be known definitively until the network device is put into service. Thus, there is a need for a network device that allows for more flexible usage of tables in memory to comport with different network traffic situations.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention that together with the description serve to explain the principles of the invention, wherein:
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FIG. 1 illustrates a network device in which an embodiment of the present invention may be implemented; -
FIG. 2 illustrates a block diagram illustrating the communication using ports of the network device ofFIG. 1 according to an embodiment of the instant invention; -
FIGS. 3A-3B illustrate memory structures to be used with the network device ofFIG. 1 , withFIG. 3A illustrating the shared memory that is external to the network device andFIG. 3B illustrating the Cell Buffer Pool of the shared memory architecture; -
FIG. 4 illustrates buffer management mechanisms that are used by the memory management unit to impose resource allocation limitations and thereby ensure fair access to resource; -
FIG. 5 illustrates a two stage parser, according to certain embodiments of the present invention; -
FIG. 6 illustrates another parser for use with interconnected port, according to certain embodiments of the present invention; -
FIG. 7 illustrates a result matcher, according to certain embodiments of the present invention; -
FIG. 8 illustrates a configuration of an egress port arbitration implemented in the present invention; and -
FIGS. 9A-9C illustrate sharing of tables, according to several embodiments of the present invention, withFIG. 9A illustrating static table separation,FIG. 9B illustrating dynamically updated tables andFIG. 9C illustrating table separation based on a key format. - Reference will now be made to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
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FIG. 1 illustrates a network device, such as a switching chip, in which an embodiment the present invention may be implemented.Device 100 includes ingress/egress modules MMU 115, aparser 130 and asearch engine 120. Ingress/egress modules are used for buffering of data and forwarding the data to the parser. Theparser 130 parses the data received and performs look ups based on the parsed data using thesearch engine 120. The primary function of MMU 115 is to efficiently manage cell buffering and packet pointer resources in a predictable manner, even under severe congestion scenarios. Through these modules, packet modification can occur and the packet can be transmitted to an appropriate destination port. - According to several embodiments, the
device 100 may also include one internal fabric high speed port, for example a HiGig™ port or high speed port, 108, one or more external Ethernet ports 109 a-109 x, and aCPU port 110.High speed port 108 is used to interconnect various network devices in a system and thus form an internal switching fabric for transporting packets between external source ports and one or more external destination ports. As such,high speed port 108 may not externally visible outside of a system that includes the multiple interconnected network devices.CPU port 110 is used to send and receive information to and from external switching/routing control entities or CPUs. According to an embodiment of the invention,CPU port 110 may be considered as one of external Ethernet ports 109 a-109 x.Device 100 interfaces with external/off-chip CPUs through aCPU processing module 111, such as a CMIC, which interfaces with a PCI bus that connectsdevice 100 to an external CPU. - In addition, the
search engine module 120 may be composed of additional search engine modules, 122, 124 and 126, that are used to perform particular look ups that are used in the characterization and modification of data being processed by thenetwork device 100. Likewise, theparser 130 also includes additional modules that are directed to parsing data received from the internal fabrichigh speed port 134 and theother ports 138, withother modules high speed port 134 and the twostage 138 parsers are discussed in greater detail below. - Network traffic enters and exits
device 100 through external Ethernet ports 109 a-109 x. Specifically, traffic indevice 100 is routed from an external Ethernet source port to one or more unique destination Ethernet ports. In one embodiment of the invention,device 100 supports twelve physical Ethernet ports 109, each of which can operate in 10/100/1000 Mbps speed and onehigh speed port 108 which operates in either 10 Gbps or 12 Gbps speed. - The structure of the physical ports 109 are further illustrated in
FIG. 2 . A series of serializing/deserializing modules 103 send and receive data, where data received as each port is managed by aport manager 102A-L. The series of port managers have atiming generator 104 and abus agent 105 that facilitate their operation. The data received and transmitted to a port information base so that the flow can be monitored. It is noted thathigh speed port 108 has similar functionalities but does not require as many elements since only one port is being managed. - In an embodiment of the invention,
device 100 is built around a shared memory architecture, as shown inFIGS. 3A-3B whereinMMU 115 enables sharing of a packet buffer among different ports while providing for resource guarantees for every ingress port, egress port and class of service queue associated with each egress port.FIG. 3A illustrates the shared memory architecture of the present invention. Specifically, the memory resources ofdevice 100 include a Cell Buffer Pool (CBP)memory 302 and a Transaction Queue (XQ)memory 304.CBP memory 302 is an off-chip resource that is made of, according to some embodiments, 4 DRAM chips 306 a-306 d. According to an embodiment of the invention, each DRAM chip has a capacity of 288 Mbits, wherein the total capacity ofCBP memory 302 is 122 Mbytes of raw storage. As shown inFIG. 3B ,CBP memory 302 is divided into 256K 576-byte cells 308 a-308 x, each of which includes a 32byte header buffer 310, up to 512 bytes forpacket data 312 and 32 bytes ofreserved space 314. As such, each incoming packet consumes at least one full 576 byte cell 308 (e.g., byte cells 308 a-308 x). Therefore in an example where an incoming packet includes a 64 byte frame, the incoming packet will have 576 bytes reserved for it even though only 64 bytes of the 576 bytes is used by the frame. - Returning to
FIG. 3A ,XQ memory 304 includes a list of packet pointers 316 a-316 x intoCBP memory 302, wherein different XQ pointers 316 may be associated with each port. A cell count ofCBP memory 302 and a packet count ofXQ memory 304 is tracked on an ingress port, egress port and class of service basis. As such,device 100 can provide resource guarantees on a cell and/or packet basis. - Once a packet enters
device 100 on a source port 109, the packet is transmitted toparser 130 for processing. During processing, packets on each of the ingress and egress ports sharesystem resources FIG. 4 illustrates buffer management mechanisms that are used byMMU 115 to impose resource allocation limitations and thereby ensure fair access to resources.MMU 115 includes aningress backpressure mechanism 404, a head ofline mechanism 406 and a weighted randomearly detection mechanism 408. Theingress backpressure mechanism 404 supports lossless behaviour and manages buffer resources fairly across ingress ports. Head ofline mechanism 406 supports access to buffering resources while optimizing throughput in the system. Weighted randomearly detection mechanism 408 improves overall network throughput. - The
ingress backpressure mechanism 404 uses packet or cell counters to track the number of packets or cells used on an ingress port basis. Theingress backpressure mechanism 404 includes registers for a set of 8 individually configurable thresholds and registers used to specify which of the 8 thresholds are to be used for every ingress port in the system. The set of thresholds include alimit threshold 412, a discardlimit threshold 414 and areset limit threshold 416. If a counter associated with the ingress port packet/cell usage rises above discardlimit threshold 414, packets at the ingress port will be dropped. Based on the counters for tracking the number of cells/packets, a pause flow control is used to stop traffic from arriving on an ingress port that have used more than its fair share of buffering resources, thereby stopping traffic from an offending ingress port and relieving congestion caused by the offending ingress port. - Specifically, each ingress port keeps track of whether or not it is in an ingress backpressure state based on ingress backpressure counters relative to the set of thresholds. When the ingress port is in ingress backpressure state, pause flow control frames with a timer value of (0xFFFF) are periodically sent out of that ingress port. When the ingress port is no longer in the ingress backpressure state, the pause flow control frame with a timer value of 0x00 is sent out of the ingress port and traffic is allowed to flow again. If an ingress port is not currently in an ingress backpressure state and the packet counter rises above
limit threshold 412, the status for the ingress port transitions into the ingress backpressure state. If the ingress port is in the ingress backpressure state and the packet counter falls belowreset limit threshold 416, the status for the port will transition out of the backpressure state. - The head of
line mechanism 406 is provided to support fair access to buffering resources while optimizing throughput in the system. The head ofline mechanism 406 relies on packet dropping to manage buffering resources and improve the overall system throughput. According to an embodiment of the invention, the head ofline mechanism 406 uses egress counters and predefined thresholds to track buffer usage on a egress port and class of service basis and thereafter makes decisions to drop any newly arriving packets on the ingress ports destined to a particular oversubscribed egress port/class of service queue. Head ofline mechanism 406 supports different thresholds depending on the color of the newly arriving packet. Packets may be colored based on metering and marking operations that take place in the ingress module and the MMU acts on these packets differently depending on the color of the packet. - According to an embodiment of the invention, head of
line mechanism 406 is configurable and operates independently on every class of service queue and across all ports, including the CPU port. Head ofline mechanism 406 uses counters that trackXQ memory 304 andCBP memory 302 usage and thresholds that are designed to support a static allocation of CBP memory buffers 302 and dynamic allocation of the available XQ memory buffers 304. A discardthreshold 422 is defined for all cells inCBP memory 302, regardless of color marking. When the cell counter associated with a port reaches discardthreshold 422, the port is transition to a head of line status. Thereafter, the port may transition out of the head of line status if its cell counter falls below areset limit threshold 424. - For the
XQ memory 304, a guaranteed fixed allocation of XQ buffers for each class of service queue is defined by a XQ entry value 430 a-430 h. Each of XQ entry value 430 a-430 h defines how many buffer entries should be reserved for an associated queue. For example, if 100 bytes of XQ memory are assigned to a port, the first four class of service queues associated with XQ entries 430 a-430 d respectively may be assigned the value of 10 bytes and the last four queues associated with XQ entries 430 d-430 h respectively may be assigned the value of 5 bytes. - According to an embodiment of the invention, even if a queue does not use up all of the buffer entries reserved for it according to the associated XQ entry value, the head of
line mechanism 406 may not assign the unused buffer to another queue. Nevertheless, the remaining unassigned 40 bytes of XQ buffers for the port may be shared among all of the class of service queues associated with the port. Limits on how much of the shared pool of the XQ buffer may be consumed by a particular class of service queue is set with a XQ set limit threshold 432. As such, set limit threshold 432 may be used to define the maximum number of buffers that can be used by one queue and to prevent one queue from using all of the available XQ buffers. To ensure that the sum of XQ entry values 430 a-430 h do not add up to more than the total number of available XQ buffers for the port and to ensure that each class of service queue has access to its quota of XQ buffers as assigned by its entry value 430, the available pool of XQ buffer for each port is tracked using a portdynamic count register 434, wherein thedynamic count register 434 keeps track of the number of available shared XQ buffers for the port. The initial value ofdynamic count register 434 is the total number of XQ buffers associated with the port minus a sum of the number of XQ entry values 430 a-430 h.Dynamic count register 434 is decremented when a class of service queue uses an available XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 430. Conversely,dynamic count register 434 is incremented when a class of service queue releases a XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 430. - When a queue requests
XQ buffer 304, head ofline mechanism 406 determines if all entries used by the queue is less than the XQ entry value 430 for the queue and grants the buffer request if the used entries are less then the XQ entry value 430. If however, the used entries are greater than the XQ entry value 430 for the queue, head ofline mechanism 406 determines if the amount requested is less than the total available buffer or less then the maximum amount set for the queue by the associated set limit threshold 432. Set limit threshold 432 is in essence a discard threshold that is associated with the queue, regardless of the color marking of the packet. As such, when the packet count associated with the packet reaches set limit threshold 432, the queue/port enters into a head of line status. When head ofline mechanism 406 detects a head of line condition, it sends an update status so that packets can be dropped on the congested port. - However, due to latency, there may be packets in transition between the
MMU 115 and the ports and when the status update is sent by head of line mechanism 306. In this case, the packet drops may occur atMMU 115 due to the head of line status. In an embodiment of the invention, due to the pipelining of packets, the dynamic pool of XQ pointers is reduced by a predefined amount. As such, when the number of available XQ pointers is equal to or less than the predefined amount, the port is transition to the head of line status and an update status is sent to byMMU 115 to the ports, thereby reducing the number of packets that may be dropped byMMU 115. To transition out of the head of line status, the XQ packet count for the queue must fall below a reset limit threshold 436. - It is possible for the XQ counter for a particular class of service queue to not reach set limit threshold 432 and still have its packet dropped if the XQ resources for the port are oversubscribed by the other class of service queues. In an embodiment of the invention, intermediate discard thresholds 438 and 439 may also be defined for packets containing specific color markings, wherein each intermediate discard threshold defines when packets of a particular color should be dropped. For example, intermediate discard threshold 438 may be used to define when packets that are colored yellow should be dropped and intermediate discard threshold 439 may be used to define when packets that are colored red should be dropped. According to an embodiment of the invention, packets may be colored one of green, yellow or red depending on the priority level assigned to the packet. To ensure that packets associated with each color are processed in proportion to the color assignment in each queue, one embodiment of the present invention includes a virtual maximum threshold 440. Virtual maximum threshold 440 is equal to the number of unassigned and available buffers divided by the sum of the number of queues and the number of currently used buffers. Virtual maximum threshold 440 ensures that the packets associated with each color are processed in a relative proportion. Therefore, if the number of available unassigned buffers is less than the set limit threshold 432 for a particular queue and the queue requests access to all of the available unassigned buffers, head of
line mechanism 406 calculates the virtual maximum threshold 440 for the queue and processes a proportional amount of packets associated with each color relative to the defined ratios for each color. - To conserve register space, the XQ thresholds may be expressed in a compressed form, wherein each unit represents a group of XQ entries. The group size is dependent upon the number of XQ buffers that are associated with a particular egress port/class of service queue.
- Weighted random
early detection mechanism 408 is a queue management mechanism that preemptively drops packets based on a probabilistic algorithm before XQ buffers 304 are exhausted. Weighted randomearly detection mechanism 408 is therefore used to optimize the overall network throughput. Weighted randomearly detection mechanism 408 includes an averaging statistic that is used to track each queue length and drop packets based on a drop profile defined for the queue. The drop profile defines a drop probability given a specific average queue size. According to an embodiment of the invention, weighted randomearly detection mechanism 408 may defined separate profiles on based on a class of service queue and packet. - As illustrated in
FIG. 1 , theMMU 115 receives packet data for storage from theparser 130. As discussed above, theparser 130 includes a two stage parser, where that portion is illustrated schematically inFIG. 5 . The data are received atports 501 of the network device, as discussed above. Data may also be received through theCMIC 502, where that data is passed to aningress CMIC interface 503. The interface acts to convert the CMIC data from a P-bus format to an ingress data format. In one embodiment, the data is converted from 45-bit to 168-bit format, such that the latter format includes 128-bit data, 16-bit control and possibly a 24-bit high speed header. The data are thereafter sent in 64-bit bursts to theingress arbiter 504. - The
ingress arbiter 504 receives data from theports 501 and theingress CMIC interface 503, and multiplexes those inputs based on time division multiplexing arbitration. Thereafter, the data are sent to theMMU 510, where any high speed header is removed and the format is set to a MMU interface format. Packet attributes are checked, such as end-to-end, Interrupted Bernoulli Process (IBP) or Head of Line (HOL) packets. In addition, the first 128 bytes of data are snooped and the high speed header is passed to theparser ASM 525. If the burst of data received contains an end marker, the CRC result is sent to theresult matcher 515. Also, the packet length is estimated from the burst length and a 126-bit packet ID is generated for debugging purposes. - The
parser ASM 525 converts the 64 data burst, at 4 cycles per burst, into 128-byte burst, at 8 cycles per burst. The 128-byte burst data is forwarded to both thetunnel parser 530 and theparser FIFO 528 at the same time to maintain the same packet order. Thetunnel parser 530 determines whether any type of tunnel encapsulation, including MPLS and IP tunnelling, is being employed. In addition, the tunnel parser also checks for outer and inner tags. Through the parsing process, the session initiated protocol (SIP) is provided for subnet based VLAN, where the SIP parsing occurs if the packet is an address resolution protocol (ARP), reverse ARP (RARP) or IP packet. A trunk port grid ID is also constructed based on the source trunk map table, unless there is no trunking or if the trunk ID is obtained from the high speed header. - The
tunnel parser 530 works with thetunnel checker 531. The tunnel checker checks the checksum of the IP header, and characteristics of UDP tunnelling and IPv6 over IPv4 packets. Thetunnel parser 530 utilizes thesearch engine 520 to determine the tunnel type through preconfigured tables. - The
parser FIFO 528 stores 128 bytes of packet headers and 12 bytes of high speed headers that is parsed again by thedeep parser 540. The header bytes are stored while the search engine completes a search and is ready for the deeper search. Other attributes are also maintained by the FIFO, such as packet length, high speed header status and the packet ID. Thedeep parser 540 provides three different types of data, including search results from thesearch engine 520 that are “flow through,” inner parser results and high speed module header. Special packet types are determined and passed along to the search engine. Thedeep parser 540 reads the data from the parser FIFO, where pre-defined fields are parsed. The search engine provides lookup results based on the values passed to the search engine, where the packet ID is checked to maintain packet order. - The
deep parser 540 also uses theprotocol checker 541 to check the inner IP header checksum, check for denial of service attack attributes, errors in the high speed module header and perform a martian check. The deep parser also works with thefield processor parser 542, to parse predefined fields and user defined fields. The predefined fields are received from the deep parser. These fields include MAC destination address, MAC source address, inner and outer tags, Ether type, IP destination and source addresses, Type of Service, IPP, IP flags, TDS, TSS, TTL, TCP flags and flow labels. User defined fields are also parsible, up to 128-bit lengths. - As discussed above, the data that is received on the high speed port is treated separately from other data received on the local ports. As illustrated in
FIG. 1 ,high speed port 108 has its own buffers and data flows from the port to itsown parser 134. The high speed parser is illustrated in greater detail thanFIG. 6 . The structure is similar to the two stage parser, illustrated inFIG. 5 , with several differences. Data received at thehigh speed port 601 is forwarded to the highspeed port assembler 604. The assembler receives the data and high speed header in 64 byte bursts, with a similar format as used for the local ports. The data are sent to theMMU 610 without the high speed header and in a MMU interface format. - The first 128 bytes of the data is snooped and sent, along with the high speed header, to the
deep parser 640. With similarity to the two stage parser, end-to-end message are checked, with the parsed results being sent in a side band. Also similarly, the CRC and packet lengths are checked by theresult matcher 615. In addition, a 16 bit packet ID is generated for use in debugging and tracking the flow of the packet. - The high speed version of the
deep parser 640 is a subset of the two stagedeep parser 540, and performs similar functions. There is, however, no pass through of information from thesearch engine 620, it cannot skip the MPLS header and parse the payload only and does not send deep data to the search engine. In function, the high speed version of theFP parser 642 is the same as theFP parser 542 discussed above. - The result matcher is illustrated in greater detail in
FIG. 7 . It is noted that the result matcher may be used commonly between the parsers or each parser may utilize its own result matcher. In the embodiment illustrated, both types ofports 710 & 720 receive data and forward quantities to the result checker through the actions of theingress assembler 715 and theingress arbiter 725. The quantities include port number, presence of EOF, the CRC and the packet length. The result matcher acts as a series of FIFOs to match search results through the use of thesearch engine 705. The tag and the Management Information Base (MIB) event are matched with the packet length and the CRC status on a per port basis. The MIB event, CRC and port are also reported to theIngress MIB 707. The search results are provided every 4 cycles for both network ports and high speed port. The structure allows for results to be stored in the result matcher per port if there is a delay that is longer than the incoming packet time and awaiting the end of packet results when the search delay is shorter than the incoming packet time. - After the process of parsing and evaluating of data received, a forwarding decision is made with regard to the received information. The forwarding decision is generally made as to what destination port the packet data should be sent to, although the decision can be made to drop a packet or forward a packet to a CPU or other controller through the
CMIC 111. On egress, the packet is modified based on the parsing and evaluation of the network device. Such modification can include tagging, modification of header information or addition of a module header, if the egress port is the high speed port. The modification is performed on a cell basis to avoid delays in the forwarding of the packet data. -
FIG. 8 illustrates a configuration of an egress port arbitration implemented in the present invention. According toFIG. 8 ,MMU 115 also includes ascheduler 802 that provides arbitration across the eight class of service queues 804 a-804 h associated with each egress port to provide minimum and maximum bandwidth guarantees. It is noted that while eight classes of service are discussed, other formulations of classes of service are also supported.Scheduler 802 is integrated with a set of minimum and maximum metering mechanisms 806 a-806 h that each monitors traffic flows on a class of service basis and an overall egress port basis. Metering mechanisms 806 a-806 h support traffic shaping functions and guarantee minimum bandwidth specifications on a class of service queue and/or egress port basis, wherein scheduling decisions byschedule 802 are configured largely via traffic shaping mechanisms 806 a-406 h along with a set of control masks that modify howscheduler 802 uses traffic shaping mechanisms 806 a-806 h. - As shown in
FIG. 8 , minimum and maximum metering mechanisms 806 a-806 h monitor traffic flows on a class of service queue basis and an overall egress port basis. Maximum and minimum bandwidth meters 806 a-806 h are used to feed state information toscheduler 802 which responds by modifying its service order across class of service queues 804. Thenetwork device 100 therefore enables system vendors to implement a quality of service model by configuring class of service queues 804 to support an explicit minimum and maximum bandwidth guarantee. In an embodiment of the invention, metering mechanisms 806 a-806 h monitor traffic flow on a class of service queue basis, provides state information regarding whether or nor a class of service flow is above or below a specified minimum and maximum bandwidth specification, and transmits the information intoscheduler 802 which uses the metering information to modify its scheduling decisions. As such, metering mechanisms 806 a-806 h aid in partitioning class of service queues 804 into a set of queues that have not met the minimum bandwidth specification, a set that have met its minimum bandwidth but not its maximum bandwidth specification and a set that have exceeded its maximum bandwidth specification. If a queue is in the set that have not met its minimum bandwidth specification and there are packets in the queue,scheduler 802 services the queue according to the configured scheduling discipline. If a queue is in the set that have met its minimum bandwidth specification but has not exceeded it maximum bandwidth specification and there are packets in the queue,scheduler 802 services the queue according to the configured scheduling discipline. If a queue is in the set that have exceeded its maximum bandwidth specification or if the queue is empty,scheduler 802 does not service the queue. - The minimum and maximum bandwidth metering mechanisms 806 a-806 h may be implemented using a simple leaky bucket mechanism which tracks whether or not a class of service queue 804 has consumed its minimum or maximum bandwidth. The range of the minimum and maximum bandwidth setting for each class of service 804 is between 64 kbps to 16 Gbps, in 64 kbps increments. The leaky bucket mechanism has a configurable number of tokens “leaking” out of buckets, each of which is associated with one of queues 804 a-804 h, at a configurable rate. In metering the minimum bandwidth for a class of service queue 804, as packets enter the class of service queue 804, a number of tokens in proportion to the size of the packet is added to a respective bucket, having a ceiling of bucket high threshold. The leaky bucket mechanism includes a refresh update interface and a minimum bandwidth which defines how many tokens are to be removed every refresh time unit. A minimum threshold is set to indicate whether a flow has satisfied at least its minimum rate and a fill threshold is set to indicate how many tokens are in leaky bucket. When the fill threshold rises above minimum threshold, a flag which indicates that the flow has satisfied its minimum bandwidth specification is set to true. When fill threshold falls below minimum threshold, the flag is set to false.
- After metering mechanisms 806 a-806 h indicate that the maximum bandwidth specified has been exceeded high threshold, the
scheduler 802 ceases to service the queue and the queue is classified as being in the set of queues that have exceeded it maximum bandwidth specification. A flag is then set to indicate that the queue has exceeded its maximum bandwidth. Thereafter, the queue will only receive service fromscheduler 802 when its fill threshold falls below high threshold and the flag indicating that it has exceeded its maximum bandwidth is reset. - Maximum
rate metering mechanism 808 is used to indicate that the maximum bandwidth specified for a port has been exceeded and operates in the same manner as meter mechanisms 806 a-806 h when the maximum total bandwidth has been exceeded. According to an embodiment of the invention, the maximum metering mechanism on a queue and port basis generally affects whether or not queue 804 or a port is to be included in scheduling arbitration. As such, the maximum metering mechanism only has a traffic limiting effect onscheduler 802. - On the other hand, minimum metering on a class of service queue 804 basis has a more complex interaction with
scheduler 802. In one embodiment of the invention,scheduler 802 is configured to support a variety of scheduling disciplines that mimic the bandwidth sharing capabilities of a weighted fair queuing scheme. The weighted fair queue scheme is a weighted version of packet based fair queuing scheme, which is defined as a method for providing “bit-based round robin” scheduling of packets. As such, packets are scheduled for access to an egress port based on their delivery time, which is computed as if the scheduler is capable of providing bit-based round robin service. A relative weight field influences the specifics of how the scheduler makes use of the minimum metering mechanism, wherein the scheduler attempts to provide a minimum bandwidth guarantee. - In one embodiment of the invention, the minimum bandwidth guarantee is a relative bandwidth guarantee wherein a relative field determines whether or not scheduler 802 will treat the minimum bandwidth metering settings as a specification for a relative or an absolute bandwidth guarantee. If the relative field is set, the scheduler treats minimum bandwidth 806 setting as a relative bandwidth specification.
Scheduler 802 then attempts to provide relative bandwidth sharing across backlogged queues 804. - As discussed above, the present invention allows for more flexible use and configuration of lookup tables in memory. It should be noted that for particular embodiments discussed above, where lookup tables are set up in memory external to the network device, the concept of table sharing may be important in allowing more tables to be kept in smaller memory areas. Three memory sharing process are discussed below, where those processes may be used separately or together.
- The first table sharing process involves the setting of static block boundaries, as illustrated in
FIG. 9A . The memory space is broken into blocks that can be designated as Table A, Table B, etc. The assignment of blocks is statically configured by software and the network device does not change the configuration. A table 901-a may be configured into a first table containing L2 entries and a second table containing L3 entries. Alternatively, the same table 901-b may be configured through different blocks, to tables having L2, L3v4 and L3v6 entries. Thus the software at start up has the option of partitioning the blocks as needed for the environment in which the network device is being used. In a particular embodiment, the table is separated into four blocks. - Another table sharing process involves more use of the hardware of the network device to control the table sharing. As illustrated in
FIG. 9B , the table entries of the table 902 are inserted in two directions. The memory space is broken into blocks, for example eight blocks, that can be designated as Table A or Table B. Table A grows top down, while Table B grows bottom up. When the hardware is instructed to insert an entry into Table A for the first time, it designatesblock 0 as Table A. When the hardware is instructed to insert an entry into Table B for the first time, it designates, for example, block 7 as Table B. When a block becomes full, a new block is assigned to dynamically grow the table either up or down. When the two tables meet, i.e. there are no further blocks left to grow, the tables are full. In other words, the table can be constructed on the fly by the network device to respond to its processing needs. - A third table sharing process involves the separation of a table based on key format. The table type is encoded into the key itself, so that there is an entry by entry sharing of the memory space.
FIG. 9C illustrates the process. In the embodiment illustrated, no blocks are needed, but the key is used to determine whether a particular table is used. The key and result entries are in table 905. The key is 64 bits, in one embodiment, and certain bits that are not used can be used to identify the type of entry. Thus, for example if bits [63:56]=FF, that may detail that the entry is an IPv6 entry, whereas other bit values may indicate that it is an IPv4 entry. - The above-discussed processes of table sharing of memory space allow for extremely configurable switching by the network device. Static table boundaries, as discussed in the first method, allow a customer to mold the tables into a configuration that is customized for their particular environment. Table separation based on the key, as discussed in the third method, and table separation based on dynamically updated block boundaries, as discussed in the above second method, allow the network device to dynamically grow and/or shrink tables based on how the customer uses and populates the tables.
- The foregoing description has been directed to specific embodiments of this invention. It will be apparent, however, that other variations and modifications may be made to the described embodiments, with the attainment of some or all of their advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.
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US13/875,068 Abandoned US20130318256A1 (en) | 2005-02-18 | 2013-05-01 | Dynamic table sharing of memory space within a network device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107102576A (en) * | 2016-02-23 | 2017-08-29 | 西门子公司 | A kind of controller, dcs and method |
CN110177046A (en) * | 2019-04-18 | 2019-08-27 | 中国人民解放军战略支援部队信息工程大学 | Secure exchange chip, implementation method and the network switching equipment based on mimicry thought |
US11012915B2 (en) * | 2018-03-26 | 2021-05-18 | Qualcomm Incorporated | Backpressure signaling for wireless communications |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8457131B2 (en) * | 2005-02-18 | 2013-06-04 | Broadcom Corporation | Dynamic table sharing of memory space within a network device |
US8059658B1 (en) * | 2005-12-23 | 2011-11-15 | Extreme Networks, Inc. | Method and system for automatic expansion and contraction of IP host forwarding database |
US7843927B1 (en) | 2006-12-22 | 2010-11-30 | Extreme Networks, Inc. | Methods, systems, and computer program products for routing packets at a multi-mode layer 3 packet forwarding device |
US20090028127A1 (en) * | 2007-07-26 | 2009-01-29 | Gordon Kent Walker | Methods and apparatus for providing computational load allocation in a network environment |
US8331373B2 (en) * | 2010-03-15 | 2012-12-11 | Extreme Networks, Inc. | Methods, systems, and computer readable media for automatically selecting between internet protocol switching modes on a per-module basis in a packet forwarding device |
US9917779B2 (en) * | 2011-08-23 | 2018-03-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Alleviating congestion in a cable modem |
US11316788B2 (en) | 2015-09-30 | 2022-04-26 | Hewlett Packard Enterprise Development Lp | Dynamic allocation of resources within network devices |
US10904147B1 (en) * | 2019-07-22 | 2021-01-26 | Arista Networks, Inc. | Boundary condition check using associative memory |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030135449A1 (en) * | 2002-01-14 | 2003-07-17 | Hong Xu | Weighted credit-based arbitration using credit history |
US20030219023A1 (en) * | 2002-05-24 | 2003-11-27 | Hiroaki Miyata | Packet transfer apparatus performing address translation |
US20040123139A1 (en) * | 2002-12-18 | 2004-06-24 | At&T Corp. | System having filtering/monitoring of secure connections |
US20050047329A1 (en) * | 2003-08-29 | 2005-03-03 | Guy Almog | Method and system for manipulating IP packets in virtual private networks |
US20050053074A1 (en) * | 2003-09-04 | 2005-03-10 | Samsung Electronics Co., Ltd. | Apparatus and method for classifying traffic in a distributed architecture router |
US20050129019A1 (en) * | 2003-11-19 | 2005-06-16 | Cheriton David R. | Tunneled security groups |
US20050135399A1 (en) * | 2003-11-10 | 2005-06-23 | Baden Eric A. | Field processor for a network device |
US20060104303A1 (en) * | 2004-11-16 | 2006-05-18 | Srihari Makineni | Packet coalescing |
US8457131B2 (en) * | 2005-02-18 | 2013-06-04 | Broadcom Corporation | Dynamic table sharing of memory space within a network device |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0439507B1 (en) * | 1988-10-20 | 1996-04-24 | CHUNG, David Siu Fu | Memory structure and method of utilization |
JPH05183828A (en) | 1991-12-27 | 1993-07-23 | Sony Corp | Electronic equipment |
DE69324204T2 (en) * | 1992-10-22 | 1999-12-23 | Cabletron Systems, Inc. | Searching for addresses during packet transmission using hashing and a content-addressed memory |
EP0600683B1 (en) * | 1992-12-04 | 2001-10-10 | AT&T Corp. | Packet network interface |
US5802287A (en) * | 1993-10-20 | 1998-09-01 | Lsi Logic Corporation | Single chip universal protocol multi-function ATM network interface |
US5625579A (en) * | 1994-05-10 | 1997-04-29 | International Business Machines Corporation | Stochastic simulation method for processes containing equilibrium steps |
US5831980A (en) * | 1996-09-13 | 1998-11-03 | Lsi Logic Corporation | Shared memory fabric architecture for very high speed ATM switches |
JP3193947B2 (en) * | 1997-01-08 | 2001-07-30 | 株式会社ディジタル・ビジョン・ラボラトリーズ | Data transmission system and data transmission method |
US6175902B1 (en) * | 1997-12-18 | 2001-01-16 | Advanced Micro Devices, Inc. | Method and apparatus for maintaining a time order by physical ordering in a memory |
US5892922A (en) * | 1997-02-28 | 1999-04-06 | 3Com Corporation | Virtual local area network memory access system |
US6011795A (en) * | 1997-03-20 | 2000-01-04 | Washington University | Method and apparatus for fast hierarchical address lookup using controlled expansion of prefixes |
US6119196A (en) * | 1997-06-30 | 2000-09-12 | Sun Microsystems, Inc. | System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates |
US5909686A (en) * | 1997-06-30 | 1999-06-01 | Sun Microsystems, Inc. | Hardware-assisted central processing unit access to a forwarding database |
US6016310A (en) * | 1997-06-30 | 2000-01-18 | Sun Microsystems, Inc. | Trunking support in a high performance network device |
US6041053A (en) * | 1997-09-18 | 2000-03-21 | Microsfot Corporation | Technique for efficiently classifying packets using a trie-indexed hierarchy forest that accommodates wildcards |
US6591299B2 (en) | 1997-11-25 | 2003-07-08 | Packeteer, Inc. | Method for automatically classifying traffic with enhanced hierarchy in a packet communications network |
GB9725374D0 (en) * | 1997-11-28 | 1998-01-28 | 3Com Ireland | Port mirroring and security in stacked communication devices |
US6259699B1 (en) * | 1997-12-30 | 2001-07-10 | Nexabit Networks, Llc | System architecture for and method of processing packets and/or cells in a common switch |
US6173384B1 (en) * | 1998-02-11 | 2001-01-09 | Nortel Networks Limited | Method of searching for a data element in a data structure |
IL124932A0 (en) * | 1998-06-16 | 1999-01-26 | Mea Motor Inspection Ltd | Method and apparatus for testing rotating machines |
AU6311299A (en) * | 1998-07-08 | 2000-02-01 | Broadcom Corporation | Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets |
US6725333B1 (en) * | 1999-04-22 | 2004-04-20 | International Business Machines Corporation | System and method for managing cachable entities |
EP1221214A4 (en) | 1999-09-25 | 2006-06-07 | Motorola Inc | Hierarchical prioritized round robin (hprr) scheduling |
AU2002232481A1 (en) * | 2000-11-07 | 2002-05-21 | Fast-Chip, Inc. | Switch-based network processor |
JP4460195B2 (en) * | 2001-08-06 | 2010-05-12 | 株式会社日立製作所 | Packet transfer device and routing control device |
US7359380B1 (en) * | 2003-06-24 | 2008-04-15 | Nvidia Corporation | Network protocol processing for routing and bridging |
US8271620B2 (en) * | 2003-11-13 | 2012-09-18 | Lantronix, Inc. | Communication protocol converter and method of protocol conversion |
US7363420B2 (en) * | 2003-12-15 | 2008-04-22 | Nortel Networks Limited | Method and file structures for managing data on a flash disk |
US7349982B2 (en) * | 2004-01-12 | 2008-03-25 | Hewlett-Packard Development Company, L.P. | Enablement of route table entries |
US7304974B2 (en) * | 2004-05-14 | 2007-12-04 | Cisco Technology, Inc. | Supporting a network behind a wireless station |
US7733857B2 (en) * | 2004-12-17 | 2010-06-08 | Samsung Electronics Co., Ltd. | Apparatus and method for sharing variables and resources in a multiprocessor routing node |
-
2005
- 2005-03-21 US US11/084,482 patent/US8457131B2/en not_active Expired - Fee Related
-
2013
- 2013-05-01 US US13/875,068 patent/US20130318256A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030135449A1 (en) * | 2002-01-14 | 2003-07-17 | Hong Xu | Weighted credit-based arbitration using credit history |
US20030219023A1 (en) * | 2002-05-24 | 2003-11-27 | Hiroaki Miyata | Packet transfer apparatus performing address translation |
US20040123139A1 (en) * | 2002-12-18 | 2004-06-24 | At&T Corp. | System having filtering/monitoring of secure connections |
US20050047329A1 (en) * | 2003-08-29 | 2005-03-03 | Guy Almog | Method and system for manipulating IP packets in virtual private networks |
US20050053074A1 (en) * | 2003-09-04 | 2005-03-10 | Samsung Electronics Co., Ltd. | Apparatus and method for classifying traffic in a distributed architecture router |
US20050135399A1 (en) * | 2003-11-10 | 2005-06-23 | Baden Eric A. | Field processor for a network device |
US20050129019A1 (en) * | 2003-11-19 | 2005-06-16 | Cheriton David R. | Tunneled security groups |
US20060104303A1 (en) * | 2004-11-16 | 2006-05-18 | Srihari Makineni | Packet coalescing |
US8457131B2 (en) * | 2005-02-18 | 2013-06-04 | Broadcom Corporation | Dynamic table sharing of memory space within a network device |
Non-Patent Citations (1)
Title |
---|
3COM; "Virtual Private Networks: Internet based VPNs", 2001 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107102576A (en) * | 2016-02-23 | 2017-08-29 | 西门子公司 | A kind of controller, dcs and method |
US11012915B2 (en) * | 2018-03-26 | 2021-05-18 | Qualcomm Incorporated | Backpressure signaling for wireless communications |
CN110177046A (en) * | 2019-04-18 | 2019-08-27 | 中国人民解放军战略支援部队信息工程大学 | Secure exchange chip, implementation method and the network switching equipment based on mimicry thought |
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US20060187930A1 (en) | 2006-08-24 |
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