US20130314138A1 - State retention supply voltage distribution using clock network shielding - Google Patents
State retention supply voltage distribution using clock network shielding Download PDFInfo
- Publication number
- US20130314138A1 US20130314138A1 US13/480,971 US201213480971A US2013314138A1 US 20130314138 A1 US20130314138 A1 US 20130314138A1 US 201213480971 A US201213480971 A US 201213480971A US 2013314138 A1 US2013314138 A1 US 2013314138A1
- Authority
- US
- United States
- Prior art keywords
- state
- state retention
- voltage
- low power
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000014759 maintenance of location Effects 0.000 title claims abstract description 150
- 239000000872 buffer Substances 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- 230000000977 initiatory effect Effects 0.000 claims 1
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 27
- 239000002184 metal Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to state retention of an integrated circuit, and more particularly to leveraging a clock network shielding to distribute a state retention supply voltage to state retention devices on the integrated circuit.
- Low Power consumption is emerging as a very important feature for many handheld and battery powered applications.
- conventional configurations however, low power design was not free and added considerable overhead in both silicon area and routing.
- an application may be configured with one or more low power states in which only a subset of the components remain powered on to maintain the state of the device.
- the state retention devices are typically distributed throughout the chip or integrated circuit (IC).
- IC integrated circuit
- a state retention supply voltage was distributed to the state retention devices using a separate state retention power grid.
- the state retention power grid consumed significant routing resources and reduced the available space for functional components. Further, the state retention power grid often required additional metal layers complicating design and substantially increasing cost.
- FIG. 1 is a simplified block diagram of an integrated circuit incorporating a state retention supply distribution using clock network shielding according to one embodiment
- FIG. 2 is a schematic and block diagram providing further details of the state retention supply distribution using clock network shielding configuration of the IC of FIG. 1 ;
- FIG. 3 is a schematic diagram of an exemplary state retention power gating flop which may be used within the register logic of FIG. 1 according to one embodiment
- FIG. 4 is a schematic diagram of the state retention buffer of FIG. 2 according to one embodiment.
- FIG. 5 is a simplified figurative side view of a wafer representing a physical structure of an exemplary embodiment of the integrated circuit of FIG. 1 illustrating an electrical connection between the clock network shielding and a terminal of a state retention device according to one embodiment.
- a state retention supply distribution system using clock network shielding reduces routing overhead.
- the system is applicable to many low power techniques including the State Retention Power Gating (SRPG) low power technique.
- SRPG State Retention Power Gating
- high speed designs including system on chip (SOC) designs
- SOC system on chip
- the clock network shielding was grounded or otherwise coupled to a VSS power supply.
- VSS is at a reference voltage level, which is any positive, negative or ground voltage level.
- a separate state retention grid was provided on the integrated circuit (IC) or chip and coupled to state retention devices on the chip. The state retention grid was coupled to a state retention voltage level. In the low power state, most of the devices of the chip were powered down whereas the state retention devices remained powered by the state retention voltage level. The separate state retention grid, however, consumed valuable space on the IC.
- the clock network shielding is coupled to the state retention power supply node rather than VSS.
- a minimal set of conductive traces is provided to couple the state retention node to the existing clock network shielding, which is already distributed near the state retention devices.
- the state retention devices are coupled to the clock network shielding. In this manner, the clock network shielding is leveraged to distribute the state retention voltage to the state retention devices rather than a separate, space consuming power grid.
- VDDC does not carry much current since it only supports a reduced number of state retention devices and some power gating buffers. In one embodiment, VDDC does not drive clock buffers. In one embodiment, the state retention devices may include the slave portion of SRPG flops.
- FIG. 1 is a simplified block diagram of an integrated circuit (IC) 100 incorporating a state retention supply distribution using clock network shielding according to one embodiment.
- the IC 100 includes power supply pins VDD 102 and VSS 104 .
- the VDD pin 102 is coupled to a power control circuit 106 , which distributes a switched or gated power supply voltage VDDG to register logic and combinatorial logic distributed across the IC 100 , and which also provides a non-gated or constant state retention power supply voltage VDDC to state retention (SR) devices as further described herein.
- the power control circuit 106 may include regulator circuitry for regulating power supply voltages.
- the power control circuit 106 provides a power gating signal PGB for switching between normal and a power reduced or low power state as further described herein.
- the register logic may be distributed in multiple sections or levels, shown figuratively as registers 108 , 112 and 116 .
- the combinatorial logic is distributed between the register logic, including combinatorial logic 110 between registers 108 and 112 and combinatorial logic 114 between registers 112 and 116 .
- VDDG and VSS are shown distributed to the register logic and the combinatorial logic for providing power during normal operation.
- a clock signal CK and the power gating signal PGB are shown distributed to the registers 108 , 112 and 116 .
- a subset of the register logic is configured with state retention devices.
- registers 108 , 112 and 116 include state retention (SR) portions 109 , 113 and 117 , respectively.
- the power control circuit 106 initiates the low power state by asserting the PGB signal, and then the power control circuit 106 reduces voltage and/or power level of VDDG to power-down most of the register logic and substantially all of the combinatorial logic to conserve power.
- the state retention supply voltage VDDC is distributed to the SR portions 109 , 113 and 117 so that the state retention devices remain powered during the low power states.
- the lower power state reduces power by a substantial factor. In one embodiment, for example, the lower power state reduces power by a factor of 10-20, although the specific power reduction factor depends on the particular implementation.
- the SR portions 109 , 113 and 117 are strategically selected to maintain the state of the IC 100 so that operations may be resumed once the power state is returned to the normal operating state.
- Each SR portion 109 , 113 and 117 includes, for example, one or more state retention devices powered by VDDC so that each state retention device maintains its logic state during the low power state.
- VDDG is re-energized to full power level and then the PGB signal is de-asserted.
- PGB is asserted low for the low power state and de-asserted high during the normal operating state.
- the VDDC voltage is distributed to the SR portions 109 , 113 and 117 via a network 118 .
- the clock network shielding distributed with the CK signal is used as the network 118 to distribute VDDC to the state retention devices as further described herein.
- FIG. 2 is a schematic and block diagram providing further details of the state retention supply distribution using clock network shielding configuration of the IC 100 .
- a phase locked loop (PLL) 202 generates a clock signal CK which is distributed across the IC 100 .
- the PLL 202 provides the clock signal CK along multiple clock branches in which it is understood that the implementation is not limited to any particular number of clock branches.
- a first clock signal branch provides CK to registers 108 (including the state retention portion 109 ), a second to registers 112 (including the state retention portion 113 ) and a third to registers 116 (including the state retention portion 117 ) as shown.
- Each clock signal branch carries a clock signal CK, in which branch CK may have the same frequency or may have a different frequency depending upon the particular implementation.
- Clock buffers 204 are distributed along the clock branches carrying the clock signal CK to the various destinations of the IC 100 , and the branches of conductive traces carrying the clock signal CK are surrounded by clock network shielding 210 to maintain clock signal integrity.
- the clock network shielding 210 is routed adjacent on both sides of each clock trace separated by a predetermined distance.
- the clock network shielding 210 may, in some cases, also be provided above and/or below a clock trace, such as provided on different layers of the IC 100 .
- Conductive links 212 are shown distributed along the clock network shielding 210 to represent that the shielding on either side (and above and below, if provided) are electrically coupled together so that the clock network shielding 210 forms a single electrical node.
- the clock signal conductive branches, the clock buffers 204 and the clock network shielding 210 collectively form the clock network for providing one or more clock signals to the register logic of the IC 100 .
- the structure of the clock network shielding 210 may have other configurations in other embodiments.
- the conductive clock signal traces are routed through interconnect layers of an integrated circuit, and the traces of the clock network shielding 210 are located on both sides of the clock signal trace and/or above and below the clock signal trace on surrounding metal layers.
- the clock signal traces may also extend through conductive vias located between the layers.
- the clock signal traces may be surrounded by conductive traces and vias of the clock network shielding 210 .
- the power control circuit 106 is shown providing the VDDC signal to a state retention node formed by one or more state retention conductive traces.
- VDDC is provided from a source provided on the IC 100 , such as being powered directly by the VDD pin.
- a separate pin 206 (shown using dashed lines) on the IC 100 is coupled to the state retention node 216 for receiving a VDDC signal which is sourced off-chip.
- VDDC is sourced on-chip or off-chip.
- a separate VDDC pin may provide additional system design flexibility at the possible expense of an additional IC pin.
- the conductive traces of the state retention node 216 are electrically coupled to the clock network shielding 210 at one or more locations 218 .
- the state retention node 216 charges the clock network shielding 210 to VDDC.
- the state retention node 216 includes a minimal number of conductive traces for establishing the clock network shielding 210 at the VDDC voltage level within a predetermined voltage tolerance level.
- the conventional state retention power grid is effectively eliminated, and instead the clock network shielding 210 is used to distribute VDDC to the desired locations.
- the minimal set of conductive traces of the state retention node 216 are provided to electrically couple VDDC to the clock network shielding 210 and to maintain VDDC within an acceptable voltage tolerance range.
- the power gating signal PGB is routed to the register logic.
- a state retention buffer 222 is provided to maintain PGB signal integrity when PGB signal might otherwise be compromised.
- the state retention buffer 222 includes supply voltage inputs coupled to VSS and to VDDC. As shown, the negative supply voltage input is coupled to VSS and a connection 224 couples the positive supply voltage input of the buffer 222 to the clock network shielding 210 carrying the VDDC power signal. Although only one state retention buffer 222 is shown, and number of the buffers 222 may be provided in any one or more of the conductive traces carrying the PGB signal to the register logic. Each state retention buffer 222 is powered by VDDC via the clock network shielding 210 .
- FIG. 3 is a schematic diagram of an exemplary state retention power gating (SRPG) flop 300 which may be used within the register logic (e.g., registers 108 , 112 , 116 ) according to one embodiment.
- the flop 300 is configured as a master/slave latch (or “flip-flop”) in which the slave portion includes state retention devices as part of the SR portion (e.g., 109 , 113 , 117 ) of the register logic of the IC 100 .
- the flop 300 includes a control circuit 302 , a master latch 304 and a slave latch 306 .
- the control circuit 302 includes a NAND gate 308 and an inverter 310 .
- the NAND gate 308 includes two inputs receiving the PGB and CK signals and has an output providing a first control signal CPN.
- the inverter 310 has an input receiving CPN and an output providing an inverted control signal CPI.
- the NAND gate 308 is configured as state retention device powered by VDDC, and the inverter 310 is powered by the gated power supply VDDG.
- the master latch 304 includes inverters 312 , 316 and 318 and pass gates 314 and 320 .
- a data input signal D is provided to the input of inverter 312 , having its output coupled to the input of the pass gate 314 .
- the output of the pass gate 314 is coupled to the input of inverter 316 at a node 315 , and the output of inverter 316 is coupled to the input of inverter 318 .
- the output of the inverter 318 is coupled to the input of the pass gate 320 , having its output coupled to node 315 .
- the inverters 312 , 316 and 318 are powered by gated supply voltage VDDG.
- the slave latch 306 includes inverters 322 , 326 , 328 and 330 and pass gates 324 and 332 .
- the output of inverter 316 is coupled to the input of inverter 322 , having its output coupled to the input of pass gate 324 .
- the output of the pass gate 324 is coupled to the inputs of inverters 326 and 328 at a node 325 .
- the output of the inverter 328 is coupled to the input of inverter 330 , having its output coupled to the input of pass gate 332 .
- the output of the pass gate 332 is coupled to node 325 .
- the output of the inverter 326 asserts a data output signal DO, which is a latched version of the input data signal D.
- the inverters 322 and 326 are powered by gated supply voltage VDDG, and the inverters 328 and 330 are powered by the state retention voltage VDDC.
- Each pass gate has an inverting control input (indicated by an input bubble) and a non-inverting input.
- each pass gate may be implemented as a P-type metal-oxide semiconductor (PMOS) transistor (not shown) coupled in a back-to-back configuration to an N-type MOS (NMOS) transistor (not shown), such as having their drains coupled together and their sources coupled together.
- the gate of the PMOS transistor forms the inverting input and the gate of the NMOS transistor forms the non-inverting input.
- CPI is provided to the inverting inputs of the pass gates 314 and 332 and to the non-inverting inputs of the pass gates 320 and 324 .
- CPN is provided to the inverting inputs of the pass gates 320 and 324 and to the non-inverting inputs of the pass gates 314 and 332 .
- the transistors and other devices are generally formed on a substrate of the IC 100 , whereas the signals routed between the devices (e.g., CK, PGB, CPN, CPI, etc.) are formed by conductive traces routed on interconnect layers or the like and/or along the substrate.
- the CK signal is routed along a separate clock layer and then routed by conductive interconnects or vias or the like to an input of the NAND gate 308 .
- the clock network shielding 210 is shown routed with CK, in which the clock network shielding 210 is normally terminated and not routed or otherwise provided to the devices on the substrate.
- the clock network shielding 210 of the IC 100 carries the state retention voltage VDDC.
- a connection 303 is coupled to the clock network shielding 210 and routed to provide VDDC to the positive supply input of the NAND gate 308 .
- another connection 305 (or multiple connections) is coupled to the clock network shielding 210 and routed to provide VDDC to the positive supply inputs of the inverters 328 and 330 .
- each of the gates and inverters include similar negative supply inputs coupled to VSS. In this manner, the NAND gate 308 and the inverters 328 and 330 are state retention devices which remain powered by VDDC during the low power state of the IC 100 .
- pass gate 314 When CK goes high, pass gate 314 is turned off while pass gate 320 is turned on.
- the input data signal D is isolated from the input of the master latch 304 and the latched state of D is held at the output of the inverter 316 while CK is high.
- the feedback inverter 318 operates as a keeper with inverter 316 to hold the latched state of D within the master latch 304 while CK is high.
- the pass gate 324 when CK goes high, the pass gate 324 is turned on to pass the latched and inverted version of D at the output of inverter 322 to the input of the inverter 326 of the slave latch 306 , which asserts a latched version of D as the output signal DO.
- the pass gate 324 When CK next goes low, the pass gate 324 is turned off to isolate the slave latch 306 from the master latch 304 , and the pass gate 332 is turned on. While CK is low, the feedback inverters 328 and 330 operate as a keeper to hold the latched and inverted state of D on node 325 within the slave latch 306 . Also, while CK is low, the master latch 304 receives the new state of input data signal D for the next cycle.
- the slave latch 306 is a state retention device since it has at least two states including logic “0” state when node 325 is pulled low to VSS and a logic “1” state when node 325 is pulled high to VDD (either VDDC or VDDG).
- the state of node 325 which reflects the last state of the flop 300 prior to the low power state, is held by the inverters 328 and 330 during the low power state. Most of the remaining devices of the flop 300 are powered down since the VDDG is gated off, so that the flop would otherwise lose its state during the low power state.
- the power control circuit 106 In order to transition back to the normal state from the low power state, the power control circuit 106 re-enables VDDG while PGB remains asserted low. Also, the PLL 202 begins transitioning CK. Once VDDG stabilizes, the inverter 310 and the gated devices of the flop 300 are powered up. PGB is initially held low until the circuit stabilizes so that the state of the flop 300 , held by the slave latch 306 , is maintained during transition to the normal power state. When the circuit is stabilized, the control circuit 106 de-asserts PGB high to resume normal operation.
- FIG. 4 is a schematic diagram of the state retention buffer 222 according to one embodiment.
- the illustrated state retention buffer 222 generally includes a pair of inverters coupled in series in which the first is powered by the state retention voltage VDDC and in which the second is powered by the gated voltage VDDG.
- the first inverter includes a PMOS transistor P 1 having its source coupled to VDDC, its gate coupled to an input node receiving an input signal PGB IN , and its drain coupled to an intermediate node 402 .
- the first inverter further includes an NMOS transistor N 1 having its drain coupled to node 402 , its gate coupled to the input node receiving PGB IN , and its source coupled to VSS.
- the second inverter includes a PMOS transistor P 2 having its source coupled to VDDG, its gate coupled to intermediate node 402 , and its drain coupled to an output node providing an output signal PGB OUT .
- the second inverter further includes an NMOS transistor N 2 having its drain coupled to the output node, its gate coupled to intermediate node 402 , and its source coupled to VSS.
- PGB IN is the PGB signal from the control circuit 106 or is a buffered version thereof
- PGB OUT is a buffered version of PGB IN
- any branch carrying PGB may include multiple state retention buffers similar to buffer 222 to ensure the signal integrity of the PGB signal across the IC 100 .
- PGB IN is de-asserted high turning N 1 on and turning P 1 off pulling node 402 low, so that P 2 is turned on and N 2 is turned off pulling PGB OUT high.
- P 1 is turned on and N 1 is turned off pulling intermediate node 402 high to VDDC (which remains active during the low power state).
- Node 402 pulled high turns N 2 on so that PGB OUT is asserted low. Node 402 pulled high also ensures that P 2 remains off. In this manner, the asserted state of the PGB signal is propagated on the IC 100 during the low power state.
- FIG. 5 is a simplified figurative side view of a wafer 500 representing a physical structure of an exemplary embodiment of the IC 100 illustrating an electrical connection between the clock network shielding 210 and a terminal of a state retention device 526 according to one embodiment.
- the wafer includes a substrate layer S 0 , five metal layers M 1 , M 2 , M 3 , M 4 and M 5 , and five dielectric layers D 1 , D 2 , D 3 , D 4 and D 5 separating the metal layers from each other and the substrate layer S 0 .
- the state retention device 526 is formed within the substrate layer S 0 .
- the substrate layer S 0 is formed by a P-substrate and the state retention device 526 is illustrated as a transistor formed in the P-substrate.
- the state retention device 526 is illustrated as a transistor formed in the P-substrate.
- an NWELL 528 is formed within the P-substrate and two P+ junctions 530 and 532 are formed within the NWELL 528 .
- An insulator layer 534 is formed between the P+ junctions 530 and 532 and a gate 536 (poly gate) is formed on the insulator layer 534 within the dielectric layer D 1 .
- Conductive traces 502 and 504 carrying the state retention voltage VDDC form part of the clock network shielding 210 routed on either side of another conductive trace 506 carrying the clock signal CK within the metal layer M 5 .
- Conductive traces 510 , 514 , 518 , and 522 within the metal layers M 4 , M 3 , M 2 and M 1 , respectively, are electrically interconnected or coupled together by interlayer connections or vias 508 , 512 , 516 , and 520 , respectively, formed within the dielectric layers D 5 , D 4 , D 3 , and D 2 , respectively.
- Another conductive via 524 formed within the dielectric layer D 1 electrically connects conductive trace 522 to the gate 536 of the device 526 . In this manner, CK is electrically coupled to the gate terminal of the device 526 .
- the clock network shielding 210 normally remains only within the metal layers of an integrated circuit and is typically not routed to the substrate.
- conductive traces 540 , 544 , 548 and 552 within the metal layers M 4 , M 3 , M 2 and M 1 , respectively, are electrically interconnected or coupled together by interlayer connections or vias 538 , 542 , 546 , and 550 , respectively, formed within the dielectric layers D 5 , D 4 , D 3 , and D 2 , respectively.
- Another via 554 formed within the dielectric layer D 1 electrically connects conductive trace 552 to the P+ junction 532 of the device 526 .
- the P+ junction 532 may represent either one of the source or drain of the device 526 depending upon the particular implementation. In this manner, VDDC is electrically coupled to an input terminal of the state retention device 526 of the IC 100 .
- the state retention device 526 represents any transistor of a state retention gate or inverter, such as any one of the NAND gate 308 or the inverters 310 , 328 or 330 .
- the state retention device 526 also represents any transistor of a state retention buffer 222 , such as transistor P 1 shown in FIG. 4 .
- a state retention supply voltage is generated on-chip or sourced off chip and coupled to the clock network shielding of the chip.
- the power inputs of the state retention devices of the chip are coupled to the clock network shielding to be powered by the state retention voltage.
- a power gating signal is distributed throughout the chip to switch between normal and low power states. State retention buffers with power inputs coupled to the clock network shielding and thus powered by the state retention voltage may be used to buffer the power gating signal.
- An integrated circuit having a low power state includes a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state.
- the state retention node receives a state retention supply voltage which remains at an operative voltage level relative to a reference voltage level during the low power state.
- the conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node.
- Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered by the state retention supply voltage during the low power state.
- the state retention node may be implemented as a minimal set of conductive traces sufficient to maintain the clock network shielding at the operative voltage level within a predetermined voltage tolerance during the low power state.
- One or more state retention buffers may be provided for buffering a power gating signal indicative of the low power state.
- Each state retention buffer has a supply voltage input coupled to the clock network shielding.
- the multiple state retention devices may include a state retention power gating flop or a master/slave latch including at least one state retention gate.
- a state retention device may be formed on a substrate of the integrate circuit, in which a conductive connection is provided between an interconnect or metal layer and the substrate to electrically couple the clock network shielding to the state retention device.
- the state retention supply voltage may be generated on-chip, such as derived from a primary power input pin, or may be provided by an off-chip source.
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to state retention of an integrated circuit, and more particularly to leveraging a clock network shielding to distribute a state retention supply voltage to state retention devices on the integrated circuit.
- 2. Description of the Related Art
- Low Power consumption is emerging as a very important feature for many handheld and battery powered applications. In conventional configurations, however, low power design was not free and added considerable overhead in both silicon area and routing. In particular, an application may be configured with one or more low power states in which only a subset of the components remain powered on to maintain the state of the device. The state retention devices are typically distributed throughout the chip or integrated circuit (IC). In the conventional configuration, a state retention supply voltage was distributed to the state retention devices using a separate state retention power grid. The state retention power grid consumed significant routing resources and reduced the available space for functional components. Further, the state retention power grid often required additional metal layers complicating design and substantially increasing cost.
- The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
-
FIG. 1 is a simplified block diagram of an integrated circuit incorporating a state retention supply distribution using clock network shielding according to one embodiment; -
FIG. 2 is a schematic and block diagram providing further details of the state retention supply distribution using clock network shielding configuration of the IC ofFIG. 1 ; -
FIG. 3 is a schematic diagram of an exemplary state retention power gating flop which may be used within the register logic ofFIG. 1 according to one embodiment; -
FIG. 4 is a schematic diagram of the state retention buffer ofFIG. 2 according to one embodiment; and -
FIG. 5 is a simplified figurative side view of a wafer representing a physical structure of an exemplary embodiment of the integrated circuit ofFIG. 1 illustrating an electrical connection between the clock network shielding and a terminal of a state retention device according to one embodiment. - The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
- A state retention supply distribution system using clock network shielding according to exemplary embodiments reduces routing overhead. The system is applicable to many low power techniques including the State Retention Power Gating (SRPG) low power technique. In many high speed designs, including system on chip (SOC) designs, same layer coupling capacitances are larger and the clock networks are typically double spaced and shielded to maintain clock signal integrity. In conventional configurations, the clock network shielding was grounded or otherwise coupled to a VSS power supply. VSS is at a reference voltage level, which is any positive, negative or ground voltage level. A separate state retention grid was provided on the integrated circuit (IC) or chip and coupled to state retention devices on the chip. The state retention grid was coupled to a state retention voltage level. In the low power state, most of the devices of the chip were powered down whereas the state retention devices remained powered by the state retention voltage level. The separate state retention grid, however, consumed valuable space on the IC.
- In embodiments described herein, the clock network shielding is coupled to the state retention power supply node rather than VSS. A minimal set of conductive traces is provided to couple the state retention node to the existing clock network shielding, which is already distributed near the state retention devices. The state retention devices are coupled to the clock network shielding. In this manner, the clock network shielding is leveraged to distribute the state retention voltage to the state retention devices rather than a separate, space consuming power grid.
- In one embodiment, VDDC does not carry much current since it only supports a reduced number of state retention devices and some power gating buffers. In one embodiment, VDDC does not drive clock buffers. In one embodiment, the state retention devices may include the slave portion of SRPG flops.
-
FIG. 1 is a simplified block diagram of an integrated circuit (IC) 100 incorporating a state retention supply distribution using clock network shielding according to one embodiment. The IC 100 includes power supply pins VDD 102 and VSS 104. TheVDD pin 102 is coupled to apower control circuit 106, which distributes a switched or gated power supply voltage VDDG to register logic and combinatorial logic distributed across theIC 100, and which also provides a non-gated or constant state retention power supply voltage VDDC to state retention (SR) devices as further described herein. Thepower control circuit 106 may include regulator circuitry for regulating power supply voltages. Thepower control circuit 106 provides a power gating signal PGB for switching between normal and a power reduced or low power state as further described herein. The register logic may be distributed in multiple sections or levels, shown figuratively asregisters combinatorial logic 110 betweenregisters combinatorial logic 114 betweenregisters registers - A subset of the register logic is configured with state retention devices. As shown, for example,
registers portions power control circuit 106 initiates the low power state by asserting the PGB signal, and then thepower control circuit 106 reduces voltage and/or power level of VDDG to power-down most of the register logic and substantially all of the combinatorial logic to conserve power. The state retention supply voltage VDDC, however, is distributed to theSR portions - The SR
portions IC 100 so that operations may be resumed once the power state is returned to the normal operating state. Each SRportion - The VDDC voltage is distributed to the
SR portions -
FIG. 2 is a schematic and block diagram providing further details of the state retention supply distribution using clock network shielding configuration of theIC 100. A phase locked loop (PLL) 202 generates a clock signal CK which is distributed across theIC 100. As shown, thePLL 202 provides the clock signal CK along multiple clock branches in which it is understood that the implementation is not limited to any particular number of clock branches. In the illustrated configuration, a first clock signal branch provides CK to registers 108 (including the state retention portion 109), a second to registers 112 (including the state retention portion 113) and a third to registers 116 (including the state retention portion 117) as shown. Each clock signal branch carries a clock signal CK, in which branch CK may have the same frequency or may have a different frequency depending upon the particular implementation. - Clock buffers 204 are distributed along the clock branches carrying the clock signal CK to the various destinations of the
IC 100, and the branches of conductive traces carrying the clock signal CK are surrounded by clock network shielding 210 to maintain clock signal integrity. The clock network shielding 210 is routed adjacent on both sides of each clock trace separated by a predetermined distance. The clock network shielding 210 may, in some cases, also be provided above and/or below a clock trace, such as provided on different layers of theIC 100.Conductive links 212 are shown distributed along the clock network shielding 210 to represent that the shielding on either side (and above and below, if provided) are electrically coupled together so that the clock network shielding 210 forms a single electrical node. The clock signal conductive branches, the clock buffers 204 and the clock network shielding 210 collectively form the clock network for providing one or more clock signals to the register logic of theIC 100. - The structure of the clock network shielding 210 may have other configurations in other embodiments. In one embodiment, the conductive clock signal traces are routed through interconnect layers of an integrated circuit, and the traces of the clock network shielding 210 are located on both sides of the clock signal trace and/or above and below the clock signal trace on surrounding metal layers. The clock signal traces may also extend through conductive vias located between the layers. The clock signal traces may be surrounded by conductive traces and vias of the clock network shielding 210.
- The
power control circuit 106 is shown providing the VDDC signal to a state retention node formed by one or more state retention conductive traces. In the illustrated embodiment, VDDC is provided from a source provided on theIC 100, such as being powered directly by the VDD pin. In an alternative embodiment, a separate pin 206 (shown using dashed lines) on theIC 100 is coupled to thestate retention node 216 for receiving a VDDC signal which is sourced off-chip. Thus VDDC is sourced on-chip or off-chip. A separate VDDC pin may provide additional system design flexibility at the possible expense of an additional IC pin. - The conductive traces of the
state retention node 216 are electrically coupled to the clock network shielding 210 at one ormore locations 218. Thestate retention node 216 charges the clock network shielding 210 to VDDC. In one embodiment, thestate retention node 216 includes a minimal number of conductive traces for establishing the clock network shielding 210 at the VDDC voltage level within a predetermined voltage tolerance level. Thus, the conventional state retention power grid is effectively eliminated, and instead the clock network shielding 210 is used to distribute VDDC to the desired locations. The minimal set of conductive traces of thestate retention node 216 are provided to electrically couple VDDC to the clock network shielding 210 and to maintain VDDC within an acceptable voltage tolerance range. - The power gating signal PGB is routed to the register logic. A
state retention buffer 222 is provided to maintain PGB signal integrity when PGB signal might otherwise be compromised. Thestate retention buffer 222 includes supply voltage inputs coupled to VSS and to VDDC. As shown, the negative supply voltage input is coupled to VSS and aconnection 224 couples the positive supply voltage input of thebuffer 222 to the clock network shielding 210 carrying the VDDC power signal. Although only onestate retention buffer 222 is shown, and number of thebuffers 222 may be provided in any one or more of the conductive traces carrying the PGB signal to the register logic. Eachstate retention buffer 222 is powered by VDDC via the clock network shielding 210. -
FIG. 3 is a schematic diagram of an exemplary state retention power gating (SRPG)flop 300 which may be used within the register logic (e.g., registers 108, 112, 116) according to one embodiment. Theflop 300 is configured as a master/slave latch (or “flip-flop”) in which the slave portion includes state retention devices as part of the SR portion (e.g., 109, 113, 117) of the register logic of theIC 100. Theflop 300 includes acontrol circuit 302, amaster latch 304 and aslave latch 306. Thecontrol circuit 302 includes aNAND gate 308 and aninverter 310. TheNAND gate 308 includes two inputs receiving the PGB and CK signals and has an output providing a first control signal CPN. Theinverter 310 has an input receiving CPN and an output providing an inverted control signal CPI. TheNAND gate 308 is configured as state retention device powered by VDDC, and theinverter 310 is powered by the gated power supply VDDG. - The
master latch 304 includesinverters gates inverter 312, having its output coupled to the input of thepass gate 314. The output of thepass gate 314 is coupled to the input ofinverter 316 at anode 315, and the output ofinverter 316 is coupled to the input ofinverter 318. The output of theinverter 318 is coupled to the input of thepass gate 320, having its output coupled tonode 315. Theinverters - The
slave latch 306 includesinverters gates inverter 316 is coupled to the input ofinverter 322, having its output coupled to the input ofpass gate 324. The output of thepass gate 324 is coupled to the inputs ofinverters node 325. The output of theinverter 328 is coupled to the input ofinverter 330, having its output coupled to the input ofpass gate 332. The output of thepass gate 332 is coupled tonode 325. The output of theinverter 326 asserts a data output signal DO, which is a latched version of the input data signal D. Theinverters inverters - Each pass gate has an inverting control input (indicated by an input bubble) and a non-inverting input. In one embodiment, each pass gate may be implemented as a P-type metal-oxide semiconductor (PMOS) transistor (not shown) coupled in a back-to-back configuration to an N-type MOS (NMOS) transistor (not shown), such as having their drains coupled together and their sources coupled together. The gate of the PMOS transistor forms the inverting input and the gate of the NMOS transistor forms the non-inverting input. CPI is provided to the inverting inputs of the
pass gates pass gates pass gates pass gates - The transistors and other devices (e.g., the devices forming the
NAND gate 308 and theinverters IC 100, whereas the signals routed between the devices (e.g., CK, PGB, CPN, CPI, etc.) are formed by conductive traces routed on interconnect layers or the like and/or along the substrate. The CK signal is routed along a separate clock layer and then routed by conductive interconnects or vias or the like to an input of theNAND gate 308. The clock network shielding 210 is shown routed with CK, in which the clock network shielding 210 is normally terminated and not routed or otherwise provided to the devices on the substrate. As previously described, the clock network shielding 210 of theIC 100 carries the state retention voltage VDDC. Aconnection 303 is coupled to the clock network shielding 210 and routed to provide VDDC to the positive supply input of theNAND gate 308. Similarly, another connection 305 (or multiple connections) is coupled to the clock network shielding 210 and routed to provide VDDC to the positive supply inputs of theinverters NAND gate 308 and theinverters IC 100. - During normal operation, PGB is de-asserted high so that CPN toggles to the opposite state of CK and CPI toggles to the opposite state of CPN (and thus to the same state as CK after any delay through
NAND gate 308 and inverter 310). When CK is low, thepass gate 314 is turned on, thepass gates inverter 312 and passed to the input ofinverter 316 atnode 315, and theinverters pass gate 324. Since thepass gate 324 is off when CK is low, the output of themaster latch 304 is isolated from the input of theslave latch 306. - When CK goes high,
pass gate 314 is turned off whilepass gate 320 is turned on. The input data signal D is isolated from the input of themaster latch 304 and the latched state of D is held at the output of theinverter 316 while CK is high. Thefeedback inverter 318 operates as a keeper withinverter 316 to hold the latched state of D within themaster latch 304 while CK is high. - Meanwhile, when CK goes high, the
pass gate 324 is turned on to pass the latched and inverted version of D at the output ofinverter 322 to the input of theinverter 326 of theslave latch 306, which asserts a latched version of D as the output signal DO. When CK next goes low, thepass gate 324 is turned off to isolate theslave latch 306 from themaster latch 304, and thepass gate 332 is turned on. While CK is low, thefeedback inverters node 325 within theslave latch 306. Also, while CK is low, themaster latch 304 receives the new state of input data signal D for the next cycle. - When PGB is asserted low to initiate the low power state, CPN is asserted high by the
NAND gate 308. CK is thus isolated from the circuit, although thePLL 202 may also be placed into a low power state so that CK is not asserted or otherwise does not transition during the low power state. After PGB is asserted low, thepower control circuit 106 disables VDDG or otherwise pulls it low. Theinverter 310 is effectively disabled since powered by VDDG, so that CPI is indeterminate or otherwise pulled low. Themaster latch 304 is effectively shut down since VDDG does not provide power during the low power state. Thepass gate 324 is turned off to isolate theslave latch 306 from themaster latch 304. Thepass gate 332, however, is turned on so that the state of theslave latch 306 is maintained onnode 325 by thestate retention inverters - It is appreciated that the
slave latch 306 is a state retention device since it has at least two states including logic “0” state whennode 325 is pulled low to VSS and a logic “1” state whennode 325 is pulled high to VDD (either VDDC or VDDG). The state ofnode 325, which reflects the last state of theflop 300 prior to the low power state, is held by theinverters flop 300 are powered down since the VDDG is gated off, so that the flop would otherwise lose its state during the low power state. - In order to transition back to the normal state from the low power state, the
power control circuit 106 re-enables VDDG while PGB remains asserted low. Also, thePLL 202 begins transitioning CK. Once VDDG stabilizes, theinverter 310 and the gated devices of theflop 300 are powered up. PGB is initially held low until the circuit stabilizes so that the state of theflop 300, held by theslave latch 306, is maintained during transition to the normal power state. When the circuit is stabilized, thecontrol circuit 106 de-asserts PGB high to resume normal operation. -
FIG. 4 is a schematic diagram of thestate retention buffer 222 according to one embodiment. The illustratedstate retention buffer 222 generally includes a pair of inverters coupled in series in which the first is powered by the state retention voltage VDDC and in which the second is powered by the gated voltage VDDG. The first inverter includes a PMOS transistor P1 having its source coupled to VDDC, its gate coupled to an input node receiving an input signal PGBIN, and its drain coupled to anintermediate node 402. The first inverter further includes an NMOS transistor N1 having its drain coupled tonode 402, its gate coupled to the input node receiving PGBIN, and its source coupled to VSS. The second inverter includes a PMOS transistor P2 having its source coupled to VDDG, its gate coupled tointermediate node 402, and its drain coupled to an output node providing an output signal PGBOUT. The second inverter further includes an NMOS transistor N2 having its drain coupled to the output node, its gate coupled tointermediate node 402, and its source coupled to VSS. - In operation, PGBIN is the PGB signal from the
control circuit 106 or is a buffered version thereof, and PGBOUT is a buffered version of PGBIN. It is noted that any branch carrying PGB may include multiple state retention buffers similar to buffer 222 to ensure the signal integrity of the PGB signal across theIC 100. During normal operation, PGBIN is de-asserted high turning N1 on and turning P1 off pullingnode 402 low, so that P2 is turned on and N2 is turned off pulling PGBOUT high. During the low power state when VDDG is not provided and PGBIN is asserted low, P1 is turned on and N1 is turned off pullingintermediate node 402 high to VDDC (which remains active during the low power state).Node 402 pulled high turns N2 on so that PGBOUT is asserted low.Node 402 pulled high also ensures that P2 remains off. In this manner, the asserted state of the PGB signal is propagated on theIC 100 during the low power state. -
FIG. 5 is a simplified figurative side view of awafer 500 representing a physical structure of an exemplary embodiment of theIC 100 illustrating an electrical connection between the clock network shielding 210 and a terminal of astate retention device 526 according to one embodiment. The wafer includes a substrate layer S0, five metal layers M1, M2, M3, M4 and M5, and five dielectric layers D1, D2, D3, D4 and D5 separating the metal layers from each other and the substrate layer S0. Thestate retention device 526 is formed within the substrate layer S0. In the illustrated embodiment, the substrate layer S0 is formed by a P-substrate and thestate retention device 526 is illustrated as a transistor formed in the P-substrate. In particular, anNWELL 528 is formed within the P-substrate and twoP+ junctions NWELL 528. Aninsulator layer 534 is formed between theP+ junctions insulator layer 534 within the dielectric layer D1. - Conductive traces 502 and 504 carrying the state retention voltage VDDC form part of the clock network shielding 210 routed on either side of another
conductive trace 506 carrying the clock signal CK within the metal layer M5. Conductive traces 510, 514, 518, and 522 within the metal layers M4, M3, M2 and M1, respectively, are electrically interconnected or coupled together by interlayer connections orvias conductive trace 522 to thegate 536 of thedevice 526. In this manner, CK is electrically coupled to the gate terminal of thedevice 526. - The clock network shielding 210 normally remains only within the metal layers of an integrated circuit and is typically not routed to the substrate. As shown in
FIG. 5 ,conductive traces vias conductive trace 552 to theP+ junction 532 of thedevice 526. TheP+ junction 532 may represent either one of the source or drain of thedevice 526 depending upon the particular implementation. In this manner, VDDC is electrically coupled to an input terminal of thestate retention device 526 of theIC 100. Thestate retention device 526 represents any transistor of a state retention gate or inverter, such as any one of theNAND gate 308 or theinverters state retention device 526 also represents any transistor of astate retention buffer 222, such as transistor P1 shown inFIG. 4 . - In summary, a state retention supply voltage is generated on-chip or sourced off chip and coupled to the clock network shielding of the chip. The power inputs of the state retention devices of the chip are coupled to the clock network shielding to be powered by the state retention voltage. A power gating signal is distributed throughout the chip to switch between normal and low power states. State retention buffers with power inputs coupled to the clock network shielding and thus powered by the state retention voltage may be used to buffer the power gating signal.
- An integrated circuit having a low power state according to one embodiment includes a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level relative to a reference voltage level during the low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered by the state retention supply voltage during the low power state.
- The state retention node may be implemented as a minimal set of conductive traces sufficient to maintain the clock network shielding at the operative voltage level within a predetermined voltage tolerance during the low power state. One or more state retention buffers may be provided for buffering a power gating signal indicative of the low power state. Each state retention buffer has a supply voltage input coupled to the clock network shielding. The multiple state retention devices may include a state retention power gating flop or a master/slave latch including at least one state retention gate. A state retention device may be formed on a substrate of the integrate circuit, in which a conductive connection is provided between an interconnect or metal layer and the substrate to electrically couple the clock network shielding to the state retention device. The state retention supply voltage may be generated on-chip, such as derived from a primary power input pin, or may be provided by an off-chip source.
- Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/480,971 US8604853B1 (en) | 2012-05-25 | 2012-05-25 | State retention supply voltage distribution using clock network shielding |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/480,971 US8604853B1 (en) | 2012-05-25 | 2012-05-25 | State retention supply voltage distribution using clock network shielding |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130314138A1 true US20130314138A1 (en) | 2013-11-28 |
US8604853B1 US8604853B1 (en) | 2013-12-10 |
Family
ID=49621134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/480,971 Active US8604853B1 (en) | 2012-05-25 | 2012-05-25 | State retention supply voltage distribution using clock network shielding |
Country Status (1)
Country | Link |
---|---|
US (1) | US8604853B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140300396A1 (en) * | 2013-04-03 | 2014-10-09 | Baiquan Shen | Low power srpg cell |
CN104977977A (en) * | 2014-04-02 | 2015-10-14 | 联发科技股份有限公司 | Clock tree circuit and memory controller |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9312834B1 (en) | 2015-01-08 | 2016-04-12 | Freescale Semiconductors,Inc. | Low leakage flip-flop circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6690221B1 (en) * | 1999-12-03 | 2004-02-10 | Intel Corporation | Method and apparatus to delay signal latching |
US7164301B2 (en) | 2005-05-10 | 2007-01-16 | Freescale Semiconductor, Inc | State retention power gating latch circuit |
US7768331B1 (en) | 2007-01-30 | 2010-08-03 | Marvell International Ltd. | State-retentive master-slave flip flop to reduce standby leakage current |
US7683697B2 (en) | 2008-05-30 | 2010-03-23 | Freescale Semiconductor, Inc. | Circuitry and method for buffering a power mode control signal |
KR20110134180A (en) * | 2010-06-08 | 2011-12-14 | 삼성전자주식회사 | Semiconductor devce comprising shield tree and layout method thereof |
-
2012
- 2012-05-25 US US13/480,971 patent/US8604853B1/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140300396A1 (en) * | 2013-04-03 | 2014-10-09 | Baiquan Shen | Low power srpg cell |
US9007112B2 (en) * | 2013-04-03 | 2015-04-14 | Freescale Semiconductor, Inc. | Low power SRPG cell |
CN104977977A (en) * | 2014-04-02 | 2015-10-14 | 联发科技股份有限公司 | Clock tree circuit and memory controller |
EP2927777B1 (en) * | 2014-04-02 | 2019-08-14 | MediaTek Inc. | Clock tree circuit |
Also Published As
Publication number | Publication date |
---|---|
US8604853B1 (en) | 2013-12-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101600947B1 (en) | Data transfer across power domains | |
US9350327B2 (en) | Flip-flops with low clock power | |
EP3245735B1 (en) | Clock-gating cell with low area, low power, and low setup time | |
US10177765B2 (en) | Integrated clock gate circuit with embedded NOR | |
CN106487361B (en) | Multi-bit flip-flop with shared clock switch | |
US8575962B2 (en) | Integrated circuit having critical path voltage scaling and method therefor | |
US9425775B2 (en) | Low swing flip-flop with reduced leakage slave latch | |
US20150084680A1 (en) | State retention power gated cell for integrated circuit | |
US8928354B2 (en) | Clock-delayed domino logic circuit and devices including the same | |
US8604853B1 (en) | State retention supply voltage distribution using clock network shielding | |
US10545556B2 (en) | Fine-grained dynamic power and clock-gating control | |
US20070257705A1 (en) | Device for managing the consumption peak of a domain on each powering-up | |
US11398814B2 (en) | Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop | |
US9319037B2 (en) | Self-adjusting clock doubler and integrated circuit clock distribution system using same | |
US9372499B2 (en) | Low insertion delay clock doubler and integrated circuit clock distribution system using same | |
US11658656B2 (en) | Low power clock gating cell and an integrated circuit including the same | |
US10181848B2 (en) | Digital forward body biasing in CMOS circuits | |
TWI543536B (en) | Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domains | |
US20090066397A1 (en) | Level shift circuit | |
US7986166B1 (en) | Clock buffer circuit | |
Hung et al. | A survey of low-voltage low-power techniques and challenges for CMOS digital circuits | |
US9264040B2 (en) | Low leakage CMOS cell with low voltage swing | |
US11744059B2 (en) | Fin field-effect transistor (FinFET) static random access memory (SRAM) having pass-gate transistors with offset gate contact regions | |
US7447099B2 (en) | Leakage mitigation logic | |
Le Huy et al. | Null convention logic primitive element architecture for ultralow power high performance portable digital systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JARRAR, ANIS M.;SANCHEZ, HECTOR;SIGNING DATES FROM 20120524 TO 20120525;REEL/FRAME:028271/0386 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030256/0706 Effective date: 20120724 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030258/0501 Effective date: 20120724 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030258/0479 Effective date: 20120724 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424 Effective date: 20130521 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0555 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0535 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0575 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212 Effective date: 20160218 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: MERGER;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:041144/0363 Effective date: 20161107 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001 Effective date: 20160218 |
|
AS | Assignment |
Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421 Effective date: 20151207 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |