US20130300484A1 - Offset-compensated active load and method - Google Patents
Offset-compensated active load and method Download PDFInfo
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- US20130300484A1 US20130300484A1 US13/469,416 US201213469416A US2013300484A1 US 20130300484 A1 US20130300484 A1 US 20130300484A1 US 201213469416 A US201213469416 A US 201213469416A US 2013300484 A1 US2013300484 A1 US 2013300484A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45766—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
- H03F3/45771—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means using switching means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45681—Indexing scheme relating to differential amplifiers the LC comprising offset compensating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled
Definitions
- the present invention relates, in general, to electronics and, more particularly, to offset compensation and methods to compensate for offset voltages.
- Circuits such as operational amplifiers, comparators, and the like are used in a variety of applications including communications, signal processing, computers, remote sensing, automotive, aviation, etc. These circuits typically include an input stage coupled to a load stage.
- a drawback with these types of circuits is that mismatches of components of the input stage may cause non-ideal circuit performance. For example, mismatches in the transistors that make up the input stage may introduce an input offset voltage in the circuit.
- Richard Palmer in Application Report SLOA59, titled DC Parameters: Input Offset Voltage (V IO ), dated March 2001, and published by Texas Instruments describes causes of input offset voltage and techniques for reducing input offset voltage.
- FIG. 1 is a schematic of an offset compensated active load in accordance with an embodiment of the present invention
- FIG. 2 is a schematic of an offset compensated active load in accordance with another embodiment of the present invention.
- FIG. 3 is a schematic of an offset compensated active load in accordance with another embodiment of the present invention.
- FIG. 4 is a schematic of an offset compensated active load in accordance with another embodiment of the present invention.
- FIG. 5 is a timing diagram illustrating timing relationships of clock signals coupled to the circuits of FIGS. 1-4 ;
- FIG. 6 is a schematic of a circuit with an offset compensated active load in accordance with an embodiment of the present invention.
- FIG. 7 is a timing diagram illustrating timing relationships of clock signals coupled to the circuit of FIG. 6 ;
- FIG. 8 is a schematic of an offset compensated active load in accordance with an embodiment of the present invention.
- FIG. 9 is a timing diagram illustrating timing relationships of clock signals coupled to the circuit of FIG. 8 .
- current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or an anode of a diode
- a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor.
- the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention.
- the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action.
- the use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position.
- a logic zero voltage level is also referred to as a logic low voltage or logic low voltage level and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family.
- CMOS Complementary Metal Oxide Semiconductor
- a logic zero voltage may be thirty percent of the power supply voltage level.
- TTL Transistor-Transistor Logic
- a logic zero voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts.
- a logic one voltage level is also referred to as a logic high voltage level, a logic high voltage, or a logic one voltage and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.
- the offset-compensated active load includes a plurality of transistors, a plurality of switches, and a plurality of charge storage elements. Two of the plurality of transistors each have a control electrode and first and second current carrying electrodes, wherein the control electrode of one transistor is coupled to the control electrode of the other transistor through the plurality of charge storage elements.
- the offset-compensated active load is capable of operating in at least two operating modes. In one operating mode, the control electrode of one transistor is coupled to its first current carrying electrode and the control electrode of the other transistor is coupled to its first current carrying electrode. In another operating mode, the control electrodes of the transistors are decoupled from their respective first current carrying electrodes.
- offset in an active load may be compensated by generating an offset current in response to coupling input terminals of an input stage together, wherein the offset current flows towards an active load.
- An offset voltage is generated in response to the offset current, and the offset voltage may be stored in a plurality of charge storage elements coupled between transistors of the active load.
- FIG. 1 is a circuit schematic of an offset-compensated active load 10 in accordance with an embodiment of the present invention.
- Active load 10 comprises mirror transistors 12 and 14 and an offset compensation stage 16 , which includes coupling devices 20 , 22 , and 24 , and charge storage elements 30 and 32 .
- transistors 12 and 14 are n-channel transistors and charge storage elements 30 and 32 are capacitors.
- Other suitable elements for charge storage devices 30 and 32 include Metal Oxide Semiconductor devices connected in a capacitor configuration or the like.
- Coupling devices 20 and 24 each have a terminal commonly connected to a drain terminal of transistor 12 to form a node 34 .
- Transistor 14 has a drain terminal connected to a terminal of coupling device 22 to form a node 36 .
- the other terminals of coupling devices 20 and 22 are connected to the gate terminals of mirror transistors 12 and 14 to form nodes 38 and 40 , respectively.
- Capacitor 30 has a terminal connected to the gate terminal of mirror transistor 12 at node 38 and capacitor 32 has a terminal connected to the gate terminal of mirror transistor 14 at node 40 .
- the other terminals of capacitors 30 and 32 are commonly connected together and to the other terminal of coupling device 24 to form a node 42 .
- the source terminals of mirror transistors 12 and 14 are commonly connected together and for receiving a source of operating potential V SS , which may be, for example, ground.
- the control terminals of coupling devices 20 , 22 , and 24 are coupled for receiving clock signals V CLK1 , V CLK2 , and V CLK3 , respectively.
- Clock signals may also be referred to as control signals.
- Suitable devices for coupling devices 20 , 22 , and 24 include MOS switches or transmission gates that may be coupled in a series configuration with voltage followers, controlled resistors, capacitors, or the like.
- FIG. 2 is a circuit schematic of an offset-compensated active load 50 in accordance with another embodiment of the present invention.
- Active load 50 comprises transistors 12 and 14 and an offset compensation stage 52 , which includes switches 54 , 56 , and 58 , and charge storage elements 30 and 32 .
- transistors 12 and 14 are n-channel transistors and energy storage elements 30 and 32 are capacitors.
- Switches 54 , 56 , and 58 each have a control terminal and a pair of conduction terminals. One of the conduction terminals of switch 54 and one of the conduction terminals of switch 58 are commonly connected with the drain terminal of transistor 12 to form a node 34 .
- One of the conduction terminals of switch 56 and the drain terminal of transistor 14 are commonly connected together to form a node 36 .
- the other conduction terminal of switch 54 is connected to the gate terminal of mirror transistor 12 to form a node 38 and the other conduction terminal of switch 56 is connected to the gate terminal of mirror transistor 14 to form a node 40 .
- Capacitor 30 has a terminal connected to the gate terminal of mirror transistor 12 at node 38 and capacitor 32 has a terminal connected to the gate terminal of mirror transistor 14 at node 40 .
- the other terminals of capacitors 30 and 32 are commonly connected together and to the other conduction terminal of switch 58 to form a node 42 .
- the source terminals of mirror transistors 12 and 14 are commonly connected together for receiving a source of operating potential V SS .
- Switches 54 , 56 , and 58 have control terminals coupled for receiving clock signals V CLK1 , V CLK2 , and V CLK3 , respectively. It should be noted that a transistor may serve as a switch where the control electrode of the transistor is analogous to the control terminal of the switch and the current carrying electrodes of the transistor are analogous to the conduction terminals of the switch.
- FIG. 3 is a circuit schematic of an offset-compensated active load 100 in accordance with an embodiment of the present invention.
- Active load 100 comprises mirror transistors 12 and 14 and an offset compensation stage 102 , which includes transistors 104 , 106 , and 108 , and charge storage elements 30 and 32 .
- transistors 12 , 14 , 104 , 106 , and 108 are n-channel transistors and energy storage elements 30 and 32 are capacitors.
- Transistors 12 , 104 , and 108 each have a drain terminal commonly connected together to form a node 34 .
- Transistors 14 and 106 each have a drain terminal commonly connected together to form a node 36 .
- the source terminals of transistors 104 and 106 are connected to the gate terminals of mirror transistors 12 and 14 to form nodes 38 and 40 , respectively.
- Capacitor 30 has a terminal connected to the gate terminal of mirror transistor 12 at node 38 and capacitor 32 has a terminal connected to the gate terminal of mirror transistor 14 at node 40 .
- the other terminals of capacitors 30 and 32 are commonly connected together and to the source terminal of transistor 108 to form a node 42 .
- the source terminals of mirror transistors 12 and 14 are commonly connected together and for receiving a source of operating potential V SS .
- the gate terminals of transistors 104 , 106 , and 108 are coupled for receiving clock signals V CLK1 , V CLK2 , and V CLK3 , respectively. It should be noted that in alternative embodiments the drain of transistor 108 may be connected to the drain of transistor 106 rather than to the drain of transistor 104 .
- FIG. 4 is a circuit schematic of an offset-compensated active load 100 A in accordance with another embodiment of the present invention.
- Active load 100 A comprises mirror transistors 12 A and 14 A and an offset compensation stage 102 A, which includes transistors 104 A, 106 A, and 108 A, and charge storage elements 30 and 32 .
- transistors 12 A, 14 A, 104 A, 106 A, and 108 A are p-channel transistors and energy storage elements 30 and 32 are capacitors.
- Transistors 12 A, 104 A, and 108 A each have a drain terminal commonly connected together to form a node 34 .
- Transistors 14 A and 106 A each have a drain terminal connected together to form a node 36 .
- the source terminals of transistors 104 A and 106 A are connected to the gate terminals of mirror transistors 12 A and 14 A to form nodes 38 and 40 , respectively.
- Capacitor 30 has a terminal connected to the gate terminal of mirror transistor 12 A at node 38 and capacitor 32 has a terminal connected to the gate terminal of mirror transistor 14 A at node 40 .
- the other terminals of capacitors 30 and 32 are commonly connected together and to the source terminal of transistor 108 A to form a node 42 .
- the source terminals of mirror transistors 12 A and 14 A are commonly connected together and for receiving a source of operating potential V DD .
- offset-compensated active load 100 A is similar to offset-compensated active load 100 except that transistors 12 A, 14 A, 104 A, 106 A, and 108 A are p-channel transistors.
- the letter “A” has been appended to reference characters 12 , 14 , 104 , 106 , and 108 to distinguish p-channel transistors from n-channel transistors.
- FIG. 5 is a timing diagram 120 of clock signals appearing at the control terminals of coupling devices such as coupling devices, 20 , 22 , and 24 of FIG. 1 , switches 54 , 56 , and 58 of FIG. 2 , or transistors 104 , 106 , and 108 of FIG. 3 , respectively.
- timing diagram 120 may be changed to make it suitable for use with transistors 104 A, 106 A, and 108 A of FIG. 4 , by inverting clock signals V CLK1 , V CLK2 , and V CLK3 , respectively.
- FIG. 5 is a timing diagram 120 of clock signals appearing at the control terminals of coupling devices such as coupling devices, 20 , 22 , and 24 of FIG. 1 , switches 54 , 56 , and 58 of FIG. 2 , or transistors 104 , 106 , and 108 of FIG. 3 , respectively.
- timing diagram 120 may be changed to make it suitable for use with transistors 104 A, 106 A, and 108 A of
- clock signals V CLK1 , V CLK2 , and V CLK3 are applied to the gate terminals of transistors 104 , 106 , and 108 , respectively.
- clock signals V CLK1 and V CLK2 are the same signals.
- offset-compensated active load 10 operates in the auto-zeroing mode.
- transistor 104 is on, connecting node 34 to node 38
- transistor 106 is on, connecting node 36 to node 40
- transistor 108 is off.
- a transistor that is on is analogous to a switch that is closed and a transistor that is off is analogous to a switch that is open. More particularly, applying a signal to the control electrode of a transistor that turns on the transistor is analogous to applying the signal to the control terminal of the switch that closes the switch and applying a signal to the control electrode of the transistor that turns off the transistor is analogous to applying the signal to the control terminal of the switch that opens the switch.
- a differential current signal flows through nodes 34 and 36 .
- a current I 1 flows into node 34 and a current ⁇ I 1 flows from node 36 .
- the differential current differentially charges capacitors 30 and 32 .
- clock signals V CLK1 and V CLK2 transition to a logic low voltage level turning off transistors 104 and 106 and at time t 2 clock signal V CLK3 transitions to a logic high voltage level turning on transistor 108 and maintaining active load 100 in a current mirror configuration.
- clock signal V CLK3 transitions to a logic high voltage level turning on transistor 108 and maintaining active load 100 in a current mirror configuration.
- offset-compensated current mirror 100 operates in an active mode. Because transistors 104 and 106 are off, node 34 is disconnected or decoupled from node 38 and node 36 is disconnected or decoupled from node 40 , respectively. In addition, because transistor 108 is on, node 34 is connected to node 42 .
- time period between times t 1 and t 2 is sufficiently short that biasing of active load 100 is maintained during the transition.
- Turning on transistor 108 creates glitches on node 42 that appear as a common mode signal at nodes 38 and 40 . Because voltage variations at node 42 appear as a common mode signal when transistors 104 and 106 are off, they have no effect on the analog information stored differentially between nodes 38 and 40 .
- clock signal V CLK3 transitions to a logic low voltage level turning off transistor 108 and at time t 4 clock signals V CLK1 and V CLK2 transition to a logic high voltage level turning on transistors 104 and 106 and offset-compensated active load 100 enters an auto-zeroing operating mode.
- clock signals V CLK1 and V CLK2 transition to a logic low voltage level turning off transistors 104 and 106 and at time t 6 clock signal V CLK3 transitions to a logic high voltage level turning on transistor 108 .
- offset-compensated current mirror 100 operates in an active mode. Offset-compensated active load 100 continues switching between the active operating mode and the auto-zeroing operating mode.
- Clocking signals V CLK1 , V CLK2 , and V CLK3 can be periodic or aperiodic signals.
- FIG. 6 is a circuit schematic of a circuit 150 including an input stage 152 connected to an offset-compensated active load 100 B having offset compensation stage 116 .
- Input stage 152 comprises a pair of transistors 158 and 160 connected together in a differential configuration.
- transistors 158 and 160 are p-channel field effect transistors, where each transistor has a control electrode and a pair of current carrying electrodes.
- the control electrodes of transistors 158 and 160 serve as input terminals 162 and 164 , respectively, of input stage 152 .
- the source terminals of transistors 158 and 160 are commonly connected together and to a terminal of a current source 165 .
- the other terminal of current source 165 is coupled for receiving a source of operating potential such as, for example, V DD .
- the drain terminals of transistors 158 and 160 serve as output terminals 166 and 168 of input stage 152 , respectively.
- a transistor 170 has a gate terminal coupled for receiving a clock signal V CLK5 , a drain terminal coupled for receiving a reference potential V BIAS2 , and a source terminal coupled to the gate terminal of transistor 158 .
- a transistor 172 has a gate terminal coupled for receiving a clock signal V CLK6 , a drain terminal coupled for receiving a reference potential V BIAS3 , and a source terminal coupled to the gate terminal of transistor 160 .
- a transistor 174 has a gate terminal commonly connected to its drain terminal to generate a biasing potential V BIAS1 , and a source terminal connected to the source terminals of mirror transistors 12 and 14 .
- the commonly connected gate and drain terminals are connected to a terminal of a current source 176 .
- Current source 176 has another terminal coupled for receiving source of operating potential V DD .
- Offset-compensated active load 100 B includes active load 100 described with reference to FIG. 3 and a transistor 109 , which sets the potential at node 42 to a predetermined level during the auto-zeroing mode of operation.
- Transistor 28 has a gate terminal coupled for receiving a clock signal V CLK4 , a drain terminal coupled for receiving a biasing potential V BIAS1 , and a source terminal connected to node 42 .
- transistor 109 is an optional element and that the offset-compensated active load has been designated by reference character 100 B in FIG. 6 because it differs from the offset-compensated active load 100 by the addition of transistor 109 , which sets a voltage at node 42 .
- the potential at node 42 may achieve a defined potential after several cycles of operation.
- circuit 150 operates in at least two operating modes: an active mode and an auto-zeroing or offset-cancellation mode.
- compensated active load 100 B compensates for charge injected into the input stage.
- Clock signals V CLK1 , V CLK2 , V CLK3 , and V CLK4 are applied to the gates of transistors 104 , 106 , 108 , and 109 , respectively, to store an offset compensation charge in capacitors 30 and 32 .
- FIG. 7 is a timing diagram 180 of the clock signals appearing at the gate terminals of transistors 104 , 106 , 108 , and 109 .
- clock signals V CLK1 and V CLK2 are the same signals and clock signals V CLK5 and V CLK6 are the same signals.
- clock signals V CLK1 , V CLK2 , V CLK4 , V CLK5 , and V CLK6 are at a logic low voltage level and clock signal V CLK3 is at a logic high voltage level.
- transistor 108 is on and connects node 34 to node 42 forming a current mirror from transistors 12 and 14 . Because clock signals V CLK5 and V CLK6 are at a logic low voltage level, transistors 170 and 172 are off.
- clock signal V CLK3 transitions to a logic low voltage level, turning off transistor 108 and at time t 2 , clock signals V CLK1 , V CLK2 , V CLK4 , V CLK5 , and V CLK6 transition to a logic high voltage level which begins an auto-zeroing or calibration mode.
- clock signals V CLK1 , V CLK2 , V CLK4 , V CLK5 , and V CLK6 transitioning to a logic high voltage level, transistors 104 , 106 , 109 , 170 , and 172 , respectively, turn on, which is analogous to closing switches in embodiments where these transistors operate as switches.
- transistor 109 In response to clock signal V CLK4 being at a logic high voltage level, transistor 109 is on and a voltage substantially equal to voltage V BIAS1 appears at node 42 . Because transistors 104 and 106 are on, node 34 is connected or coupled to node 38 and node 36 is connected or coupled to node 40 , respectively. In addition, because transistor 108 is off, node 34 is disconnected from node 42 and because transistor 109 is on, bias voltage V BIAS1 is connected to node 42 . It should be noted that the time period from time t 1 to time t 2 is sufficiently short that mirror transistors 12 and 14 continue to operate as a current mirror.
- bias potentials V BIAS2 and V BIAS3 are set to the same potential, which shorts the input terminals of input stage 152 together.
- any difference between the drain currents of transistors 158 and 160 flows differentially from output terminals 166 and 168 into mirror transistors 12 and 14 , respectively.
- This current which may be referred to as a differential offset current
- transistors 12 and 14 are converted into a differential voltage by transistors 12 and 14 , wherein the differential voltage is stored in capacitors 30 and 32 .
- This voltage may be referred to as an offset compensation voltage.
- transistor 12 in response to a first portion of the differential offset current transistor 12 generates a voltage and transistor 14 generates another voltage that cooperate to form the differential input offset compensation voltage.
- Transistor 12 generates a first portion of the offset compensation voltage which may be stored in capacitor 30 and transistor 14 generates another portion of the offset compensation voltage, which may be stored in capacitor 32 .
- the voltages stored in capacitors 30 and 32 are an image of the input offset voltage.
- clock signals V CLK5 and V CLK6 transition to a logic low voltage level, turning off transistors 170 and 172 , and disconnecting input terminals 162 and 164 from bias signals V BIAS2 and V BIAS3 .
- transistors 170 and 172 inject charges into input terminals 162 and 164 of input stage 152 , respectively.
- additional circuitry may be connected to input terminals 162 and 164 through which charge may be injected. For the sake of clarity, this circuitry has been omitted. The injected charges cancel each other because of the circuit's differential configuration.
- any residual charge imbalance at input terminals 162 and 164 is further cancelled in response to clock signals V CLK1 , V CLK2 , and V CLK4 being at a logic high voltage level because transistors 12 and 14 are still connected as diodes in this state.
- clock signals V CLK1 and V CLK2 transition to a logic low voltage level, turning off transistors 104 and 106 , and ending the auto-zeroing operating mode.
- clock signal V CLK4 transitions to a logic low voltage level turning off transistor 109 , and circuit 150 enters an active operating mode in response to clock signal V CLK3 transitioning to a logic high voltage level and turning on transistor 108 at time t 6 , which reconfigures mirror transistor 12 as an input transistor of a current mirror. Because transistors 104 and 106 are off, node 34 is disconnected or decoupled from node 38 and node 36 is disconnected or decoupled from node 40 , respectively.
- Clocking signals V CLK1 , V CLK2 , and V CLK3 can be periodic or aperiodic signals.
- Transistor 174 provides a DC bias to node 42 during the auto-zeroing operating mode.
- FIG. 8 is a circuit schematic of an offset-compensated active load 200 in accordance with another embodiment of the present invention.
- Active load 200 comprises mirror transistors 12 and 14 and an offset compensation stage 202 , which includes transistors 104 and 106 , and a charge storage element 204 .
- transistors 12 , 14 , 104 , and 106 are n-channel transistors and energy storage element 204 is a capacitor.
- Transistors 12 and 104 each have a drain terminal commonly connected together to form a node 206 .
- Transistors 14 and 106 each have a drain terminal commonly connected together to form node 36 .
- the source terminals of transistors 104 and 106 are connected to the gate terminals of mirror transistors 12 and 14 to form nodes 38 and 40 , respectively.
- Capacitor 204 has a terminal connected to the gate terminal of mirror transistor 12 at node 38 and a terminal connected to the gate terminal of mirror transistor 14 at node 40 .
- the source terminals of mirror transistors 12 and 14 are commonly connected together and for receiving a source of operating potential V SS .
- the gate terminals of transistors 104 and 106 are coupled for receiving clock signals V CLK1 and V CLK2 , respectively.
- offset-compensated active load 200 operates in at least two operating modes: an active mode and an auto-zeroing or offset-cancellation mode.
- Clock signals V CLK1 and V CLK2 are applied to the gates of transistors 104 and 106 , respectively.
- FIG. 9 is a timing diagram 220 of the clock signals appearing at the gate terminals of transistors 104 and 106 .
- offset-compensation active load 200 operates in the auto-zeroing mode.
- transistor 104 is on, connecting node 206 to node 38 and transistor 106 is also on, connecting node 36 to node 40 so that transistors 12 and 14 are configured as diodes.
- the offsets associated with currents injected into nodes 206 and 36 are stored differentially across capacitor 204 .
- clock signals V CLK1 and V CLK2 transition to a logic low voltage level turning off transistors 104 and 106 and at time t 2 clock signal V CLK1 transitions to a logic high voltage level turning on transistor 104 .
- offset-compensated current mirror 200 operates in an active mode. Because of the gate-to-source capacitance intrinsic to a field effect transistor, glitches occur at node 38 in response to entering the active operating mode. These glitches are attenuated at node 40 by a capacitive divider formed by capacitor 204 and the gate-to-source capacitance (C gs14 ) of transistor 14 .
- clock signal V CLK2 transitions to a logic high voltage level turning on transistor 106 and offset-compensated active load 200 enters an auto-zeroing operating mode.
- clock signals V CLK1 and V CLK2 transition to a logic low voltage level turning off transistors 104 and 106 and at time t 5 clock signal V CLK1 transitions to a logic high voltage level.
- clock signal V CLK1 transitioning to the logic high voltage level at time t 5 offset-compensated active load 200 enters an active operating mode.
- Clocking signals V CLK1 and V CLK2 can be periodic or aperiodic signals.
- the active load includes coupling devices that short nodes within the active load together.
- the active load includes a current mirror having at least two transistors
- the gate and drain terminals of one transistor are coupled together via a coupling device such as a switch or a transistor
- the gate and drain terminals of another transistor are coupled together via another coupling device, and the gate terminals of the transistors are coupled to each other through a plurality of capacitors.
- the offset-compensation can provide differential compensation in circuit configurations in which the normal operating mode of the circuit is single-ended.
- the active load has been shown as a current mirror, this is not a limitation of the present invention.
- Other suitable active loads include current sources, current sources degenerated with resistors, cascode mirrors or sources, or the like. It should be noted that for cascoded sources and mirrors, the coupling devices connect the gates of mirror transistors to the drains of their cascode elements and the drains of cascoding devices are analogous to the drains of the transistors connected in series with them.
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Abstract
Description
- The present invention relates, in general, to electronics and, more particularly, to offset compensation and methods to compensate for offset voltages.
- Circuits such as operational amplifiers, comparators, and the like are used in a variety of applications including communications, signal processing, computers, remote sensing, automotive, aviation, etc. These circuits typically include an input stage coupled to a load stage. A drawback with these types of circuits is that mismatches of components of the input stage may cause non-ideal circuit performance. For example, mismatches in the transistors that make up the input stage may introduce an input offset voltage in the circuit. Richard Palmer in Application Report SLOA59, titled DC Parameters: Input Offset Voltage (VIO), dated March 2001, and published by Texas Instruments describes causes of input offset voltage and techniques for reducing input offset voltage. In addition, U.S. Pat. No. 7,920,009 B2 issued to Stephen Robert Kosic et al. on Apr. 5, 2011, and U.S. Pat. No. 7,623,054 B2 issued to Masao Iriguchi et al. on Nov. 24, 2009, describe techniques for canceling an offset voltage. These techniques include switches that may introduce noise or inject charge into the input stages, but fail to compensate for this noise or injected charge.
- Accordingly, it would be advantageous to have a circuit and a method for mitigating input offset voltage. It is desirable for the circuit and method to be cost and time efficient to implement.
- The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:
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FIG. 1 is a schematic of an offset compensated active load in accordance with an embodiment of the present invention; -
FIG. 2 is a schematic of an offset compensated active load in accordance with another embodiment of the present invention; -
FIG. 3 is a schematic of an offset compensated active load in accordance with another embodiment of the present invention; -
FIG. 4 is a schematic of an offset compensated active load in accordance with another embodiment of the present invention; -
FIG. 5 is a timing diagram illustrating timing relationships of clock signals coupled to the circuits ofFIGS. 1-4 ; -
FIG. 6 is a schematic of a circuit with an offset compensated active load in accordance with an embodiment of the present invention; -
FIG. 7 is a timing diagram illustrating timing relationships of clock signals coupled to the circuit ofFIG. 6 ; -
FIG. 8 is a schematic of an offset compensated active load in accordance with an embodiment of the present invention; and -
FIG. 9 is a timing diagram illustrating timing relationships of clock signals coupled to the circuit ofFIG. 8 . - For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or an anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten per cent (10%) (and up to twenty per cent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.
- It should be noted that a logic zero voltage level (VL) is also referred to as a logic low voltage or logic low voltage level and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Transistor-Transistor Logic (TTL) system a logic zero voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VH) is also referred to as a logic high voltage level, a logic high voltage, or a logic one voltage and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.
- The present description includes, among other features, a semiconductor component that includes an offset-compensated active load and a method for compensating for offsets. In accordance with one aspect, the offset-compensated active load includes a plurality of transistors, a plurality of switches, and a plurality of charge storage elements. Two of the plurality of transistors each have a control electrode and first and second current carrying electrodes, wherein the control electrode of one transistor is coupled to the control electrode of the other transistor through the plurality of charge storage elements. By way of example, the offset-compensated active load is capable of operating in at least two operating modes. In one operating mode, the control electrode of one transistor is coupled to its first current carrying electrode and the control electrode of the other transistor is coupled to its first current carrying electrode. In another operating mode, the control electrodes of the transistors are decoupled from their respective first current carrying electrodes.
- In accordance with another aspect, offset in an active load may be compensated by generating an offset current in response to coupling input terminals of an input stage together, wherein the offset current flows towards an active load. An offset voltage is generated in response to the offset current, and the offset voltage may be stored in a plurality of charge storage elements coupled between transistors of the active load.
-
FIG. 1 is a circuit schematic of an offset-compensatedactive load 10 in accordance with an embodiment of the present invention.Active load 10 comprisesmirror transistors coupling devices 20, 22, and 24, andcharge storage elements transistors charge storage elements charge storage devices Coupling devices 20 and 24 each have a terminal commonly connected to a drain terminal oftransistor 12 to form anode 34.Transistor 14 has a drain terminal connected to a terminal of coupling device 22 to form anode 36. The other terminals of coupling devices 20 and 22 are connected to the gate terminals ofmirror transistors nodes Capacitor 30 has a terminal connected to the gate terminal ofmirror transistor 12 atnode 38 andcapacitor 32 has a terminal connected to the gate terminal ofmirror transistor 14 atnode 40. The other terminals ofcapacitors coupling device 24 to form anode 42. The source terminals ofmirror transistors coupling devices 20, 22, and 24 are coupled for receiving clock signals VCLK1, VCLK2, and VCLK3, respectively. Clock signals may also be referred to as control signals. Suitable devices forcoupling devices 20, 22, and 24 include MOS switches or transmission gates that may be coupled in a series configuration with voltage followers, controlled resistors, capacitors, or the like. -
FIG. 2 is a circuit schematic of an offset-compensatedactive load 50 in accordance with another embodiment of the present invention.Active load 50 comprisestransistors switches charge storage elements transistors energy storage elements Switches switch 54 and one of the conduction terminals ofswitch 58 are commonly connected with the drain terminal oftransistor 12 to form anode 34. One of the conduction terminals of switch 56 and the drain terminal oftransistor 14 are commonly connected together to form anode 36. The other conduction terminal ofswitch 54 is connected to the gate terminal ofmirror transistor 12 to form anode 38 and the other conduction terminal of switch 56 is connected to the gate terminal ofmirror transistor 14 to form anode 40.Capacitor 30 has a terminal connected to the gate terminal ofmirror transistor 12 atnode 38 andcapacitor 32 has a terminal connected to the gate terminal ofmirror transistor 14 atnode 40. The other terminals ofcapacitors switch 58 to form anode 42. The source terminals ofmirror transistors -
FIG. 3 is a circuit schematic of an offset-compensatedactive load 100 in accordance with an embodiment of the present invention.Active load 100 comprisesmirror transistors transistors charge storage elements transistors energy storage elements Transistors node 34.Transistors node 36. The source terminals oftransistors mirror transistors nodes Capacitor 30 has a terminal connected to the gate terminal ofmirror transistor 12 atnode 38 andcapacitor 32 has a terminal connected to the gate terminal ofmirror transistor 14 atnode 40. The other terminals ofcapacitors transistor 108 to form anode 42. The source terminals ofmirror transistors transistors transistor 108 may be connected to the drain oftransistor 106 rather than to the drain oftransistor 104. -
FIG. 4 is a circuit schematic of an offset-compensatedactive load 100A in accordance with another embodiment of the present invention.Active load 100A comprises mirror transistors 12A and 14A and an offsetcompensation stage 102A, which includestransistors charge storage elements transistors energy storage elements Transistors 12A, 104A, and 108A each have a drain terminal commonly connected together to form anode 34.Transistors 14A and 106A each have a drain terminal connected together to form anode 36. The source terminals oftransistors 104A and 106A are connected to the gate terminals of mirror transistors 12A and 14A to formnodes Capacitor 30 has a terminal connected to the gate terminal of mirror transistor 12A atnode 38 andcapacitor 32 has a terminal connected to the gate terminal of mirror transistor 14A atnode 40. The other terminals ofcapacitors transistor 108A to form anode 42. The source terminals of mirror transistors 12A and 14A are commonly connected together and for receiving a source of operating potential VDD. The gate terminals oftransistors active load 100A is similar to offset-compensatedactive load 100 except thattransistors reference characters - In operation, the offset-compensated active load operates in at least two operating modes: an active mode and an auto-zeroing or offset-cancellation mode.
FIG. 5 is a timing diagram 120 of clock signals appearing at the control terminals of coupling devices such as coupling devices, 20, 22, and 24 ofFIG. 1 , switches 54, 56, and 58 ofFIG. 2 , ortransistors FIG. 3 , respectively. It should be noted that timing diagram 120 may be changed to make it suitable for use withtransistors FIG. 4 , by inverting clock signals VCLK1, VCLK2, and VCLK3, respectively. For the sake of clarity,FIG. 5 will be described with reference toFIG. 3 . Thus, clock signals VCLK1, VCLK2, and VCLK3 are applied to the gate terminals oftransistors active load 10 operates in the auto-zeroing mode. Thus,transistor 104 is on, connectingnode 34 tonode 38,transistor 106 is on, connectingnode 36 tonode 40, andtransistor 108 is off. It should be noted that a transistor that is on is analogous to a switch that is closed and a transistor that is off is analogous to a switch that is open. More particularly, applying a signal to the control electrode of a transistor that turns on the transistor is analogous to applying the signal to the control terminal of the switch that closes the switch and applying a signal to the control electrode of the transistor that turns off the transistor is analogous to applying the signal to the control terminal of the switch that opens the switch. In accordance with this embodiment, a differential current signal flows throughnodes node 34 and a current −I1 flows fromnode 36. The differential current differentially chargescapacitors - At time t1, clock signals VCLK1 and VCLK2 transition to a logic low voltage level turning off
transistors transistor 108 and maintainingactive load 100 in a current mirror configuration. In response totransistors transistor 108 turning on, offset-compensatedcurrent mirror 100 operates in an active mode. Becausetransistors node 34 is disconnected or decoupled fromnode 38 andnode 36 is disconnected or decoupled fromnode 40, respectively. In addition, becausetransistor 108 is on,node 34 is connected tonode 42. It should be noted that the time period between times t1 and t2 is sufficiently short that biasing ofactive load 100 is maintained during the transition. Turning ontransistor 108 creates glitches onnode 42 that appear as a common mode signal atnodes node 42 appear as a common mode signal whentransistors nodes - At time t3, clock signal VCLK3 transitions to a logic low voltage level turning off
transistor 108 and at time t4 clock signals VCLK1 and VCLK2 transition to a logic high voltage level turning ontransistors active load 100 enters an auto-zeroing operating mode. - At time t5, clock signals VCLK1 and VCLK2 transition to a logic low voltage level turning off
transistors transistor 108. As described above, in response totransistors transistor 108 turning on, offset-compensatedcurrent mirror 100 operates in an active mode. Offset-compensatedactive load 100 continues switching between the active operating mode and the auto-zeroing operating mode. It should be noted that a clocking scheme for a single period is shown and described with reference toFIG. 5 . However, this is not a limitation of the present invention. Clocking signals VCLK1, VCLK2, and VCLK3 can be periodic or aperiodic signals. -
FIG. 6 is a circuit schematic of acircuit 150 including aninput stage 152 connected to an offset-compensatedactive load 100B having offsetcompensation stage 116.Input stage 152 comprises a pair oftransistors transistors transistors input terminals input stage 152. The source terminals oftransistors current source 165. The other terminal ofcurrent source 165 is coupled for receiving a source of operating potential such as, for example, VDD. The drain terminals oftransistors output terminals input stage 152, respectively. - A transistor 170 has a gate terminal coupled for receiving a clock signal VCLK5, a drain terminal coupled for receiving a reference potential VBIAS2, and a source terminal coupled to the gate terminal of
transistor 158. Atransistor 172 has a gate terminal coupled for receiving a clock signal VCLK6, a drain terminal coupled for receiving a reference potential VBIAS3, and a source terminal coupled to the gate terminal oftransistor 160. - A
transistor 174 has a gate terminal commonly connected to its drain terminal to generate a biasing potential VBIAS1, and a source terminal connected to the source terminals ofmirror transistors current source 176.Current source 176 has another terminal coupled for receiving source of operating potential VDD. - Offset-compensated
active load 100B includesactive load 100 described with reference toFIG. 3 and atransistor 109, which sets the potential atnode 42 to a predetermined level during the auto-zeroing mode of operation. Transistor 28 has a gate terminal coupled for receiving a clock signal VCLK4, a drain terminal coupled for receiving a biasing potential VBIAS1, and a source terminal connected tonode 42. It should be noted thattransistor 109 is an optional element and that the offset-compensated active load has been designated byreference character 100B inFIG. 6 because it differs from the offset-compensatedactive load 100 by the addition oftransistor 109, which sets a voltage atnode 42. It should be further noted that in embodiments in whichtransistor 109 is absent, the potential atnode 42 may achieve a defined potential after several cycles of operation. - In operation,
circuit 150 operates in at least two operating modes: an active mode and an auto-zeroing or offset-cancellation mode. In response to operation in the auto-zeroing mode, compensatedactive load 100B compensates for charge injected into the input stage. Clock signals VCLK1, VCLK2, VCLK3, and VCLK4 are applied to the gates oftransistors capacitors FIG. 7 is a timing diagram 180 of the clock signals appearing at the gate terminals oftransistors transistor 108 is on and connectsnode 34 tonode 42 forming a current mirror fromtransistors transistors 170 and 172 are off. - At time t1, clock signal VCLK3 transitions to a logic low voltage level, turning off
transistor 108 and at time t2, clock signals VCLK1, VCLK2, VCLK4, VCLK5, and VCLK6 transition to a logic high voltage level which begins an auto-zeroing or calibration mode. As discussed above, in response to clock signals VCLK1, VCLK2, VCLK4, VCLK5, and VCLK6 transitioning to a logic high voltage level,transistors transistor 109 is on and a voltage substantially equal to voltage VBIAS1 appears atnode 42. Becausetransistors node 34 is connected or coupled tonode 38 andnode 36 is connected or coupled tonode 40, respectively. In addition, becausetransistor 108 is off,node 34 is disconnected fromnode 42 and becausetransistor 109 is on, bias voltage VBIAS1 is connected tonode 42. It should be noted that the time period from time t1 to time t2 is sufficiently short thatmirror transistors input stage 152 together. In this configuration, any difference between the drain currents oftransistors output terminals mirror transistors transistors capacitors current transistor 12 generates a voltage andtransistor 14 generates another voltage that cooperate to form the differential input offset compensation voltage.Transistor 12 generates a first portion of the offset compensation voltage which may be stored incapacitor 30 andtransistor 14 generates another portion of the offset compensation voltage, which may be stored incapacitor 32. The voltages stored incapacitors - At time t3, clock signals VCLK5 and VCLK6 transition to a logic low voltage level, turning off
transistors 170 and 172, and disconnectinginput terminals transistors 170 and 172 inject charges intoinput terminals input stage 152, respectively. It should be noted that additional circuitry may be connected to inputterminals input terminals transistors - At time t4, clock signals VCLK1 and VCLK2 transition to a logic low voltage level, turning off
transistors transistor 109, andcircuit 150 enters an active operating mode in response to clock signal VCLK3 transitioning to a logic high voltage level and turning ontransistor 108 at time t6, which reconfiguresmirror transistor 12 as an input transistor of a current mirror. Becausetransistors node 34 is disconnected or decoupled fromnode 38 andnode 36 is disconnected or decoupled fromnode 40, respectively. In addition, becausetransistor 108 is on,node 34 is connected tonode 42 and becausetransistor 109 is off, bias voltage VBIAS1 is disconnected fromnode 42. Although a clocking scheme for a single period is shown and described with reference toFIG. 5 , this is not a limitation of the present invention. Clocking signals VCLK1, VCLK2, and VCLK3 can be periodic or aperiodic signals. - It should be noted that charge injection into
node 42 does not contribute to the offset voltage becausenode 42 acts as a common-mode bias totransistors Transistor 174 provides a DC bias tonode 42 during the auto-zeroing operating mode. -
FIG. 8 is a circuit schematic of an offset-compensatedactive load 200 in accordance with another embodiment of the present invention.Active load 200 comprisesmirror transistors compensation stage 202, which includestransistors charge storage element 204. By way of example,transistors energy storage element 204 is a capacitor.Transistors node 206.Transistors node 36. The source terminals oftransistors mirror transistors nodes Capacitor 204 has a terminal connected to the gate terminal ofmirror transistor 12 atnode 38 and a terminal connected to the gate terminal ofmirror transistor 14 atnode 40. The source terminals ofmirror transistors transistors - Like
active load 10, offset-compensatedactive load 200 operates in at least two operating modes: an active mode and an auto-zeroing or offset-cancellation mode. Clock signals VCLK1 and VCLK2 are applied to the gates oftransistors FIG. 9 is a timing diagram 220 of the clock signals appearing at the gate terminals oftransistors active load 200 operates in the auto-zeroing mode. Thus,transistor 104 is on, connectingnode 206 tonode 38 andtransistor 106 is also on, connectingnode 36 tonode 40 so thattransistors nodes capacitor 204. - At time t1, clock signals VCLK1 and VCLK2 transition to a logic low voltage level turning off
transistors transistor 104. In response totransistor 104 turning on, offset-compensatedcurrent mirror 200 operates in an active mode. Because of the gate-to-source capacitance intrinsic to a field effect transistor, glitches occur atnode 38 in response to entering the active operating mode. These glitches are attenuated atnode 40 by a capacitive divider formed bycapacitor 204 and the gate-to-source capacitance (Cgs14) oftransistor 14. - At time t3, clock signal VCLK2 transitions to a logic high voltage level turning on
transistor 106 and offset-compensatedactive load 200 enters an auto-zeroing operating mode. - At time t4, clock signals VCLK1 and VCLK2 transition to a logic low voltage level turning off
transistors active load 200 enters an active operating mode. Although a clocking scheme for a single period is shown and described with reference toFIG. 9 , this is not a limitation of the present invention. Clocking signals VCLK1 and VCLK2 can be periodic or aperiodic signals. - By now it should be appreciated that a circuit with an offset-compensated active load and a method for compensating for offset have been provided. Compensating for offset may be referred to as auto-zeroing wherein a compensation signal compensates for an offset signal. In accordance with embodiments, the active load includes coupling devices that short nodes within the active load together. For example, in embodiments in which the active load includes a current mirror having at least two transistors, the gate and drain terminals of one transistor are coupled together via a coupling device such as a switch or a transistor, and the gate and drain terminals of another transistor are coupled together via another coupling device, and the gate terminals of the transistors are coupled to each other through a plurality of capacitors. The offset-compensation can provide differential compensation in circuit configurations in which the normal operating mode of the circuit is single-ended. Although the active load has been shown as a current mirror, this is not a limitation of the present invention. Other suitable active loads include current sources, current sources degenerated with resistors, cascode mirrors or sources, or the like. It should be noted that for cascoded sources and mirrors, the coupling devices connect the gates of mirror transistors to the drains of their cascode elements and the drains of cascoding devices are analogous to the drains of the transistors connected in series with them.
- Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.
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US13/469,416 US8570095B1 (en) | 2012-05-11 | 2012-05-11 | Offset-compensated active load and method |
CN2013202496229U CN203352544U (en) | 2012-05-11 | 2013-05-10 | Detuning compensation active load |
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US13/469,416 US8570095B1 (en) | 2012-05-11 | 2012-05-11 | Offset-compensated active load and method |
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US20130300484A1 true US20130300484A1 (en) | 2013-11-14 |
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CN111614333A (en) * | 2020-01-03 | 2020-09-01 | 东南大学 | High-speed sampling amplifier with offset cancellation function |
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IT201800005777A1 (en) * | 2018-05-28 | 2019-11-28 | DIFFERENTIAL AMPLIFIER, INTEGRATED CIRCUIT, SYSTEM, CORRESPONDING INSTRUMENT AMPLIFIER AND PROCEDURE |
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US10326418B2 (en) * | 2017-05-19 | 2019-06-18 | Stmicroelectronics S.R.L. | Large input swing circuit, corresponding device and method |
CN111614333A (en) * | 2020-01-03 | 2020-09-01 | 东南大学 | High-speed sampling amplifier with offset cancellation function |
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