US20130270649A1 - Bipolar transistor manufacturing method - Google Patents
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- US20130270649A1 US20130270649A1 US13/859,341 US201313859341A US2013270649A1 US 20130270649 A1 US20130270649 A1 US 20130270649A1 US 201313859341 A US201313859341 A US 201313859341A US 2013270649 A1 US2013270649 A1 US 2013270649A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7371—Vertical transistors
Definitions
- the present disclosure relates to bipolar transistors formed on an integrated circuit. More specifically, the present disclosure relates to a method for manufacturing such a transistor.
- MOS transistors In integrated circuits, it may be advantageous to integrate, on a same wafer, MOS transistors and bipolar transistors (integration better known as “BiCMOS”). Indeed, these two types of transistors have specific advantages.
- MOS transistors allow fast switchings for digital processings
- bipolar transistors have a particularly good performance at high frequencies, for example, higher than some hundred GHz, and may have a high output power.
- these last transistors may be used to form circuits for controlling optical circuits, for example, lasers.
- FIG. 1 illustrates an example of a conventional bipolar transistor formed on a solid substrate where MOS transistors can also be formed.
- a heavily-doped region 14 forming the collector of the bipolar transistor extends in depth in the active area of substrate 10 delimited by trenches 12 . Region 14 extends in depth in substrate 10 across a thickness on the order of 1 ⁇ m, leaving a less heavily-doped layer 16 at the substrate surface.
- a stack of an insulating layer 22 for example, an oxide, and of a heavily-doped polysilicon layer 24 (of type P if the transistor is an NPN transistor).
- the stack of layers 22 and 24 extends above the apparent surface of substrate 10 (region 16 ) and stops above a portion of shallow trench 18 .
- a portion of insulating layer 22 is replaced with a stack 25 of a silicon-germanium layer and of a silicon layer.
- Stack 25 forms the base of the bipolar transistor.
- An opening is also provided in layer 24 , opposite to region 16 and on a smaller surface area than the opening in region 22 .
- a heavily-doped region 26 forming the emitter region of the bipolar transistor is provided in this opening defined in layer 24 , as well as at the surface of layer 25 .
- Region 26 is separated from layer 22 by spacers 28 made of insulating material.
- An emitter contact 29 is provided on semiconductor material 26 via a silicide layer 30 formed at the surface of semiconductor material 26 .
- a base contact 32 is provided on layer 24 via a silicide layer 34 formed at the surface of layer 24 , and a collector contact 36 is provided on regions 20 via a silicide layer 38 formed at the surface of these regions.
- an insulating material layer (having region 22 forming a portion thereof at the end of the manufacturing) is formed over the entire active region, after which a heavily-doped polysilicon layer (having region 24 forming a portion thereof at the end of the manufacturing) is formed at the surface of the substrate.
- a dopant implantation is then performed in region 16 , through the insulating material present above this region, to form a collector region localized in this region.
- An opening is then formed in heavily-doped polysilicon layer 24 opposite to region 16 , this opening corresponding to the final opening defined in layer 24 .
- An insulating material layer is then formed at the surface of layer 24 and on the walls of the previously-defined opening.
- An etching is then performed from the bottom of the opening defined in layer 24 to remove the material of insulating layer 22 under the opening, but also to laterally define a cavity in the layer of material 22 , under layer 24 .
- Silicon-germanium 25 grows from the lower surface of polysilicon layer 24 as well as from the upper surface of region 16 , to fill the cavity formed in insulating layer 22 . Then, spacers 28 are formed at the surface of silicon-germanium region 25 . The opening remaining at the surface of silicon-germanium layer 25 is then filled with material 26 forming the transistor emitter.
- a last step comprises performing etchings to obtain the topology of the transistor of FIG. 1 and thus to expose the upper surfaces of regions 20 and 24 , after which a silicidation of the device is carried out to form silicide regions 30 , 34 , and 38 .
- a first disadvantage of a bipolar transistor such as that in FIG. 1 is its bulk. Indeed, in order to operate properly, collector region 14 typically has, in substrate 10 , a depth on the order of one micrometer. Such a depth is not compatible with recent methods for manufacturing MOS transistors on substrates of silicon-on-insulator type (SOI) where the upper substrate is very thin (thickness smaller than 15 nm). Such substrates, currently used in new semiconductor technologies, are called FD-SOI (fully depleted semiconductor on insulator).
- SOI silicon-on-insulator type
- the access to the base is performed via a layer 24 of heavily-doped polysilicon, the contact between layer 24 and silicon-germanium region 25 being achieved on a horizontal surface.
- This contact is illustrated in FIG. 1 by a region in dotted lines 39 .
- polysilicon layer to access the base alters the transistor performance. Indeed, polysilicon has a higher resistivity than, for example, a metal or heavily-doped single-crystal silicon. Thus, there is a significant access resistance between base contact 32 and base 25 , which is not desired. It should be noted that the forming of single-crystal silicon for the access to the base is not compatible with the above method, a growth or a deposition of single-crystal silicon being impossible to perform on an insulating material.
- the junction between base region 25 and collector region 16 has a relatively extensive surface area, which implies a significant junction capacitance between these two regions.
- the junction capacitances it is desired for the junction capacitances to be as low as possible.
- the bipolar transistor of FIG. 1 has junction capacitances and access resistances which are generally not compatible with a high-performance bipolar transistor.
- One or more embodiments provide a method for manufacturing an integrated bipolar transistor having a very high frequency performance.
- One embodiment provides such a method compatible with substrates currently used for the forming of MOS transistors.
- Another embodiment relates to a bipolar transistor obtained by this method, and at an integrated circuit comprising such a bipolar transistor as well as conventional MOS transistors.
- an embodiment provides a method for manufacturing a bipolar transistor, comprising the successive steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.
- the semiconductor layer has a thickness ranging between 5 and 15 nm and the first insulating layer has a thickness ranging between 10 and 50 nm.
- the method comprises an initial step of forming shallow insulating trenches which extend in the semiconductor layer, the first insulating layer, and the semiconductor substrate to delimit active areas.
- the step of defining an opening is preceded by a step of forming a third insulating layer on the walls of the trench and the step of forming a single-crystal silicon region in the opening is followed by a step of removal of the third insulating layer.
- the step of forming a second doped region at least in the remaining space of the trench is preceded by a step of forming spacers on the remaining walls of the trench.
- the method further comprises a final step of defining openings of access to the first doped region and to the silicon layer.
- the openings of access to the silicon layer and to the first doped region are obtained by performing a first etching of a portion of the second insulating layer and a second etching of the silicon layer and of the semiconductor layer.
- the method further comprises a final step of annealing the structure.
- the method further comprises a final step of silicidation of the device.
- An embodiment further provides a bipolar transistor formed in a structure comprising a semiconductor layer extending on a semiconductor substrate with an interposed insulating layer, the transistor comprising a collector region defined at the surface of the semiconductor substrate, a buffer region between base and collector defined in an opening formed in the insulating layer opposite to the collector region, and base and emitter regions formed at the surface of the buffer region.
- the transistor further comprises a region of access to the base made of a single-crystal semiconductor material.
- An embodiment further provides an integrated circuit comprising an association of at least one MOS transistor and of at least one bipolar transistor such as defined hereabove.
- FIG. 1 previously described, illustrates a bipolar transistor formed on a solid substrate by a known method
- FIGS. 2 to 18 illustrate results of steps of a method for manufacturing a bipolar transistor according to an embodiment.
- FIGS. 2 to 18 illustrate results of steps of such a method.
- FIG. 2 it is started from a structure of FD-SOI type comprising an upper semiconductor layer 40 which extends on a semiconductor substrate 42 with an interposed insulating layer 44 .
- a structure of FD-SOI type comprising an upper semiconductor layer 40 which extends on a semiconductor substrate 42 with an interposed insulating layer 44 .
- such structures have an insulating layer 44 with a thickness ranging between 10 and 50 nm, for example, 25 nm, and a fully-depleted upper layer 40 with a thickness ranging between 5 and 15 nm, for example, 10 nm.
- shallow insulating trenches 46 which cross semiconductor layer 40 , insulating layer 44 , and which penetrate in depth into semiconductor substrate 42 are formed.
- Trenches 46 extend down to a total depth ranging between 150 and 350 nm, for example, a depth equal to 250 nm.
- a dopant implantation has been performed through semiconductor layer 40 and insulating layer 44 , to form a heavily-doped region 48 at the surface of substrate 42 and in the active area laterally defined by insulating trenches 46 .
- Region 48 may extend in substrate 42 across a thickness ranging between 100 and 300 nm and is doped at a dopant concentration ranging between 5.10 18 and 5.10 19 at/cm 3 , for example, on the order of 10 19 at/cm 3 .
- Region 48 forms the collector region of the bipolar transistor.
- region 48 may be obtained by an arsenic implantation if the desired bipolar transistor is of type NPN.
- a heavily-doped single-crystal silicon layer 50 of the conductivity type desired for the transistor base for example, heavily doped with boron if an NPN bipolar transistor is desired, has been formed.
- Single-crystal silicon layer 50 is preferably formed by selective epitaxial growth (SEG), which enables the growth of a heavily-doped single-crystal silicon layer 50 only at the surface of layer 40 , and not at the surface of insulating trenches 46 .
- Silicon layer 50 has a thickness ranging between 20 and 60 nm, so that the stack of semiconductor layer 40 and of layer 50 has a total thickness ranging between 25 and 75 nm.
- first layer 52 may be made of a dielectric material such as tetraethoxysilane (TEOS) having a thickness ranging between 5 and 10 nm, for example, 8 nm
- layer 54 may be a silicon nitride layer having a thickness ranging between 30 and 80 nm, for example, equal to 50 nm.
- Layers 52 and 54 extend at the surface of heavily-doped single-crystal silicon layer 50 , on the walls of this layer, and cover insulating trenches 46 .
- an insulating material 62 for example, made of silicon nitride, has been formed.
- a nitride layer may be conformally deposited over the entire structure, after which an anisotropic etching is performed to remove the horizontal portions of the layer thus formed. Only regions 62 thus remain on the walls of trench 60 .
- insulating layer 44 has been etched through the mask delimited by walls 62 to form a second trench 64 which extends through this layer to expose semiconductor substrate 42 , at the level of heavily-doped region 48 formed at the surface of this substrate. The etching performed to remove layer 44 is selective over the nitride of walls 62 and/or of layer 54 .
- a single-crystal silicon layer 66 has been grown from heavily-doped region 48 .
- the growth of layer 66 is performed by low-temperature selective epitaxy, which provides a single-crystal silicon layer 66 having a well-controlled profile at the surface of region 48 .
- the upper surface of layer 66 is provided to be flush with the surface of insulating layer 44 . It should be noted that a slight misalignment between the surfaces of layers 66 and 44 is not critical, as long as this misalignment does not exceed some ten nanometers.
- Single-crystal silicon layer 66 forms a buffer area between base and collector.
- insulating regions 62 have been etched.
- the silicon nitride has been selectively etched, this etching also eliminating an upper portion of nitride layer 54 .
- the etching may be an isotropic plasma etching.
- Layer 70 is formed of a stack of several layers, for example, a silicon-germanium layer and a silicon layer.
- the silicon-germanium layer contains the dopant of the base (boron if the transistor is an NPN transistor).
- the silicon-germanium layer may also contain carbon atoms to decrease the boron diffusion during subsequent anneals.
- the growth of layer 70 advantageously is a selective growth, easy to control, so that the upper surface of layer 70 extends under the upper surface of single-crystal silicon layer 50 , or is flush with the upper surface of layer 50 .
- spacers 72 made of an insulating material, for example, an oxide, have been formed at the surface of layer 70 .
- Spacers 72 extend on the contour of the upper surface of layer 70 and on the walls of trench 60 .
- spacers 72 cover the edges of insulating regions 52 and 54 , as well as the remaining edge, if present, of single-crystal silicon layer 50 .
- spacers 72 may be formed by deposition of an oxide, followed by the deposition of amorphous silicon over the entire structure.
- amorphous silicon An anisotropic etching of the amorphous silicon, followed by an etching of the material forming the spacers via the mask formed by the amorphous silicon, are then performed.
- the amorphous silicon may then be removed, which enables to obtain “L” shapes, characteristic of spacers, above layer 70 .
- the amorphous silicon may also be kept above layer 70 , this material mixing afterwards with the material deposited to form the transistor emitter.
- a region of a heavily-doped material of a conductivity type capable of forming the emitter region of the bipolar transistor has been formed over the entire structure, to fill the space remaining in trench 60 .
- this region may be heavily doped with arsenic atoms.
- An etching is then performed to only leave a heavily-doped emitter-forming portion 74 above layer 70 , as well as above a portion of insulating material layer 54 .
- insulating layers 54 and 52 have been etched.
- the surfaces of insulating trenches 46 are exposed, as well as the surface of heavily-doped single-crystal silicon layer 50 .
- This etching may be of any known type capable of removing insulating layers 54 and 52 .
- a new etching has been performed, via a mask of adapted shape, to remove portions of layer 50 , of layer 40 , and of insulating layer 44 located on the contour of the device, that is, on the contour of the active area, for example in contact with insulating trenches 46 .
- an access to heavily-doped region 48 forming the bipolar transistor collector is opened.
- This step may be carried out in several etch steps, a first step being capable of removing the semiconductor material of layers 50 and 40 , and a second step being capable of removing the insulating material of layer 44 .
- a step illustrated in FIG. 16 via the same mask as that used to perform the etching of the step of FIG. 15 , an implantation of dopants of the same conductivity type as that of region 48 has been performed at the surface of the exposed portions of region 48 .
- heavily-doped regions 78 are formed, for example, at a dopant concentration ranging between 5.10 19 and 5.10 20 at/cm 3 , for example, at 10 20 at/cm 3 .
- the entire structure has been annealed.
- This anneal allows the diffusion of the doped regions of the different elements of the structure.
- this anneal enables to extend heavily-doped region 78 formed at the surface of layer 48 , to form a more extended heavily-doped region 82 at the surface of this region.
- This anneal further enables for the dopant atoms of heavily-doped layer 50 to partly migrate to silicon layer 40 in order to form a single region 80 .
- the obtained region 80 forms the region of access to the formed base of layer 70 .
- the diffusion anneal further develops collector region 74 so that it extends slightly at the surface of layer 70 .
- the anneal also implies a diffusion of dopant atoms from emitter 74 to the silicon layer comprised in the stack forming layer 70 .
- a silicidation of the entire device that is, a nickel deposition followed by a heat treatment and by adapted chemical treatments, has been performed without using a mask, which enables to transform the apparent silicon regions into conductive silicide regions.
- region 82 sees its surface covered with a silicide region 84
- region 80 sees its surface covered with a silicide region 86
- region 74 sees its surface covered with a silicide region 88 .
- Regions 84 , 86 , and 88 respectively form the contact regions of the collector, of the base, and of the emitter.
- a bipolar transistor is obtained, having its structure extending in depth in the substrate of FD-SOI type, and thus avoiding having too large a thickness, at the surface of the device.
- the method provided herein is particularly compatible with the forming, in parallel, of MOS transistors on the FD-SOI substrate.
- the material of access to base 70 of semiconductor region 80 advantageously is heavily-doped single-crystal silicon.
- the resistance of access to the base is smaller than in the case of prior art where the access to the base was performed by means of a polysilicon region.
- the method provided herein also enables to finely control the thicknesses of the emitter region, of the base region, of the buffer region between the collector and the base, and of the collector region, which provides a fine-quality vertical profile of the bipolar transistor, with characteristics that can easily be adjusted.
- junction surface area between the base and the collector region is decreased, which enables to limit the base-collector junction capacitance with respect to prior art bipolar transistors.
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Abstract
A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.
Description
- 1. Technical Field
- The present disclosure relates to bipolar transistors formed on an integrated circuit. More specifically, the present disclosure relates to a method for manufacturing such a transistor.
- 2. Description of the Related Art
- In integrated circuits, it may be advantageous to integrate, on a same wafer, MOS transistors and bipolar transistors (integration better known as “BiCMOS”). Indeed, these two types of transistors have specific advantages. In particular, MOS transistors allow fast switchings for digital processings, while bipolar transistors have a particularly good performance at high frequencies, for example, higher than some hundred GHz, and may have a high output power. Thus, these last transistors may be used to form circuits for controlling optical circuits, for example, lasers.
- Thus, methods for simultaneously manufacturing MOS transistors and bipolar transistors on a same substrate are needed.
-
FIG. 1 illustrates an example of a conventional bipolar transistor formed on a solid substrate where MOS transistors can also be formed. - At the surface of a
solid substrate 10 is defined an active area delimited by deep insulatingtrenches 12.Trenches 12 are conventionally formed and are currently known as DTI (for Deep Trench Isolation) trenches. - A heavily-
doped region 14 forming the collector of the bipolar transistor extends in depth in the active area ofsubstrate 10 delimited bytrenches 12.Region 14 extends in depth insubstrate 10 across a thickness on the order of 1 μm, leaving a less heavily-dopedlayer 16 at the substrate surface. - Shallow
trenches 18, currently known as STI (for Shallow Trench Isolation) trenches, are provided on either side of the active area and stop deep inregion 14. In the middle ofshallow trenches 18 are providedregions 20 of access tocollector region 14.Regions 20 are in practice a heavily-doped region ofsubstrate 10. - At the surface of
substrate 10 is formed a stack of aninsulating layer 22, for example, an oxide, and of a heavily-doped polysilicon layer 24 (of type P if the transistor is an NPN transistor). The stack oflayers shallow trench 18. Opposite toregion 16, a portion ofinsulating layer 22 is replaced with astack 25 of a silicon-germanium layer and of a silicon layer.Stack 25 forms the base of the bipolar transistor. - An opening is also provided in
layer 24, opposite toregion 16 and on a smaller surface area than the opening inregion 22. In this opening defined inlayer 24, as well as at the surface oflayer 25, a heavily-doped region 26 forming the emitter region of the bipolar transistor is provided.Region 26 is separated fromlayer 22 byspacers 28 made of insulating material. - An
emitter contact 29 is provided onsemiconductor material 26 via asilicide layer 30 formed at the surface ofsemiconductor material 26. Abase contact 32 is provided onlayer 24 via asilicide layer 34 formed at the surface oflayer 24, and acollector contact 36 is provided onregions 20 via asilicide layer 38 formed at the surface of these regions. - To obtain the device of
FIG. 1 , the following steps may be carried out. At an initial step, heavily dopedregion 14 is formed in depth in asemiconductor substrate 10. A semiconductor material epitaxy may then be performed to obtain a less heavily dopedregion 16 of adapted thickness. Insulatingtrenches 12 for delimiting the active area, as well astrenches 18, are then defined (by means of adapted masks). The dopant implantation enabling to formregions 20 is then performed. - Then, an insulating material layer (having
region 22 forming a portion thereof at the end of the manufacturing) is formed over the entire active region, after which a heavily-doped polysilicon layer (havingregion 24 forming a portion thereof at the end of the manufacturing) is formed at the surface of the substrate. A dopant implantation is then performed inregion 16, through the insulating material present above this region, to form a collector region localized in this region. An opening is then formed in heavily-dopedpolysilicon layer 24 opposite toregion 16, this opening corresponding to the final opening defined inlayer 24. An insulating material layer is then formed at the surface oflayer 24 and on the walls of the previously-defined opening. - An etching is then performed from the bottom of the opening defined in
layer 24 to remove the material of insulatinglayer 22 under the opening, but also to laterally define a cavity in the layer ofmaterial 22, underlayer 24. - A silicon-germanium growth is then carried out in the cavity thus defined. Silicon-
germanium 25 grows from the lower surface ofpolysilicon layer 24 as well as from the upper surface ofregion 16, to fill the cavity formed in insulatinglayer 22. Then, spacers 28 are formed at the surface of silicon-germanium region 25. The opening remaining at the surface of silicon-germanium layer 25 is then filled withmaterial 26 forming the transistor emitter. - A last step comprises performing etchings to obtain the topology of the transistor of
FIG. 1 and thus to expose the upper surfaces ofregions silicide regions - A first disadvantage of a bipolar transistor such as that in
FIG. 1 is its bulk. Indeed, in order to operate properly,collector region 14 typically has, insubstrate 10, a depth on the order of one micrometer. Such a depth is not compatible with recent methods for manufacturing MOS transistors on substrates of silicon-on-insulator type (SOI) where the upper substrate is very thin (thickness smaller than 15 nm). Such substrates, currently used in new semiconductor technologies, are called FD-SOI (fully depleted semiconductor on insulator). - Further, with the device of
FIG. 1 , the access to the base is performed via alayer 24 of heavily-doped polysilicon, the contact betweenlayer 24 and silicon-germanium region 25 being achieved on a horizontal surface. This contact is illustrated inFIG. 1 by a region indotted lines 39. - The use of a polysilicon layer to access the base alters the transistor performance. Indeed, polysilicon has a higher resistivity than, for example, a metal or heavily-doped single-crystal silicon. Thus, there is a significant access resistance between
base contact 32 andbase 25, which is not desired. It should be noted that the forming of single-crystal silicon for the access to the base is not compatible with the above method, a growth or a deposition of single-crystal silicon being impossible to perform on an insulating material. - Further, with the device of
FIG. 1 , the junction betweenbase region 25 andcollector region 16 has a relatively extensive surface area, which implies a significant junction capacitance between these two regions. To obtain a bipolar transistor having a satisfactory performance, it is desired for the junction capacitances to be as low as possible. - Thus, the bipolar transistor of
FIG. 1 has junction capacitances and access resistances which are generally not compatible with a high-performance bipolar transistor. - Thus, there is a need for a method for manufacturing a high-performance bipolar transistor on a substrate of FD-SOI type.
- One or more embodiments provide a method for manufacturing an integrated bipolar transistor having a very high frequency performance.
- One embodiment provides such a method compatible with substrates currently used for the forming of MOS transistors.
- Another embodiment relates to a bipolar transistor obtained by this method, and at an integrated circuit comprising such a bipolar transistor as well as conventional MOS transistors.
- Thus, an embodiment provides a method for manufacturing a bipolar transistor, comprising the successive steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.
- According to an embodiment, the semiconductor layer has a thickness ranging between 5 and 15 nm and the first insulating layer has a thickness ranging between 10 and 50 nm.
- According to an embodiment, the method comprises an initial step of forming shallow insulating trenches which extend in the semiconductor layer, the first insulating layer, and the semiconductor substrate to delimit active areas.
- According to an embodiment, the step of defining an opening is preceded by a step of forming a third insulating layer on the walls of the trench and the step of forming a single-crystal silicon region in the opening is followed by a step of removal of the third insulating layer.
- According to an embodiment, the step of forming a second doped region at least in the remaining space of the trench is preceded by a step of forming spacers on the remaining walls of the trench.
- According to an embodiment, the method further comprises a final step of defining openings of access to the first doped region and to the silicon layer.
- According to an embodiment, the openings of access to the silicon layer and to the first doped region are obtained by performing a first etching of a portion of the second insulating layer and a second etching of the silicon layer and of the semiconductor layer.
- According to an embodiment, the method further comprises a final step of annealing the structure.
- According to an embodiment, the method further comprises a final step of silicidation of the device.
- An embodiment further provides a bipolar transistor formed in a structure comprising a semiconductor layer extending on a semiconductor substrate with an interposed insulating layer, the transistor comprising a collector region defined at the surface of the semiconductor substrate, a buffer region between base and collector defined in an opening formed in the insulating layer opposite to the collector region, and base and emitter regions formed at the surface of the buffer region.
- According to an embodiment, the semiconductor layer has a thickness ranging between 5 and 15 nm and the insulating layer has a thickness ranging between 10 and 50 nm.
- According to an embodiment, the transistor further comprises a region of access to the base made of a single-crystal semiconductor material.
- An embodiment further provides an integrated circuit comprising an association of at least one MOS transistor and of at least one bipolar transistor such as defined hereabove.
- The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
-
FIG. 1 , previously described, illustrates a bipolar transistor formed on a solid substrate by a known method; and -
FIGS. 2 to 18 illustrate results of steps of a method for manufacturing a bipolar transistor according to an embodiment. - For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, the various drawings are not to scale.
- A method for manufacturing a bipolar transistor on a FD-SOI-type substrate is here provided.
FIGS. 2 to 18 illustrate results of steps of such a method. - At a step illustrated in
FIG. 2 , it is started from a structure of FD-SOI type comprising anupper semiconductor layer 40 which extends on asemiconductor substrate 42 with an interposed insulatinglayer 44. Conventionally, such structures have an insulatinglayer 44 with a thickness ranging between 10 and 50 nm, for example, 25 nm, and a fully-depletedupper layer 40 with a thickness ranging between 5 and 15 nm, for example, 10 nm. - At a step illustrated in
FIG. 3 , shallow insulating trenches 46 (STI trenches) which crosssemiconductor layer 40, insulatinglayer 44, and which penetrate in depth intosemiconductor substrate 42 are formed.Trenches 46 extend down to a total depth ranging between 150 and 350 nm, for example, a depth equal to 250 nm. - At a step illustrated in
FIG. 4 , a dopant implantation has been performed throughsemiconductor layer 40 and insulatinglayer 44, to form a heavily-dopedregion 48 at the surface ofsubstrate 42 and in the active area laterally defined by insulatingtrenches 46.Region 48 may extend insubstrate 42 across a thickness ranging between 100 and 300 nm and is doped at a dopant concentration ranging between 5.1018 and 5.1019 at/cm3, for example, on the order of 1019 at/cm3.Region 48 forms the collector region of the bipolar transistor. As an example,region 48 may be obtained by an arsenic implantation if the desired bipolar transistor is of type NPN. - At a step illustrated in
FIG. 5 , a heavily-doped single-crystal silicon layer 50 of the conductivity type desired for the transistor base, for example, heavily doped with boron if an NPN bipolar transistor is desired, has been formed. Single-crystal silicon layer 50 is preferably formed by selective epitaxial growth (SEG), which enables the growth of a heavily-doped single-crystal silicon layer 50 only at the surface oflayer 40, and not at the surface of insulatingtrenches 46.Silicon layer 50 has a thickness ranging between 20 and 60 nm, so that the stack ofsemiconductor layer 40 and oflayer 50 has a total thickness ranging between 25 and 75 nm. - At a step illustrated in
FIG. 6 , a deposition, over the entire structure, of a first insulatinglayer 52 and of a second insulatinglayer 54 has been performed, second insulatinglayer 54 being made of a material different from that of insulatinglayer 52. As an example,first layer 52 may be made of a dielectric material such as tetraethoxysilane (TEOS) having a thickness ranging between 5 and 10 nm, for example, 8 nm, andlayer 54 may be a silicon nitride layer having a thickness ranging between 30 and 80 nm, for example, equal to 50 nm.Layers crystal silicon layer 50, on the walls of this layer, and cover insulatingtrenches 46. - At a step illustrated in
FIG. 7 , afirst trench 60, at the center of the active area, which crosses the stack oflayers layer 44. The etching enabling to definetrench 60 may of course be, in practice, formed in several steps for etching the different materials of the above-mentioned layers. - At a step illustrated in
FIG. 8 , on the walls oftrench 60, an insulatingmaterial 62, for example, made of silicon nitride, has been formed. To formregion 62 on the walls oftrench 60, a nitride layer may be conformally deposited over the entire structure, after which an anisotropic etching is performed to remove the horizontal portions of the layer thus formed.Only regions 62 thus remain on the walls oftrench 60. After, insulatinglayer 44 has been etched through the mask delimited bywalls 62 to form asecond trench 64 which extends through this layer to exposesemiconductor substrate 42, at the level of heavily-dopedregion 48 formed at the surface of this substrate. The etching performed to removelayer 44 is selective over the nitride ofwalls 62 and/or oflayer 54. - At a step illustrated in
FIG. 9 , a single-crystal silicon layer 66 has been grown from heavily-dopedregion 48. The growth oflayer 66 is performed by low-temperature selective epitaxy, which provides a single-crystal silicon layer 66 having a well-controlled profile at the surface ofregion 48. The upper surface oflayer 66 is provided to be flush with the surface of insulatinglayer 44. It should be noted that a slight misalignment between the surfaces oflayers crystal silicon layer 66 forms a buffer area between base and collector. - At a step illustrated in
FIG. 10 , insulatingregions 62 have been etched. To achieve this, the silicon nitride has been selectively etched, this etching also eliminating an upper portion ofnitride layer 54. As an example, the etching may be an isotropic plasma etching. - At a step illustrated in
FIG. 11 , on single-crystal silicon 66 and at the bottom oftrench 60, alayer 70 has been grown.Layer 70 is formed of a stack of several layers, for example, a silicon-germanium layer and a silicon layer. The silicon-germanium layer contains the dopant of the base (boron if the transistor is an NPN transistor). The silicon-germanium layer may also contain carbon atoms to decrease the boron diffusion during subsequent anneals. The growth oflayer 70 advantageously is a selective growth, easy to control, so that the upper surface oflayer 70 extends under the upper surface of single-crystal silicon layer 50, or is flush with the upper surface oflayer 50. - At a step illustrated in
FIG. 12 , conventional in the forming of vertical bipolar transistors,spacers 72 made of an insulating material, for example, an oxide, have been formed at the surface oflayer 70.Spacers 72 extend on the contour of the upper surface oflayer 70 and on the walls oftrench 60. Thus, spacers 72 cover the edges of insulatingregions crystal silicon layer 50. Conventionally, spacers 72 may be formed by deposition of an oxide, followed by the deposition of amorphous silicon over the entire structure. An anisotropic etching of the amorphous silicon, followed by an etching of the material forming the spacers via the mask formed by the amorphous silicon, are then performed. The amorphous silicon may then be removed, which enables to obtain “L” shapes, characteristic of spacers, abovelayer 70. The amorphous silicon may also be kept abovelayer 70, this material mixing afterwards with the material deposited to form the transistor emitter. - At a step illustrated in
FIG. 13 , a region of a heavily-doped material of a conductivity type capable of forming the emitter region of the bipolar transistor has been formed over the entire structure, to fill the space remaining intrench 60. Thus, if an NPN-type bipolar transistor is desired to be formed, this region may be heavily doped with arsenic atoms. An etching is then performed to only leave a heavily-doped emitter-formingportion 74 abovelayer 70, as well as above a portion of insulatingmaterial layer 54. - At a step illustrated in
FIG. 14 , via the mask formed ofportion 74, insulatinglayers trenches 46 are exposed, as well as the surface of heavily-doped single-crystal silicon layer 50. This etching may be of any known type capable of removing insulatinglayers - At a step illustrated in
FIG. 15 , a new etching has been performed, via a mask of adapted shape, to remove portions oflayer 50, oflayer 40, and of insulatinglayer 44 located on the contour of the device, that is, on the contour of the active area, for example in contact with insulatingtrenches 46. Thus, an access to heavily-dopedregion 48 forming the bipolar transistor collector is opened. This step may be carried out in several etch steps, a first step being capable of removing the semiconductor material oflayers layer 44. - At a step illustrated in
FIG. 16 , via the same mask as that used to perform the etching of the step ofFIG. 15 , an implantation of dopants of the same conductivity type as that ofregion 48 has been performed at the surface of the exposed portions ofregion 48. Thus, at the surface of the exposed regions ofregion 48, heavily-dopedregions 78 are formed, for example, at a dopant concentration ranging between 5.1019 and 5.1020 at/cm3, for example, at 1020 at/cm3. - At the step illustrated in
FIG. 17 , the entire structure has been annealed. This anneal allows the diffusion of the doped regions of the different elements of the structure. In particular, this anneal enables to extend heavily-dopedregion 78 formed at the surface oflayer 48, to form a more extended heavily-dopedregion 82 at the surface of this region. This anneal further enables for the dopant atoms of heavily-dopedlayer 50 to partly migrate tosilicon layer 40 in order to form asingle region 80. The obtainedregion 80 forms the region of access to the formed base oflayer 70. The diffusion anneal further developscollector region 74 so that it extends slightly at the surface oflayer 70. The anneal also implies a diffusion of dopant atoms fromemitter 74 to the silicon layer comprised in thestack forming layer 70. - At a step illustrated in
FIG. 18 , a silicidation of the entire device, that is, a nickel deposition followed by a heat treatment and by adapted chemical treatments, has been performed without using a mask, which enables to transform the apparent silicon regions into conductive silicide regions. Thus,region 82 sees its surface covered with asilicide region 84,region 80 sees its surface covered with asilicide region 86, andregion 74 sees its surface covered with asilicide region 88.Regions - Thus, a bipolar transistor is obtained, having its structure extending in depth in the substrate of FD-SOI type, and thus avoiding having too large a thickness, at the surface of the device. The method provided herein is particularly compatible with the forming, in parallel, of MOS transistors on the FD-SOI substrate.
- Further, the material of access to
base 70 ofsemiconductor region 80 advantageously is heavily-doped single-crystal silicon. Thus, the resistance of access to the base is smaller than in the case of prior art where the access to the base was performed by means of a polysilicon region. - The method provided herein also enables to finely control the thicknesses of the emitter region, of the base region, of the buffer region between the collector and the base, and of the collector region, which provides a fine-quality vertical profile of the bipolar transistor, with characteristics that can easily be adjusted.
- Further, the junction surface area between the base and the collector region is decreased, which enables to limit the base-collector junction capacitance with respect to prior art bipolar transistors.
- Specific embodiments of the present disclosure have been described. Various alterations and modifications will occur to those skilled in the art. In particular, it should be noted that the conductivity types provided for the different regions of the bipolar transistor may be inverted to form, instead of an NPN transistor, a PNP transistor.
- Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.
- The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Claims (19)
1. A method for forming a bipolar transistor, the method comprising:
forming a first doped region at a surface of a semiconductor substrate;
forming a semiconductor layer over the surface of the semiconductor substrate;
forming a first insulating layer between the first doped region and the semiconductor layer;
forming a stack that includes a silicon layer and a second insulating layer over the semiconductor layer;
forming an opening through said stack, said semiconductor layer, and the first insulating layer above the first doped region;
forming a single-crystal silicon region in said opening;
forming a silicon-germanium region at a surface of the single-crystal silicon region and in contact with side surfaces of the semiconductor layer and of the silicon layer; and
forming a second doped region in the opening and over the single-crystal silicon region.
2. The method of claim 1 , wherein the semiconductor layer has a thickness ranging approximately between 5 nm and 15 nm and the first insulating layer has a thickness ranging approximately between 10 nm and 50 nm.
3. The method of claim 1 , wherein prior to forming the first doped region, the method comprises forming shallow insulating trenches that extend into the semiconductor layer, the first insulating layer, and the semiconductor substrate.
4. The method of claim 1 , wherein forming the opening comprises etching a first opening having sidewalls through said stack and semiconductor layer, and etching a second opening through the first insulating layer, and before etching the second opening, the method comprises forming a third insulating layer on the walls of the first opening, and after forming a single-crystal silicon region in the opening, the method comprises removing the third insulating layer.
5. The method of claim 1 , wherein prior to forming a second doped region, the method comprises forming spacers on a portion of sidewalls of the opening.
6. The method of claim 1 , further comprising forming openings to access the first doped region and the silicon layer.
7. The method of claim 6 , wherein forming openings to access the silicon layer and the first doped region comprises in a first etch process, etching a portion of the second insulating layer, and in a second etch process, etching the silicon layer and of the semiconductor layer.
8. The method of claim 1 , further comprising annealing the substrate and layers.
9. The method of claim 1 , further comprising exposing the transistor to silicidation .
10. The method of claim 1 , wherein forming the second doped region in the opening and over the single-crystal silicon region comprises filling remaining portions of the opening with the second doped region.
11. A bipolar transistor formed in a structure comprising:
a semiconductor substrate having a first surface:
a semiconductor layer over the first surface of the semiconductor substrate with a first insulating layer located between the semiconductor substrate and the semiconductor layer;
a stack formed over the semiconductor layer, the stack including a silicon layer and a second insulating layer;
a collector region defined at the surface of the semiconductor substrate;
a base region that is in lateral contact with the semiconductor layer;
a buffer region located in an opening in the first insulating layer and between the base region and the collector region; and
an emitter region formed at the surface of said buffer region.
12. The transistor of claim 11 , wherein the semiconductor layer has a thickness ranging between approximately 5 nm and 15 nm and the insulating layer has a thickness ranging between approximately 10 nm and 50 nm.
13. The transistor of claim 11 , the base is made of a single-crystal silicon semiconductor material.
14. The transistor of claim 11 , wherein electrical connection to the base is provided through the at least one silicon layer by a vertical contact.
15. An integrated circuit comprising:
a MOS transistor; and
a bipolar transistor associated with the MOS transistor, the bipolar transistor including:
a semiconductor substrate having a first surface:
a semiconductor layer located over the first surface of the semiconductor substrate with first insulating layer located between the semiconductor substrate and the semiconductor layer;
a stack formed over the semiconductor layer, the stack including a silicon layer and a second insulating layer;
a collector region located at the surface of the semiconductor substrate;
a base region that is formed from a single-crystal semiconductor material; and
a buffer region located in an opening in the first insulating layer and between the base region and the collector region.
16. The integrated circuit of claim 15 , further comprising an emitter region formed at the surface of said buffer region.
17. The integrated circuit of claim 15 , wherein electrical connection to the base is provided through the at least one silicon layer by a vertical contact therebetween.
18. The integrated circuit of claim 15 , further comprising contact pads that provide electrical contact to the collector and the base, respectively.
19. The integrated circuit of claim 15 , wherein the single-crystal semiconductor material is single-crystal silicon.
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US11776995B2 (en) | 2019-08-19 | 2023-10-03 | Stmicroelectronics (Crolles 2) Sas | Device comprising a transistor |
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US11276752B2 (en) * | 2019-08-19 | 2022-03-15 | Stmicroelectronics (Crolles 2) Sas | Method for forming a device comprising a bipolar transistor |
US11710776B2 (en) | 2020-08-24 | 2023-07-25 | Stmicroelectronics (Crolles 2) Sas | Bipolar transistor |
US20230062567A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistor (bjt) and fabricating method thereof |
Also Published As
Publication number | Publication date |
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FR2989514A1 (en) | 2013-10-18 |
US9640631B2 (en) | 2017-05-02 |
US20160099334A1 (en) | 2016-04-07 |
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