US20130234249A1 - Methods and Apparatus for LDMOS Transistors - Google Patents
Methods and Apparatus for LDMOS Transistors Download PDFInfo
- Publication number
- US20130234249A1 US20130234249A1 US13/869,674 US201313869674A US2013234249A1 US 20130234249 A1 US20130234249 A1 US 20130234249A1 US 201313869674 A US201313869674 A US 201313869674A US 2013234249 A1 US2013234249 A1 US 2013234249A1
- Authority
- US
- United States
- Prior art keywords
- region
- gate
- drain
- transistor
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title description 17
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 45
- 239000007943 implant Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- 239000000758 substrate Substances 0.000 description 10
- 238000007667 floating Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
Definitions
- the following disclosure relates to semiconductor devices, and more particularly to transistors, such as lateral double-diffused MOSFET (LDMOS) transistors.
- transistors such as lateral double-diffused MOSFET (LDMOS) transistors.
- LDMOS lateral double-diffused MOSFET
- Voltage regulators such as DC to DC converters
- DC to DC converters are used to provide stable voltage sources for electronic systems. Efficient DC to DC converters are particularly needed for battery management in low power devices, such as laptop notebooks and cellular phones.
- Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC to DC converter.
- a switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency input voltage to generate the output DC voltage.
- the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit.
- An output filter typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage.
- a controller such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
- LDMOS transistors are commonly used in switching regulators as a result of their performance in terms of a tradeoff between their specific on-resistance (R dson ) and drain-to-source breakdown voltage (BV d — s ).
- Conventional LDMOS transistors are typically fabricated having optimized device performance characteristics through a complex process, such as a Bipolar-CMOS (BiCMOS) process or a Bipolar-CMOS-DMOS (BCD) process, that includes one or more process steps that are not compatible with sub-micron CMOS processes typically used by foundries specializing in production of large volumes of digital CMOS devices (e.g, 0.5 ⁇ m DRAM production technologies), as described in greater detail below.
- BiCMOS Bipolar-CMOS
- BCD Bipolar-CMOS-DMOS
- the invention is directed to method of fabricating a transistor having a source, drain, and a gate on a substrate.
- the method includes implanting a first impurity region, forming a gate insulator between a source region and a drain region of the transistor, covering the gate insulator with a conductive material, and implanting, into the drain region of the transistor, a second impurity region.
- the first impurity region has a first volume and a first surface area and is of a first type
- the gate insulator covers a portion of the first surface area
- the second impurity region has a second volume and a second surface area and is of an opposite second impurity type, the second volume impinging the first volume.
- the invention is directed to a transistor.
- the transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region.
- the first impurity region is of a first type
- the second impurity region is of an opposite second type.
- the third impurity region extends from the source region under the gate and is of the first type.
- the fourth impurity region is of the second type
- the fifth impurity region is of the second type
- the fourth impurity region impinges the third impurity region.
- the invention is directed to a transistor.
- the transistor includes a gate with a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, a drain including a fourth impurity region and a fifth impurity region, and a resurf impurity region.
- the first impurity region is of a first type
- the second impurity region is of an opposite second type
- the third impurity region is of the first type
- the fourth impurity region is of the second type
- the fifth impurity region is of the second type
- the resurf impurity region is of the first type.
- the third impurity region extends from the source region under the gate, and the resurf impurity region extends laterally beneath a potion of the fourth impurity region.
- FIG. 1A is a schematic cross-sectional view of an LDMOS transistor.
- FIG. 1B is a schematic cross-sectional view of another implementation of an LDMOS transistor.
- FIG. 2 is a flow diagram of a process for manufacturing an LDMOS transistor.
- FIGS. 3A-3G illustrate a process for manufacturing an LDMOS transistor.
- FIG. 4 is a flow diagram of another implementation of a process for manufacturing an LDMOS transistor.
- FIG. 5 is a schematic cross-sectional view of another implementation of an LDMOS transistor.
- FIG. 6 is a schematic cross-sectional view of another implementation of an LDMOS transistor.
- FIG. 1A shows a schematic cross-sectional view of an LDMOS transistor 100 .
- This LDMOS transistor 100 can be a switch in a switched-mode power supply voltage regulator operable to convert an input DC voltage into a high frequency voltage.
- the LDMOS transistor 100 can be fabricated on a high voltage n-type well (HV n-well) 103 implanted in a p-type substrate 102 .
- An HV n-well implant is typically a deep implant and is generally more lightly doped relative to a CMOS n-well.
- HV n-well 103 can have a retrograded vertical doping profile.
- the LDMOS transistor 100 includes a drain region 104 , a source region 106 , and a gate 108 .
- the gate 108 includes a gate conductor layer 108 b and a gate oxide 108 a .
- the gate can also include an oxide spacer formed around the gate conductor layer 108 b and gate oxide 108 a .
- the drain region 104 includes an n-doped n+ region 110 and an n-doped drain (NDD) 112 .
- NDD n-doped drain
- the n+ region 110 can be self-aligned to the gate (e.g., so that the edge of the n+ region 120 is aligned with the outer edge of the oxide spacer).
- the source region 106 includes an n-doped n+ region 114 and a p-doped p+ region 116 .
- the n+ region 114 of the source 106 can include an N-LDD implanted after creation of the gate oxide but before formation of oxide spacer, and an n+ implanted after formation of the oxide spacer.
- the n+ region 114 of the source 106 includes an N-LDD but the n+ region 110 of the drain 104 does not include an N-LDD.
- a p-doped P-body 118 extends beneath the gate 108 and abuts the NDD 112 .
- a portion of the n+ region 114 can extend partially beneath the gate 108 .
- the interface between the P-body 118 and the NDD 112 can be aligned with the drain-side edge of the gate 108 .
- the interface between the P-body 118 and the NDD 112 can be positioned beneath the gate 108 .
- placement of the interface at the drain-side edge of the gate can be useful for high-frequency applications, whereas placement of the interface nearer to the source-side edge of the gate 108 can be useful for high-power applications.
- the HV n-well 103 , the NDD 112 , and the n+ region 110 in drain region 104 are volumes composed of doped material generated by discrete implant steps. Both the NDD 112 and the HV n-well 103 are generated with implant steps which have a lower concentration of impurities than the implant steps which generate the n+ regions 110 , 114 . Of course, portions at which these volumes overlap have a higher doping concentration than the individual volumes separately. A portion 120 that contains the overlapping volumes of the n+ region 110 , the NDD 112 , and the HV n-well 103 has the highest doping concentration of all the overlapping volume portions.
- the n+ region 114 , the p+ region 116 , and the P-body 118 in source region 106 are volumes ( 126 , 128 , and 130 , respectively) composed of doped material.
- FIG. 2 illustrates a process 200 of fabricating a semiconductor device, including an LDMOS transistor. Conventional CMOS transistors can also be fabricated through process 200 .
- the process 100 begins with forming a substrate (step 202 ).
- the substrate can be a p type substrate or an n type substrate.
- a semiconductor layer consisting of a p-type substrate 102 is formed.
- an HV n-well 103 for the LDMOS transistor is implanted into the substrate (step 204 ).
- an n-well for a the PMOS transistor with floating operation capability, or NMOS transistor with floating operation capability can be implanted.
- unillustrated CMOS n-wells for conventional PMOS transistors and unillustrated CMOS p-wells for conventional NMOS transistors can be implanted into the substrate (step 206 ).
- a non self-aligned P-body 118 for the drain region of the LDMOS transistor is implanted (step 208 ). As shown in FIG. 3C , the P-body 118 is implanted into the HV n well 103 . During step 206 , a P-body can also be implanted for the NMOS transistor with floating operation capability.
- the gate oxide for each of the LDMOS transistor is formed (step 210 ).
- the gate oxide for other components such as the PMOS transistor with floating operation capability, and the NMOS transistor with floating operation capability, and the conventional CMOS transistors can also be formed.
- the gate oxide for the LDMOS transistor can be formed at the same time as a gate oxide of the conventional CMOS transistors.
- the LDMOS transistor can, therefore, have a similar threshold voltage and gate oxide thickness and as the conventional CMOS transistors, and can be driven directly by conventional CMOS logic circuits.
- the gate oxide of the LDMOS transistor can formed at a different time than the gate oxide of the conventional CMOS transistors to allow the LDMOS transistor to be implemented with a dedicated thick gate oxide.
- the LDMOS transistor When implemented with a thick gate oxide, the LDMOS transistor allows for higher gate drive in applications where a lower voltage power supply may not be readily available. This flexibility allows for optimization of the LDMOS transistor depending on specific requirements of a power delivery application, such as efficiency targets at a particular frequency of operation.
- the LDMOS gate oxide 108 a is formed on a surface 302 of the substrate such that drain-side edge of the gate is aligned with an inner edge 304 of the P-body 118 , or such that the gate overlies the inner edge 304 of the P-body 118 . Exact alignment is not required, as the final position of the interface between the P-body and NDD will be determined by the NDD implant step.
- a polysilicon layer is deposited over the gate oxide (step 210 ). As shown in FIG. 3E , a polysilicon layer 108 a is deposited over the LDMOS gate oxide 108 b . A polysilicon layer can also be deposited over the conventional PMOS and NMOS gates.
- a shallow drain is implanted and diffused into the drain of the LDMOS transistor (step 114 ).
- the shallow drain can be implanted after the LDMOS gate is formed so that the shallow drain is self aligned with respect to the LDMOS gate.
- the shallow drain can be implanted through a LAT implant or a normal angle tilt implant.
- the shallow drain is the n-doped drain NDD 112 .
- the n-doped drain NDD 112 is implanted such that the NDD abuts the P-body 118 .
- the distance 307 by which the NDD extends under the gate 108 can be controlled.
- the spacing 307 can be sized such that that the NDD 112 implant extends a predetermined distance under the LDMOS gate.
- the doping concentration of NDD is can be greater than the P-body so that the NDD implant extends into the P-body to define the channel.
- the n+ regions and p+ regions of the LDMOS transistor, the PMOS transistor with floating operation capability, and the NMOS transistor with floating operation capability, and the conventional CMOS transistors, are implanted (step 216 ).
- a p+ region 116 is implanted at the source of the LDMOS transistor.
- the LDMOS transistor also include an n+ region 110 implanted at the drain and an n+ region 114 implanted at the source.
- the process 200 provides several potential advantages.
- the P-body of the LDMOS transistor is implanted and diffused prior to formation of the gate oxide of the conventional CMOS transistors.
- the thermal cycle associated with the P-body implant therefore does not substantially affect the fixed thermal budget associated with sub-micron CMOS process steps (e.g., process step 206 ).
- the placement of the interface between the P-body and the NDD can be tightly controlled due to the self-alignment of the NDD relative to the gate.
- the process described above forms the gate 108 after the P-body 118 is implanted, it is also possible for the P-body 118 to be implanted after formation of the gate 108 , so that the P-body is self-aligned relative to the gate.
- the CMOS gates can be formed after the P-body implant.
- the CMOS gates can be formed at the same time as the LDMOS gate.
- the NDD 112 can be shallower than the P-body 118 .
- the NDD 112 ′ is driven beneath the gate 108 and into the P-body 118 ′ such that the P-body has a portion 502 that extends laterally beneath the NDD 112 ′.
- This portion 502 can provide an implanted resurf region that reduces the peak surface electric field, particularly near the drain-side edge of the gate.
- the a p-resurf implant is performed to produce a p-resurf region 602 that extends below NDD 112 .
- the p-resurf region can extend over just the source and gate as illustrated, or it can extend across the entire n-well.
- the p-resurf region can be spaced from the P-body and NDD, or in contact with one or both of the P-body and NDD. This portion p-resurf region 602 can reduce the peak surface electric field, particularly near the drain-side edge of the gate.
- Reduction of the peak surface electric field can reduce hot carrier degradation, thus permitting the devices to be scaled smaller while maintaining device lifetime.
Abstract
An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
Description
- This application claims priority to U.S. application Ser. No. 60/700,395, filed on Jul. 18, 2005.
- The following disclosure relates to semiconductor devices, and more particularly to transistors, such as lateral double-diffused MOSFET (LDMOS) transistors.
- Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC to DC converters are particularly needed for battery management in low power devices, such as laptop notebooks and cellular phones. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC to DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency input voltage to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
- LDMOS transistors are commonly used in switching regulators as a result of their performance in terms of a tradeoff between their specific on-resistance (Rdson) and drain-to-source breakdown voltage (BVd
— s). Conventional LDMOS transistors are typically fabricated having optimized device performance characteristics through a complex process, such as a Bipolar-CMOS (BiCMOS) process or a Bipolar-CMOS-DMOS (BCD) process, that includes one or more process steps that are not compatible with sub-micron CMOS processes typically used by foundries specializing in production of large volumes of digital CMOS devices (e.g, 0.5 μm DRAM production technologies), as described in greater detail below. As a result, conventional LDMOS transistors are, therefore, not typically fabricated at such foundries. - In one aspect, the invention is directed to method of fabricating a transistor having a source, drain, and a gate on a substrate. The method includes implanting a first impurity region, forming a gate insulator between a source region and a drain region of the transistor, covering the gate insulator with a conductive material, and implanting, into the drain region of the transistor, a second impurity region. The first impurity region has a first volume and a first surface area and is of a first type, the gate insulator covers a portion of the first surface area, and the second impurity region has a second volume and a second surface area and is of an opposite second impurity type, the second volume impinging the first volume.
- In another aspect, the invention is directed to a transistor. The transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
- In another aspect, the invention is directed to a transistor. The transistor includes a gate with a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, a drain including a fourth impurity region and a fifth impurity region, and a resurf impurity region. The first impurity region is of a first type, the second impurity region is of an opposite second type, the third impurity region is of the first type, the fourth impurity region is of the second type, the fifth impurity region is of the second type, and the resurf impurity region is of the first type. The third impurity region extends from the source region under the gate, and the resurf impurity region extends laterally beneath a potion of the fourth impurity region.
- The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
-
FIG. 1A is a schematic cross-sectional view of an LDMOS transistor. -
FIG. 1B is a schematic cross-sectional view of another implementation of an LDMOS transistor. -
FIG. 2 is a flow diagram of a process for manufacturing an LDMOS transistor. -
FIGS. 3A-3G illustrate a process for manufacturing an LDMOS transistor. -
FIG. 4 is a flow diagram of another implementation of a process for manufacturing an LDMOS transistor. -
FIG. 5 is a schematic cross-sectional view of another implementation of an LDMOS transistor. -
FIG. 6 is a schematic cross-sectional view of another implementation of an LDMOS transistor. - Like reference symbols in the various drawings indicate like elements.
-
FIG. 1A shows a schematic cross-sectional view of anLDMOS transistor 100. ThisLDMOS transistor 100 can be a switch in a switched-mode power supply voltage regulator operable to convert an input DC voltage into a high frequency voltage. - The
LDMOS transistor 100 can be fabricated on a high voltage n-type well (HV n-well) 103 implanted in a p-type substrate 102. An HV n-well implant is typically a deep implant and is generally more lightly doped relative to a CMOS n-well. HV n-well 103 can have a retrograded vertical doping profile. - The
LDMOS transistor 100 includes adrain region 104, asource region 106, and agate 108. Thegate 108 includes agate conductor layer 108 b and agate oxide 108 a. The gate can also include an oxide spacer formed around thegate conductor layer 108 b andgate oxide 108 a. Thedrain region 104 includes an n-doped n+ region 110 and an n-doped drain (NDD) 112. Although illustrated as spaced from thegate oxide 108 a, then+ region 110 can be self-aligned to the gate (e.g., so that the edge of then+ region 120 is aligned with the outer edge of the oxide spacer). Thesource region 106 includes an n-doped n+ region 114 and a p-dopedp+ region 116. Then+ region 114 of thesource 106 can include an N-LDD implanted after creation of the gate oxide but before formation of oxide spacer, and an n+ implanted after formation of the oxide spacer. In one implementation, then+ region 114 of thesource 106 includes an N-LDD but then+ region 110 of thedrain 104 does not include an N-LDD. - A p-doped P-
body 118, at least a portion of which can be considered part of thesource region 106, extends beneath thegate 108 and abuts the NDD 112. A portion of then+ region 114 can extend partially beneath thegate 108. The interface between the P-body 118 and the NDD 112 can be aligned with the drain-side edge of thegate 108. Alternatively, as shown inFIG. 1B , the interface between the P-body 118 and the NDD 112 can be positioned beneath thegate 108. In general, placement of the interface at the drain-side edge of the gate can be useful for high-frequency applications, whereas placement of the interface nearer to the source-side edge of thegate 108 can be useful for high-power applications. - The HV n-
well 103, the NDD 112, and then+ region 110 indrain region 104 are volumes composed of doped material generated by discrete implant steps. Both theNDD 112 and the HV n-well 103 are generated with implant steps which have a lower concentration of impurities than the implant steps which generate then+ regions portion 120 that contains the overlapping volumes of then+ region 110, theNDD 112, and the HV n-well 103 has the highest doping concentration of all the overlapping volume portions. Aportion 122 that contains the overlapping volumes of theNDD 112 and the HV n-well 103, but not then+ region 110, has a lower doping concentration thanportion 120. Aportion 124 that only includes the HV n-well 103 has a lower doping concentration than eitherportions n+ region 114, thep+ region 116, and the P-body 118 insource region 106 are volumes (126, 128, and 130, respectively) composed of doped material. -
FIG. 2 illustrates aprocess 200 of fabricating a semiconductor device, including an LDMOS transistor. Conventional CMOS transistors can also be fabricated throughprocess 200. - The
process 100 begins with forming a substrate (step 202). The substrate can be a p type substrate or an n type substrate. Referring to the example ofFIG. 3A , a semiconductor layer consisting of a p-type substrate 102 is formed. As shown inFIG. 3B , an HV n-well 103 for the LDMOS transistor is implanted into the substrate (step 204). In addition, an n-well for a the PMOS transistor with floating operation capability, or NMOS transistor with floating operation capability can be implanted. Optionally, unillustrated CMOS n-wells for conventional PMOS transistors and unillustrated CMOS p-wells for conventional NMOS transistors can be implanted into the substrate (step 206). A non self-aligned P-body 118 for the drain region of the LDMOS transistor is implanted (step 208). As shown inFIG. 3C , the P-body 118 is implanted into the HV n well 103. Duringstep 206, a P-body can also be implanted for the NMOS transistor with floating operation capability. - The gate oxide for each of the LDMOS transistor is formed (step 210). The gate oxide for other components, such as the PMOS transistor with floating operation capability, and the NMOS transistor with floating operation capability, and the conventional CMOS transistors can also be formed. The gate oxide for the LDMOS transistor can be formed at the same time as a gate oxide of the conventional CMOS transistors. The LDMOS transistor can, therefore, have a similar threshold voltage and gate oxide thickness and as the conventional CMOS transistors, and can be driven directly by conventional CMOS logic circuits. Alternatively, the gate oxide of the LDMOS transistor can formed at a different time than the gate oxide of the conventional CMOS transistors to allow the LDMOS transistor to be implemented with a dedicated thick gate oxide. When implemented with a thick gate oxide, the LDMOS transistor allows for higher gate drive in applications where a lower voltage power supply may not be readily available. This flexibility allows for optimization of the LDMOS transistor depending on specific requirements of a power delivery application, such as efficiency targets at a particular frequency of operation.
- Referring to the example of
FIG. 3D , theLDMOS gate oxide 108 a is formed on asurface 302 of the substrate such that drain-side edge of the gate is aligned with aninner edge 304 of the P-body 118, or such that the gate overlies theinner edge 304 of the P-body 118. Exact alignment is not required, as the final position of the interface between the P-body and NDD will be determined by the NDD implant step. A polysilicon layer is deposited over the gate oxide (step 210). As shown inFIG. 3E , apolysilicon layer 108 a is deposited over theLDMOS gate oxide 108 b. A polysilicon layer can also be deposited over the conventional PMOS and NMOS gates. - A shallow drain is implanted and diffused into the drain of the LDMOS transistor (step 114). The shallow drain can be implanted after the LDMOS gate is formed so that the shallow drain is self aligned with respect to the LDMOS gate. The shallow drain can be implanted through a LAT implant or a normal angle tilt implant. In the example of
FIG. 3F , the shallow drain is the n-dopeddrain NDD 112. - The n-doped
drain NDD 112 is implanted such that the NDD abuts the P-body 118. In addition, by controlling the diffusion process, thedistance 307 by which the NDD extends under thegate 108 can be controlled. Thus, the position of the interface between the NDD and the P-body can be controlled in an aligned fashion relative to the drain-side edge of thegate 108. The spacing 307 can be sized such that that theNDD 112 implant extends a predetermined distance under the LDMOS gate. The doping concentration of NDD is can be greater than the P-body so that the NDD implant extends into the P-body to define the channel. - The n+ regions and p+ regions of the LDMOS transistor, the PMOS transistor with floating operation capability, and the NMOS transistor with floating operation capability, and the conventional CMOS transistors, are implanted (step 216). A
p+ region 116 is implanted at the source of the LDMOS transistor. The LDMOS transistor also include ann+ region 110 implanted at the drain and ann+ region 114 implanted at the source. - The
process 200 provides several potential advantages. First, the P-body of the LDMOS transistor is implanted and diffused prior to formation of the gate oxide of the conventional CMOS transistors. The thermal cycle associated with the P-body implant therefore does not substantially affect the fixed thermal budget associated with sub-micron CMOS process steps (e.g., process step 206). Second, the placement of the interface between the P-body and the NDD can be tightly controlled due to the self-alignment of the NDD relative to the gate. - Referring to
FIG. 4 , although the process described above forms thegate 108 after the P-body 118 is implanted, it is also possible for the P-body 118 to be implanted after formation of thegate 108, so that the P-body is self-aligned relative to the gate. In this case, the CMOS gates can be formed after the P-body implant. Alternatively, if the thermal budget permits, the CMOS gates can be formed at the same time as the LDMOS gate. - The
NDD 112 can be shallower than the P-body 118. Referring toFIG. 5 , in another implementation, during the NDD implant step, theNDD 112′ is driven beneath thegate 108 and into the P-body 118′ such that the P-body has aportion 502 that extends laterally beneath theNDD 112′. Thisportion 502 can provide an implanted resurf region that reduces the peak surface electric field, particularly near the drain-side edge of the gate. - Referring to
FIG. 6 , in another implementation, the a p-resurf implant is performed to produce a p-resurf region 602 that extends belowNDD 112. The p-resurf region the can extend over just the source and gate as illustrated, or it can extend across the entire n-well. In addition, the p-resurf region can be spaced from the P-body and NDD, or in contact with one or both of the P-body and NDD. This portion p-resurf region 602 can reduce the peak surface electric field, particularly near the drain-side edge of the gate. - Reduction of the peak surface electric field can reduce hot carrier degradation, thus permitting the devices to be scaled smaller while maintaining device lifetime.
- A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.
Claims (12)
1-18. (canceled)
19. A transistor comprising:
a gate including a conductive material over an insulator material;
a source including a p+ region and an n+ region, the p+ region being on a side of the n+ region farther from the gate;
a p-body abutting the p+ region and the n+ region and extending from the source region under the gate, the p-body implanted in an high-voltage (HV) n-well and has a drain-side edge aligned with a drain-side edge of the gate; and
a drain including an n-doped drain region and an n+ region surrounded by the n-doped drain region, the n+ region of the drain having a higher concentration than the n-doped drain region, the n-doped drain region impinging upon the p-body, is shallower than the p-body, and extends above a portion of the p-body.
20. The transistor of claim 9, wherein the p+ region and the n+ region of the source are within the p-body.
21. The transistor of claim 10, wherein the p-body is deeper than the p+ region and the n+ region.
22. The transistor of claim 9, wherein the n+ region of the drain is within the n-doped drain region.
23. The transistor of claim 12, wherein the n-doped drain region is deeper than the n+ region of the drain.
24. The transistor of claim 9, wherein the gate extends over a drain-side edge of the p-body.
25. A transistor comprising:
a gate including a conductive material over an insulator material;
a source including a p+ region and an n+ region, the p+ region being on a side of the n+ region farther from the gate;
a p-body abutting the p+ region and the n+ region and extending from the source region under the gate; and
a drain including an n-doped drain region and an n+ region surrounded by the n-doped drain region, the n-doped drain region impinging upon the p-body beneath the gate, is shallower than the p-body, and extends above a portion of the p-body.
26. The transistor of claim 15, wherein a drain side edge of the p-body aligns with a drain-side edge of the gate, and the n-doped drain region has a source-side edge that extends past the drain-side edge of the gate.
27. The transistor of claim 15, wherein the n+ region of the source has a portion that extends beneath the gate.
28. The transistor of claim 15, wherein the n+ region of the drain is within the n-doped drain region.
29. The transistor of claim 15, wherein the p-body is implanted in an high-voltage (HV) n-well.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/869,674 US20130234249A1 (en) | 2005-07-18 | 2013-04-24 | Methods and Apparatus for LDMOS Transistors |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US70039505P | 2005-07-18 | 2005-07-18 | |
US11/488,378 US7868378B1 (en) | 2005-07-18 | 2006-07-17 | Methods and apparatus for LDMOS transistors |
US12/987,905 US8431450B1 (en) | 2005-07-18 | 2011-01-10 | Methods and apparatus for LDMOS transistors |
US13/869,674 US20130234249A1 (en) | 2005-07-18 | 2013-04-24 | Methods and Apparatus for LDMOS Transistors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/987,905 Continuation US8431450B1 (en) | 2005-07-18 | 2011-01-10 | Methods and apparatus for LDMOS transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
US20130234249A1 true US20130234249A1 (en) | 2013-09-12 |
Family
ID=43415632
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/488,378 Active 2027-08-08 US7868378B1 (en) | 2005-07-18 | 2006-07-17 | Methods and apparatus for LDMOS transistors |
US12/987,905 Active US8431450B1 (en) | 2005-07-18 | 2011-01-10 | Methods and apparatus for LDMOS transistors |
US13/869,674 Abandoned US20130234249A1 (en) | 2005-07-18 | 2013-04-24 | Methods and Apparatus for LDMOS Transistors |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/488,378 Active 2027-08-08 US7868378B1 (en) | 2005-07-18 | 2006-07-17 | Methods and apparatus for LDMOS transistors |
US12/987,905 Active US8431450B1 (en) | 2005-07-18 | 2011-01-10 | Methods and apparatus for LDMOS transistors |
Country Status (1)
Country | Link |
---|---|
US (3) | US7868378B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130087828A1 (en) * | 2010-06-21 | 2013-04-11 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing same |
US20180337250A1 (en) * | 2017-05-17 | 2018-11-22 | Nxp B.V. | Method of making a semiconductor switch device |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7868378B1 (en) * | 2005-07-18 | 2011-01-11 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
US7851314B2 (en) * | 2008-04-30 | 2010-12-14 | Alpha And Omega Semiconductor Incorporated | Short channel lateral MOSFET and method |
TWI487105B (en) * | 2009-12-16 | 2015-06-01 | Macronix Int Co Ltd | Lateral power mosfet structure and method of manufacture |
CN103782390B (en) | 2011-08-11 | 2016-11-16 | 沃特拉半导体公司 | Vertical gate radio frequency lateral diffusion metal-oxide half field effect transistor (LDMOS) device |
CN102263125B (en) * | 2011-08-24 | 2013-04-03 | 苏州市职业大学 | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides |
WO2014044748A1 (en) * | 2012-09-21 | 2014-03-27 | Elmos Semiconductor Ag | Nmos transistor and method for producing it |
US10229993B2 (en) | 2016-03-14 | 2019-03-12 | Maxin Integrated Products, Inc. | LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods |
US10276679B2 (en) * | 2017-05-30 | 2019-04-30 | Vanguard International Semiconductor Corporation | Semiconductor device and method for manufacturing the same |
CN108682689B (en) | 2018-05-25 | 2023-12-01 | 矽力杰半导体技术(杭州)有限公司 | Laterally diffused metal oxide semiconductor structure and method of forming the same |
CN116759455A (en) * | 2018-05-25 | 2023-09-15 | 矽力杰半导体技术(杭州)有限公司 | Laterally diffused metal oxide semiconductor device and method of manufacturing the same |
CN108807543B (en) * | 2018-05-25 | 2023-12-15 | 矽力杰半导体技术(杭州)有限公司 | Laterally diffused metal oxide semiconductor device and method of manufacturing the same |
CN108598156A (en) | 2018-05-29 | 2018-09-28 | 矽力杰半导体技术(杭州)有限公司 | Ldmos transistor and its manufacturing method |
CN108847423B (en) | 2018-05-30 | 2022-10-21 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor device and method for manufacturing the same |
CN109346467A (en) | 2018-08-17 | 2019-02-15 | 矽力杰半导体技术(杭州)有限公司 | The manufacturing method of semiconductor structure, driving chip and semiconductor structure |
CN109346466B (en) | 2018-08-17 | 2020-10-16 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor structure and driving chip |
CN109326594A (en) | 2018-08-20 | 2019-02-12 | 矽力杰半导体技术(杭州)有限公司 | A kind of semiconductor wafer |
CN111668186A (en) | 2020-06-08 | 2020-09-15 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor device and method for manufacturing the same |
CN112234094B (en) | 2020-09-29 | 2022-07-29 | 矽力杰半导体技术(杭州)有限公司 | Metal oxide semiconductor device and method for manufacturing the same |
CN113823694B (en) * | 2021-08-19 | 2023-10-31 | 电子科技大学 | Lateral power semiconductor device integrated with submicron super junction and manufacturing method thereof |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5306652A (en) * | 1991-12-30 | 1994-04-26 | Texas Instruments Incorporated | Lateral double diffused insulated gate field effect transistor fabrication process |
US5517046A (en) * | 1993-11-19 | 1996-05-14 | Micrel, Incorporated | High voltage lateral DMOS device with enhanced drift region |
KR100468342B1 (en) * | 1996-05-15 | 2005-06-02 | 텍사스 인스트루먼츠 인코포레이티드 | LDMOS device with self-aligned RESURF region and method of manufacturing the same |
KR100244282B1 (en) * | 1997-08-25 | 2000-02-01 | 김영환 | Transistor for high voltage and manufactruing method thereof |
US6211552B1 (en) * | 1999-05-27 | 2001-04-03 | Texas Instruments Incorporated | Resurf LDMOS device with deep drain region |
JP3602751B2 (en) * | 1999-09-28 | 2004-12-15 | 株式会社東芝 | High voltage semiconductor device |
JP3723410B2 (en) * | 2000-04-13 | 2005-12-07 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
US6593621B2 (en) * | 2001-08-23 | 2003-07-15 | Micrel, Inc. | LDMOS field effect transistor with improved ruggedness in narrow curved areas |
KR100867574B1 (en) * | 2002-05-09 | 2008-11-10 | 페어차일드코리아반도체 주식회사 | Power device and method for manufacturing the same |
KR100958421B1 (en) * | 2002-09-14 | 2010-05-18 | 페어차일드코리아반도체 주식회사 | Power device and method for manufacturing the same |
US6825531B1 (en) * | 2003-07-11 | 2004-11-30 | Micrel, Incorporated | Lateral DMOS transistor with a self-aligned drain region |
KR20060064659A (en) * | 2003-08-27 | 2006-06-13 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Electronic device comprising an ldmos transistor |
US6927453B2 (en) * | 2003-09-30 | 2005-08-09 | Agere Systems Inc. | Metal-oxide-semiconductor device including a buried lightly-doped drain region |
SE0303106D0 (en) * | 2003-11-21 | 2003-11-21 | Infineon Technologies Ag | Ldmos transistor device, integrated circuit, and fabrication method thereof |
US7282410B2 (en) * | 2004-07-21 | 2007-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flash memory process with high voltage LDMOS embedded |
US7262476B2 (en) * | 2004-11-30 | 2007-08-28 | Agere Systems Inc. | Semiconductor device having improved power density |
US7868378B1 (en) * | 2005-07-18 | 2011-01-11 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
-
2006
- 2006-07-17 US US11/488,378 patent/US7868378B1/en active Active
-
2011
- 2011-01-10 US US12/987,905 patent/US8431450B1/en active Active
-
2013
- 2013-04-24 US US13/869,674 patent/US20130234249A1/en not_active Abandoned
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130087828A1 (en) * | 2010-06-21 | 2013-04-11 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing same |
US11114527B2 (en) | 2010-06-21 | 2021-09-07 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing same |
US20180337250A1 (en) * | 2017-05-17 | 2018-11-22 | Nxp B.V. | Method of making a semiconductor switch device |
US10431666B2 (en) * | 2017-05-17 | 2019-10-01 | Nxp B.V. | Method of making a semiconductor switch device |
Also Published As
Publication number | Publication date |
---|---|
US7868378B1 (en) | 2011-01-11 |
US8431450B1 (en) | 2013-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7868378B1 (en) | Methods and apparatus for LDMOS transistors | |
US7405117B2 (en) | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor | |
US8455340B2 (en) | Method of fabricating heavily doped region in double-diffused source MOSFET (LDMOS) transistor | |
US8405148B1 (en) | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor | |
US8071436B2 (en) | Method of fabricating a semiconductor device having a lateral double diffused MOSFET transistor with a lightly doped source and CMOS transistor | |
US8994106B2 (en) | Lateral double-diffused MOSFET | |
US7465621B1 (en) | Method of fabricating a switching regulator with a high-side p-type device | |
US7468537B2 (en) | Drain extended PMOS transistors and methods for making the same | |
US8936980B1 (en) | Dual gate lateral double-diffused MOSFET (LDMOS) transistor | |
US7344947B2 (en) | Methods of performance improvement of HVMOS devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: VOLTERRA SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZUNIGA, MARCO A.;YOU, BUDONG;LU, YANG;REEL/FRAME:031138/0148 Effective date: 20061114 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |