US20130183808A1 - Memory device and method of fabricating the same - Google Patents
Memory device and method of fabricating the same Download PDFInfo
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- US20130183808A1 US20130183808A1 US13/784,346 US201313784346A US2013183808A1 US 20130183808 A1 US20130183808 A1 US 20130183808A1 US 201313784346 A US201313784346 A US 201313784346A US 2013183808 A1 US2013183808 A1 US 2013183808A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Abstract
A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
Description
- This is a divisional application of U.S. application Ser. No. 12/945,423, filed on Nov. 12, 2010, the entirety of which is herein incorporated by reference.
- 1. Technical Field
- The present invention relates to a memory device, and more particularly relates to a memory device with a trench cell structure and a method of fabricating the same.
- 2. Background
- Due to their structural simplicity, DRAMs (dynamic random access memories) can provide more memory per unit chip area than other types of memories such as static random access memories. A DRAM is comprised of a plurality of DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line is asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, the data to be written is provided on the bit line while the word line is asserted.
- To satisfy the demand for greater memory storage, there is a need for DRAM memory cells of reduced size. DRAM memory cell size can be reduced in several ways. One way is to reduce the minimum feature size of a DRAM memory cell through the advances in process technology. Another way to reduce the size of a DRAM memory cell is by designing a memory cell having a smaller feature size. For example, many DRAM chips on the market today have a memory cell size of 6F2, where F stands for the photolithographic minimum feature width.
- However, the decrease of the size of memory cells results in some issues. The disturbance between memory cells or between word lines may easily occur and the resistance of the word line increases due to the decrease of its cross-sectional area.
- One conventional DRAM device includes an array having a plurality of access transistors. A word line functioning as a gate extends from one side of the array to an opposite side of the array such that each transistor can operate as a double gate transistor. Due to the resistance of the word line, the voltage supplied to the word line drops along the word line. Consequently, two corresponding locations on the opposite sides of the array have significant voltage drop, resulting in problematic operation of the corresponding access transistor.
- In view of the above problems, the present invention provides an embodied memory device comprising a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
- The present invention further provides a method of fabricating a memory device comprising the steps of: filling a first dielectric material in a plurality of deep trenches and shallow trenches to separately form a plurality of deep isolations and a plurality of shallow isolations, wherein each shallow trench is formed between two adjacent ones of the plurality of the deep trenches; forming a plurality of depressions transverse to the deep isolations, wherein two adjacent ones of the plurality of depressions define a mesa structure, and the depression is wider than the mesa structure; filling the plurality of depressions with a second dielectric material; removing a portion of the first dielectric material from the shallow trenches and the deep trenches and a portion of the second dielectric material from the depressions; forming a conductive layer in the shallow trenches, the deep trenches and the depressions; and removing a portion of the conductive layer in the depression to form two word lines
- The foregoing has outlined rather broadly the features of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features of the invention will be described hereinafter, and form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
- The objectives of the present invention will become apparent upon reading the following description and upon reference to the accompanying drawings in which:
-
FIG. 1 is a perspective view of a memory device according to one embodiment of the present invention; and -
FIGS. 2 through 19 are cross-sectional views showing process steps for essentially forming a memory device according to one embodiment of the present invention. -
FIG. 1 is a perspective view of amemory device 1 according to one embodiment of the present invention. Referring toFIG. 1 , thememory device 1 comprises amesa structure 11 in which at least one pair of source/drain regions 101, at least oneisolation pillar 102 corresponding to the at least one pair of source/drain regions 101 and at least onechannel base region 103 corresponding to the at least one pair of source/drain regions 101 are formed. Each pair of source/drain regions 101 partially defines a top of themesa structure 11, are separated by the at least oneisolation pillar 102, and are connected by the at least onechannel base region 103 at their bottoms to provide channel current flow. In addition, theisolation pillar 102 can be made of any suitable dielectric material such as silicon oxide. - A
word line 12 is configured to extend from one side to an opposite side of themesa structure 11 as shown inFIG. 1 , around an end portion of themesa structure 11, and has twolinear sections opposite side surfaces 111 of themesa structure 11, separated from themesa structure 11 by oxide layers, and disposed adjacent to thechannel base region 103 for forming gates so as to address thechannel base region 103. Theword line 12 can be formed of, for example, titanium nitride or any suitable conductive material. In addition, theword line 12 may include at least oneinterconnecting portion 123 penetrating through themesa structure 11, connecting the twolinear sections linear sections mesa structure 11. - The at least one interconnecting
portion 123 is isolated from the at least one pair of source/drain regions 101 and the at least onechannel base region 103 by, for example, silicon dioxide. The at least one interconnectingportion 123 can penetrate at any suitable location. In one embodiment, the at least one interconnectingportion 123 penetrates through oneisolation pillar 102. Further, eachisolation pillar 102 can be formed within atrough 112 formed in themesa structure 11, and, in one embodiment, the at least one interconnectingportion 123 can be adjacent the bottom of thetrough 112. - A plurality of
isolation structures 13 can be formed in themesa structure 11. Each pair of source/drain regions 101 and their correspondingchannel base region 103 are defined by two correspondingadjacent isolation structures 13. Theisolation structures 13 can also be formed using any suitable dielectric material such as silicon oxide. In one embodiment, the at least one interconnectingportion 123 can penetrate through theisolation structure 13. - As shown in
FIG. 1 , eachword line 12 includes a plurality of interconnectingportions 123. These interconnectingportions 123 are arranged along the extension direction of the word line, penetrating themesa structure 11 to connect thelinear sections portions 123 correspondingly penetrate through theisolation structures 13 and theisolation pillars 102. - As illustrate in
FIG. 1 , one of the pair of source/drain regions 101 of the transistor of one embodiment of the present invention can connect acapacitor 14, and another of the pair of source/drain regions 101 can connect acorresponding bit line 17 for performing reading or writing operations. A finished memory cell in one embodiment of the present invention can have an area of approximately 4F2 or less, where F is the minimum lithographic feature size. - The transistor of one embodiment of the present invention can be an n-channel device, which is built on a layer of a second conductivity type (n−) on a substrate of a first conductivity type (p) and has source/
drain regions 101 of a second conductivity type (n+) and achannel base region 103 of a first conductivity type (p−). If a p-channel device is desired, the doping types and levels of the elements of the transistor can be adjusted, as is well known in the art. -
Adjacent mesa structures 11 are separated by adepression 15 that can be filled with dielectric material to form anisolation 16, isolating thelinear sections word lines 12 from each other in thesame depression 15. In the present embodiment, thelinear sections depression 15 overlie on therespective side surfaces 111 of themesa structure 11, separated from each other to the greatest possible extent so that theword lines 12 can be suitably isolated from one another so as to avoid the mutual disturbance. In addition, theword line 12 is oriented vertically such that it can be formed wider to lower its resistance while not being limited by the confined area of the memory cell. In one embodiment, the plurality ofmesa structures 11 are arranged in a direction and the length of themesa structure 11 measured along the direction is approximately one-third the spaced apart distance of two adjacent themesa structures 11. - The
memory device 1 is fabricated through processes described as follows, illustrated byFIGS. 2 through 19 . Referring toFIG. 2 , asubstrate 30 is initially processed to include alayer 301 of a second conductivity type (n−), alayer 302 of a first conductivity type (p−) on thelayer 301, and alayer 303 of a second conductivity type (n+) on thelayer 302. Thesubstrate 30 is a silicon substrate in the present embodiment, but can alternatively be any other type of substrate for different purposes. Thesubstrate 30 can be undoped or doped, but a p+ type doped wafer is preferred. - An
oxide layer 31, anitride layer 32, apolysilicon layer 33, a tetraethyl orthosilicate (TEOS)layer 34 and aphotoresist layer 35 are deposited on the top of thesubstrate 30 by suitable means such as a chemical deposition process or a spin-on process. Thephotoresist layer 35 is then patterned to define a line and space pattern by photolithographic techniques. In one embodiment, the line and space pattern includes a plurality of lines spaced apart from each other by a distance, which can be the photolithographic minimum feature width F. - As shown in
FIG. 3 , theTEOS layer 34 is etched to form a line-and-space pattern therein with the patternedphotoresist layer 35 acting as an etching mask. Then, after thephotoresist layer 35 is removed, the etchedTEOS layer 34 is used as a hard mask to etch thepolysilicon layer 33 to form a line-and-space pattern therein. Thereafter,sidewall spacers 36 made of silicon oxide are formed on the sidewalls of the lines of the patternedpolysilicon layer 33 andTEOS layer 34. The sidewall spacers 36 are formed to an extent that twosidewall spacers 36 facing each other are spaced by a distance equal to one-half of the photolithographic minimum feature width F. Next, a dry etch process such as plasma etching or reactive ion etching is performed to etch the exposed regions of thesubstrate 30 between thesidewall spacers 36, through thenitride layer 32 and theoxide layer 31, and into thelayer 302 to form a plurality ofdeep trenches 38 with a width of one-half of the photolithographic minimum feature width F. - Dielectric material is deposited to fill the plurality of
deep trenches 38 by a spin-on process or a chemical vapor deposition process. Next, a chemical mechanical polishing (CMP) process is used to remove theTEOS layer 34 and thesidewall spacers 36 above thepolysilicon layer 33 so as to form a plurality ofdeep isolations 40 as shown inFIG. 4 . - As illustrated in
FIGS. 4 and 5 , thepolysilicon layer 33 is stripped to expose theunderlying nitride layer 32 by a suitable stripping technique. Thereafter,sidewall spacers 37 made of silicon oxide are formed on theoriginal sidewall spacers 36, and twosidewall spacers 37 facing each other define a groove having a width of approximately one-half of the photolithographic minimum feature width F. Next, through the grooves, a dry etch process such as plasma etching or reactive ion etching is applied to etch thesubstrate 30 beneath the grooves, through thenitride layer 32 and theoxide layer 31, and into thelayer 302 to form a plurality ofshallow trenches 39 with a width of approximately one-half of the photolithographic minimum feature width F as shown inFIG. 5 . - Referring to
FIGS. 5 and 6 , theshallow trenches 39 are then filled with dielectric material by a deposition process, and a CMP process is then employed to remove the dielectric material above thenitride layer 32 and the siliconoxide sidewall spacers nitride layer 32 and a plurality ofshallow isolations 41 are created as shown inFIG. 6 . Eachshallow isolation 41 creates two separated source/drain regions 101 between two adjacentdeep isolations 40 as shown inFIG. 1 . - Referring to
FIGS. 7 and 8 , silicon nitride is deposited to form asilicon nitride layer 42. Next, ahard mask layer 44, and aphotoresist layer 45 are sequentially formed by suitable processes. Thephotoresist layer 45 is then patterned to form a plurality ofphotoresist lines 451 extending transverse to the extension direction of thedeep isolation 40 orshallow isolation 41. In one embodiment, thephotoresist line 451 has a width of approximately the photolithographic minimum feature width F, and twoadjacent photoresist lines 451 are spaced a distance approximately equal to the photolithographic minimum feature width F. - As shown in
FIG. 8 , thephotoresist lines 451 are trimmed, and thehard mask layer 44 is then etched by a dry etch process using the trimmed photoresist lines 451. Subsequently, an etching process is performed to form a plurality ofdepressions 15 and a plurality ofmesa structures 11 between thedepressions 15 by using the etchedhard mask layer 44. In one embodiment, thephotoresist lines 451 are trimmed in such a manner that the ratio of the width of thedepression 15, measured in a direction transverse to the extension direction of thephotoresist line 451, to the width of themesa structure 11 is approximately 3:1. After that, thehard mask layer 44 is stripped. In one embodiment, thehard mask 44 can include a TEOS layer. - Referring to
FIG. 9 ,dielectric material 46, for example silicon oxide, is deposited to fill thedepressions 15, and a CMP process is followed and stopped at thesilicon nitride layer 42. - As illustrated in
FIG. 10 , an etch process, e.g. a dry etch process, is carried out to partially etch back the depositeddielectric material 46 to remove a portion ofdielectric material 46 from thedeep trenches 38, theshallow trenches 39, and thedepressions 15. Due to the existence of thesilicon nitride layer 42 on thedeep isolations 40 shown inFIG. 8 , thedielectric material 46 in thedeep trenches 38 is not etched as deep as that indepressions 15. After the etch back process is performed, thedielectric material layer 46 may be left in thedepressions 15. - Referring to
FIG. 11 , an oxidation process is employed to form athin oxide layer 47 on thesubstrate 30. After that, aconductive material 48 such as titanium nitride is deposited to a level above thesubstrate 30. Thereafter, an etch back process is performed to partially remove the depositedconductive material 48 to formdepressions 49 as shown inFIG. 12 . In the mean time, a plurality of interconnectingportions 123 are formed in the respectiveshallow trenches 39 anddeep trenches 39. Afterwards, adielectric material 50 is deposited to fill thedepressions 49, theshallow trenches 39 and thedeep trenches 39. A CMP process is then performed to partially remove thedielectric material 50 and stopped at thesilicon nitride layer 42. - Referring to
FIGS. 13 to 15 , whereinFIG. 14 is a cross-sectional view along the section line 1-1 inFIG. 13 , andFIG. 15 is a cross-sectional view along the section line 2-2 inFIG. 13 . Ahard mask layer 51 including a plurality of lines is formed by using aphotoresist layer 52 including a plurality of lines extending parallel to the extension direction ofdepressions 15. Each line of thehard mask layer 51 is above acorresponding mesa structure 11 as shown inFIGS. 14 and 15 .Spacers 55 are formed on the sidewalls of the lines of thehard mask layer 51 and thephotoresist layer 52, wherein two opposite facingspacers 55 are separated by a distance of approximately equal to the photolithographic minimum feature width F. Each space of two opposite facingspacers 55 expose a portion of thedielectric material 50. - Referring to
FIGS. 16 and 17 , whereinFIG. 16 is a cross-sectional view showing a process step subsequent to that ofFIGS. 14 and 15 , viewed along the section line 1-1 inFIG. 13 , andFIG. 17 is a cross-sectional view showing a process step subsequent to that ofFIGS. 14 and 15 , viewed along the section line 2-2 inFIG. 13 . Using thehard mask layer 51, a portion of thedielectric material 50 and theconductive material 48 between themesa structures 11 is removed to form a plurality oftrenches 53 so that a plurality ofword lines 12 are formed on the side surface of themesa structures 11. It can be seen that the vertical length of the cross section of theword line 12 extending in parallel to the sidewall of themesa structures 11 is greater than the horizontal length of the cross section of theword line 12, andword lines 14 with such a configuration can be more easily isolated from each other in the horizontal direction. In addition, the resistance of theword line 12 can be decreased by widening it vertically, with no significant impact on the size of memory cell. - Referring to
FIGS. 18 and 19 , whereinFIG. 18 is a cross-sectional view showing a process step subsequent to that ofFIGS. 16 and 17 , viewed along the section line 1-1 inFIG. 13 , andFIG. 19 is a cross-sectional view showing a process step subsequent to that ofFIGS. 16 and 17 , viewed along the section line 2-2 inFIG. 13 . Thetrenches 53 formed in the process shown inFIGS. 16 and 17 are filled withdielectric material 54 such as silicon dioxide, and a CMP process is then carried out and stopped at thesilicon nitride layer 42. Thereafter, referring back toFIG. 1 ,capacitors 14 andbit lines 17 are formed, connecting respective source/drain regions 101. Amemory device 1, as shown inFIG. 1 , is essentially completed. - Although the present invention and its objectives have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
- Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (7)
1. A method of fabricating a memory device, comprising steps of:
filling a first dielectric material in a plurality of deep trenches and shallow trenches to separately form a plurality of deep isolations and a plurality of shallow isolations in a substrate, wherein each shallow trench is formed between two adjacent ones of the plurality of the deep trenches;
forming a plurality of depressions transverse to the deep isolations, wherein two adjacent ones of the plurality of depressions define a mesa structure, and the depression is wider than the mesa structure;
filling the plurality of depressions with a second dielectric material;
removing a portion of the first dielectric material from the shallow trenches and the deep trenches and a portion of the second dielectric material from the depressions;
forming a conductive layer in the shallow trenches, the deep trenches and the depressions; and
removing a portion of the conductive layer in the depression to form two word lines.
2. The method of claim 1 , wherein the forming of the plurality of deep isolations in the substrate comprises steps of:
forming a mask on the substrate, wherein the mask includes a plurality of lines, each having a width, spaced apart by a distance equal to the width;
forming first sidewall spacers on sidewalls of the lines of the mask, wherein the sidewall spacers facing each other are spaced by a distance equal to one half of the width of the lines; and
etching and filling the substrate between the first sidewall spacers to form the plurality of deep isolations in the substrate.
3. The method of claim 2 , wherein the forming of the plurality of shallow isolations comprises steps of:
removing the mask;
forming second sidewall spacers from the first sidewall spacers, wherein the second sidewall spacers facing each other are spaced by a distance equal to one half of the width of the line of the mask; and
etching and filling the substrate between the second sidewall spacers to form the plurality of shallow isolations in the substrate.
4. The method of claim 1 , wherein a ratio of the width of the depression to the width of the mesa structure is approximately 3:1.
5. The method of claim 1 , wherein the width of the deep isolation is one half of the minimum lithographic feature size.
6. The method of claim 1 , wherein the width of the shallow isolation is one half of the minimum lithographic feature size.
7. The method of claim 1 , wherein the deep isolation and the shallow isolation are spaced apart by a distance of one half of the minimum lithographic feature size.
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US8415728B2 (en) * | 2010-11-12 | 2013-04-09 | Nanya Technology Corp. | Memory device and method of fabricating the same |
US9276001B2 (en) | 2012-05-23 | 2016-03-01 | Nanya Technology Corporation | Semiconductor device and method for manufacturing the same |
US8890110B2 (en) * | 2012-06-19 | 2014-11-18 | SK Hynix Inc. | Vertical memory device and method of fabricating the same |
US8946050B2 (en) * | 2012-10-30 | 2015-02-03 | Globalfoundries Inc. | Double trench well formation in SRAM cells |
US10903110B2 (en) * | 2018-12-06 | 2021-01-26 | Nanya Technology Corporation | Method of forming fine interconnection for a semiconductor device |
KR20220043981A (en) * | 2020-09-28 | 2022-04-06 | 삼성전자주식회사 | Semiconductor memory device |
TWI825909B (en) * | 2022-06-03 | 2023-12-11 | 南亞科技股份有限公司 | Method of manufacturing semiconductor device with word lines |
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US4417325A (en) * | 1981-07-13 | 1983-11-22 | Eliyahou Harari | Highly scaleable dynamic ram cell with self-signal amplification |
US8058142B2 (en) * | 1996-11-04 | 2011-11-15 | Besang Inc. | Bonded semiconductor structure and method of making the same |
US6064589A (en) * | 1998-02-02 | 2000-05-16 | Walker; Darryl G. | Double gate DRAM memory cell |
US7045844B2 (en) * | 2002-06-21 | 2006-05-16 | Micron Technology, Inc. | Memory cell and method for forming the same |
US7867822B2 (en) * | 2003-06-24 | 2011-01-11 | Sang-Yun Lee | Semiconductor memory device |
US7232719B2 (en) * | 2005-03-28 | 2007-06-19 | Promos Technologies Inc. | Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate |
JP2008098313A (en) * | 2006-10-10 | 2008-04-24 | Toshiba Corp | Semiconductor memory device |
CN101170113A (en) * | 2006-10-26 | 2008-04-30 | 力晶半导体股份有限公司 | Non volatile memory with insulation structure and its making method |
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