US20130175656A1 - Isolated zener diode - Google Patents
Isolated zener diode Download PDFInfo
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- US20130175656A1 US20130175656A1 US13/345,881 US201213345881A US2013175656A1 US 20130175656 A1 US20130175656 A1 US 20130175656A1 US 201213345881 A US201213345881 A US 201213345881A US 2013175656 A1 US2013175656 A1 US 2013175656A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
Definitions
- the disclosed embodiments relate to Zener diodes and, more particularly, to an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (V b ), to an integrated circuit incorporating multiple instances of the Zener diode, at least two of which have different reverse-bias breakdown voltages, to a method of forming the Zener diode and to a design structure for the Zener diode.
- V b scalable reverse-bias breakdown voltage
- Zener diodes like conventional diodes, allow current to flow in a forward direction.
- Zener diodes exhibit a reverse-bias breakdown voltage (V b ) that is low relative that of conventional diodes.
- V b reverse-bias breakdown voltage
- current typically does not flow, when the diode is reverse-biased (i.e., when the voltage on the N-type cathode region of the diode is greater than the voltage on the P-type anode region).
- a large breakdown current will flow, when the diode is reverse-biased and the voltage on the N-type cathode region exceeds the reverse-bias breakdown voltage (V b ).
- Zener diodes In the case of a Zener diode, the reverse-bias breakdown voltage (V b ) is relatively low. As a result, Zener diodes can be used to protect other circuits against over-voltage conditions. For example, Zener diodes can be used as voltage regulators or as electrostatic discharge (ESD) protection circuits.
- ESD electrostatic discharge
- an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (V b ) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions.
- V b reverse-bias breakdown voltage
- cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. While the anode contact region is contained entirely within the anode well region, one end of the cathode contact region can extend laterally into the anode well region.
- the length of this end (i.e., the length of the portion of the cathode contact region that extends from the cathode well region to anode well region interface to the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (V b ) of the Zener diode. Specifically, increasing this length reduces the reverse-bias breakdown voltage (V b ) of the Zener diode and vice versa.
- Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the Zener diode, having different reverse-bias breakdown voltages, of a method of forming the Zener diode and of a design structure for the Zener diode.
- This Zener diode can comprise a semiconductor layer, a first well region in the semiconductor layer and a second well region in the semiconductor layer positioned laterally adjacent to and abutting the first well region at an interface.
- the first well region can have a first type conductivity and the second well region can have a second type conductivity different from the first type conductivity.
- This Zener diode can further comprise a first contact region and a second contact region.
- the first contact region can have the first type conductivity at a relatively higher conductivity level than the first well region, can be positioned at the top surface of the semiconductor layer and can be contained entirely within the first well region.
- the second contact region can have the second type conductivity at a relatively higher conductivity level than the second well region, can be positioned at the top surface of the semiconductor layer and can further traverse the first well region to second well region interface such that a first end of the second contact region extends laterally into the first well region and a second end of the second contact region extends laterally into the second well region.
- the Zener diode can further comprise an isolation region at the top surface of the semiconductor layer, contained entirely within the first well region, and positioned laterally between and abutting the first contact region and the first end of the second contact region.
- the first end of the second contact region i.e., the portion of the second contact region that extends from the first well region to second well region interface to the isolation region
- V b predetermined reverse-bias breakdown voltage
- the Zener diode can further comprise a conductive field plate on the top surface of the semiconductor layer to further ensure that the Zener diode has the desired reverse-bias breakdown voltage (V b ).
- the conductive field plate can have a first sidewall aligned above the isolation region and a second sidewall opposite the first sidewall aligned above the first end of the second contact region. That is, the conductive field plate should not extend laterally over the first contact region or the second well region.
- the integrated circuit can comprise a semiconductor layer and a plurality of diodes in the semiconductor layer.
- Each Zener diode can comprise a semiconductor layer, a first well region in the semiconductor layer and a second well region in the semiconductor layer positioned laterally adjacent to and abutting the first well region at an interface.
- the first well region can have a first type conductivity and the second well region can have a second type conductivity different from the first type conductivity.
- Each Zener diode can further comprise a first contact region and a second contact region.
- the first contact region can have the first type conductivity at a relatively higher conductivity level than the first well region, can be positioned at the top surface of the semiconductor layer and can be contained entirely within the first well region.
- the second contact region can have the second type conductivity at a relatively higher conductivity level than the second well region, can be positioned at the top surface of the semiconductor layer and can further traverse the first well region to second well region interface such that a first end of the second contact region extends laterally into the first well region and a second end of the second contact region extends laterally into the second well region.
- Each Zener diode can further comprise an isolation region at the top surface of the semiconductor layer, contained entirely within the first well region, and positioned laterally between and abutting the first contact region and the first end of the second contact region.
- the first end of the second contact region i.e., the portion of the second contact region that extends from the first well region to second well region interface to the isolation region
- V b predetermined reverse-bias breakdown voltage
- the first end of the second contact region of at least two of the Zener diodes can have different predetermined lengths such that at least two of the Zener diodes have different reverse-bias breakdown voltages.
- the first end of the second contact region of a first Zener diode can have a first length and the first end of the second contact region of a second Zener diode can have a second length that is less than the first length such that the first reverse-bias breakdown voltage (V b ) of the first Zener diode is less than the second reverse-bias breakdown voltage (V b ) of the second Zener diode.
- any one or more of the Zener diodes can further comprise a conductive field plate on the top surface of the semiconductor layer to further ensure that the Zener diode has the desired reverse-bias breakdown voltage (V b ).
- the conductive field plate can have a first sidewall aligned above the isolation region and a second sidewall opposite the first sidewall aligned above the first end of the second contact region. That is, the conductive plate should not extend laterally over the first contact region or the second well region.
- a method of forming a Zener diode such as the Zener diode described above.
- the method can comprise forming adjacent well regions in a semiconductor layer such that the adjacent well regions comprise: a first well region, having a first type conductivity; and a second well region, having a second type conductivity different from the first type conductivity, positioned laterally adjacent to and abutting the first well region at an interface.
- the method can further comprise forming contact regions and at least one isolation region at the top surface of the semiconductor layer such that a first contact region, having the first type conductivity, is positioned within the first well region; such that a second contact region, having the second type conductivity, traverses the first well region to second well region interface and, thereby has a first end extending laterally into the first well region and a second end extending laterally into the second well region; and such that an isolation region is positioned within the first well region between and abutting both the first contact region and the first end of the second contact region.
- the length of the first end of the second contact region (i.e., the length of the portion of the second contact region extending from the first well region to second well region interface to the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (V b ) of the Zener diode (i.e., in order to achieve a predetermined reverse-bias breakdown voltage (V b )).
- the method can further comprise forming a conductive field plate on the top surface of the semiconductor layer in order to further reduce the reverse-bias breakdown voltage (V b ) of the Zener diode and ensure that the desired reverse-bias breakdown voltage (V b ) is achieved.
- the conductive field plate should be formed so that a first sidewall is aligned above the isolation region and a second sidewall opposite the first sidewall is aligned above the first end of the second contact region (i.e., so that the conductive field plate does not extend laterally over the first contact region or the second well region).
- design structures for the above-mentioned Zener diode and integrated circuit.
- Such design structures can be stored on a non-transitory storage medium, which is readable by a computer, and can comprise data and instructions that when executed by the computer can generate a machine-executable representation of the Zener diode or integrated circuit.
- FIG. 1 is a cross-section diagram illustrating an embodiment of a Zener diode
- FIG. 2 is a top view diagram of the Zener diode of FIG. 1 ;
- FIG. 3 is a graph illustrating current to voltage (I/V) curves for Zener diodes having selectively different reverse-bias breakdown voltages (V b );
- FIG. 4 a is a cross-section diagram illustrating an embodiment of a bulk integrated circuit structure incorporating multiple instances of a Zener diode, each instance having a selectively different reverse-bias breakdown voltage (V b );
- FIG. 4 b is a cross section diagram of an embodiment of a semiconductor-on-insulator (SOI) integrated circuit structure incorporating multiple instances of a Zener diode, each instance having a selectively different reverse-bias breakdown voltage (V b );
- SOI semiconductor-on-insulator
- FIG. 5 is a flow diagram illustrating an embodiment of a method of forming a Zener diode
- FIG. 6 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method of FIG. 5 ;
- FIG. 7 is a top view diagram of the same partially completed Zener diode as shown in FIG. 6 ;
- FIG. 8 is a flow diagram further detailing process 506 of the flow diagram of FIG. 5 ;
- FIG. 9 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method of FIG. 5 ;
- FIG. 10 is a top view diagram of the same partially completed Zener diode as shown in FIG. 9 ;
- FIG. 11 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method of FIG. 5 ;
- FIG. 12 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method of FIG. 5 ;
- FIG. 13 is a flow diagram of a design process used in semiconductor design, manufacture and/or test.
- FIG. 14 is a schematic diagram illustrating an exemplary hardware environment for implementing the disclosed design process.
- Zener diodes like conventional diodes, allow current to flow in a forward direction.
- Zener diodes exhibit a reverse-bias breakdown voltage (V b ) that is low relative that of conventional diodes.
- V b reverse-bias breakdown voltage
- current typically does not flow, when the diode is reverse-biased (i.e., when the voltage on the N-type cathode region of the diode is greater than the voltage on the P-type anode region).
- a large breakdown current will flow, when the diode is reverse-biased and the voltage on the N-type cathode region exceeds the reverse-bias breakdown voltage (V b ).
- Zener diodes In the case of a Zener diode, the reverse-bias breakdown voltage (V b ) is relatively low. As a result, Zener diodes can be used to protect other circuits against over-voltage conditions. For example, Zener diodes can be used as voltage regulators or as electrostatic discharge (ESD) protection circuits.
- ESD electrostatic discharge
- an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (V b ) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions.
- V b reverse-bias breakdown voltage
- cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. While the anode contact region is contained entirely within the anode well region, one end of the cathode contact region can extend laterally into the anode well region.
- the length of this end (i.e., the length of the portion of the cathode contact region that extends from the cathode well region to anode well region interface to the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (V b ) of the Zener diode. Specifically, increasing the length reduces the reverse-bias breakdown voltage (V b ) of the Zener diode and vice versa. Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the Zener diode, having different reverse-bias breakdown voltages, of a method of forming the Zener diode and of a design structure for the Zener diode.
- the first type conductivity can comprise P-type conductivity and the second type conductivity can comprise N-type conductivity.
- the first type conductivity can comprise P-type conductivity and the second type conductivity can comprise N-type conductivity.
- the different dopants can be used to achieve different type conductivities in different semiconductor materials.
- a silicon-based semiconductor material having N-type conductivity is typically doped with an N-type dopant (e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)), whereas a silicon-based semiconductor material having P-type conductivity is typically doped with a P-type dopant (e.g., a Group III dopant, such as boron (B) or indium (In)).
- N-type dopant e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)
- P-type dopant e.g., a Group III dopant, such as boron (B) or indium (In)
- a gallium nitride (GaN)-based semiconductor material having P-type conductivity is typically doped with magnesium (MG), whereas a gallium nitride (GaN)-based semiconductor material having an N-type conductivity is typically doped with silicon (Si).
- MG magnesium
- Si silicon
- FIGS. 1-2 illustrate an embodiment of a Zener diode 100 .
- FIG. 1 is a cross-section illustration of the Zener diode 100 through a vertical plan that cuts across the active regions of the device and
- FIG. 2 is a cross-section illustration of the same Zener diode 100 through a horizontal plane A-A′, as shown in FIG. 1 .
- the Zener diode 100 can comprise a semiconductor layer 103 , having a top surface 105 .
- the Zener diode 100 can further comprise a first well region 111 and a second well region 112 in the semiconductor layer 103 .
- the second well region 112 can be positioned laterally adjacent to and can abut the first well region 111 at an interface 113 .
- the second well region 112 can laterally surround (e.g., encircle) the first well region 111 .
- the first well region 111 can have a first type conductivity and the second well region 112 can have a second type conductivity different from the first type conductivity.
- the first well region 111 can have a P-type conductivity such that it comprises an anode well region and the second well region 112 can have an N-type conductivity such that it comprises a cathode well region.
- this semiconductor layer 103 can be a bulk semiconductor substrate (e.g., a bulk silicon substrate).
- a buried well region 102 having the second type conductivity (e.g., a buried N-well region), can isolate the active regions of the diode 100 from a lower portion 101 of the substrate, which has the first type conductivity (e.g., a P ⁇ lower substrate).
- the semiconductor layer 103 can be a semiconductor layer of a semiconductor-on-insulator (SOI) structure.
- SOI semiconductor-on-insulator
- Such an SOI structure can comprise a semiconductor substrate 101 , having the first type conductivity (e.g., a P ⁇ silicon substrate), an isolation layer 102 (e.g., a silicon dioxide (SiO 2 ) layer, a sapphire layer or some other suitable isolation layer) on the substrate 101 , and a semiconductor layer 103 (e.g., a silicon layer or some other suitable semiconductor layer) on the isolation layer 102 .
- the first type conductivity e.g., a P ⁇ silicon substrate
- an isolation layer 102 e.g., a silicon dioxide (SiO 2 ) layer, a sapphire layer or some other suitable isolation layer
- a semiconductor layer 103 e.g., a silicon layer or some other suitable semiconductor layer
- the Zener diode 100 can further comprise a first contact region 131 , a second contact region 132 and, optionally, an additional contact region 133 in the semiconductor layer 103 at the top surface 105 .
- the first contact region 131 can comprise a doped region contained entirely within the first well region 111 and can have the first type conductivity at a relatively higher conductivity level than the first well region 111 .
- the first contact region 131 can comprise a P+ anode contact region.
- the second contact region 132 can comprise another doped region and can have the second type conductivity at a relatively higher conductivity level than the second well region 112 .
- the second contact region 132 can comprise an N+ cathode contact region.
- the second contact region 132 can further traverse the interface 113 (i.e., the first well region 111 to second well region 112 interface 113 ) such that a first end 132 a of the second contact region 132 extends laterally into the first well region 111 and a second end 132 b of the second contact region 132 extends laterally into the second well region 112 .
- the additional contact region 133 can comprise an additional doped region contained entirely within the second well region 112 and can have the second type conductivity at a relatively higher conductivity level than the second well region 111 .
- the additional contact region 133 can comprise an additional N+ cathode contact region.
- the Zener diode 100 can further comprise isolation regions 121 and 122 , which are positioned at the top surface of the semiconductor layer 103 and which define the limits (i.e., the boundaries, shapes, etc.) of the contact regions 131 - 133 .
- the isolation region 121 can be contained entirely within the first well region 111 and can be positioned laterally between and can abut both the first contact region 131 and the first end 132 a of the second contact region 132 .
- this isolation region 121 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of the first contact region 131 (see FIG. 2 ).
- This isolation region 121 can have a first side (i.e., an inner side) adjacent to the first contact region 131 and a second side (i.e., an outer side) opposite the first side adjacent to the first end 132 a of the second contact region 132 .
- the additional isolation region 122 can be contained entirely within the second well region 112 and can be positioned laterally between and can abut both the second end 132 b of the second contact region 132 and the additional contact region 133 .
- this additional isolation region 122 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of the second contact region 132 and the additional contact region 133 can be positioned laterally around (i.e., can laterally surround, border, etc.) the additional isolation region 122 (see FIG. 2 ).
- the isolation regions 121 and 122 can comprise, for example, conventional shallow trench isolation (STI) regions. That is, each of the isolation regions 121 , 122 can comprise a patterned, relatively shallow, trench extending vertically into the semiconductor layer 103 from the top surface 105 .
- the trench can further be filled with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.).
- the first end 132 a of the second contact region 132 (i.e., the portion of the second contact region the extends from the first well region to second well region interface 113 to the isolation region 121 ) can have a predetermined length 140 .
- the length 140 of this end 132 a can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (V b ) of the Zener diode 100 .
- increasing the length 140 reduces the reverse-bias breakdown voltage (V b ) of the diode 100 and vice versa.
- FIG. 3 is a graph that illustrates current to voltage (UV) curves for three Zener diodes 100 that are essentially identical in structure except that the ends 132 a of the second contact regions 132 of each of three Zener diodes have different lengths.
- UV curve 301 represents a Zener diode wherein the end 132 a is relatively short (e.g., the side of the STI 121 is almost aligned above the interface 113 ) and, thus, the reverse-bias breakdown voltage (V b ) at which a significant amount of current flows through the diode is relative large (e.g., ⁇ 7V).
- UV curve 303 represents a Zener diode wherein the end 132 a is relatively long (e.g., 0.5 ⁇ m) and, thus, the reverse-bias breakdown voltage (V b ) at which a significant amount of current flows through the diode is relative small (e.g., ⁇ 5.2V).
- UV curve 302 represents a Zener diode wherein the end 132 a is somewhere in between (e.g., 0.14 ⁇ m) and, thus, the reverse-bias breakdown voltage (V b ) at which a significant amount of current flows through the diode is somewhere in between (e.g., ⁇ 6.2V).
- the Zener diode 100 can further comprise a conductive field plate 150 on the top surface 105 of the semiconductor layer 103 to further ensure that the Zener diode 100 has the desired reverse-bias breakdown voltage (V b ).
- the conductive field plate 150 can have a first sidewall 151 aligned above the isolation region 121 and a second sidewall 152 opposite the first sidewall 151 aligned above the first end 132 a of the second contact region 132 . That is, the conductive field plate 150 should not extend laterally over the first contact region 131 or the second well region 112 .
- This conductive field plate 150 can comprise, for example, a metal field plate, a metal alloy field plate, a doped polysilicon field plate, etc. Such a conductive field plate 150 is particularly useful to reduce the reverse-bias breakdown voltage (V b ) when the sidewall of the isolation region 121 immediately adjacent to the first contact region 131 is not perpendicular (e.g., is rounded as a result of formation processing techniques), a condition which tends to increase the reverse-bias breakdown voltage (V b ).
- Zener diode such as the diode described above having a scalable reverse-bias breakdown voltage (V b )
- V b scalable reverse-bias breakdown voltage
- the perimeters (or shapes) of the diode components are shown in FIG. 2 as being rectangular. However, those skilled in the art will recognize that these diode components may alternatively have any other suitable shape (e.g., square, circle, oval, etc.).
- FIGS. 4 a and 4 b also disclosed herein are embodiments of an integrated circuit structure 499 a , 499 b incorporating multiple instances of a Zener diode 400 . 1 , 400 . 2 on the same chip where at least some of the Zener diodes 400 . 1 , 400 . 2 have different reverse-bias breakdown voltages.
- the integrated circuit structure 499 a , 499 b can comprise a semiconductor layer 403 , having a top surface 405 .
- this semiconductor layer 403 can comprise either a bulk semiconductor layer, as shown in the integrated circuit structure 499 a of FIG. 4 a or a semiconductor layer of a semiconductor-on-insulator wafer, as shown in the integrated circuit structure 499 b of FIG. 4 b.
- the semiconductor layer 403 can be a bulk semiconductor substrate (e.g., a bulk silicon substrate).
- buried well isolation regions 402 . 1 , 402 . 2 having the second type conductivity (e.g., buried N-well isolation regions), can isolate the active regions of the Zener diodes 400 . 1 , 400 . 2 , respectively, from a lower portion 401 of the substrate, which has a first type conductivity (e.g., a P ⁇ lower substrate).
- an additional isolation well region 413 having the first type conductivity (e.g., a P-well isolation region), can be positioned laterally between the Zener diodes 400 . 1 , 400 . 2 to isolate the devices from each other.
- the semiconductor layer 403 can be a semiconductor layer of a semiconductor-on-insulator (SOT) structure.
- Such an SOI structure can comprise a semiconductor substrate 401 , having the first type conductivity (e.g., a P ⁇ silicon substrate), an isolation layer 402 (e.g., a silicon dioxide (SiO 2 ) layer, a sapphire layer, or some other suitable isolation layer) on the substrate 401 , and a semiconductor layer (e.g., a silicon layer or some other suitable semiconductor layer) on the isolation layer 402 .
- a deep trench isolation region e.g., a deep trench filled with one or more isolation materials, such a silicon oxide, silicon nitride, silicon oxynitride, etc.
- each of the Zener diodes 400 . 1 , 400 . 2 in the integrated circuit structure 499 a , 499 b of FIGS. 4 a and 4 b can comprise a first well region 411 and a second well region 412 in the semiconductor layer 403 .
- the second well region 412 can be positioned laterally adjacent to and can abut the first well region 411 at an interface 413 .
- the second well region 412 can laterally surround (e.g., encircle) the first well region 411 .
- the first well region 411 can have a first type conductivity and the second well region 412 can have a second type conductivity different from the first type conductivity.
- the first well region 411 can have a P-type conductivity such that it comprises an anode well region and the second well region 412 can have an N-type conductivity such that it comprises a cathode well region.
- Each of the Zener diodes 400 . 1 , 400 . 2 can further comprise a first contact region 431 , a second contact region 432 , and an additional contact region 433 in the semiconductor layer 403 at the top surface 405 .
- the first contact region 431 can comprise a doped region contained entirely within the first well region 411 and can have the first type conductivity at a relatively higher conductivity level than the first well region 411 .
- the first contact region 431 can comprise a P+ anode contact region.
- the second contact region 432 can comprise another doped region and can have the second type conductivity at a relatively higher conductivity level than the second well region 412 .
- the second contact region 432 can comprise an N+ cathode contact region.
- the second contact region 432 can further traverse the interface 413 such that a first end 432 a of the second contact region 432 extends laterally into the first well region 411 and a second end 432 b of the second contact region 432 extends laterally into the second well region 412 .
- the additional contact region 433 can comprise an additional doped region contained entirely within the second well region 412 and can have the second type conductivity at a relatively higher conductivity level than the second well region 411 .
- the additional contact region 433 can comprise an additional N+ cathode contact region.
- Each of the Zener diodes 400 . 1 , 400 . 2 can further comprise isolation regions 421 and 422 , which are at the top surface of the semiconductor layer 403 and which define the limits (i.e., the boundaries, shapes, etc.) of the contact regions 431 - 433 .
- the isolation region 421 can be contained entirely within the first well region 411 and can be positioned laterally between and can abut both the first contact region 431 and the first end 432 a of the second contact region 432 . Specifically, this isolation region 421 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of the first contact region 431 .
- the additional isolation region 422 can be contained entirely within the second well region 412 and can be positioned laterally between and can abut both the second end 432 b of the second contact region 432 and the additional contact region 433 . Specifically, this additional isolation region 422 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of the second contact region 432 and the additional contact region 433 can be positioned laterally around (i.e., can laterally surround, border, etc.) the additional isolation region 422 .
- the isolation regions 421 and 422 can comprise, for example, conventional shallow trench isolation (STI) regions. That is, each of the isolation regions 421 , 422 can comprise a patterned, relatively shallow, trench extending vertically into the semiconductor layer 403 from the top surface 405 .
- the trench can further be filled with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.).
- the first end 432 a of the second contact region 432 i.e., the portion of the second contact region that extends from the interface 413 to the isolation region 421 ) of the first Zener diode 400 . 1 can have a different predetermined length 440 , than that of the first end 432 a of the second contact region 432 of the second Zener diode 400 . 2 .
- the lengths 440 of the ends 432 a of the different Zener diodes 400 can have a different predetermined length 440 , than that of the first end 432 a of the second contact region 432 of the second Zener diode 400 . 2 .
- the first Zener diode 400 . 1 will have a smaller reverse-bias breakdown voltage (V b ). See detail discussion above regarding the graph of FIG. 3 and the relationship between this length and the reverse-bias breakdown voltage (V b ).
- At least one of the Zener diodes can further comprise a conductive field plate 450 on the top surface 405 of the semiconductor layer 403 to further ensure that the Zener diode 400 . 1 has the desired reverse-bias breakdown voltage (V b ).
- the conductive field plate 450 can have a first sidewall 451 aligned above the isolation region 421 and a second sidewall 452 opposite the first sidewall 451 aligned above the first end 432 a of the second contact region 432 . That is, the conductive field plate 450 should not extend laterally over the first contact region 431 or the second well region 412 .
- This conductive field plate 450 can comprise, for example, a metal field plate, a metal alloy field plate, a doped polysilicon field plate, etc. Such a conductive field plate 450 is particularly useful in reducing the reverse-bias breakdown voltage (V b ) when the sidewall of the isolation region 421 immediately adjacent to the first contact region 431 is not perpendicular (e.g., is rounded), a condition which tends to increase the reverse-bias breakdown voltage (V b ).
- Zener diodes such as Zener diodes 400 . 1 , 400 . 2 described above, having different reverse-bias breakdown voltages, can be incorporated into the integrated circuit structure 499 a , 499 b for different purposes (e.g., for voltage regulation and electrostatic discharge (ESD) protection, respectively).
- ESD electrostatic discharge
- the method embodiments can comprise providing a semiconductor layer 103 ( 502 ) and forming adjacent well regions in the semiconductor layer 103 such that the adjacent well regions comprise: a first well region 111 having a first type conductivity (e.g., a P-type anode well region) and a second well region 112 having a second type conductivity different from the first type conductivity (e.g., an N-type cathode well region) positioned laterally adjacent to and, particularly, laterally surrounding and abutting and the first well region at an interface 113 ( 504 , see the cross-section illustration of FIG.
- a first type conductivity e.g., a P-type anode well region
- second well region 112 having a second type conductivity different from the first type conductivity (e.g., an N-type cathode well region) positioned laterally adjacent to and, particularly, laterally surrounding and abutting and the first well region at an interface 113 ( 504 , see the cross-section illustration of FIG.
- the semiconductor layer 103 provided at process 502 could be a bulk semiconductor substrate (e.g., a bulk silicon substrate).
- a buried well region 102 having the second type conductivity (e.g., a buried N-well region), can be formed deep in the substrate so as to isolate subsequently formed active regions of the Zener diode from a lower portion 101 of the substrate, which has a the first type conductivity (e.g., a P ⁇ lower substrate).
- the semiconductor layer 103 provided at process 502 could be a semiconductor layer of a semiconductor-on-insulator (SOI) structure.
- SOI semiconductor-on-insulator
- Such an SOI structure can comprise a semiconductor substrate 101 , having the first type conductivity (e.g., a P ⁇ silicon substrate), an isolation layer 102 (e.g., a silicon dioxide (SiO 2 ) layer, sapphire layer or some other suitable isolation layer) on the substrate 101 , and a semiconductor layer (e.g., a silicon layer or some other suitable semiconductor layer) on the isolation layer 102 .
- the first type conductivity e.g., a P ⁇ silicon substrate
- an isolation layer 102 e.g., a silicon dioxide (SiO 2 ) layer, sapphire layer or some other suitable isolation layer
- a semiconductor layer e.g., a silicon layer or some other suitable semiconductor layer
- the method embodiments can further comprise forming shallow trench isolation (STI) regions 121 - 122 and anode and cathode contact regions 131 - 133 at the top surface 105 of the semiconductor layer 103 ( 506 ).
- STI shallow trench isolation
- Process 506 can specifically be performed so as to form the various contact regions and isolation regions, as shown in FIGS. 1 and 2 and described in detail above.
- process 506 can be performed so as to form a first contact region 131 , which is contained entirely within the first well region 111 and which has the first type conductivity at a relatively higher conductivity level than the first well region 111 (e.g., a P+ anode contact region) ( 507 ).
- first contact region 131 which is contained entirely within the first well region 111 and which has the first type conductivity at a relatively higher conductivity level than the first well region 111 (e.g., a P+ anode contact region) ( 507 ).
- Process 506 can be performed so as to form an isolation region 121 such that the isolation region 121 is contained entirely within the first well region 111 and such that the isolation region 121 is positioned adjacent to (e.g., laterally surrounds, borders, etc.) and abuts the first contact region 131 ( 508 ).
- Process 506 can further be performed so as to form a second contact region 132 such that the second contact region 132 traverses the interface 113 between the well regions 111 - 112 (i.e., has a first end 132 a extending laterally into the first well region 111 and a second end 132 b extending laterally into the second well region 112 ), such that the second contact region 132 is positioned adjacent to (e.g., laterally surrounds, borders, etc.) and abuts the isolation region 121 and such that the second contact region 132 has a second type conductivity at a relatively higher conductivity level than the second well region 112 (e.g., a N+ cathode region) ( 509 ).
- a second type conductivity at a relatively higher conductivity level than the second well region 112 (e.g., a N+ cathode region) ( 509 ).
- this second contact region 132 should specifically be formed so that the first end 132 a between the interface 113 and the isolation region 121 has a predetermined length 140 and, thereby so that the Zener diode 100 has a predetermined reverse-bias breakdown voltage (V b ) ( 510 ).
- Process 506 can further be performed so as to form an additional isolation region 122 such that the additional isolation region 122 is contained entirely within the second well region 111 and such that the additional isolation region is adjacent to (e.g., laterally surrounds, borders, etc.) and abuts the second contact region 132 ( 511 ).
- process 506 can be performed so as to form an additional contact region 133 such that the additional contact region 133 is contained entirely within the second well region 112 , such that the additional contact region is positioned adjacent to (e.g., laterally surrounds, borders, etc.) and abuts the additional isolation region 122 and such that the additional contact region 133 has the second type conductivity at a relatively higher conductivity level than the second well region 111 (e.g., an additional N+ cathode contact region) ( 512 ).
- this process 506 of forming the isolation regions 121 - 122 and anode and cathode contact regions 131 - 133 for the Zener diode 100 can comprise forming shallow trench isolation (STI) regions 121 - 122 that define the limits (i.e., boundaries, shapes, etc.) of the contact regions 131 - 133 , as described above ( 802 ). That is, conventional STI formation techniques can be used to pattern, etch and fill the trenches for each of the STI regions 121 - 122 and to, thereby define the limits (i.e., boundaries, shapes, etc.) of the contact regions 131 - 133 (see the cross-section and top view diagrams of FIG. 9 and FIG.
- STI shallow trench isolation
- the novelty in this case is not how the STI regions 121 are formed but that the STI trenches are patterned so that the defined area for the second contact region 132 (i.e., the N+ cathode region) in particular, which lies between the trenches, traverses the interface 113 between the well regions 111 - 112 as opposed to being contained entirely within the well region 112 .
- the position of the STI trenches relative to the interface 113 is selectively adjusted so as to selectively adjust the position and overall length of the second contact region 132 and, thereby to selectively adjust the length 140 of the end 132 a of that second contact region 132 that extends from the interface 113 to the STI region 121 .
- the reverse-bias breakdown voltage (V b ) of the Zener diode 100 can be selectively adjusted ( 803 ). See also the detailed discussion above regarding the graph of FIG.
- the STI trenches can be filled using conventional STI formation techniques with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.).
- isolation materials e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.
- the contact regions 131 - 133 can be appropriately doped ( 804 ).
- a mask 901 can be formed so as to cover the exposed portion of the semiconductor layer 103 surrounded by the STI region 121 and a dopant implantation process or other doping process can be performed in order to doped the exposed areas of the top surface 105 of the semiconductor layer 103 adjacent to the STI region 122 and, thereby form contact regions 132 and 133 having the second type conductivity (e.g., N+ cathode regions) (see FIG. 11 ).
- the second type conductivity e.g., N+ cathode regions
- the mask 901 can be removed, another mask 902 can be formed so as to cover the exposed portion of the semiconductor layer 103 adjacent to the STI region 122 , and another dopant implantation or other doping process can be performed in order to doped the exposed area of the top surface 105 of the semiconductor layer 103 surrounded by the STI region 121 and, thereby form contact region 131 having the first type conductivity (e.g., a P+ anode region) (see FIG. 12 ).
- the first type conductivity e.g., a P+ anode region
- the method embodiments can further comprise forming a conductive field plate 150 (e.g., a doped polysilicon, metal or metal alloy conductive field plate) on the top surface 105 of the semiconductor layer 103 in order to further reduce the reverse-bias breakdown voltage (V b ) of the diode and ensure that a desired reverse-bias breakdown voltage (V b ) is achieved ( 514 , see FIG. 1 ).
- a conductive field plate 150 e.g., a doped polysilicon, metal or metal alloy conductive field plate
- the conductive field plate 150 should be formed so that a first sidewall 151 is aligned above the isolation region 121 and a second sidewall 152 opposite the first sidewall 151 is aligned above the first end 132 a of the second contact region 132 (i.e., so that the conductive field plate 150 does not extend laterally over the first contact 131 or the second well region 112 ).
- Such a conductive field plate 150 can be formed essentially simultaneously with the formation of polysilicon and/or metal gate structures on the top surface 105 of the semiconductor layer 103 .
- discrete buried well isolation regions 402 . 1 , 402 . 2 having the second type conductivity (e.g., buried N-well isolation regions), can be formed (e.g., implanted) prior to device formation to isolate the active regions of the subsequently formed diodes 400 . 1 , 400 . 2 , respectively, from a lower portion 401 of the first type conductivity substrate (e.g., P ⁇ substrate).
- an additional isolation well region 413 having the first type conductivity (e.g., a P-well isolation region), can be formed (e.g., implanted) such that it is positioned laterally between the Zener diodes 400 .
- the SOI isolation layer 402 e.g., a silicon dioxide (SiO 2 ) layer, sapphire layer or some other suitable isolation layer
- SiO 2 silicon dioxide
- a deep trench isolation region e.g., a deep trench filled with one or more isolation materials, such a silicon oxide, silicon nitride, silicon oxynitride, etc.
- isolation materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.
- design structures for the above-mentioned Zener diode and integrated circuit.
- Such design structures can be stored on a non-transitory storage medium readable by a computer and can comprise data and instructions that when executed by the computer can generate a machine-executable representation of the diode or integrated circuit.
- FIG. 13 shows a block diagram of an exemplary design flow 1300 used for example, in semiconductor design, manufacturing, and/or test.
- Design flow 1300 may vary depending on the type of IC being designed.
- a design flow 1300 for building an application specific IC (ASIC) may differ from a design flow 1300 for designing a standard component.
- Design structure 1320 is preferably an input (e.g., of data and instructions) to a design process 1310 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources.
- Design structure 1320 comprises an embodiment of a Zener diode 100 as shown in FIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400 .
- Design structure 1320 may be contained on (i.e., stored on) one or more machine-readable medium.
- design structure 1320 may be a text file or a graphical representation of an embodiment of a Zener diode 100 as shown in FIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400 . 1 , 400 . 2 , as shown in FIGS. 4 a and 4 b.
- Design process 1310 preferably executes the data and instructions in order to synthesize (or translate) an embodiment of a Zener diode 100 as shown in FIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400 . 1 , 400 . 2 , as shown in FIGS. 4 a and 4 b , into a netlist 1380 , where netlist 1380 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 1380 is resynthesized one or more times depending on design specifications and parameters for the circuit.
- Design process 1310 may include using a variety of inputs; for example, inputs from library elements 1330 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1340 , characterization data 1350 , verification data 1360 , design rules 1370 , test data files 1385 (which may include test patterns and other testing information), and instructions.
- library elements 1330 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1340 , characterization data 1350 , verification data 1360 , design rules 1370 , test data files 1385 (which may include test patterns and other testing information), and instructions.
- design specifications 1340 e.g
- Design process 1310 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- Design process 1310 preferably translates an embodiment of a Zener diode 100 as shown in FIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400 . 1 , 400 . 2 , as shown in FIGS. 4 a and 4 b , along with any additional integrated circuit design or data (if applicable), into a second design structure 1390 .
- Design structure 1390 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures).
- GDSII GDS2
- GL1 GL1, OASIS
- Design structure 1390 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of a Zener diode 100 as shown in FIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400 . 1 , 400 . 2 , as shown in FIGS. 4 a and 4 b . Design structure 1390 may then proceed to a stage 1395 where, for example, design structure 1390 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
- FIG. 14 A representative hardware environment for implementing the design flow process, described above and illustrated in FIG. 13 , is depicted in FIG. 14 .
- the system comprises at least one processor or central processing unit (CPU) 10 .
- the CPUs 10 are interconnected via system bus 12 to various devices such as a random access memory (RAM) 14 , read-only memory (ROM) 16 , and an input/output (I/O) adapter 18 .
- RAM random access memory
- ROM read-only memory
- I/O input/output
- the I/O adapter 18 can connect to peripheral devices, such as disk units 11 and tape drives 13 , or other program storage devices that are readable by the system.
- the system can read the inventive instructions on the program storage devices and follow these instructions to execute the methodology of the embodiments herein.
- the system further includes a user interface adapter 19 that connects a keyboard 15 , mouse 17 , speaker 24 , microphone 22 , and/or other user interface devices such as a touch screen device (not shown) to the bus 12 to gather user input.
- a communication adapter 20 connects the bus 12 to a data processing network 25
- a display adapter 21 connects the bus 12 to a display device 23 which may be embodied as an output device such as a monitor, printer, or transmitter, for example.
- a “semiconductor” is a material or structure that may include an implanted impurity that allows the material to sometimes be a conductor and sometimes be an insulator, based on electron and hole carrier concentration.
- implantation processes can take any appropriate form (whether now known or developed in the future) and can comprise, for example, ion implantation, etc.
- an “insulator” is a relative term that means a material or structure that allows substantially less ( ⁇ 95%) electrical current to flow than does a “conductor.”
- the dielectrics (insulators) mentioned herein can oxide-based dielectrics, such oxide-based dielectrics can be grown, for example, from either a dry oxygen ambient or steam and then patterned.
- the dielectrics herein may be formed from any of the many candidate dielectric materials, including but not limited to silicon nitride, silicon oxynitride, or a metal oxide (e.g., tantalum oxide).
- the thickness of dielectrics herein may vary contingent upon the required device performance.
- the conductors mentioned herein can be formed of any conductive material, such as polycrystalline silicon (polysilicon), amorphous silicon, a combination of amorphous silicon and polysilicon, and polysilicon-germanium, rendered conductive by the presence of a suitable dopant.
- the conductors herein may be one or more metals, such as tungsten, hafnium, tantalum, molybdenum, titanium, or nickel, or a metal silicide, any alloys of such metals, and may be deposited using physical vapor deposition, chemical vapor deposition, or any other technique known in the art.
- metals such as tungsten, hafnium, tantalum, molybdenum, titanium, or nickel, or a metal silicide, any alloys of such metals, and may be deposited using physical vapor deposition, chemical vapor deposition, or any other technique known in the art.
- an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (V b ) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions.
- V b reverse-bias breakdown voltage
- cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. While the anode contact region is contained entirely within the anode well region, one end of the cathode contact region can extend laterally into the anode well region.
- the length of this end (i.e., the length of the portion of the cathode contact region between the interface and the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (V b ) of the diode. Specifically, increasing the length reduces the reverse-bias breakdown voltage (V b ) of the diode and vice versa. Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the Zener diode, having different reverse-bias breakdown voltages, of a method of forming the Zener diode and of a design structure for the Zener diode.
- these embodiments allow scaling of the reverse-bias breakdown voltage (V b ) of a Zener diode to be achieved by simply selectively adjusting the position of the cathode contact region and, optionally, adding a conductive field plate.
- V b reverse-bias breakdown voltage
- These technique can be incorporated into conventional device processing (e.g., well implantation, STI formation, and gate formation) without requiring additional masking and doping processes (i.e., it is a zero-mask adder technique).
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Abstract
Description
- 1. Field of the Invention
- The disclosed embodiments relate to Zener diodes and, more particularly, to an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (Vb), to an integrated circuit incorporating multiple instances of the Zener diode, at least two of which have different reverse-bias breakdown voltages, to a method of forming the Zener diode and to a design structure for the Zener diode.
- 2. Description of the Related Art
- Zener diodes, like conventional diodes, allow current to flow in a forward direction. However, Zener diodes exhibit a reverse-bias breakdown voltage (Vb) that is low relative that of conventional diodes. Specifically, in the case of a conventional diode, current typically does not flow, when the diode is reverse-biased (i.e., when the voltage on the N-type cathode region of the diode is greater than the voltage on the P-type anode region). However, a large breakdown current will flow, when the diode is reverse-biased and the voltage on the N-type cathode region exceeds the reverse-bias breakdown voltage (Vb). In the case of a Zener diode, the reverse-bias breakdown voltage (Vb) is relatively low. As a result, Zener diodes can be used to protect other circuits against over-voltage conditions. For example, Zener diodes can be used as voltage regulators or as electrostatic discharge (ESD) protection circuits.
- Unfortunately, in order to achieve such a relatively low reverse-bias breakdown voltage (Vb), additional masking and doping processes are required to either form the P-type anode region or N-type cathode region of the Zener diode or to add an additional amount of dopant to an already formed P-type anode region or N-type cathode region of the Zener diode. These additional masking and doping processes can be costly and time consuming. Thus, there is a need in the art for a Zener diode structure and method of forming the structure that allows a desired, relatively low, reverse-bias breakdown voltage (Vb) to be achieved without requiring additional masking and doping processes.
- In view of the foregoing, disclosed herein are embodiments of an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. While the anode contact region is contained entirely within the anode well region, one end of the cathode contact region can extend laterally into the anode well region. The length of this end (i.e., the length of the portion of the cathode contact region that extends from the cathode well region to anode well region interface to the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (Vb) of the Zener diode. Specifically, increasing this length reduces the reverse-bias breakdown voltage (Vb) of the Zener diode and vice versa. Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the Zener diode, having different reverse-bias breakdown voltages, of a method of forming the Zener diode and of a design structure for the Zener diode.
- More particularly, disclosed herein are embodiments of a Zener diode. This Zener diode can comprise a semiconductor layer, a first well region in the semiconductor layer and a second well region in the semiconductor layer positioned laterally adjacent to and abutting the first well region at an interface. The first well region can have a first type conductivity and the second well region can have a second type conductivity different from the first type conductivity.
- This Zener diode can further comprise a first contact region and a second contact region. The first contact region can have the first type conductivity at a relatively higher conductivity level than the first well region, can be positioned at the top surface of the semiconductor layer and can be contained entirely within the first well region. The second contact region can have the second type conductivity at a relatively higher conductivity level than the second well region, can be positioned at the top surface of the semiconductor layer and can further traverse the first well region to second well region interface such that a first end of the second contact region extends laterally into the first well region and a second end of the second contact region extends laterally into the second well region.
- The Zener diode can further comprise an isolation region at the top surface of the semiconductor layer, contained entirely within the first well region, and positioned laterally between and abutting the first contact region and the first end of the second contact region. The first end of the second contact region (i.e., the portion of the second contact region that extends from the first well region to second well region interface to the isolation region) can have a predetermined length so that the Zener diode has a predetermined reverse-bias breakdown voltage (Vb).
- Optionally, the Zener diode can further comprise a conductive field plate on the top surface of the semiconductor layer to further ensure that the Zener diode has the desired reverse-bias breakdown voltage (Vb). The conductive field plate can have a first sidewall aligned above the isolation region and a second sidewall opposite the first sidewall aligned above the first end of the second contact region. That is, the conductive field plate should not extend laterally over the first contact region or the second well region.
- Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the above-described Zener diode, wherein at least some of the Zener diodes have different reverse-bias breakdown voltages. Specifically, the integrated circuit can comprise a semiconductor layer and a plurality of diodes in the semiconductor layer. Each Zener diode can comprise a semiconductor layer, a first well region in the semiconductor layer and a second well region in the semiconductor layer positioned laterally adjacent to and abutting the first well region at an interface. The first well region can have a first type conductivity and the second well region can have a second type conductivity different from the first type conductivity.
- Each Zener diode can further comprise a first contact region and a second contact region. The first contact region can have the first type conductivity at a relatively higher conductivity level than the first well region, can be positioned at the top surface of the semiconductor layer and can be contained entirely within the first well region. The second contact region can have the second type conductivity at a relatively higher conductivity level than the second well region, can be positioned at the top surface of the semiconductor layer and can further traverse the first well region to second well region interface such that a first end of the second contact region extends laterally into the first well region and a second end of the second contact region extends laterally into the second well region.
- Each Zener diode can further comprise an isolation region at the top surface of the semiconductor layer, contained entirely within the first well region, and positioned laterally between and abutting the first contact region and the first end of the second contact region. The first end of the second contact region (i.e., the portion of the second contact region that extends from the first well region to second well region interface to the isolation region) can have a predetermined length so that the diode has a predetermined reverse-bias breakdown voltage (Vb). In this case, the first end of the second contact region of at least two of the Zener diodes can have different predetermined lengths such that at least two of the Zener diodes have different reverse-bias breakdown voltages. For example, the first end of the second contact region of a first Zener diode can have a first length and the first end of the second contact region of a second Zener diode can have a second length that is less than the first length such that the first reverse-bias breakdown voltage (Vb) of the first Zener diode is less than the second reverse-bias breakdown voltage (Vb) of the second Zener diode.
- Optionally, any one or more of the Zener diodes can further comprise a conductive field plate on the top surface of the semiconductor layer to further ensure that the Zener diode has the desired reverse-bias breakdown voltage (Vb). The conductive field plate can have a first sidewall aligned above the isolation region and a second sidewall opposite the first sidewall aligned above the first end of the second contact region. That is, the conductive plate should not extend laterally over the first contact region or the second well region.
- Also disclosed herein are embodiments of a method of forming a Zener diode, such as the Zener diode described above. The method can comprise forming adjacent well regions in a semiconductor layer such that the adjacent well regions comprise: a first well region, having a first type conductivity; and a second well region, having a second type conductivity different from the first type conductivity, positioned laterally adjacent to and abutting the first well region at an interface. The method can further comprise forming contact regions and at least one isolation region at the top surface of the semiconductor layer such that a first contact region, having the first type conductivity, is positioned within the first well region; such that a second contact region, having the second type conductivity, traverses the first well region to second well region interface and, thereby has a first end extending laterally into the first well region and a second end extending laterally into the second well region; and such that an isolation region is positioned within the first well region between and abutting both the first contact region and the first end of the second contact region. In forming these contact regions and the isolation region(s), the length of the first end of the second contact region (i.e., the length of the portion of the second contact region extending from the first well region to second well region interface to the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (Vb) of the Zener diode (i.e., in order to achieve a predetermined reverse-bias breakdown voltage (Vb)).
- Optionally, the method can further comprise forming a conductive field plate on the top surface of the semiconductor layer in order to further reduce the reverse-bias breakdown voltage (Vb) of the Zener diode and ensure that the desired reverse-bias breakdown voltage (Vb) is achieved. In this case, the conductive field plate should be formed so that a first sidewall is aligned above the isolation region and a second sidewall opposite the first sidewall is aligned above the first end of the second contact region (i.e., so that the conductive field plate does not extend laterally over the first contact region or the second well region).
- Also disclosed herein are embodiments of design structures for the above-mentioned Zener diode and integrated circuit. Such design structures can be stored on a non-transitory storage medium, which is readable by a computer, and can comprise data and instructions that when executed by the computer can generate a machine-executable representation of the Zener diode or integrated circuit.
- The embodiments herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
-
FIG. 1 is a cross-section diagram illustrating an embodiment of a Zener diode; -
FIG. 2 is a top view diagram of the Zener diode ofFIG. 1 ; -
FIG. 3 is a graph illustrating current to voltage (I/V) curves for Zener diodes having selectively different reverse-bias breakdown voltages (Vb); -
FIG. 4 a is a cross-section diagram illustrating an embodiment of a bulk integrated circuit structure incorporating multiple instances of a Zener diode, each instance having a selectively different reverse-bias breakdown voltage (Vb); -
FIG. 4 b is a cross section diagram of an embodiment of a semiconductor-on-insulator (SOI) integrated circuit structure incorporating multiple instances of a Zener diode, each instance having a selectively different reverse-bias breakdown voltage (Vb); -
FIG. 5 is a flow diagram illustrating an embodiment of a method of forming a Zener diode; -
FIG. 6 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method ofFIG. 5 ; -
FIG. 7 is a top view diagram of the same partially completed Zener diode as shown inFIG. 6 ; -
FIG. 8 is a flow diagram further detailingprocess 506 of the flow diagram ofFIG. 5 ; -
FIG. 9 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method ofFIG. 5 ; -
FIG. 10 is a top view diagram of the same partially completed Zener diode as shown inFIG. 9 ; -
FIG. 11 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method ofFIG. 5 ; -
FIG. 12 is a cross-section diagram illustrating a partially completed Zener diode formed according to the method ofFIG. 5 ; -
FIG. 13 is a flow diagram of a design process used in semiconductor design, manufacture and/or test; and -
FIG. 14 is a schematic diagram illustrating an exemplary hardware environment for implementing the disclosed design process. - The descriptions of the various embodiments disclosed herein have been presented for purposes of illustration and are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. Furthermore, it should be noted that the terminology used herein was chosen to best explain the principles of the disclosed embodiments, the practical application of the disclosed embodiments or the technical improvements over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the disclosed embodiments.
- As mentioned above, Zener diodes, like conventional diodes, allow current to flow in a forward direction. However, Zener diodes exhibit a reverse-bias breakdown voltage (Vb) that is low relative that of conventional diodes. Specifically, in the case of a conventional diode, current typically does not flow, when the diode is reverse-biased (i.e., when the voltage on the N-type cathode region of the diode is greater than the voltage on the P-type anode region). However, a large breakdown current will flow, when the diode is reverse-biased and the voltage on the N-type cathode region exceeds the reverse-bias breakdown voltage (Vb). In the case of a Zener diode, the reverse-bias breakdown voltage (Vb) is relatively low. As a result, Zener diodes can be used to protect other circuits against over-voltage conditions. For example, Zener diodes can be used as voltage regulators or as electrostatic discharge (ESD) protection circuits.
- Unfortunately, in order to achieve such a relatively low reverse-bias breakdown voltage (Vb), additional masking and doping processes are required to either form the P-type anode region or N-type cathode region of the Zener diode or to add an additional amount of dopant to an already formed P-type anode region or N-type cathode region of the Zener diode. These additional masking and doping processes can be costly and time consuming. Thus, there is a need in the art for a Zener diode structure and method of forming the structure that allows a desired, relatively low, reverse-bias breakdown voltage (Vb) to be achieved without requiring additional masking and doping processes.
- In view of the foregoing, disclosed herein are embodiments of an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. While the anode contact region is contained entirely within the anode well region, one end of the cathode contact region can extend laterally into the anode well region. The length of this end (i.e., the length of the portion of the cathode contact region that extends from the cathode well region to anode well region interface to the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (Vb) of the Zener diode. Specifically, increasing the length reduces the reverse-bias breakdown voltage (Vb) of the Zener diode and vice versa. Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the Zener diode, having different reverse-bias breakdown voltages, of a method of forming the Zener diode and of a design structure for the Zener diode.
- It should be noted that in this Zener diode, as described in detail below, the first type conductivity can comprise P-type conductivity and the second type conductivity can comprise N-type conductivity. However, alternatively, the first type conductivity can comprise P-type conductivity and the second type conductivity can comprise N-type conductivity. Those skilled in the art will recognize that the different dopants can be used to achieve different type conductivities in different semiconductor materials. For example, a silicon-based semiconductor material having N-type conductivity is typically doped with an N-type dopant (e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)), whereas a silicon-based semiconductor material having P-type conductivity is typically doped with a P-type dopant (e.g., a Group III dopant, such as boron (B) or indium (In)). Alternatively, a gallium nitride (GaN)-based semiconductor material having P-type conductivity is typically doped with magnesium (MG), whereas a gallium nitride (GaN)-based semiconductor material having an N-type conductivity is typically doped with silicon (Si). Additionally, those skilled in the art will further recognize that different conductivity levels will depend upon the relative concentration levels of the dopants. For example, a higher P-type conductivity level in one P-type component can be achieved using a higher relative dopant concentration as compared to another P-type component.
- More particularly,
FIGS. 1-2 illustrate an embodiment of aZener diode 100.FIG. 1 is a cross-section illustration of theZener diode 100 through a vertical plan that cuts across the active regions of the device andFIG. 2 is a cross-section illustration of thesame Zener diode 100 through a horizontal plane A-A′, as shown inFIG. 1 . - Referring to
FIGS. 1 and 2 in combination, theZener diode 100 can comprise asemiconductor layer 103, having atop surface 105. TheZener diode 100 can further comprise afirst well region 111 and asecond well region 112 in thesemiconductor layer 103. Thesecond well region 112 can be positioned laterally adjacent to and can abut thefirst well region 111 at aninterface 113. For example, thesecond well region 112 can laterally surround (e.g., encircle) thefirst well region 111. Thefirst well region 111 can have a first type conductivity and thesecond well region 112 can have a second type conductivity different from the first type conductivity. For example, thefirst well region 111 can have a P-type conductivity such that it comprises an anode well region and thesecond well region 112 can have an N-type conductivity such that it comprises a cathode well region. - In one embodiment, this
semiconductor layer 103 can be a bulk semiconductor substrate (e.g., a bulk silicon substrate). In this case, a buriedwell region 102, having the second type conductivity (e.g., a buried N-well region), can isolate the active regions of thediode 100 from alower portion 101 of the substrate, which has the first type conductivity (e.g., a P− lower substrate). In another embodiment, thesemiconductor layer 103 can be a semiconductor layer of a semiconductor-on-insulator (SOI) structure. Such an SOI structure can comprise asemiconductor substrate 101, having the first type conductivity (e.g., a P− silicon substrate), an isolation layer 102 (e.g., a silicon dioxide (SiO2) layer, a sapphire layer or some other suitable isolation layer) on thesubstrate 101, and a semiconductor layer 103 (e.g., a silicon layer or some other suitable semiconductor layer) on theisolation layer 102. - The
Zener diode 100 can further comprise afirst contact region 131, asecond contact region 132 and, optionally, anadditional contact region 133 in thesemiconductor layer 103 at thetop surface 105. Specifically, thefirst contact region 131 can comprise a doped region contained entirely within thefirst well region 111 and can have the first type conductivity at a relatively higher conductivity level than thefirst well region 111. For example, thefirst contact region 131 can comprise a P+ anode contact region. Thesecond contact region 132 can comprise another doped region and can have the second type conductivity at a relatively higher conductivity level than thesecond well region 112. For example, thesecond contact region 132 can comprise an N+ cathode contact region. However, rather than being contained within thesecond well region 112, thesecond contact region 132 can further traverse the interface 113 (i.e., thefirst well region 111 tosecond well region 112 interface 113) such that afirst end 132 a of thesecond contact region 132 extends laterally into thefirst well region 111 and asecond end 132 b of thesecond contact region 132 extends laterally into thesecond well region 112. - The
additional contact region 133 can comprise an additional doped region contained entirely within thesecond well region 112 and can have the second type conductivity at a relatively higher conductivity level than thesecond well region 111. For example, theadditional contact region 133 can comprise an additional N+ cathode contact region. - The
Zener diode 100 can further compriseisolation regions semiconductor layer 103 and which define the limits (i.e., the boundaries, shapes, etc.) of the contact regions 131-133. Theisolation region 121 can be contained entirely within thefirst well region 111 and can be positioned laterally between and can abut both thefirst contact region 131 and thefirst end 132 a of thesecond contact region 132. Specifically, thisisolation region 121 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of the first contact region 131 (seeFIG. 2 ). Thisisolation region 121 can have a first side (i.e., an inner side) adjacent to thefirst contact region 131 and a second side (i.e., an outer side) opposite the first side adjacent to thefirst end 132 a of thesecond contact region 132. Theadditional isolation region 122 can be contained entirely within thesecond well region 112 and can be positioned laterally between and can abut both thesecond end 132 b of thesecond contact region 132 and theadditional contact region 133. Specifically, thisadditional isolation region 122 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of thesecond contact region 132 and theadditional contact region 133 can be positioned laterally around (i.e., can laterally surround, border, etc.) the additional isolation region 122 (seeFIG. 2 ). - The
isolation regions isolation regions semiconductor layer 103 from thetop surface 105. The trench can further be filled with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.). - In order to achieve the desired reverse-bias breakdown voltage (Vb) (i.e., a predetermined reverse-bias breakdown voltage) given the Zener diode structure described above, the
first end 132 a of the second contact region 132 (i.e., the portion of the second contact region the extends from the first well region to secondwell region interface 113 to the isolation region 121) can have apredetermined length 140. Specifically, thelength 140 of thisend 132 a can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (Vb) of theZener diode 100. In particular, increasing thelength 140 reduces the reverse-bias breakdown voltage (Vb) of thediode 100 and vice versa. - For example,
FIG. 3 is a graph that illustrates current to voltage (UV) curves for threeZener diodes 100 that are essentially identical in structure except that the ends 132 a of thesecond contact regions 132 of each of three Zener diodes have different lengths.UV curve 301 represents a Zener diode wherein theend 132 a is relatively short (e.g., the side of theSTI 121 is almost aligned above the interface 113) and, thus, the reverse-bias breakdown voltage (Vb) at which a significant amount of current flows through the diode is relative large (e.g., −7V).UV curve 303 represents a Zener diode wherein theend 132 a is relatively long (e.g., 0.5 μm) and, thus, the reverse-bias breakdown voltage (Vb) at which a significant amount of current flows through the diode is relative small (e.g., −5.2V).UV curve 302 represents a Zener diode wherein theend 132 a is somewhere in between (e.g., 0.14 μm) and, thus, the reverse-bias breakdown voltage (Vb) at which a significant amount of current flows through the diode is somewhere in between (e.g., −6.2V). - Referring again to
FIGS. 1 and 2 in combination, optionally, theZener diode 100 can further comprise aconductive field plate 150 on thetop surface 105 of thesemiconductor layer 103 to further ensure that theZener diode 100 has the desired reverse-bias breakdown voltage (Vb). Theconductive field plate 150 can have afirst sidewall 151 aligned above theisolation region 121 and asecond sidewall 152 opposite thefirst sidewall 151 aligned above thefirst end 132 a of thesecond contact region 132. That is, theconductive field plate 150 should not extend laterally over thefirst contact region 131 or thesecond well region 112. Thisconductive field plate 150 can comprise, for example, a metal field plate, a metal alloy field plate, a doped polysilicon field plate, etc. Such aconductive field plate 150 is particularly useful to reduce the reverse-bias breakdown voltage (Vb) when the sidewall of theisolation region 121 immediately adjacent to thefirst contact region 131 is not perpendicular (e.g., is rounded as a result of formation processing techniques), a condition which tends to increase the reverse-bias breakdown voltage (Vb). - Those skilled in the art will recognize that a Zener diode, such as the diode described above having a scalable reverse-bias breakdown voltage (Vb), can be incorporated into an integrated circuit structure for various different purposes, for example, for voltage regulation or for electrostatic discharge (ESD) protection. Furthermore, for illustration purposes, the perimeters (or shapes) of the diode components (e.g., the
first contact region 131,STI region 121, thesecond contact region 132, theSTI region 122, etc.) are shown inFIG. 2 as being rectangular. However, those skilled in the art will recognize that these diode components may alternatively have any other suitable shape (e.g., square, circle, oval, etc.). - Referring to
FIGS. 4 a and 4 b, also disclosed herein are embodiments of anintegrated circuit structure integrated circuit structure top surface 405. As with the Zener diode embodiments described in detail above and illustrated inFIGS. 1-2 , this semiconductor layer 403 can comprise either a bulk semiconductor layer, as shown in theintegrated circuit structure 499 a ofFIG. 4 a or a semiconductor layer of a semiconductor-on-insulator wafer, as shown in theintegrated circuit structure 499 b ofFIG. 4 b. - More specifically, referring to
FIG. 4 a, in one embodiment of theintegrated circuit structure 499 a, the semiconductor layer 403 can be a bulk semiconductor substrate (e.g., a bulk silicon substrate). In this case, buried well isolation regions 402.1, 402.2, having the second type conductivity (e.g., buried N-well isolation regions), can isolate the active regions of the Zener diodes 400.1, 400.2, respectively, from alower portion 401 of the substrate, which has a first type conductivity (e.g., a P− lower substrate). Furthermore, an additionalisolation well region 413, having the first type conductivity (e.g., a P-well isolation region), can be positioned laterally between the Zener diodes 400.1, 400.2 to isolate the devices from each other. Referring toFIG. 4 b, in another embodiment of theintegrated circuit structure 499 b, the semiconductor layer 403 can be a semiconductor layer of a semiconductor-on-insulator (SOT) structure. Such an SOI structure can comprise asemiconductor substrate 401, having the first type conductivity (e.g., a P− silicon substrate), an isolation layer 402 (e.g., a silicon dioxide (SiO2) layer, a sapphire layer, or some other suitable isolation layer) on thesubstrate 401, and a semiconductor layer (e.g., a silicon layer or some other suitable semiconductor layer) on theisolation layer 402. Furthermore, a deep trench isolation region (e.g., a deep trench filled with one or more isolation materials, such a silicon oxide, silicon nitride, silicon oxynitride, etc.) can be positioned laterally between the Zener diodes 400.1, 400.2 and can extend vertically to the isolation layer 403 to isolate the devices from each other. - In any case, each of the Zener diodes 400.1, 400.2 in the
integrated circuit structure FIGS. 4 a and 4 b can comprise afirst well region 411 and asecond well region 412 in the semiconductor layer 403. Thesecond well region 412 can be positioned laterally adjacent to and can abut thefirst well region 411 at aninterface 413. For example, thesecond well region 412 can laterally surround (e.g., encircle) thefirst well region 411. Thefirst well region 411 can have a first type conductivity and thesecond well region 412 can have a second type conductivity different from the first type conductivity. For example, thefirst well region 411 can have a P-type conductivity such that it comprises an anode well region and thesecond well region 412 can have an N-type conductivity such that it comprises a cathode well region. - Each of the Zener diodes 400.1, 400.2 can further comprise a
first contact region 431, asecond contact region 432, and anadditional contact region 433 in the semiconductor layer 403 at thetop surface 405. Specifically, thefirst contact region 431 can comprise a doped region contained entirely within thefirst well region 411 and can have the first type conductivity at a relatively higher conductivity level than thefirst well region 411. For example, thefirst contact region 431 can comprise a P+ anode contact region. Thesecond contact region 432 can comprise another doped region and can have the second type conductivity at a relatively higher conductivity level than thesecond well region 412. For example, thesecond contact region 432 can comprise an N+ cathode contact region. However, rather than being contained within thesecond well region 412, thesecond contact region 432 can further traverse theinterface 413 such that afirst end 432 a of thesecond contact region 432 extends laterally into thefirst well region 411 and asecond end 432 b of thesecond contact region 432 extends laterally into thesecond well region 412. Theadditional contact region 433 can comprise an additional doped region contained entirely within thesecond well region 412 and can have the second type conductivity at a relatively higher conductivity level than thesecond well region 411. For example, theadditional contact region 433 can comprise an additional N+ cathode contact region. - Each of the Zener diodes 400.1, 400.2 can further comprise
isolation regions isolation region 421 can be contained entirely within thefirst well region 411 and can be positioned laterally between and can abut both thefirst contact region 431 and thefirst end 432 a of thesecond contact region 432. Specifically, thisisolation region 421 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of thefirst contact region 431. Theadditional isolation region 422 can be contained entirely within thesecond well region 412 and can be positioned laterally between and can abut both thesecond end 432 b of thesecond contact region 432 and theadditional contact region 433. Specifically, thisadditional isolation region 422 can be positioned laterally around (i.e., can laterally surround, border, etc.) the perimeter (i.e., outer edge) of thesecond contact region 432 and theadditional contact region 433 can be positioned laterally around (i.e., can laterally surround, border, etc.) theadditional isolation region 422. - The
isolation regions isolation regions top surface 405. The trench can further be filled with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.). - In order to achieve the selectively different reverse-bias breakdown voltages (i.e., the different predetermined reverse-bias breakdown voltages) given the Zener diode structures 400.1, 400.2 described above, the
first end 432 a of the second contact region 432 (i.e., the portion of the second contact region that extends from theinterface 413 to the isolation region 421) of the first Zener diode 400.1 can have a differentpredetermined length 440, than that of thefirst end 432 a of thesecond contact region 432 of the second Zener diode 400.2. Specifically, thelengths 440 of theends 432 a of the different Zener diodes 400.1 and 400 can be selectively different in order to achieve selectively different reverse-bias breakdown voltages (Vb) in the Zener diodes 400.1 and 400.2. In particular, sincelength 440 of thefirst end 432 a of thesecond contact region 432 of the first Zener diode 400.1 is greater than that of the second Zener diode 400.2, the first Zener diode 400.1 will have a smaller reverse-bias breakdown voltage (Vb). See detail discussion above regarding the graph ofFIG. 3 and the relationship between this length and the reverse-bias breakdown voltage (Vb). - Referring again to
FIGS. 4 a and 4 b, optionally, at least one of the Zener diodes (e.g., see Zener diode 400.1) can further comprise aconductive field plate 450 on thetop surface 405 of the semiconductor layer 403 to further ensure that the Zener diode 400.1 has the desired reverse-bias breakdown voltage (Vb). Theconductive field plate 450 can have afirst sidewall 451 aligned above theisolation region 421 and asecond sidewall 452 opposite thefirst sidewall 451 aligned above thefirst end 432 a of thesecond contact region 432. That is, theconductive field plate 450 should not extend laterally over thefirst contact region 431 or thesecond well region 412. Thisconductive field plate 450 can comprise, for example, a metal field plate, a metal alloy field plate, a doped polysilicon field plate, etc. Such aconductive field plate 450 is particularly useful in reducing the reverse-bias breakdown voltage (Vb) when the sidewall of theisolation region 421 immediately adjacent to thefirst contact region 431 is not perpendicular (e.g., is rounded), a condition which tends to increase the reverse-bias breakdown voltage (Vb). - Those skilled in the art will recognize that Zener diodes, such as Zener diodes 400.1, 400.2 described above, having different reverse-bias breakdown voltages, can be incorporated into the
integrated circuit structure - Referring to
FIG. 5 , also disclosed herein are embodiments of a method of forming a Zener diode, such as theZener diode 100 ofFIG. 1 described in detail above. The method embodiments can comprise providing a semiconductor layer 103 (502) and forming adjacent well regions in thesemiconductor layer 103 such that the adjacent well regions comprise: afirst well region 111 having a first type conductivity (e.g., a P-type anode well region) and asecond well region 112 having a second type conductivity different from the first type conductivity (e.g., an N-type cathode well region) positioned laterally adjacent to and, particularly, laterally surrounding and abutting and the first well region at an interface 113 (504, see the cross-section illustration ofFIG. 6 and the top view illustration ofFIG. 7 ). Techniques for forming such well regions are well known in the art (e.g., using multiple masked dopant implantation processes) and, thus, are omitted from this specification in order to allow the user to focus on the salient aspects of the invention. - It should be noted that in one embodiment, the
semiconductor layer 103 provided atprocess 502 could be a bulk semiconductor substrate (e.g., a bulk silicon substrate). In this case, prior to the formation of thewell regions process 504, a buriedwell region 102, having the second type conductivity (e.g., a buried N-well region), can be formed deep in the substrate so as to isolate subsequently formed active regions of the Zener diode from alower portion 101 of the substrate, which has a the first type conductivity (e.g., a P− lower substrate). In another embodiment, thesemiconductor layer 103 provided atprocess 502 could be a semiconductor layer of a semiconductor-on-insulator (SOI) structure. Such an SOI structure can comprise asemiconductor substrate 101, having the first type conductivity (e.g., a P− silicon substrate), an isolation layer 102 (e.g., a silicon dioxide (SiO2) layer, sapphire layer or some other suitable isolation layer) on thesubstrate 101, and a semiconductor layer (e.g., a silicon layer or some other suitable semiconductor layer) on theisolation layer 102. - Referring again to
FIG. 5 , the method embodiments can further comprise forming shallow trench isolation (STI) regions 121-122 and anode and cathode contact regions 131-133 at thetop surface 105 of the semiconductor layer 103 (506).Process 506 can specifically be performed so as to form the various contact regions and isolation regions, as shown inFIGS. 1 and 2 and described in detail above. - Specifically,
process 506 can be performed so as to form afirst contact region 131, which is contained entirely within thefirst well region 111 and which has the first type conductivity at a relatively higher conductivity level than the first well region 111 (e.g., a P+ anode contact region) (507). -
Process 506 can be performed so as to form anisolation region 121 such that theisolation region 121 is contained entirely within thefirst well region 111 and such that theisolation region 121 is positioned adjacent to (e.g., laterally surrounds, borders, etc.) and abuts the first contact region 131 (508). -
Process 506 can further be performed so as to form asecond contact region 132 such that thesecond contact region 132 traverses theinterface 113 between the well regions 111-112 (i.e., has afirst end 132 a extending laterally into thefirst well region 111 and asecond end 132 b extending laterally into the second well region 112), such that thesecond contact region 132 is positioned adjacent to (e.g., laterally surrounds, borders, etc.) and abuts theisolation region 121 and such that thesecond contact region 132 has a second type conductivity at a relatively higher conductivity level than the second well region 112 (e.g., a N+ cathode region) (509). It should be noted that thissecond contact region 132 should specifically be formed so that thefirst end 132 a between theinterface 113 and theisolation region 121 has apredetermined length 140 and, thereby so that theZener diode 100 has a predetermined reverse-bias breakdown voltage (Vb) (510). -
Process 506 can further be performed so as to form anadditional isolation region 122 such that theadditional isolation region 122 is contained entirely within thesecond well region 111 and such that the additional isolation region is adjacent to (e.g., laterally surrounds, borders, etc.) and abuts the second contact region 132 (511). - Finally,
process 506 can be performed so as to form anadditional contact region 133 such that theadditional contact region 133 is contained entirely within thesecond well region 112, such that the additional contact region is positioned adjacent to (e.g., laterally surrounds, borders, etc.) and abuts theadditional isolation region 122 and such that theadditional contact region 133 has the second type conductivity at a relatively higher conductivity level than the second well region 111 (e.g., an additional N+ cathode contact region) (512). - More specifically, referring to
FIG. 8 , thisprocess 506 of forming the isolation regions 121-122 and anode and cathode contact regions 131-133 for theZener diode 100 can comprise forming shallow trench isolation (STI) regions 121-122 that define the limits (i.e., boundaries, shapes, etc.) of the contact regions 131-133, as described above (802). That is, conventional STI formation techniques can be used to pattern, etch and fill the trenches for each of the STI regions 121-122 and to, thereby define the limits (i.e., boundaries, shapes, etc.) of the contact regions 131-133 (see the cross-section and top view diagrams ofFIG. 9 andFIG. 10 , respectively). It should be noted that the novelty in this case is not how theSTI regions 121 are formed but that the STI trenches are patterned so that the defined area for the second contact region 132 (i.e., the N+ cathode region) in particular, which lies between the trenches, traverses theinterface 113 between the well regions 111-112 as opposed to being contained entirely within thewell region 112. Furthermore, during the patterning of the STI trenches, the position of the STI trenches relative to theinterface 113 is selectively adjusted so as to selectively adjust the position and overall length of thesecond contact region 132 and, thereby to selectively adjust thelength 140 of theend 132 a of thatsecond contact region 132 that extends from theinterface 113 to theSTI region 121. By selectively adjusting thelength 140 of theend 132 a of thesecond contact region 132, the reverse-bias breakdown voltage (Vb) of theZener diode 100 can be selectively adjusted (803). See also the detailed discussion above regarding the graph ofFIG. 3 illustrating the inverse relationship between thelength 140 of theend 132 of thesecond contact region 132 that extends into thewell region 111 and the reverse-bias breakdown voltage (Vb) of theZener diode 100. Once the STI trenches are patterned and etched, they can be filled using conventional STI formation techniques with one or more isolation materials (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.). - Following STI 121-122 formation at
process 802, the contact regions 131-133 can be appropriately doped (804). For example, amask 901 can be formed so as to cover the exposed portion of thesemiconductor layer 103 surrounded by theSTI region 121 and a dopant implantation process or other doping process can be performed in order to doped the exposed areas of thetop surface 105 of thesemiconductor layer 103 adjacent to theSTI region 122 and, thereby formcontact regions FIG. 11 ). Next, themask 901 can be removed, anothermask 902 can be formed so as to cover the exposed portion of thesemiconductor layer 103 adjacent to theSTI region 122, and another dopant implantation or other doping process can be performed in order to doped the exposed area of thetop surface 105 of thesemiconductor layer 103 surrounded by theSTI region 121 and, thereby formcontact region 131 having the first type conductivity (e.g., a P+ anode region) (seeFIG. 12 ). - Those skilled in the art will recognize that the order of the process steps set forth in
FIG. 8 are offered for illustration purposes only. Alternatively, areas of the top surface of thesemiconductor layer 103 that will contain the contact regions 131-133 can be appropriately doped and, then, theSTI regions 121 can be formed to specifically define the limits/boundaries of those regions. Additionally, it should be noted that the disclosed process described above for selectively adjusting the reverse-bias breakdown voltage (Vb) is an improvement over prior art techniques because it is achieved by simply selectively adjusting the position of thesecond contact region 132 and not by requiring additional masking and doping processes (i.e., it is a less costly zero-mask adder process). - Referring again to
FIG. 5 , optionally, the method embodiments can further comprise forming a conductive field plate 150 (e.g., a doped polysilicon, metal or metal alloy conductive field plate) on thetop surface 105 of thesemiconductor layer 103 in order to further reduce the reverse-bias breakdown voltage (Vb) of the diode and ensure that a desired reverse-bias breakdown voltage (Vb) is achieved (514, seeFIG. 1 ). In this case, theconductive field plate 150 should be formed so that afirst sidewall 151 is aligned above theisolation region 121 and asecond sidewall 152 opposite thefirst sidewall 151 is aligned above thefirst end 132 a of the second contact region 132 (i.e., so that theconductive field plate 150 does not extend laterally over thefirst contact 131 or the second well region 112). Such aconductive field plate 150 can be formed essentially simultaneously with the formation of polysilicon and/or metal gate structures on thetop surface 105 of thesemiconductor layer 103. Thus, it should be noted that this process for further adjusting the reverse-bias breakdown voltage (Vb) is also an improvement over prior art techniques because it too is achieved by without requiring additional masking (i.e., it is a less costly zero-mask adder process) - Finally, it should be noted that, although the embodiments of the method are described above with reference to the
Zener diode 100 illustrated inFIGS. 1-2 , essentially the same method steps may be used to form the Zener diodes 400.1, 400.2 of theintegrated circuit embodiments FIGS. 4 a and 4 b, respectively, and described in detail above. Those skilled in the art will, however, recognize that depending upon the whether a bulk semiconductor wafer or semiconductor-on-insulator wafer is used different conventional process steps can be performed to provide isolation between the device-to-substrate isolation and device-to-device isolation. For example, in the case of theintegrated circuit structure 499 a ofFIG. 4 a, which is formed on a bulk semiconductor wafer, discrete buried well isolation regions 402.1, 402.2, having the second type conductivity (e.g., buried N-well isolation regions), can be formed (e.g., implanted) prior to device formation to isolate the active regions of the subsequently formed diodes 400.1, 400.2, respectively, from alower portion 401 of the first type conductivity substrate (e.g., P− substrate). Furthermore, an additionalisolation well region 413, having the first type conductivity (e.g., a P-well isolation region), can be formed (e.g., implanted) such that it is positioned laterally between the Zener diodes 400.1, 400.2 to isolate the devices from each other. Alternatively, in the case of theintegrated circuit structure 499 b ofFIG. 4 b, wherein the Zener diodes 400.1, 400.2 are formed in a semiconductor layer 403 of a semiconductor-on-insulator (SOI) wafer, the SOI isolation layer 402 (e.g., a silicon dioxide (SiO2) layer, sapphire layer or some other suitable isolation layer) can provide the device to substrate isolation. Furthermore, a deep trench isolation region (e.g., a deep trench filled with one or more isolation materials, such a silicon oxide, silicon nitride, silicon oxynitride, etc.) can be formed (e.g., using conventional deep trench isolation processing techniques) such it will be positioned laterally between the Zener diodes 400.1, 400.2 and extends vertically to the isolation layer 403 to isolate the devices from each other. - Also disclosed herein are embodiments of design structures for the above-mentioned Zener diode and integrated circuit. Such design structures can be stored on a non-transitory storage medium readable by a computer and can comprise data and instructions that when executed by the computer can generate a machine-executable representation of the diode or integrated circuit.
- Specifically,
FIG. 13 shows a block diagram of anexemplary design flow 1300 used for example, in semiconductor design, manufacturing, and/or test.Design flow 1300 may vary depending on the type of IC being designed. For example, adesign flow 1300 for building an application specific IC (ASIC) may differ from adesign flow 1300 for designing a standard component.Design structure 1320 is preferably an input (e.g., of data and instructions) to adesign process 1310 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources.Design structure 1320 comprises an embodiment of aZener diode 100 as shown inFIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400.1, 400.2, as shown inFIGS. 4 a and 4 b, in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.).Design structure 1320 may be contained on (i.e., stored on) one or more machine-readable medium. For example,design structure 1320 may be a text file or a graphical representation of an embodiment of aZener diode 100 as shown inFIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400.1, 400.2, as shown inFIGS. 4 a and 4 b. -
Design process 1310 preferably executes the data and instructions in order to synthesize (or translate) an embodiment of aZener diode 100 as shown inFIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400.1, 400.2, as shown inFIGS. 4 a and 4 b, into anetlist 1380, wherenetlist 1380 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 1380 is resynthesized one or more times depending on design specifications and parameters for the circuit. -
Design process 1310 may include using a variety of inputs; for example, inputs fromlibrary elements 1330 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.),design specifications 1340,characterization data 1350,verification data 1360,design rules 1370, test data files 1385 (which may include test patterns and other testing information), and instructions. -
Design process 1310 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process X10 without deviating from the scope and spirit of the embodiments herein. The design structures of the embodiments are not limited to any specific design flow. -
Design process 1310 preferably translates an embodiment of aZener diode 100 as shown inFIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400.1, 400.2, as shown inFIGS. 4 a and 4 b, along with any additional integrated circuit design or data (if applicable), into asecond design structure 1390.Design structure 1390 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures).Design structure 1390 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of aZener diode 100 as shown inFIGS. 1-2 or an integrated circuit with multiple instances of Zener diode 400.1, 400.2, as shown inFIGS. 4 a and 4 b.Design structure 1390 may then proceed to astage 1395 where, for example, design structure 1390: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. - A representative hardware environment for implementing the design flow process, described above and illustrated in
FIG. 13 , is depicted inFIG. 14 . This schematic drawing illustrates a hardware configuration of an information handling/computer system in accordance with the embodiments herein. The system comprises at least one processor or central processing unit (CPU) 10. TheCPUs 10 are interconnected viasystem bus 12 to various devices such as a random access memory (RAM) 14, read-only memory (ROM) 16, and an input/output (I/O)adapter 18. The I/O adapter 18 can connect to peripheral devices, such asdisk units 11 and tape drives 13, or other program storage devices that are readable by the system. The system can read the inventive instructions on the program storage devices and follow these instructions to execute the methodology of the embodiments herein. The system further includes auser interface adapter 19 that connects akeyboard 15,mouse 17,speaker 24,microphone 22, and/or other user interface devices such as a touch screen device (not shown) to thebus 12 to gather user input. Additionally, acommunication adapter 20 connects thebus 12 to adata processing network 25, and adisplay adapter 21 connects thebus 12 to adisplay device 23 which may be embodied as an output device such as a monitor, printer, or transmitter, for example. - It should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of those embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Additionally, it should be understood that terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., used herein are understood to be relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated). Terms such as “touching”, “on”, “in direct contact”, “abutting”, “directly adjacent to”, etc., mean that at least one element physically contacts another element (without other elements separating the described elements).
- It should further be understood that for purposes of this disclosure, a “semiconductor” is a material or structure that may include an implanted impurity that allows the material to sometimes be a conductor and sometimes be an insulator, based on electron and hole carrier concentration. As used herein, “implantation processes” can take any appropriate form (whether now known or developed in the future) and can comprise, for example, ion implantation, etc. Furthermore, an “insulator” is a relative term that means a material or structure that allows substantially less (<95%) electrical current to flow than does a “conductor.” The dielectrics (insulators) mentioned herein can oxide-based dielectrics, such oxide-based dielectrics can be grown, for example, from either a dry oxygen ambient or steam and then patterned. Alternatively, the dielectrics herein may be formed from any of the many candidate dielectric materials, including but not limited to silicon nitride, silicon oxynitride, or a metal oxide (e.g., tantalum oxide). The thickness of dielectrics herein may vary contingent upon the required device performance. The conductors mentioned herein can be formed of any conductive material, such as polycrystalline silicon (polysilicon), amorphous silicon, a combination of amorphous silicon and polysilicon, and polysilicon-germanium, rendered conductive by the presence of a suitable dopant. Alternatively, the conductors herein may be one or more metals, such as tungsten, hafnium, tantalum, molybdenum, titanium, or nickel, or a metal silicide, any alloys of such metals, and may be deposited using physical vapor deposition, chemical vapor deposition, or any other technique known in the art.
- Finally, it should be understood that the corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the embodiments contained in the specification have been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments.
- Therefore, disclosed above are embodiments of an isolated Zener diode structure having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. While the anode contact region is contained entirely within the anode well region, one end of the cathode contact region can extend laterally into the anode well region. The length of this end (i.e., the length of the portion of the cathode contact region between the interface and the isolation region) can be selectively adjusted in order to selectively adjust the reverse-bias breakdown voltage (Vb) of the diode. Specifically, increasing the length reduces the reverse-bias breakdown voltage (Vb) of the diode and vice versa. Also disclosed herein are embodiments of an integrated circuit incorporating multiple instances of the Zener diode, having different reverse-bias breakdown voltages, of a method of forming the Zener diode and of a design structure for the Zener diode. In other words, these embodiments allow scaling of the reverse-bias breakdown voltage (Vb) of a Zener diode to be achieved by simply selectively adjusting the position of the cathode contact region and, optionally, adding a conductive field plate. These technique can be incorporated into conventional device processing (e.g., well implantation, STI formation, and gate formation) without requiring additional masking and doping processes (i.e., it is a zero-mask adder technique).
Claims (25)
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US13/345,881 US8492866B1 (en) | 2012-01-09 | 2012-01-09 | Isolated Zener diode |
US13/945,967 US8796108B2 (en) | 2012-01-09 | 2013-07-19 | Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode |
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US13/345,881 US8492866B1 (en) | 2012-01-09 | 2012-01-09 | Isolated Zener diode |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140034967A1 (en) * | 2012-08-06 | 2014-02-06 | Denso Corporation | Diode |
CN110649013A (en) * | 2018-06-26 | 2020-01-03 | 恩智浦美国有限公司 | Dynamic substrate biasing for extended voltage operation |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9018673B2 (en) | 2012-08-31 | 2015-04-28 | Freescale Semiconductor Inc. | Zener diode device and fabrication |
US9059008B2 (en) * | 2012-10-19 | 2015-06-16 | Freescale Semiconductor, Inc. | Resurf high voltage diode |
US9099487B2 (en) * | 2013-12-05 | 2015-08-04 | Freescale Semiconductor Inc. | Zener diode devices and related fabrication methods |
JP2015141996A (en) * | 2014-01-28 | 2015-08-03 | 株式会社東芝 | Semiconductor device and method for manufacturing the same |
KR102223206B1 (en) | 2014-07-31 | 2021-03-08 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US10845395B2 (en) | 2018-02-08 | 2020-11-24 | Honeywell International Inc. | Intrinsically safe Zener diode barrier with indication |
JP6981365B2 (en) * | 2018-05-17 | 2021-12-15 | 日本電信電話株式会社 | Photodetector |
US11869986B2 (en) | 2021-08-27 | 2024-01-09 | Texas Instruments Incorporated | Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4173022A (en) | 1978-05-09 | 1979-10-30 | Rca Corp. | Integrated gate field effect transistors having closed gate structure with controlled avalanche characteristics |
US5559044A (en) | 1992-09-21 | 1996-09-24 | Siliconix Incorporated | BiCDMOS process technology |
US5545926A (en) * | 1993-10-12 | 1996-08-13 | Kabushiki Kaisha Toshiba | Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts |
JP3846395B2 (en) | 1994-11-21 | 2006-11-15 | 富士電機デバイステクノロジー株式会社 | MOS type semiconductor device |
US5602404A (en) * | 1995-01-18 | 1997-02-11 | National Semiconductor Corporation | Low voltage triggering silicon controlled rectifier structures for ESD protection |
US5998837A (en) | 1995-06-02 | 1999-12-07 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode having adjustable breakdown voltage |
US5751042A (en) * | 1996-02-15 | 1998-05-12 | Winbond Electronics Corporation | Internal ESD protection circuit for semiconductor devices |
US5856214A (en) * | 1996-03-04 | 1999-01-05 | Winbond Electronics Corp. | Method of fabricating a low voltage zener-triggered SCR for ESD protection in integrated circuits |
US5882967A (en) | 1997-05-07 | 1999-03-16 | International Business Machines Corporation | Process for buried diode formation in CMOS |
JPH1168085A (en) | 1997-08-15 | 1999-03-09 | Toshiba Corp | Corner structure of semiconductor device |
TW411607B (en) * | 1998-12-02 | 2000-11-11 | Winbond Electronics Corp | Electrostatic discharge protection circuit |
JP4326606B2 (en) * | 1998-03-26 | 2009-09-09 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US6153918A (en) * | 1998-04-20 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with improved planarity and reduced parasitic capacitance |
KR100359161B1 (en) * | 1999-12-31 | 2002-10-31 | 주식회사 하이닉스반도체 | A method for fabricating transistor of a semiconductor device |
US6344385B1 (en) | 2000-03-27 | 2002-02-05 | Chartered Semiconductor Manufacturing Ltd. | Dummy layer diode structures for ESD protection |
US6603177B2 (en) * | 2001-05-18 | 2003-08-05 | United Microelectronics Corp. | Electrostatic discharge protection circuit device |
US6791146B2 (en) * | 2002-06-25 | 2004-09-14 | Macronix International Co., Ltd. | Silicon controlled rectifier structure with guard ring controlled circuit |
US8120079B2 (en) * | 2002-09-19 | 2012-02-21 | Quantum Semiconductor Llc | Light-sensing device for multi-spectral imaging |
US7056761B1 (en) * | 2003-03-14 | 2006-06-06 | National Semiconductor Corporation | Avalanche diode with breakdown voltage controlled by gate length |
GB0316362D0 (en) | 2003-07-12 | 2003-08-13 | Koninkl Philips Electronics Nv | Insulated gate power semiconductor devices |
TWI302031B (en) * | 2003-07-16 | 2008-10-11 | Realtek Semiconductor Corp | Cascaded diode structure with deep n-well and method for making the same |
US8264039B2 (en) * | 2004-04-26 | 2012-09-11 | Synopsys, Inc. | High-voltage LDMOSFET and applications therefor in standard CMOS |
JP5021301B2 (en) * | 2004-08-17 | 2012-09-05 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
US7420250B2 (en) | 2004-08-30 | 2008-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device having light doped regions |
JP2006080160A (en) * | 2004-09-07 | 2006-03-23 | Toshiba Corp | Electrostatic protective circuit |
JP4845410B2 (en) * | 2005-03-31 | 2011-12-28 | 株式会社リコー | Semiconductor device |
EP1742272A1 (en) * | 2005-07-08 | 2007-01-10 | STMicroelectronics S.r.l. | Power device having monolithic cascode structure and integrated Zener diode |
JP5044950B2 (en) | 2006-03-14 | 2012-10-10 | 株式会社デンソー | Semiconductor device |
JP2008010667A (en) * | 2006-06-29 | 2008-01-17 | Mitsumi Electric Co Ltd | Semiconductor device |
WO2008011617A2 (en) * | 2006-07-21 | 2008-01-24 | The Regents Of The University Of California | Shallow-trench-isolation (sti)-bounded single-photon avalanche photodetectors |
US7888767B2 (en) * | 2006-07-21 | 2011-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structures of high-voltage MOS devices with improved electrical performance |
JP2008205053A (en) * | 2007-02-17 | 2008-09-04 | Seiko Instruments Inc | Semiconductor device |
US7719026B2 (en) * | 2007-04-11 | 2010-05-18 | Fairchild Semiconductor Corporation | Un-assisted, low-trigger and high-holding voltage SCR |
US7834378B2 (en) * | 2007-08-28 | 2010-11-16 | Fairchild Korea Semiconductor Ltd | SCR controlled by the power bias |
US8198651B2 (en) * | 2008-10-13 | 2012-06-12 | Infineon Technologies Ag | Electro static discharge protection device |
US7902604B2 (en) | 2009-02-09 | 2011-03-08 | Alpha & Omega Semiconductor, Inc. | Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection |
JP5452146B2 (en) * | 2009-09-17 | 2014-03-26 | セイコーインスツル株式会社 | Semiconductor device |
US8217421B2 (en) * | 2010-07-21 | 2012-07-10 | Amazing Microelectronic Corp. | ESD protection device with vertical transistor structure |
US8278710B2 (en) * | 2010-07-23 | 2012-10-02 | Freescale Semiconductor, Inc. | Guard ring integrated LDMOS |
-
2012
- 2012-01-09 US US13/345,881 patent/US8492866B1/en active Active
-
2013
- 2013-07-19 US US13/945,967 patent/US8796108B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140034967A1 (en) * | 2012-08-06 | 2014-02-06 | Denso Corporation | Diode |
US9478672B2 (en) * | 2012-08-06 | 2016-10-25 | Denso Corporation | Diode |
US20170012140A1 (en) * | 2012-08-06 | 2017-01-12 | Denso Corporation | Diode |
US9853168B2 (en) * | 2012-08-06 | 2017-12-26 | Denso Corporation | Diode |
CN110649013A (en) * | 2018-06-26 | 2020-01-03 | 恩智浦美国有限公司 | Dynamic substrate biasing for extended voltage operation |
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US20130299938A1 (en) | 2013-11-14 |
US8492866B1 (en) | 2013-07-23 |
US8796108B2 (en) | 2014-08-05 |
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